Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2009 Intel Corporation |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: |
| 25 | * Eric Anholt <eric@anholt.net> |
| 26 | * Jesse Barnes <jesse.barnes@intel.com> |
| 27 | */ |
| 28 | |
| 29 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 31 | #include <linux/delay.h> |
| 32 | #include "drmP.h" |
| 33 | #include "drm.h" |
| 34 | #include "drm_crtc.h" |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 35 | #include "drm_edid.h" |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 36 | #include "intel_drv.h" |
| 37 | #include "i915_drm.h" |
| 38 | #include "i915_drv.h" |
| 39 | |
Daniel Vetter | afba018 | 2012-06-12 16:36:45 +0200 | [diff] [blame] | 40 | static void |
| 41 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) |
| 42 | { |
| 43 | struct drm_device *dev = intel_hdmi->base.base.dev; |
| 44 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 45 | uint32_t enabled_bits; |
| 46 | |
| 47 | enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
| 48 | |
| 49 | WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits, |
| 50 | "HDMI port enabled, expecting disabled\n"); |
| 51 | } |
| 52 | |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 53 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 54 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 55 | return container_of(encoder, struct intel_hdmi, base.base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 56 | } |
| 57 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 58 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
| 59 | { |
| 60 | return container_of(intel_attached_encoder(connector), |
| 61 | struct intel_hdmi, base); |
| 62 | } |
| 63 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 64 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 65 | { |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 66 | uint8_t *data = (uint8_t *)frame; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 67 | uint8_t sum = 0; |
| 68 | unsigned i; |
| 69 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 70 | frame->checksum = 0; |
| 71 | frame->ecc = 0; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 72 | |
Jesse Barnes | 64a8fc0 | 2011-09-22 11:16:00 +0530 | [diff] [blame] | 73 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 74 | sum += data[i]; |
| 75 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 76 | frame->checksum = 0x100 - sum; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 77 | } |
| 78 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 79 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 80 | { |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 81 | switch (frame->type) { |
| 82 | case DIP_TYPE_AVI: |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 83 | return VIDEO_DIP_SELECT_AVI; |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 84 | case DIP_TYPE_SPD: |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 85 | return VIDEO_DIP_SELECT_SPD; |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 86 | default: |
| 87 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 88 | return 0; |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 89 | } |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 90 | } |
| 91 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 92 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 93 | { |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 94 | switch (frame->type) { |
| 95 | case DIP_TYPE_AVI: |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 96 | return VIDEO_DIP_ENABLE_AVI; |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 97 | case DIP_TYPE_SPD: |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 98 | return VIDEO_DIP_ENABLE_SPD; |
Paulo Zanoni | fa193ff | 2012-05-04 17:18:20 -0300 | [diff] [blame] | 99 | default: |
| 100 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 101 | return 0; |
Paulo Zanoni | fa193ff | 2012-05-04 17:18:20 -0300 | [diff] [blame] | 102 | } |
Paulo Zanoni | fa193ff | 2012-05-04 17:18:20 -0300 | [diff] [blame] | 103 | } |
| 104 | |
Paulo Zanoni | 2da8af5 | 2012-05-14 17:12:51 -0300 | [diff] [blame] | 105 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
| 106 | { |
| 107 | switch (frame->type) { |
| 108 | case DIP_TYPE_AVI: |
| 109 | return VIDEO_DIP_ENABLE_AVI_HSW; |
| 110 | case DIP_TYPE_SPD: |
| 111 | return VIDEO_DIP_ENABLE_SPD_HSW; |
| 112 | default: |
| 113 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
| 114 | return 0; |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) |
| 119 | { |
| 120 | switch (frame->type) { |
| 121 | case DIP_TYPE_AVI: |
| 122 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); |
| 123 | case DIP_TYPE_SPD: |
| 124 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); |
| 125 | default: |
| 126 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
| 127 | return 0; |
| 128 | } |
| 129 | } |
| 130 | |
Daniel Vetter | a3da1df | 2012-05-08 15:19:06 +0200 | [diff] [blame] | 131 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
| 132 | struct dip_infoframe *frame) |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 133 | { |
| 134 | uint32_t *data = (uint32_t *)frame; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 135 | struct drm_device *dev = encoder->dev; |
| 136 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 137 | u32 val = I915_READ(VIDEO_DIP_CTL); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 138 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 139 | |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 140 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
| 141 | |
Paulo Zanoni | 1d4f85a | 2012-05-04 17:18:18 -0300 | [diff] [blame] | 142 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 143 | val |= g4x_infoframe_index(frame); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 144 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 145 | val &= ~g4x_infoframe_enable(frame); |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 146 | |
| 147 | I915_WRITE(VIDEO_DIP_CTL, val); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 148 | |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 149 | mmiowb(); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 150 | for (i = 0; i < len; i += 4) { |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 151 | I915_WRITE(VIDEO_DIP_DATA, *data); |
| 152 | data++; |
| 153 | } |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 154 | mmiowb(); |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 155 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 156 | val |= g4x_infoframe_enable(frame); |
Paulo Zanoni | 60c5ea2 | 2012-05-04 17:18:22 -0300 | [diff] [blame] | 157 | val &= ~VIDEO_DIP_FREQ_MASK; |
Daniel Vetter | 4b24c93 | 2012-05-08 14:41:00 +0200 | [diff] [blame] | 158 | val |= VIDEO_DIP_FREQ_VSYNC; |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 159 | |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 160 | I915_WRITE(VIDEO_DIP_CTL, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 161 | POSTING_READ(VIDEO_DIP_CTL); |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 162 | } |
| 163 | |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 164 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
| 165 | struct dip_infoframe *frame) |
| 166 | { |
| 167 | uint32_t *data = (uint32_t *)frame; |
| 168 | struct drm_device *dev = encoder->dev; |
| 169 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 170 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 171 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 172 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
| 173 | u32 val = I915_READ(reg); |
| 174 | |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 175 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
| 176 | |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 177 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 178 | val |= g4x_infoframe_index(frame); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 179 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 180 | val &= ~g4x_infoframe_enable(frame); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 181 | |
| 182 | I915_WRITE(reg, val); |
| 183 | |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 184 | mmiowb(); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 185 | for (i = 0; i < len; i += 4) { |
| 186 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
| 187 | data++; |
| 188 | } |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 189 | mmiowb(); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 190 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 191 | val |= g4x_infoframe_enable(frame); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 192 | val &= ~VIDEO_DIP_FREQ_MASK; |
Daniel Vetter | 4b24c93 | 2012-05-08 14:41:00 +0200 | [diff] [blame] | 193 | val |= VIDEO_DIP_FREQ_VSYNC; |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 194 | |
| 195 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 196 | POSTING_READ(reg); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 197 | } |
| 198 | |
| 199 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
| 200 | struct dip_infoframe *frame) |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 201 | { |
| 202 | uint32_t *data = (uint32_t *)frame; |
| 203 | struct drm_device *dev = encoder->dev; |
| 204 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 205 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 206 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 207 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 208 | u32 val = I915_READ(reg); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 209 | |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 210 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
| 211 | |
Jesse Barnes | 64a8fc0 | 2011-09-22 11:16:00 +0530 | [diff] [blame] | 212 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 213 | val |= g4x_infoframe_index(frame); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 214 | |
Paulo Zanoni | ecb9785 | 2012-05-04 17:18:21 -0300 | [diff] [blame] | 215 | /* The DIP control register spec says that we need to update the AVI |
| 216 | * infoframe without clearing its enable bit */ |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 217 | if (frame->type != DIP_TYPE_AVI) |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 218 | val &= ~g4x_infoframe_enable(frame); |
Paulo Zanoni | ecb9785 | 2012-05-04 17:18:21 -0300 | [diff] [blame] | 219 | |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 220 | I915_WRITE(reg, val); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 221 | |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 222 | mmiowb(); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 223 | for (i = 0; i < len; i += 4) { |
| 224 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
| 225 | data++; |
| 226 | } |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 227 | mmiowb(); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 228 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 229 | val |= g4x_infoframe_enable(frame); |
Paulo Zanoni | 60c5ea2 | 2012-05-04 17:18:22 -0300 | [diff] [blame] | 230 | val &= ~VIDEO_DIP_FREQ_MASK; |
Daniel Vetter | 4b24c93 | 2012-05-08 14:41:00 +0200 | [diff] [blame] | 231 | val |= VIDEO_DIP_FREQ_VSYNC; |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 232 | |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 233 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 234 | POSTING_READ(reg); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 235 | } |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 236 | |
| 237 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
| 238 | struct dip_infoframe *frame) |
| 239 | { |
| 240 | uint32_t *data = (uint32_t *)frame; |
| 241 | struct drm_device *dev = encoder->dev; |
| 242 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 243 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 244 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 245 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 246 | u32 val = I915_READ(reg); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 247 | |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 248 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
| 249 | |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 250 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 251 | val |= g4x_infoframe_index(frame); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 252 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 253 | val &= ~g4x_infoframe_enable(frame); |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 254 | |
| 255 | I915_WRITE(reg, val); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 256 | |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 257 | mmiowb(); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 258 | for (i = 0; i < len; i += 4) { |
| 259 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
| 260 | data++; |
| 261 | } |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 262 | mmiowb(); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 263 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 264 | val |= g4x_infoframe_enable(frame); |
Paulo Zanoni | 60c5ea2 | 2012-05-04 17:18:22 -0300 | [diff] [blame] | 265 | val &= ~VIDEO_DIP_FREQ_MASK; |
Daniel Vetter | 4b24c93 | 2012-05-08 14:41:00 +0200 | [diff] [blame] | 266 | val |= VIDEO_DIP_FREQ_VSYNC; |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 267 | |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 268 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 269 | POSTING_READ(reg); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 270 | } |
| 271 | |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 272 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 273 | struct dip_infoframe *frame) |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 274 | { |
Paulo Zanoni | 2da8af5 | 2012-05-14 17:12:51 -0300 | [diff] [blame] | 275 | uint32_t *data = (uint32_t *)frame; |
| 276 | struct drm_device *dev = encoder->dev; |
| 277 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 278 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 279 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 280 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); |
| 281 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; |
| 282 | u32 val = I915_READ(ctl_reg); |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 283 | |
Paulo Zanoni | 2da8af5 | 2012-05-14 17:12:51 -0300 | [diff] [blame] | 284 | if (data_reg == 0) |
| 285 | return; |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 286 | |
Paulo Zanoni | 2da8af5 | 2012-05-14 17:12:51 -0300 | [diff] [blame] | 287 | val &= ~hsw_infoframe_enable(frame); |
| 288 | I915_WRITE(ctl_reg, val); |
| 289 | |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 290 | mmiowb(); |
Paulo Zanoni | 2da8af5 | 2012-05-14 17:12:51 -0300 | [diff] [blame] | 291 | for (i = 0; i < len; i += 4) { |
| 292 | I915_WRITE(data_reg + i, *data); |
| 293 | data++; |
| 294 | } |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 295 | mmiowb(); |
Paulo Zanoni | 2da8af5 | 2012-05-14 17:12:51 -0300 | [diff] [blame] | 296 | |
| 297 | val |= hsw_infoframe_enable(frame); |
| 298 | I915_WRITE(ctl_reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 299 | POSTING_READ(ctl_reg); |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 300 | } |
| 301 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 302 | static void intel_set_infoframe(struct drm_encoder *encoder, |
| 303 | struct dip_infoframe *frame) |
| 304 | { |
| 305 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 306 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 307 | intel_dip_infoframe_csum(frame); |
| 308 | intel_hdmi->write_infoframe(encoder, frame); |
| 309 | } |
| 310 | |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 311 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
Paulo Zanoni | c846b61 | 2012-04-13 16:31:41 -0300 | [diff] [blame] | 312 | struct drm_display_mode *adjusted_mode) |
Jesse Barnes | b055c8f | 2011-07-08 11:31:57 -0700 | [diff] [blame] | 313 | { |
| 314 | struct dip_infoframe avi_if = { |
| 315 | .type = DIP_TYPE_AVI, |
| 316 | .ver = DIP_VERSION_AVI, |
| 317 | .len = DIP_LEN_AVI, |
| 318 | }; |
Jesse Barnes | b055c8f | 2011-07-08 11:31:57 -0700 | [diff] [blame] | 319 | |
Paulo Zanoni | c846b61 | 2012-04-13 16:31:41 -0300 | [diff] [blame] | 320 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 321 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; |
| 322 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 323 | intel_set_infoframe(encoder, &avi_if); |
Jesse Barnes | b055c8f | 2011-07-08 11:31:57 -0700 | [diff] [blame] | 324 | } |
| 325 | |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 326 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
Jesse Barnes | c0864cb | 2011-08-03 09:22:56 -0700 | [diff] [blame] | 327 | { |
| 328 | struct dip_infoframe spd_if; |
| 329 | |
| 330 | memset(&spd_if, 0, sizeof(spd_if)); |
| 331 | spd_if.type = DIP_TYPE_SPD; |
| 332 | spd_if.ver = DIP_VERSION_SPD; |
| 333 | spd_if.len = DIP_LEN_SPD; |
| 334 | strcpy(spd_if.body.spd.vn, "Intel"); |
| 335 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); |
| 336 | spd_if.body.spd.sdi = DIP_SPD_PC; |
| 337 | |
| 338 | intel_set_infoframe(encoder, &spd_if); |
| 339 | } |
| 340 | |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 341 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
| 342 | struct drm_display_mode *adjusted_mode) |
| 343 | { |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 344 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 345 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 346 | u32 reg = VIDEO_DIP_CTL; |
| 347 | u32 val = I915_READ(reg); |
Paulo Zanoni | 72b78c9 | 2012-05-28 16:42:54 -0300 | [diff] [blame] | 348 | u32 port; |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 349 | |
Daniel Vetter | afba018 | 2012-06-12 16:36:45 +0200 | [diff] [blame] | 350 | assert_hdmi_port_disabled(intel_hdmi); |
| 351 | |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 352 | /* If the registers were not initialized yet, they might be zeroes, |
| 353 | * which means we're selecting the AVI DIP and we're setting its |
| 354 | * frequency to once. This seems to really confuse the HW and make |
| 355 | * things stop working (the register spec says the AVI always needs to |
| 356 | * be sent every VSync). So here we avoid writing to the register more |
| 357 | * than we need and also explicitly select the AVI DIP and explicitly |
| 358 | * set its frequency to every VSync. Avoiding to write it twice seems to |
| 359 | * be enough to solve the problem, but being defensive shouldn't hurt us |
| 360 | * either. */ |
| 361 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
| 362 | |
| 363 | if (!intel_hdmi->has_hdmi_sink) { |
| 364 | if (!(val & VIDEO_DIP_ENABLE)) |
| 365 | return; |
| 366 | val &= ~VIDEO_DIP_ENABLE; |
| 367 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 368 | POSTING_READ(reg); |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 369 | return; |
| 370 | } |
| 371 | |
Paulo Zanoni | f278d97 | 2012-05-28 16:42:50 -0300 | [diff] [blame] | 372 | switch (intel_hdmi->sdvox_reg) { |
| 373 | case SDVOB: |
Paulo Zanoni | 72b78c9 | 2012-05-28 16:42:54 -0300 | [diff] [blame] | 374 | port = VIDEO_DIP_PORT_B; |
Paulo Zanoni | f278d97 | 2012-05-28 16:42:50 -0300 | [diff] [blame] | 375 | break; |
| 376 | case SDVOC: |
Paulo Zanoni | 72b78c9 | 2012-05-28 16:42:54 -0300 | [diff] [blame] | 377 | port = VIDEO_DIP_PORT_C; |
Paulo Zanoni | f278d97 | 2012-05-28 16:42:50 -0300 | [diff] [blame] | 378 | break; |
| 379 | default: |
| 380 | return; |
| 381 | } |
| 382 | |
Paulo Zanoni | 72b78c9 | 2012-05-28 16:42:54 -0300 | [diff] [blame] | 383 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
| 384 | if (val & VIDEO_DIP_ENABLE) { |
| 385 | val &= ~VIDEO_DIP_ENABLE; |
| 386 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 387 | POSTING_READ(reg); |
Paulo Zanoni | 72b78c9 | 2012-05-28 16:42:54 -0300 | [diff] [blame] | 388 | } |
| 389 | val &= ~VIDEO_DIP_PORT_MASK; |
| 390 | val |= port; |
| 391 | } |
| 392 | |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 393 | val |= VIDEO_DIP_ENABLE; |
Paulo Zanoni | 0dd87d2 | 2012-05-28 16:42:53 -0300 | [diff] [blame] | 394 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 395 | |
Paulo Zanoni | f278d97 | 2012-05-28 16:42:50 -0300 | [diff] [blame] | 396 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 397 | POSTING_READ(reg); |
Paulo Zanoni | f278d97 | 2012-05-28 16:42:50 -0300 | [diff] [blame] | 398 | |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 399 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
| 400 | intel_hdmi_set_spd_infoframe(encoder); |
| 401 | } |
| 402 | |
| 403 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
| 404 | struct drm_display_mode *adjusted_mode) |
| 405 | { |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 406 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 407 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 408 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 409 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 410 | u32 val = I915_READ(reg); |
Paulo Zanoni | 72b78c9 | 2012-05-28 16:42:54 -0300 | [diff] [blame] | 411 | u32 port; |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 412 | |
Daniel Vetter | afba018 | 2012-06-12 16:36:45 +0200 | [diff] [blame] | 413 | assert_hdmi_port_disabled(intel_hdmi); |
| 414 | |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 415 | /* See the big comment in g4x_set_infoframes() */ |
| 416 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
| 417 | |
| 418 | if (!intel_hdmi->has_hdmi_sink) { |
| 419 | if (!(val & VIDEO_DIP_ENABLE)) |
| 420 | return; |
| 421 | val &= ~VIDEO_DIP_ENABLE; |
| 422 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 423 | POSTING_READ(reg); |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 424 | return; |
| 425 | } |
| 426 | |
Paulo Zanoni | f278d97 | 2012-05-28 16:42:50 -0300 | [diff] [blame] | 427 | switch (intel_hdmi->sdvox_reg) { |
| 428 | case HDMIB: |
Paulo Zanoni | 72b78c9 | 2012-05-28 16:42:54 -0300 | [diff] [blame] | 429 | port = VIDEO_DIP_PORT_B; |
Paulo Zanoni | f278d97 | 2012-05-28 16:42:50 -0300 | [diff] [blame] | 430 | break; |
| 431 | case HDMIC: |
Paulo Zanoni | 72b78c9 | 2012-05-28 16:42:54 -0300 | [diff] [blame] | 432 | port = VIDEO_DIP_PORT_C; |
Paulo Zanoni | f278d97 | 2012-05-28 16:42:50 -0300 | [diff] [blame] | 433 | break; |
| 434 | case HDMID: |
Paulo Zanoni | 72b78c9 | 2012-05-28 16:42:54 -0300 | [diff] [blame] | 435 | port = VIDEO_DIP_PORT_D; |
Paulo Zanoni | f278d97 | 2012-05-28 16:42:50 -0300 | [diff] [blame] | 436 | break; |
| 437 | default: |
| 438 | return; |
| 439 | } |
| 440 | |
Paulo Zanoni | 72b78c9 | 2012-05-28 16:42:54 -0300 | [diff] [blame] | 441 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
| 442 | if (val & VIDEO_DIP_ENABLE) { |
| 443 | val &= ~VIDEO_DIP_ENABLE; |
| 444 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 445 | POSTING_READ(reg); |
Paulo Zanoni | 72b78c9 | 2012-05-28 16:42:54 -0300 | [diff] [blame] | 446 | } |
| 447 | val &= ~VIDEO_DIP_PORT_MASK; |
| 448 | val |= port; |
| 449 | } |
| 450 | |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 451 | val |= VIDEO_DIP_ENABLE; |
Paulo Zanoni | 0dd87d2 | 2012-05-28 16:42:53 -0300 | [diff] [blame] | 452 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
| 453 | VIDEO_DIP_ENABLE_GCP); |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 454 | |
Paulo Zanoni | f278d97 | 2012-05-28 16:42:50 -0300 | [diff] [blame] | 455 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 456 | POSTING_READ(reg); |
Paulo Zanoni | f278d97 | 2012-05-28 16:42:50 -0300 | [diff] [blame] | 457 | |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 458 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
| 459 | intel_hdmi_set_spd_infoframe(encoder); |
| 460 | } |
| 461 | |
| 462 | static void cpt_set_infoframes(struct drm_encoder *encoder, |
| 463 | struct drm_display_mode *adjusted_mode) |
| 464 | { |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 465 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 466 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 467 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 468 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 469 | u32 val = I915_READ(reg); |
| 470 | |
Daniel Vetter | afba018 | 2012-06-12 16:36:45 +0200 | [diff] [blame] | 471 | assert_hdmi_port_disabled(intel_hdmi); |
| 472 | |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 473 | /* See the big comment in g4x_set_infoframes() */ |
| 474 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
| 475 | |
| 476 | if (!intel_hdmi->has_hdmi_sink) { |
| 477 | if (!(val & VIDEO_DIP_ENABLE)) |
| 478 | return; |
| 479 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); |
| 480 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 481 | POSTING_READ(reg); |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 482 | return; |
| 483 | } |
| 484 | |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 485 | /* Set both together, unset both together: see the spec. */ |
| 486 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; |
Paulo Zanoni | 0dd87d2 | 2012-05-28 16:42:53 -0300 | [diff] [blame] | 487 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
| 488 | VIDEO_DIP_ENABLE_GCP); |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 489 | |
| 490 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 491 | POSTING_READ(reg); |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 492 | |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 493 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
| 494 | intel_hdmi_set_spd_infoframe(encoder); |
| 495 | } |
| 496 | |
| 497 | static void vlv_set_infoframes(struct drm_encoder *encoder, |
| 498 | struct drm_display_mode *adjusted_mode) |
| 499 | { |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 500 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 501 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 502 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 503 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 504 | u32 val = I915_READ(reg); |
| 505 | |
Daniel Vetter | afba018 | 2012-06-12 16:36:45 +0200 | [diff] [blame] | 506 | assert_hdmi_port_disabled(intel_hdmi); |
| 507 | |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 508 | /* See the big comment in g4x_set_infoframes() */ |
| 509 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; |
| 510 | |
| 511 | if (!intel_hdmi->has_hdmi_sink) { |
| 512 | if (!(val & VIDEO_DIP_ENABLE)) |
| 513 | return; |
| 514 | val &= ~VIDEO_DIP_ENABLE; |
| 515 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 516 | POSTING_READ(reg); |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 517 | return; |
| 518 | } |
| 519 | |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 520 | val |= VIDEO_DIP_ENABLE; |
Paulo Zanoni | 0dd87d2 | 2012-05-28 16:42:53 -0300 | [diff] [blame] | 521 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
| 522 | VIDEO_DIP_ENABLE_GCP); |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 523 | |
| 524 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 525 | POSTING_READ(reg); |
Paulo Zanoni | 822974a | 2012-05-28 16:42:51 -0300 | [diff] [blame] | 526 | |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 527 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
| 528 | intel_hdmi_set_spd_infoframe(encoder); |
| 529 | } |
| 530 | |
| 531 | static void hsw_set_infoframes(struct drm_encoder *encoder, |
| 532 | struct drm_display_mode *adjusted_mode) |
| 533 | { |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 534 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 535 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 536 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 537 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); |
Paulo Zanoni | 0dd87d2 | 2012-05-28 16:42:53 -0300 | [diff] [blame] | 538 | u32 val = I915_READ(reg); |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 539 | |
Daniel Vetter | afba018 | 2012-06-12 16:36:45 +0200 | [diff] [blame] | 540 | assert_hdmi_port_disabled(intel_hdmi); |
| 541 | |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 542 | if (!intel_hdmi->has_hdmi_sink) { |
| 543 | I915_WRITE(reg, 0); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 544 | POSTING_READ(reg); |
Paulo Zanoni | 0c14c7f | 2012-05-28 16:42:49 -0300 | [diff] [blame] | 545 | return; |
| 546 | } |
| 547 | |
Paulo Zanoni | 0dd87d2 | 2012-05-28 16:42:53 -0300 | [diff] [blame] | 548 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
| 549 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); |
| 550 | |
| 551 | I915_WRITE(reg, val); |
Paulo Zanoni | 9d9740f | 2012-05-28 16:43:00 -0300 | [diff] [blame] | 552 | POSTING_READ(reg); |
Paulo Zanoni | 0dd87d2 | 2012-05-28 16:42:53 -0300 | [diff] [blame] | 553 | |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 554 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
| 555 | intel_hdmi_set_spd_infoframe(encoder); |
| 556 | } |
| 557 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 558 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
| 559 | struct drm_display_mode *mode, |
| 560 | struct drm_display_mode *adjusted_mode) |
| 561 | { |
| 562 | struct drm_device *dev = encoder->dev; |
| 563 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 564 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 565 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 566 | u32 sdvox; |
| 567 | |
Paulo Zanoni | b659c3d | 2012-05-28 16:42:56 -0300 | [diff] [blame] | 568 | sdvox = SDVO_ENCODING_HDMI; |
Jesse Barnes | 5d4fac9 | 2011-06-24 12:19:19 -0700 | [diff] [blame] | 569 | if (!HAS_PCH_SPLIT(dev)) |
| 570 | sdvox |= intel_hdmi->color_range; |
Adam Jackson | b599c0b | 2010-07-16 14:46:31 -0400 | [diff] [blame] | 571 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 572 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
| 573 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 574 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 575 | |
Jesse Barnes | 020f670 | 2011-06-24 12:19:25 -0700 | [diff] [blame] | 576 | if (intel_crtc->bpp > 24) |
| 577 | sdvox |= COLOR_FORMAT_12bpc; |
| 578 | else |
| 579 | sdvox |= COLOR_FORMAT_8bpc; |
| 580 | |
Zhenyu Wang | 2e3d600 | 2010-09-10 10:39:40 +0800 | [diff] [blame] | 581 | /* Required on CPT */ |
| 582 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) |
| 583 | sdvox |= HDMI_MODE_SELECT; |
| 584 | |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 585 | if (intel_hdmi->has_audio) { |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 586 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
| 587 | pipe_name(intel_crtc->pipe)); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 588 | sdvox |= SDVO_AUDIO_ENABLE; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 589 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 590 | intel_write_eld(encoder, adjusted_mode); |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 591 | } |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 592 | |
Jesse Barnes | 7577056 | 2011-10-12 09:01:58 -0700 | [diff] [blame] | 593 | if (HAS_PCH_CPT(dev)) |
| 594 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
Daniel Vetter | 7a87c28 | 2012-06-05 11:03:39 +0200 | [diff] [blame] | 595 | else if (intel_crtc->pipe == PIPE_B) |
Jesse Barnes | 7577056 | 2011-10-12 09:01:58 -0700 | [diff] [blame] | 596 | sdvox |= SDVO_PIPE_B_SELECT; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 597 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 598 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
| 599 | POSTING_READ(intel_hdmi->sdvox_reg); |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 600 | |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 601 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 602 | } |
| 603 | |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 604 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
| 605 | enum pipe *pipe) |
| 606 | { |
| 607 | struct drm_device *dev = encoder->base.dev; |
| 608 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 609 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
| 610 | u32 tmp; |
| 611 | |
| 612 | tmp = I915_READ(intel_hdmi->sdvox_reg); |
| 613 | |
| 614 | if (!(tmp & SDVO_ENABLE)) |
| 615 | return false; |
| 616 | |
| 617 | if (HAS_PCH_CPT(dev)) |
| 618 | *pipe = PORT_TO_PIPE_CPT(tmp); |
| 619 | else |
| 620 | *pipe = PORT_TO_PIPE(tmp); |
| 621 | |
| 622 | return true; |
| 623 | } |
| 624 | |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 625 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 626 | { |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 627 | struct drm_device *dev = encoder->base.dev; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 628 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 629 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 630 | u32 temp; |
Wu Fengguang | 2deed76 | 2011-12-09 20:42:20 +0800 | [diff] [blame] | 631 | u32 enable_bits = SDVO_ENABLE; |
| 632 | |
| 633 | if (intel_hdmi->has_audio) |
| 634 | enable_bits |= SDVO_AUDIO_ENABLE; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 635 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 636 | temp = I915_READ(intel_hdmi->sdvox_reg); |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 637 | |
Daniel Vetter | 7a87c28 | 2012-06-05 11:03:39 +0200 | [diff] [blame] | 638 | /* HW workaround for IBX, we need to move the port to transcoder A |
| 639 | * before disabling it. */ |
| 640 | if (HAS_PCH_IBX(dev)) { |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 641 | struct drm_crtc *crtc = encoder->base.crtc; |
Daniel Vetter | 7a87c28 | 2012-06-05 11:03:39 +0200 | [diff] [blame] | 642 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
| 643 | |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 644 | /* Restore the transcoder select bit. */ |
| 645 | if (pipe == PIPE_B) |
| 646 | enable_bits |= SDVO_PIPE_B_SELECT; |
| 647 | } |
Daniel Vetter | 7a87c28 | 2012-06-05 11:03:39 +0200 | [diff] [blame] | 648 | |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 649 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
| 650 | * we do this anyway which shows more stable in testing. |
| 651 | */ |
| 652 | if (HAS_PCH_SPLIT(dev)) { |
| 653 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
| 654 | POSTING_READ(intel_hdmi->sdvox_reg); |
| 655 | } |
Daniel Vetter | 7a87c28 | 2012-06-05 11:03:39 +0200 | [diff] [blame] | 656 | |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 657 | temp |= enable_bits; |
| 658 | |
| 659 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
| 660 | POSTING_READ(intel_hdmi->sdvox_reg); |
| 661 | |
| 662 | /* HW workaround, need to write this twice for issue that may result |
| 663 | * in first write getting masked. |
| 664 | */ |
| 665 | if (HAS_PCH_SPLIT(dev)) { |
| 666 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
| 667 | POSTING_READ(intel_hdmi->sdvox_reg); |
| 668 | } |
| 669 | } |
| 670 | |
| 671 | static void intel_disable_hdmi(struct intel_encoder *encoder) |
| 672 | { |
| 673 | struct drm_device *dev = encoder->base.dev; |
| 674 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 675 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
| 676 | u32 temp; |
| 677 | u32 enable_bits = SDVO_ENABLE; |
| 678 | |
| 679 | if (intel_hdmi->has_audio) |
| 680 | enable_bits |= SDVO_AUDIO_ENABLE; |
| 681 | |
| 682 | temp = I915_READ(intel_hdmi->sdvox_reg); |
| 683 | |
| 684 | /* HW workaround for IBX, we need to move the port to transcoder A |
| 685 | * before disabling it. */ |
| 686 | if (HAS_PCH_IBX(dev)) { |
| 687 | struct drm_crtc *crtc = encoder->base.crtc; |
| 688 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
| 689 | |
| 690 | if (temp & SDVO_PIPE_B_SELECT) { |
| 691 | temp &= ~SDVO_PIPE_B_SELECT; |
| 692 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
| 693 | POSTING_READ(intel_hdmi->sdvox_reg); |
| 694 | |
| 695 | /* Again we need to write this twice. */ |
| 696 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
| 697 | POSTING_READ(intel_hdmi->sdvox_reg); |
| 698 | |
| 699 | /* Transcoder selection bits only update |
| 700 | * effectively on vblank. */ |
| 701 | if (crtc) |
| 702 | intel_wait_for_vblank(dev, pipe); |
| 703 | else |
| 704 | msleep(50); |
Daniel Vetter | 7a87c28 | 2012-06-05 11:03:39 +0200 | [diff] [blame] | 705 | } |
| 706 | } |
| 707 | |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 708 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
| 709 | * we do this anyway which shows more stable in testing. |
| 710 | */ |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 711 | if (HAS_PCH_SPLIT(dev)) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 712 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
| 713 | POSTING_READ(intel_hdmi->sdvox_reg); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 714 | } |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 715 | |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 716 | temp &= ~enable_bits; |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 717 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 718 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
| 719 | POSTING_READ(intel_hdmi->sdvox_reg); |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 720 | |
| 721 | /* HW workaround, need to write this twice for issue that may result |
| 722 | * in first write getting masked. |
| 723 | */ |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 724 | if (HAS_PCH_SPLIT(dev)) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 725 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
| 726 | POSTING_READ(intel_hdmi->sdvox_reg); |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 727 | } |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 728 | } |
| 729 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 730 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
| 731 | struct drm_display_mode *mode) |
| 732 | { |
| 733 | if (mode->clock > 165000) |
| 734 | return MODE_CLOCK_HIGH; |
| 735 | if (mode->clock < 20000) |
Nicolas Kaiser | 5cbba41 | 2011-05-30 12:48:26 +0200 | [diff] [blame] | 736 | return MODE_CLOCK_LOW; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 737 | |
| 738 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 739 | return MODE_NO_DBLESCAN; |
| 740 | |
| 741 | return MODE_OK; |
| 742 | } |
| 743 | |
| 744 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 745 | const struct drm_display_mode *mode, |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 746 | struct drm_display_mode *adjusted_mode) |
| 747 | { |
| 748 | return true; |
| 749 | } |
| 750 | |
Chris Wilson | 8ec22b2 | 2012-05-11 18:01:34 +0100 | [diff] [blame] | 751 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) |
| 752 | { |
| 753 | struct drm_device *dev = intel_hdmi->base.base.dev; |
| 754 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 755 | uint32_t bit; |
| 756 | |
| 757 | switch (intel_hdmi->sdvox_reg) { |
Chris Wilson | eeafaac | 2012-05-25 10:23:37 +0100 | [diff] [blame] | 758 | case SDVOB: |
Chris Wilson | 8ec22b2 | 2012-05-11 18:01:34 +0100 | [diff] [blame] | 759 | bit = HDMIB_HOTPLUG_LIVE_STATUS; |
| 760 | break; |
Chris Wilson | eeafaac | 2012-05-25 10:23:37 +0100 | [diff] [blame] | 761 | case SDVOC: |
Chris Wilson | 8ec22b2 | 2012-05-11 18:01:34 +0100 | [diff] [blame] | 762 | bit = HDMIC_HOTPLUG_LIVE_STATUS; |
| 763 | break; |
Chris Wilson | 8ec22b2 | 2012-05-11 18:01:34 +0100 | [diff] [blame] | 764 | default: |
| 765 | bit = 0; |
| 766 | break; |
| 767 | } |
| 768 | |
| 769 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
| 770 | } |
| 771 | |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 772 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 773 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 774 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 775 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 776 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 777 | struct edid *edid; |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 778 | enum drm_connector_status status = connector_status_disconnected; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 779 | |
Chris Wilson | 8ec22b2 | 2012-05-11 18:01:34 +0100 | [diff] [blame] | 780 | if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi)) |
| 781 | return status; |
| 782 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 783 | intel_hdmi->has_hdmi_sink = false; |
Zhenyu Wang | 2e3d600 | 2010-09-10 10:39:40 +0800 | [diff] [blame] | 784 | intel_hdmi->has_audio = false; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 785 | edid = drm_get_edid(connector, |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 786 | intel_gmbus_get_adapter(dev_priv, |
| 787 | intel_hdmi->ddc_bus)); |
ling.ma@intel.com | 2ded9e2 | 2009-07-16 17:23:09 +0800 | [diff] [blame] | 788 | |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 789 | if (edid) { |
Eric Anholt | be9f1c4 | 2009-06-21 22:14:55 -0700 | [diff] [blame] | 790 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 791 | status = connector_status_connected; |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 792 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
| 793 | intel_hdmi->has_hdmi_sink = |
| 794 | drm_detect_hdmi_monitor(edid); |
Zhenyu Wang | 2e3d600 | 2010-09-10 10:39:40 +0800 | [diff] [blame] | 795 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 796 | } |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 797 | connector->display_info.raw_edid = NULL; |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 798 | kfree(edid); |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 799 | } |
ling.ma@intel.com | 2ded9e2 | 2009-07-16 17:23:09 +0800 | [diff] [blame] | 800 | |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 801 | if (status == connector_status_connected) { |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 802 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
| 803 | intel_hdmi->has_audio = |
| 804 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 805 | } |
| 806 | |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 807 | return status; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 808 | } |
| 809 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 810 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
| 811 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 812 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 813 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 814 | |
| 815 | /* We should parse the EDID data and find out if it's an HDMI sink so |
| 816 | * we can send audio to it. |
| 817 | */ |
| 818 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 819 | return intel_ddc_get_modes(connector, |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 820 | intel_gmbus_get_adapter(dev_priv, |
| 821 | intel_hdmi->ddc_bus)); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 822 | } |
| 823 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 824 | static bool |
| 825 | intel_hdmi_detect_audio(struct drm_connector *connector) |
| 826 | { |
| 827 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
| 828 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 829 | struct edid *edid; |
| 830 | bool has_audio = false; |
| 831 | |
| 832 | edid = drm_get_edid(connector, |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 833 | intel_gmbus_get_adapter(dev_priv, |
| 834 | intel_hdmi->ddc_bus)); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 835 | if (edid) { |
| 836 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
| 837 | has_audio = drm_detect_monitor_audio(edid); |
| 838 | |
| 839 | connector->display_info.raw_edid = NULL; |
| 840 | kfree(edid); |
| 841 | } |
| 842 | |
| 843 | return has_audio; |
| 844 | } |
| 845 | |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 846 | static int |
| 847 | intel_hdmi_set_property(struct drm_connector *connector, |
Paulo Zanoni | ed517fb | 2012-05-14 17:12:50 -0300 | [diff] [blame] | 848 | struct drm_property *property, |
| 849 | uint64_t val) |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 850 | { |
| 851 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 852 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 853 | int ret; |
| 854 | |
| 855 | ret = drm_connector_property_set_value(connector, property, val); |
| 856 | if (ret) |
| 857 | return ret; |
| 858 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 859 | if (property == dev_priv->force_audio_property) { |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 860 | enum hdmi_force_audio i = val; |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 861 | bool has_audio; |
| 862 | |
| 863 | if (i == intel_hdmi->force_audio) |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 864 | return 0; |
| 865 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 866 | intel_hdmi->force_audio = i; |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 867 | |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 868 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 869 | has_audio = intel_hdmi_detect_audio(connector); |
| 870 | else |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 871 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 872 | |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 873 | if (i == HDMI_AUDIO_OFF_DVI) |
| 874 | intel_hdmi->has_hdmi_sink = 0; |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 875 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 876 | intel_hdmi->has_audio = has_audio; |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 877 | goto done; |
| 878 | } |
| 879 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 880 | if (property == dev_priv->broadcast_rgb_property) { |
| 881 | if (val == !!intel_hdmi->color_range) |
| 882 | return 0; |
| 883 | |
| 884 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; |
| 885 | goto done; |
| 886 | } |
| 887 | |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 888 | return -EINVAL; |
| 889 | |
| 890 | done: |
| 891 | if (intel_hdmi->base.base.crtc) { |
| 892 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 893 | intel_set_mode(crtc, &crtc->mode, |
| 894 | crtc->x, crtc->y, crtc->fb); |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 895 | } |
| 896 | |
| 897 | return 0; |
| 898 | } |
| 899 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 900 | static void intel_hdmi_destroy(struct drm_connector *connector) |
| 901 | { |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 902 | drm_sysfs_connector_remove(connector); |
| 903 | drm_connector_cleanup(connector); |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 904 | kfree(connector); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 905 | } |
| 906 | |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 907 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = { |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 908 | .mode_fixup = intel_hdmi_mode_fixup, |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 909 | .mode_set = intel_ddi_mode_set, |
Daniel Vetter | 1f70385 | 2012-07-11 16:51:39 +0200 | [diff] [blame^] | 910 | .disable = intel_encoder_noop, |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 911 | }; |
| 912 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 913 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 914 | .mode_fixup = intel_hdmi_mode_fixup, |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 915 | .mode_set = intel_hdmi_mode_set, |
Daniel Vetter | 1f70385 | 2012-07-11 16:51:39 +0200 | [diff] [blame^] | 916 | .disable = intel_encoder_noop, |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 917 | }; |
| 918 | |
| 919 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 920 | .dpms = intel_connector_dpms, |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 921 | .detect = intel_hdmi_detect, |
| 922 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 923 | .set_property = intel_hdmi_set_property, |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 924 | .destroy = intel_hdmi_destroy, |
| 925 | }; |
| 926 | |
| 927 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { |
| 928 | .get_modes = intel_hdmi_get_modes, |
| 929 | .mode_valid = intel_hdmi_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 930 | .best_encoder = intel_best_encoder, |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 931 | }; |
| 932 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 933 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 934 | .destroy = intel_encoder_destroy, |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 935 | }; |
| 936 | |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 937 | static void |
| 938 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) |
| 939 | { |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 940 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 941 | intel_attach_broadcast_rgb_property(connector); |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 942 | } |
| 943 | |
Daniel Vetter | 08d644a | 2012-07-12 20:19:59 +0200 | [diff] [blame] | 944 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 945 | { |
| 946 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 947 | struct drm_connector *connector; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 948 | struct intel_encoder *intel_encoder; |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 949 | struct intel_connector *intel_connector; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 950 | struct intel_hdmi *intel_hdmi; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 951 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 952 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
| 953 | if (!intel_hdmi) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 954 | return; |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 955 | |
| 956 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
| 957 | if (!intel_connector) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 958 | kfree(intel_hdmi); |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 959 | return; |
| 960 | } |
| 961 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 962 | intel_encoder = &intel_hdmi->base; |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 963 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
| 964 | DRM_MODE_ENCODER_TMDS); |
| 965 | |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 966 | connector = &intel_connector->base; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 967 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
Adam Jackson | 8d91104 | 2009-09-23 15:08:29 -0400 | [diff] [blame] | 968 | DRM_MODE_CONNECTOR_HDMIA); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 969 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
| 970 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 971 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 972 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 973 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
Peter Ross | c3febcc | 2012-01-28 14:49:26 +0100 | [diff] [blame] | 974 | connector->interlace_allowed = 1; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 975 | connector->doublescan_allowed = 0; |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 976 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 977 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 978 | intel_encoder->cloneable = false; |
| 979 | |
Daniel Vetter | 08d644a | 2012-07-12 20:19:59 +0200 | [diff] [blame] | 980 | intel_hdmi->ddi_port = port; |
| 981 | switch (port) { |
| 982 | case PORT_B: |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 983 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 984 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
Daniel Vetter | 08d644a | 2012-07-12 20:19:59 +0200 | [diff] [blame] | 985 | break; |
| 986 | case PORT_C: |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 987 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 988 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
Daniel Vetter | 08d644a | 2012-07-12 20:19:59 +0200 | [diff] [blame] | 989 | break; |
| 990 | case PORT_D: |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 991 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 992 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
Daniel Vetter | 08d644a | 2012-07-12 20:19:59 +0200 | [diff] [blame] | 993 | break; |
| 994 | case PORT_A: |
| 995 | /* Internal port only for eDP. */ |
| 996 | default: |
Eugeni Dodonov | 6e4c167 | 2012-05-09 15:37:13 -0300 | [diff] [blame] | 997 | BUG(); |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 998 | } |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 999 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1000 | intel_hdmi->sdvox_reg = sdvox_reg; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1001 | |
Jesse Barnes | 64a8fc0 | 2011-09-22 11:16:00 +0530 | [diff] [blame] | 1002 | if (!HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | a3da1df | 2012-05-08 15:19:06 +0200 | [diff] [blame] | 1003 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 1004 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 1005 | } else if (IS_VALLEYVIEW(dev)) { |
| 1006 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 1007 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 1008 | } else if (IS_HASWELL(dev)) { |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 1009 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 1010 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 1011 | } else if (HAS_PCH_IBX(dev)) { |
| 1012 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 1013 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 1014 | } else { |
| 1015 | intel_hdmi->write_infoframe = cpt_write_infoframe; |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 1016 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
Jesse Barnes | 64a8fc0 | 2011-09-22 11:16:00 +0530 | [diff] [blame] | 1017 | } |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 1018 | |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 1019 | if (IS_HASWELL(dev)) { |
| 1020 | intel_encoder->enable = intel_enable_ddi; |
| 1021 | intel_encoder->disable = intel_disable_ddi; |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1022 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 1023 | drm_encoder_helper_add(&intel_encoder->base, |
| 1024 | &intel_hdmi_helper_funcs_hsw); |
| 1025 | } else { |
| 1026 | intel_encoder->enable = intel_enable_hdmi; |
| 1027 | intel_encoder->disable = intel_disable_hdmi; |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1028 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 1029 | drm_encoder_helper_add(&intel_encoder->base, |
| 1030 | &intel_hdmi_helper_funcs); |
| 1031 | } |
Daniel Vetter | 85234cd | 2012-07-02 13:27:29 +0200 | [diff] [blame] | 1032 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 1033 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1034 | |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1035 | intel_hdmi_add_properties(intel_hdmi, connector); |
| 1036 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1037 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1038 | drm_sysfs_connector_add(connector); |
| 1039 | |
| 1040 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 1041 | * 0xd. Failure to do so will result in spurious interrupts being |
| 1042 | * generated on the port when a cable is not attached. |
| 1043 | */ |
| 1044 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 1045 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 1046 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 1047 | } |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1048 | } |