blob: 566587d0a5003726dc75e5fe7ea67ad639581c54 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef CCISS_H
2#define CCISS_H
3
4#include <linux/genhd.h>
5
6#include "cciss_cmd.h"
7
8
9#define NWD 16
10#define NWD_SHIFT 4
11#define MAX_PART (1 << NWD_SHIFT)
12
13#define IO_OK 0
14#define IO_ERROR 1
15
16#define MAJOR_NR COMPAQ_CISS_MAJOR
17
18struct ctlr_info;
19typedef struct ctlr_info ctlr_info_t;
20
21struct access_method {
22 void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
23 void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
24 unsigned long (*fifo_full)(ctlr_info_t *h);
25 unsigned long (*intr_pending)(ctlr_info_t *h);
26 unsigned long (*command_completed)(ctlr_info_t *h);
27};
28typedef struct _drive_info_struct
29{
30 __u32 LunID;
31 int usage_count;
Mike Millerad2b9312005-07-28 01:07:31 -070032 struct request_queue *queue;
Linus Torvalds1da177e2005-04-16 15:20:36 -070033 sector_t nr_blocks;
34 int block_size;
35 int heads;
36 int sectors;
37 int cylinders;
38 int raid_level;
39} drive_info_struct;
40
41struct ctlr_info
42{
43 int ctlr;
44 char devname[8];
45 char *product_name;
46 char firm_ver[4]; // Firmware version
47 struct pci_dev *pdev;
48 __u32 board_id;
49 void __iomem *vaddr;
50 unsigned long paddr;
51 unsigned long io_mem_addr;
52 unsigned long io_mem_length;
53 CfgTable_struct __iomem *cfgtable;
54 unsigned int intr;
55 int interrupts_enabled;
56 int major;
57 int max_commands;
58 int commands_outstanding;
59 int max_outstanding; /* Debug */
60 int num_luns;
61 int highest_lun;
62 int usage_count; /* number of opens all all minor devices */
63
64 // information about each logical volume
65 drive_info_struct drv[CISS_MAX_LUN];
66
67 struct access_method access;
68
69 /* queue and queue Info */
70 CommandList_struct *reqQ;
71 CommandList_struct *cmpQ;
72 unsigned int Qdepth;
73 unsigned int maxQsinceinit;
74 unsigned int maxSG;
75 spinlock_t lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -070076
77 //* pointers to command and error info pool */
78 CommandList_struct *cmd_pool;
79 dma_addr_t cmd_pool_dhandle;
80 ErrorInfo_struct *errinfo_pool;
81 dma_addr_t errinfo_pool_dhandle;
82 unsigned long *cmd_pool_bits;
83 int nr_allocs;
84 int nr_frees;
85 int busy_configuring;
86
87 /* This element holds the zero based queue number of the last
88 * queue to be started. It is used for fairness.
89 */
90 int next_to_run;
91
92 // Disk structures we need to pass back
93 struct gendisk *gendisk[NWD];
94#ifdef CONFIG_CISS_SCSI_TAPE
95 void *scsi_ctlr; /* ptr to structure containing scsi related stuff */
96#endif
97};
98
99/* Defining the diffent access_menthods */
100/*
101 * Memory mapped FIFO interface (SMART 53xx cards)
102 */
103#define SA5_DOORBELL 0x20
104#define SA5_REQUEST_PORT_OFFSET 0x40
105#define SA5_REPLY_INTR_MASK_OFFSET 0x34
106#define SA5_REPLY_PORT_OFFSET 0x44
107#define SA5_INTR_STATUS 0x30
108#define SA5_SCRATCHPAD_OFFSET 0xB0
109
110#define SA5_CTCFG_OFFSET 0xB4
111#define SA5_CTMEM_OFFSET 0xB8
112
113#define SA5_INTR_OFF 0x08
114#define SA5B_INTR_OFF 0x04
115#define SA5_INTR_PENDING 0x08
116#define SA5B_INTR_PENDING 0x04
117#define FIFO_EMPTY 0xffffffff
118#define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
119
120#define CISS_ERROR_BIT 0x02
121
122#define CCISS_INTR_ON 1
123#define CCISS_INTR_OFF 0
124/*
125 Send the command to the hardware
126*/
127static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
128{
129#ifdef CCISS_DEBUG
130 printk("Sending %x - down to controller\n", c->busaddr );
131#endif /* CCISS_DEBUG */
132 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
133 h->commands_outstanding++;
134 if ( h->commands_outstanding > h->max_outstanding)
135 h->max_outstanding = h->commands_outstanding;
136}
137
138/*
139 * This card is the opposite of the other cards.
140 * 0 turns interrupts on...
141 * 0x08 turns them off...
142 */
143static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
144{
145 if (val)
146 { /* Turn interrupts on */
147 h->interrupts_enabled = 1;
148 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
149 } else /* Turn them off */
150 {
151 h->interrupts_enabled = 0;
152 writel( SA5_INTR_OFF,
153 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
154 }
155}
156/*
157 * This card is the opposite of the other cards.
158 * 0 turns interrupts on...
159 * 0x04 turns them off...
160 */
161static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
162{
163 if (val)
164 { /* Turn interrupts on */
165 h->interrupts_enabled = 1;
166 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
167 } else /* Turn them off */
168 {
169 h->interrupts_enabled = 0;
170 writel( SA5B_INTR_OFF,
171 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
172 }
173}
174/*
175 * Returns true if fifo is full.
176 *
177 */
178static unsigned long SA5_fifo_full(ctlr_info_t *h)
179{
180 if( h->commands_outstanding >= h->max_commands)
181 return(1);
182 else
183 return(0);
184
185}
186/*
187 * returns value read from hardware.
188 * returns FIFO_EMPTY if there is nothing to read
189 */
190static unsigned long SA5_completed(ctlr_info_t *h)
191{
192 unsigned long register_value
193 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
194 if(register_value != FIFO_EMPTY)
195 {
196 h->commands_outstanding--;
197#ifdef CCISS_DEBUG
198 printk("cciss: Read %lx back from board\n", register_value);
199#endif /* CCISS_DEBUG */
200 }
201#ifdef CCISS_DEBUG
202 else
203 {
204 printk("cciss: FIFO Empty read\n");
205 }
206#endif
207 return ( register_value);
208
209}
210/*
211 * Returns true if an interrupt is pending..
212 */
213static unsigned long SA5_intr_pending(ctlr_info_t *h)
214{
215 unsigned long register_value =
216 readl(h->vaddr + SA5_INTR_STATUS);
217#ifdef CCISS_DEBUG
218 printk("cciss: intr_pending %lx\n", register_value);
219#endif /* CCISS_DEBUG */
220 if( register_value & SA5_INTR_PENDING)
221 return 1;
222 return 0 ;
223}
224
225/*
226 * Returns true if an interrupt is pending..
227 */
228static unsigned long SA5B_intr_pending(ctlr_info_t *h)
229{
230 unsigned long register_value =
231 readl(h->vaddr + SA5_INTR_STATUS);
232#ifdef CCISS_DEBUG
233 printk("cciss: intr_pending %lx\n", register_value);
234#endif /* CCISS_DEBUG */
235 if( register_value & SA5B_INTR_PENDING)
236 return 1;
237 return 0 ;
238}
239
240
241static struct access_method SA5_access = {
242 SA5_submit_command,
243 SA5_intr_mask,
244 SA5_fifo_full,
245 SA5_intr_pending,
246 SA5_completed,
247};
248
249static struct access_method SA5B_access = {
250 SA5_submit_command,
251 SA5B_intr_mask,
252 SA5_fifo_full,
253 SA5B_intr_pending,
254 SA5_completed,
255};
256
257struct board_type {
258 __u32 board_id;
259 char *product_name;
260 struct access_method *access;
261};
262
Mike Millerad2b9312005-07-28 01:07:31 -0700263#define CCISS_LOCK(i) (&hba[i]->lock)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264
265#endif /* CCISS_H */
266