blob: 91e7b0c3fce790fb28904c03dfd602e14202e075 [file] [log] [blame]
Sagar Dharia7c927c02016-11-23 11:51:43 -07001/*
2 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/i2c.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/module.h>
22#include <linux/of.h>
Karthikeyan Ramasubramanian0d578b72017-04-26 10:44:02 -060023#include <linux/of_platform.h>
Sagar Dharia7c927c02016-11-23 11:51:43 -070024#include <linux/platform_device.h>
Sagar Dhariab44003b2017-03-10 15:34:26 -070025#include <linux/pm_runtime.h>
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -060026#include <linux/dma-mapping.h>
Sagar Dharia7c927c02016-11-23 11:51:43 -070027#include <linux/qcom-geni-se.h>
Sagar Dharia818623c2017-04-27 13:13:29 -060028#include <linux/ipc_logging.h>
Sagar Dharia673a4502017-04-14 14:20:21 -060029#include <linux/dmaengine.h>
30#include <linux/msm_gpi.h>
Sagar Dharia7c927c02016-11-23 11:51:43 -070031
32#define SE_I2C_TX_TRANS_LEN (0x26C)
33#define SE_I2C_RX_TRANS_LEN (0x270)
34#define SE_I2C_SCL_COUNTERS (0x278)
Sagar Dharia818623c2017-04-27 13:13:29 -060035#define SE_GENI_IOS (0x908)
Sagar Dharia7c927c02016-11-23 11:51:43 -070036
37#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
38 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
39#define SE_I2C_ABORT (1U << 1)
40/* M_CMD OP codes for I2C */
41#define I2C_WRITE (0x1)
42#define I2C_READ (0x2)
43#define I2C_WRITE_READ (0x3)
44#define I2C_ADDR_ONLY (0x4)
45#define I2C_BUS_CLEAR (0x6)
46#define I2C_STOP_ON_BUS (0x7)
47/* M_CMD params for I2C */
48#define PRE_CMD_DELAY (BIT(0))
49#define TIMESTAMP_BEFORE (BIT(1))
50#define STOP_STRETCH (BIT(2))
51#define TIMESTAMP_AFTER (BIT(3))
52#define POST_COMMAND_DELAY (BIT(4))
53#define IGNORE_ADD_NACK (BIT(6))
54#define READ_FINISHED_WITH_ACK (BIT(7))
55#define BYPASS_ADDR_PHASE (BIT(8))
56#define SLV_ADDR_MSK (GENMASK(15, 9))
57#define SLV_ADDR_SHFT (9)
58
Sagar Dharia673a4502017-04-14 14:20:21 -060059#define I2C_PACK_EN (BIT(0) | BIT(1))
Karthikeyan Ramasubramanian0d578b72017-04-26 10:44:02 -060060#define I2C_CORE2X_VOTE (10000)
Sagar Dharia818623c2017-04-27 13:13:29 -060061#define GP_IRQ0 0
62#define GP_IRQ1 1
63#define GP_IRQ2 2
64#define GP_IRQ3 3
65#define GP_IRQ4 4
66#define GP_IRQ5 5
67#define GENI_OVERRUN 6
68#define GENI_ILLEGAL_CMD 7
69#define GENI_ABORT_DONE 8
70#define GENI_TIMEOUT 9
71
72#define I2C_NACK GP_IRQ1
73#define I2C_BUS_PROTO GP_IRQ3
74#define I2C_ARB_LOST GP_IRQ4
75#define DM_I2C_RX_ERR ((GP_IRQ1 | GP_IRQ3 | GP_IRQ4) >> 4)
Karthikeyan Ramasubramanian0d578b72017-04-26 10:44:02 -060076
Sagar Dharia673a4502017-04-14 14:20:21 -060077enum i2c_se_mode {
78 UNINITIALIZED,
79 FIFO_SE_DMA,
80 GSI_ONLY,
81};
82
Sagar Dharia7c927c02016-11-23 11:51:43 -070083struct geni_i2c_dev {
84 struct device *dev;
85 void __iomem *base;
Karthikeyan Ramasubramanian0d578b72017-04-26 10:44:02 -060086 unsigned int tx_wm;
Sagar Dharia7c927c02016-11-23 11:51:43 -070087 int irq;
88 int err;
89 struct i2c_adapter adap;
90 struct completion xfer;
91 struct i2c_msg *cur;
Sagar Dhariab44003b2017-03-10 15:34:26 -070092 struct se_geni_rsc i2c_rsc;
Sagar Dharia7c927c02016-11-23 11:51:43 -070093 int cur_wr;
94 int cur_rd;
Karthikeyan Ramasubramanian0d578b72017-04-26 10:44:02 -060095 struct device *wrapper_dev;
Sagar Dharia818623c2017-04-27 13:13:29 -060096 void *ipcl;
Shrey Vijay6f231202017-07-11 11:16:16 +053097 int clk_fld_idx;
Sagar Dharia673a4502017-04-14 14:20:21 -060098 struct dma_chan *tx_c;
99 struct dma_chan *rx_c;
100 struct msm_gpi_tre cfg0_t;
101 struct msm_gpi_tre go_t;
102 struct msm_gpi_tre tx_t;
103 struct msm_gpi_tre rx_t;
104 dma_addr_t tx_ph;
105 dma_addr_t rx_ph;
106 struct msm_gpi_ctrl tx_ev;
107 struct msm_gpi_ctrl rx_ev;
108 struct scatterlist tx_sg[5]; /* lock, cfg0, go, TX, unlock */
109 struct scatterlist rx_sg;
110 int cfg_sent;
111 struct dma_async_tx_descriptor *tx_desc;
112 struct dma_async_tx_descriptor *rx_desc;
113 struct msm_gpi_dma_async_tx_cb_param tx_cb;
114 struct msm_gpi_dma_async_tx_cb_param rx_cb;
115 enum i2c_se_mode se_mode;
Sagar Dharia818623c2017-04-27 13:13:29 -0600116};
117
118struct geni_i2c_err_log {
119 int err;
120 const char *msg;
121};
122
123static struct geni_i2c_err_log gi2c_log[] = {
124 [GP_IRQ0] = {-EINVAL, "Unknown I2C err GP_IRQ0"},
125 [I2C_NACK] = {-ENOTCONN,
126 "NACK: slv unresponsive, check its power/reset-ln"},
127 [GP_IRQ2] = {-EINVAL, "Unknown I2C err GP IRQ2"},
128 [I2C_BUS_PROTO] = {-EPROTO,
129 "Bus proto err, noisy/unepxected start/stop"},
130 [I2C_ARB_LOST] = {-EBUSY,
131 "Bus arbitration lost, clock line undriveable"},
132 [GP_IRQ5] = {-EINVAL, "Unknown I2C err GP IRQ5"},
133 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
134 [GENI_ILLEGAL_CMD] = {-EILSEQ,
135 "Illegal cmd, check GENI cmd-state machine"},
136 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
137 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
Sagar Dharia7c927c02016-11-23 11:51:43 -0700138};
139
Shrey Vijay6f231202017-07-11 11:16:16 +0530140struct geni_i2c_clk_fld {
141 u32 clk_freq_out;
142 u8 clk_div;
143 u8 t_high;
144 u8 t_low;
145 u8 t_cycle;
146};
147
148static struct geni_i2c_clk_fld geni_i2c_clk_map[] = {
149 {KHz(100), 7, 10, 11, 26},
150 {KHz(400), 2, 5, 12, 24},
151 {KHz(1000), 1, 3, 9, 18},
152};
153
154static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
Sagar Dharia7c927c02016-11-23 11:51:43 -0700155{
Shrey Vijay6f231202017-07-11 11:16:16 +0530156 int i;
157 int ret = 0;
158 bool clk_map_present = false;
159 struct geni_i2c_clk_fld *itr = geni_i2c_clk_map;
160
161 for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) {
162 if (itr->clk_freq_out == gi2c->i2c_rsc.clk_freq_out) {
163 clk_map_present = true;
164 break;
165 }
166 }
167
168 if (clk_map_present)
169 gi2c->clk_fld_idx = i;
170 else
171 ret = -EINVAL;
172
173 return ret;
174}
175
176static inline void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c, int dfs)
177{
178 struct geni_i2c_clk_fld *itr = geni_i2c_clk_map + gi2c->clk_fld_idx;
179
180 geni_write_reg(dfs, gi2c->base, SE_GENI_CLK_SEL);
181
182 geni_write_reg((itr->clk_div << 4) | 1, gi2c->base, GENI_SER_M_CLK_CFG);
183 geni_write_reg(((itr->t_high << 20) | (itr->t_low << 10) |
184 itr->t_cycle), gi2c->base, SE_I2C_SCL_COUNTERS);
185
Sagar Dharia7c927c02016-11-23 11:51:43 -0700186 /*
Shrey Vijay6f231202017-07-11 11:16:16 +0530187 * Ensure Clk config completes before return.
188 */
Sagar Dharia7c927c02016-11-23 11:51:43 -0700189 mb();
190}
191
Sagar Dharia818623c2017-04-27 13:13:29 -0600192static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
193{
Sagar Dharia818623c2017-04-27 13:13:29 -0600194 u32 m_cmd = readl_relaxed(gi2c->base + SE_GENI_M_CMD0);
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600195 u32 m_stat = readl_relaxed(gi2c->base + SE_GENI_M_IRQ_STATUS);
Sagar Dharia818623c2017-04-27 13:13:29 -0600196 u32 geni_s = readl_relaxed(gi2c->base + SE_GENI_STATUS);
197 u32 geni_ios = readl_relaxed(gi2c->base + SE_GENI_IOS);
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600198 u32 dma = readl_relaxed(gi2c->base + SE_GENI_DMA_MODE_EN);
199 u32 rx_st, tx_st;
200
201 if (gi2c->cur)
202 GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev,
203 "len:%d, slv-addr:0x%x, RD/WR:%d\n", gi2c->cur->len,
204 gi2c->cur->addr, gi2c->cur->flags);
Sagar Dharia818623c2017-04-27 13:13:29 -0600205
206 if (err == I2C_NACK || err == GENI_ABORT_DONE) {
207 GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev, "%s\n",
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600208 gi2c_log[err].msg);
209 goto err_ret;
Sagar Dharia818623c2017-04-27 13:13:29 -0600210 } else {
211 GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev, "%s\n",
212 gi2c_log[err].msg);
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600213 }
Sagar Dharia673a4502017-04-14 14:20:21 -0600214 if (gi2c->se_mode == GSI_ONLY)
215 goto err_out;
216
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600217 if (dma) {
218 rx_st = readl_relaxed(gi2c->base + SE_DMA_RX_IRQ_STAT);
219 tx_st = readl_relaxed(gi2c->base + SE_DMA_TX_IRQ_STAT);
220 } else {
221 rx_st = readl_relaxed(gi2c->base + SE_GENI_RX_FIFO_STATUS);
222 tx_st = readl_relaxed(gi2c->base + SE_GENI_TX_FIFO_STATUS);
223 }
224 GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev,
225 "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
226 dma, tx_st, rx_st, m_stat);
Sagar Dharia673a4502017-04-14 14:20:21 -0600227err_out:
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600228 GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev,
Sagar Dharia818623c2017-04-27 13:13:29 -0600229 "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
230 m_cmd, geni_s, geni_ios);
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600231err_ret:
Sagar Dharia818623c2017-04-27 13:13:29 -0600232 gi2c->err = gi2c_log[err].err;
233}
234
Sagar Dharia7c927c02016-11-23 11:51:43 -0700235static irqreturn_t geni_i2c_irq(int irq, void *dev)
236{
237 struct geni_i2c_dev *gi2c = dev;
238 int i, j;
239 u32 m_stat = readl_relaxed(gi2c->base + SE_GENI_M_IRQ_STATUS);
Sagar Dharia818623c2017-04-27 13:13:29 -0600240 u32 rx_st = readl_relaxed(gi2c->base + SE_GENI_RX_FIFO_STATUS);
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600241 u32 dm_tx_st = readl_relaxed(gi2c->base + SE_DMA_TX_IRQ_STAT);
242 u32 dm_rx_st = readl_relaxed(gi2c->base + SE_DMA_RX_IRQ_STAT);
243 u32 dma = readl_relaxed(gi2c->base + SE_GENI_DMA_MODE_EN);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700244 struct i2c_msg *cur = gi2c->cur;
245
Sagar Dharia818623c2017-04-27 13:13:29 -0600246 if (!cur || (m_stat & M_CMD_FAILURE_EN) ||
247 (dm_rx_st & (DM_I2C_RX_ERR)) ||
248 (m_stat & M_CMD_ABORT_EN)) {
249
250 if (m_stat & M_GP_IRQ_1_EN)
251 geni_i2c_err(gi2c, I2C_NACK);
252 if (m_stat & M_GP_IRQ_3_EN)
253 geni_i2c_err(gi2c, I2C_BUS_PROTO);
254 if (m_stat & M_GP_IRQ_4_EN)
255 geni_i2c_err(gi2c, I2C_ARB_LOST);
256 if (m_stat & M_CMD_OVERRUN_EN)
257 geni_i2c_err(gi2c, GENI_OVERRUN);
258 if (m_stat & M_ILLEGAL_CMD_EN)
259 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
260 if (m_stat & M_CMD_ABORT_EN)
261 geni_i2c_err(gi2c, GENI_ABORT_DONE);
262 if (m_stat & M_GP_IRQ_0_EN)
263 geni_i2c_err(gi2c, GP_IRQ0);
264
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600265 if (!dma)
266 writel_relaxed(0, (gi2c->base +
267 SE_GENI_TX_WATERMARK_REG));
Sagar Dharia7c927c02016-11-23 11:51:43 -0700268 goto irqret;
269 }
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600270
271 if (dma) {
272 dev_dbg(gi2c->dev, "i2c dma tx:0x%x, dma rx:0x%x\n", dm_tx_st,
273 dm_rx_st);
274 goto irqret;
275 }
276
Sagar Dharia7c927c02016-11-23 11:51:43 -0700277 if (((m_stat & M_RX_FIFO_WATERMARK_EN) ||
278 (m_stat & M_RX_FIFO_LAST_EN)) && (cur->flags & I2C_M_RD)) {
Sagar Dharia818623c2017-04-27 13:13:29 -0600279 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
Sagar Dharia7c927c02016-11-23 11:51:43 -0700280
281 for (j = 0; j < rxcnt; j++) {
282 u32 temp;
283 int p;
284
285 temp = readl_relaxed(gi2c->base + SE_GENI_RX_FIFOn);
286 for (i = gi2c->cur_rd, p = 0; (i < cur->len && p < 4);
287 i++, p++)
288 cur->buf[i] = (u8) ((temp >> (p * 8)) & 0xff);
289 gi2c->cur_rd = i;
290 if (gi2c->cur_rd == cur->len) {
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600291 dev_dbg(gi2c->dev, "FIFO i:%d,read 0x%x\n",
292 i, temp);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700293 break;
294 }
Sagar Dharia7c927c02016-11-23 11:51:43 -0700295 }
296 } else if ((m_stat & M_TX_FIFO_WATERMARK_EN) &&
297 !(cur->flags & I2C_M_RD)) {
Karthikeyan Ramasubramanian0d578b72017-04-26 10:44:02 -0600298 for (j = 0; j < gi2c->tx_wm; j++) {
Sagar Dharia7c927c02016-11-23 11:51:43 -0700299 u32 temp = 0;
300 int p;
301
302 for (i = gi2c->cur_wr, p = 0; (i < cur->len && p < 4);
303 i++, p++)
304 temp |= (((u32)(cur->buf[i]) << (p * 8)));
305 writel_relaxed(temp, gi2c->base + SE_GENI_TX_FIFOn);
306 gi2c->cur_wr = i;
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600307 dev_dbg(gi2c->dev, "FIFO i:%d,wrote 0x%x\n", i, temp);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700308 if (gi2c->cur_wr == cur->len) {
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600309 dev_dbg(gi2c->dev, "FIFO i2c bytes done writing\n");
Sagar Dharia7c927c02016-11-23 11:51:43 -0700310 writel_relaxed(0,
311 (gi2c->base + SE_GENI_TX_WATERMARK_REG));
312 break;
313 }
314 }
315 }
316irqret:
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600317 if (m_stat)
318 writel_relaxed(m_stat, gi2c->base + SE_GENI_M_IRQ_CLEAR);
319
320 if (dma) {
321 if (dm_tx_st)
322 writel_relaxed(dm_tx_st, gi2c->base +
323 SE_DMA_TX_IRQ_CLR);
324 if (dm_rx_st)
325 writel_relaxed(dm_rx_st, gi2c->base +
326 SE_DMA_RX_IRQ_CLR);
327 /* Ensure all writes are done before returning from ISR. */
328 wmb();
Sagar Dharia7c927c02016-11-23 11:51:43 -0700329 }
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600330 /* if this is err with done-bit not set, handle that thr' timeout. */
331 if (m_stat & M_CMD_DONE_EN)
332 complete(&gi2c->xfer);
333 else if ((dm_tx_st & TX_DMA_DONE) || (dm_rx_st & RX_DMA_DONE))
334 complete(&gi2c->xfer);
335
Sagar Dharia7c927c02016-11-23 11:51:43 -0700336 return IRQ_HANDLED;
337}
338
Sagar Dharia673a4502017-04-14 14:20:21 -0600339static void gi2c_ev_cb(struct dma_chan *ch, struct msm_gpi_cb const *cb_str,
340 void *ptr)
341{
342 struct geni_i2c_dev *gi2c = ptr;
343 u32 m_stat = cb_str->status;
344
345 switch (cb_str->cb_event) {
346 case MSM_GPI_QUP_ERROR:
347 case MSM_GPI_QUP_SW_ERROR:
348 case MSM_GPI_QUP_MAX_EVENT:
349 /* fall through to stall impacted channel */
350 case MSM_GPI_QUP_CH_ERROR:
351 case MSM_GPI_QUP_PENDING_EVENT:
352 case MSM_GPI_QUP_EOT_DESC_MISMATCH:
353 break;
354 case MSM_GPI_QUP_NOTIFY:
355 if (m_stat & M_GP_IRQ_1_EN)
356 geni_i2c_err(gi2c, I2C_NACK);
357 if (m_stat & M_GP_IRQ_3_EN)
358 geni_i2c_err(gi2c, I2C_BUS_PROTO);
359 if (m_stat & M_GP_IRQ_4_EN)
360 geni_i2c_err(gi2c, I2C_ARB_LOST);
361 complete(&gi2c->xfer);
362 break;
363 default:
364 break;
365 }
366 if (cb_str->cb_event != MSM_GPI_QUP_NOTIFY)
367 GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
368 "GSI QN err:0x%x, status:0x%x, err:%d\n",
369 cb_str->error_log.error_code,
370 m_stat, cb_str->cb_event);
371}
372
373static void gi2c_gsi_tx_cb(void *ptr)
374{
375 struct msm_gpi_dma_async_tx_cb_param *tx_cb = ptr;
376 struct geni_i2c_dev *gi2c = tx_cb->userdata;
377
378 if (!(gi2c->cur->flags & I2C_M_RD))
379 complete(&gi2c->xfer);
380}
381
382static void gi2c_gsi_rx_cb(void *ptr)
383{
384 struct msm_gpi_dma_async_tx_cb_param *rx_cb = ptr;
385 struct geni_i2c_dev *gi2c = rx_cb->userdata;
386
387 if (gi2c->cur->flags & I2C_M_RD) {
388 if (rx_cb->status & DM_I2C_RX_ERR) {
389 GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev,
390 "RX TCE Unexpected Err, stat:0x%x\n",
391 rx_cb->status);
392 if (rx_cb->status & GP_IRQ1)
393 geni_i2c_err(gi2c, I2C_NACK);
394 if (rx_cb->status & GP_IRQ3)
395 geni_i2c_err(gi2c, I2C_BUS_PROTO);
396 if (rx_cb->status & GP_IRQ4)
397 geni_i2c_err(gi2c, I2C_ARB_LOST);
398 }
399 complete(&gi2c->xfer);
400 }
401}
402
403static int geni_i2c_gsi_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
404 int num)
405{
406 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
407 int i, ret = 0, timeout = 0;
408
409 if (!gi2c->tx_c) {
410 gi2c->tx_c = dma_request_slave_channel(gi2c->dev, "tx");
411 if (!gi2c->tx_c) {
412 GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
413 "tx dma req slv chan ret :%d\n", ret);
414 return -EIO;
415 }
416 gi2c->tx_ev.init.callback = gi2c_ev_cb;
417 gi2c->tx_ev.init.cb_param = gi2c;
418 gi2c->tx_ev.cmd = MSM_GPI_INIT;
419 gi2c->tx_c->private = &gi2c->tx_ev;
420 ret = dmaengine_slave_config(gi2c->tx_c, NULL);
421 if (ret) {
422 GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
423 "tx dma slave config ret :%d\n", ret);
424 return ret;
425 }
426 }
427 if (!gi2c->rx_c) {
428 gi2c->rx_c = dma_request_slave_channel(gi2c->dev, "rx");
429 if (!gi2c->rx_c) {
430 GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
431 "rx dma req slv chan ret :%d\n", ret);
432 return -EIO;
433 }
434 gi2c->rx_ev.init.cb_param = gi2c;
435 gi2c->rx_ev.init.callback = gi2c_ev_cb;
436 gi2c->rx_ev.cmd = MSM_GPI_INIT;
437 gi2c->rx_c->private = &gi2c->rx_ev;
438 ret = dmaengine_slave_config(gi2c->rx_c, NULL);
439 if (ret) {
440 GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
441 "rx dma slave config ret :%d\n", ret);
442 return ret;
443 }
444 }
445
446 if (!gi2c->cfg_sent) {
447 struct geni_i2c_clk_fld *itr = geni_i2c_clk_map +
448 gi2c->clk_fld_idx;
449 struct msm_gpi_tre *cfg0 = &gi2c->cfg0_t;
450
451 /* config0 */
452 cfg0->dword[0] = MSM_GPI_I2C_CONFIG0_TRE_DWORD0(I2C_PACK_EN,
453 itr->t_cycle,
454 itr->t_high,
455 itr->t_low);
456 cfg0->dword[1] = MSM_GPI_I2C_CONFIG0_TRE_DWORD1(0, 0);
457 cfg0->dword[2] = MSM_GPI_I2C_CONFIG0_TRE_DWORD2(0,
458 itr->clk_div);
459 cfg0->dword[3] = MSM_GPI_I2C_CONFIG0_TRE_DWORD3(0, 0, 0, 1);
460
461 gi2c->tx_cb.userdata = gi2c;
462 gi2c->rx_cb.userdata = gi2c;
463 }
464
465 for (i = 0; i < num; i++) {
466 u8 op = (msgs[i].flags & I2C_M_RD) ? 2 : 1;
467 int segs = 3 - op;
468 int index = 0;
469 int stretch = (i < (num - 1));
470 dma_cookie_t tx_cookie, rx_cookie;
471 struct msm_gpi_tre *go_t = &gi2c->go_t;
472 struct device *rx_dev = gi2c->rx_c->device->dev;
473 struct device *tx_dev = gi2c->tx_c->device->dev;
474
475 gi2c->cur = &msgs[i];
476 if (!gi2c->cfg_sent) {
477 segs++;
478 sg_init_table(gi2c->tx_sg, segs);
479 sg_set_buf(gi2c->tx_sg, &gi2c->cfg0_t,
480 sizeof(gi2c->cfg0_t));
481 gi2c->cfg_sent = 1;
482 index++;
483 } else {
484 sg_init_table(gi2c->tx_sg, segs);
485 }
486
487 go_t->dword[0] = MSM_GPI_I2C_GO_TRE_DWORD0((stretch << 2),
488 msgs[i].addr, op);
489 go_t->dword[1] = MSM_GPI_I2C_GO_TRE_DWORD1;
490
491 if (msgs[i].flags & I2C_M_RD) {
492 go_t->dword[2] = MSM_GPI_I2C_GO_TRE_DWORD2(msgs[i].len);
493 go_t->dword[3] = MSM_GPI_I2C_GO_TRE_DWORD3(0, 0, 1, 0);
494 } else {
495 go_t->dword[2] = MSM_GPI_I2C_GO_TRE_DWORD2(0);
496 go_t->dword[3] = MSM_GPI_I2C_GO_TRE_DWORD3(0, 0, 0, 1);
497 }
498
499 sg_set_buf(&gi2c->tx_sg[index++], &gi2c->go_t,
500 sizeof(gi2c->go_t));
501
502 if (msgs[i].flags & I2C_M_RD) {
503 sg_init_table(&gi2c->rx_sg, 1);
504 gi2c->rx_ph = dma_map_single(rx_dev, msgs[i].buf,
505 msgs[i].len,
506 DMA_FROM_DEVICE);
507 gi2c->rx_t.dword[0] =
508 MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(gi2c->rx_ph);
509 gi2c->rx_t.dword[1] =
510 MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(gi2c->rx_ph);
511 gi2c->rx_t.dword[2] =
512 MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(msgs[i].len);
513 gi2c->rx_t.dword[3] =
514 MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(0, 1, 0, 0);
515
516 sg_set_buf(&gi2c->rx_sg, &gi2c->rx_t,
517 sizeof(gi2c->rx_t));
518 gi2c->rx_desc = dmaengine_prep_slave_sg(gi2c->rx_c,
519 &gi2c->rx_sg, 1,
520 DMA_DEV_TO_MEM,
521 (DMA_PREP_INTERRUPT |
522 DMA_CTRL_ACK));
523 if (!gi2c->rx_desc) {
524 GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
525 "prep_slave_sg for rx failed\n");
526 gi2c->err = -ENOMEM;
527 return gi2c->err;
528 }
529 gi2c->rx_desc->callback = gi2c_gsi_rx_cb;
530 gi2c->rx_desc->callback_param = &gi2c->rx_cb;
531
532 /* Issue RX */
533 rx_cookie = dmaengine_submit(gi2c->rx_desc);
534 dma_async_issue_pending(gi2c->rx_c);
535 } else {
536 gi2c->tx_ph = dma_map_single(tx_dev, msgs[i].buf,
537 msgs[i].len,
538 DMA_TO_DEVICE);
539 gi2c->tx_t.dword[0] =
540 MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(gi2c->tx_ph);
541 gi2c->tx_t.dword[1] =
542 MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(gi2c->tx_ph);
543 gi2c->tx_t.dword[2] =
544 MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(msgs[i].len);
545 gi2c->tx_t.dword[3] =
546 MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(0, 1, 0, 0);
547
548 sg_set_buf(&gi2c->tx_sg[index++], &gi2c->tx_t,
549 sizeof(gi2c->tx_t));
550 }
551
552 gi2c->tx_desc = dmaengine_prep_slave_sg(gi2c->tx_c, gi2c->tx_sg,
553 segs, DMA_MEM_TO_DEV,
554 (DMA_PREP_INTERRUPT |
555 DMA_CTRL_ACK));
556 if (!gi2c->tx_desc) {
557 GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
558 "prep_slave_sg for tx failed\n");
559 gi2c->err = -ENOMEM;
560 return gi2c->err;
561 }
562 gi2c->tx_desc->callback = gi2c_gsi_tx_cb;
563 gi2c->tx_desc->callback_param = &gi2c->tx_cb;
564
565 /* Issue TX */
566 tx_cookie = dmaengine_submit(gi2c->tx_desc);
567 dma_async_issue_pending(gi2c->tx_c);
568
569 timeout = wait_for_completion_timeout(&gi2c->xfer, HZ);
570 if (msgs[i].flags & I2C_M_RD)
571 dma_unmap_single(rx_dev, gi2c->rx_ph, msgs[i].len,
572 DMA_FROM_DEVICE);
573 else
574 dma_unmap_single(tx_dev, gi2c->tx_ph, msgs[i].len,
575 DMA_TO_DEVICE);
576
577 if (!timeout) {
578 GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
579 "GSI Txn timed out\n");
580 gi2c->err = -ETIMEDOUT;
581 }
582 if (gi2c->err) {
583 dmaengine_terminate_all(gi2c->tx_c);
584 gi2c->cfg_sent = 0;
585 return gi2c->err;
586 }
587 }
588 return gi2c->err;
589}
590
Sagar Dharia7c927c02016-11-23 11:51:43 -0700591static int geni_i2c_xfer(struct i2c_adapter *adap,
592 struct i2c_msg msgs[],
593 int num)
594{
595 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
596 int i, ret = 0, timeout = 0;
597
598 gi2c->err = 0;
599 gi2c->cur = &msgs[0];
600 reinit_completion(&gi2c->xfer);
Sagar Dhariab44003b2017-03-10 15:34:26 -0700601 ret = pm_runtime_get_sync(gi2c->dev);
602 if (ret < 0) {
Sagar Dharia818623c2017-04-27 13:13:29 -0600603 GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
604 "error turning SE resources:%d\n", ret);
Sagar Dhariab44003b2017-03-10 15:34:26 -0700605 pm_runtime_put_noidle(gi2c->dev);
606 /* Set device in suspended since resume failed */
607 pm_runtime_set_suspended(gi2c->dev);
608 return ret;
609 }
Sagar Dharia673a4502017-04-14 14:20:21 -0600610 if (gi2c->se_mode == GSI_ONLY) {
611 ret = geni_i2c_gsi_xfer(adap, msgs, num);
612 goto geni_i2c_txn_ret;
613 }
614
Shrey Vijay6f231202017-07-11 11:16:16 +0530615 qcom_geni_i2c_conf(gi2c, 0);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700616 dev_dbg(gi2c->dev, "i2c xfer:num:%d, msgs:len:%d,flg:%d\n",
617 num, msgs[0].len, msgs[0].flags);
618 for (i = 0; i < num; i++) {
619 int stretch = (i < (num - 1));
620 u32 m_param = 0;
621 u32 m_cmd = 0;
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600622 dma_addr_t tx_dma = 0;
623 dma_addr_t rx_dma = 0;
624 enum se_xfer_mode mode = FIFO_MODE;
Sagar Dharia7c927c02016-11-23 11:51:43 -0700625
Girish Mahadevand5890b22017-03-30 13:20:02 -0600626 m_param |= (stretch ? STOP_STRETCH : 0);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700627 m_param |= ((msgs[i].addr & 0x7F) << SLV_ADDR_SHFT);
628
629 gi2c->cur = &msgs[i];
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600630 mode = msgs[i].len > 32 ? SE_DMA : FIFO_MODE;
631 ret = geni_se_select_mode(gi2c->base, mode);
632 if (ret) {
633 dev_err(gi2c->dev, "%s: Error mode init %d:%d:%d\n",
634 __func__, mode, i, msgs[i].len);
635 break;
636 }
Sagar Dharia7c927c02016-11-23 11:51:43 -0700637 if (msgs[i].flags & I2C_M_RD) {
638 dev_dbg(gi2c->dev,
639 "READ,n:%d,i:%d len:%d, stretch:%d\n",
640 num, i, msgs[i].len, stretch);
641 geni_write_reg(msgs[i].len,
642 gi2c->base, SE_I2C_RX_TRANS_LEN);
643 m_cmd = I2C_READ;
644 geni_setup_m_cmd(gi2c->base, m_cmd, m_param);
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600645 if (mode == SE_DMA) {
646 ret = geni_se_rx_dma_prep(gi2c->wrapper_dev,
647 gi2c->base, msgs[i].buf,
648 msgs[i].len, &rx_dma);
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600649 if (ret) {
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600650 mode = FIFO_MODE;
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600651 ret = geni_se_select_mode(gi2c->base,
652 mode);
653 }
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600654 }
Sagar Dharia7c927c02016-11-23 11:51:43 -0700655 } else {
656 dev_dbg(gi2c->dev,
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600657 "WRITE:n:%d,i:%d len:%d, stretch:%d, m_param:0x%x\n",
658 num, i, msgs[i].len, stretch, m_param);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700659 geni_write_reg(msgs[i].len, gi2c->base,
660 SE_I2C_TX_TRANS_LEN);
661 m_cmd = I2C_WRITE;
662 geni_setup_m_cmd(gi2c->base, m_cmd, m_param);
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600663 if (mode == SE_DMA) {
664 ret = geni_se_tx_dma_prep(gi2c->wrapper_dev,
665 gi2c->base, msgs[i].buf,
666 msgs[i].len, &tx_dma);
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600667 if (ret) {
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600668 mode = FIFO_MODE;
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600669 ret = geni_se_select_mode(gi2c->base,
670 mode);
671 }
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600672 }
Sagar Dharia1bfc8d12017-06-29 17:50:18 -0600673 if (mode == FIFO_MODE) /* Get FIFO IRQ */
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600674 geni_write_reg(1, gi2c->base,
675 SE_GENI_TX_WATERMARK_REG);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700676 }
677 /* Ensure FIFO write go through before waiting for Done evet */
678 mb();
679 timeout = wait_for_completion_timeout(&gi2c->xfer, HZ);
680 if (!timeout) {
Sagar Dharia818623c2017-04-27 13:13:29 -0600681 geni_i2c_err(gi2c, GENI_TIMEOUT);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700682 gi2c->cur = NULL;
683 geni_abort_m_cmd(gi2c->base);
684 timeout = wait_for_completion_timeout(&gi2c->xfer, HZ);
685 }
686 gi2c->cur_wr = 0;
687 gi2c->cur_rd = 0;
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600688 if (mode == SE_DMA) {
689 if (gi2c->err) {
690 if (msgs[i].flags != I2C_M_RD)
691 writel_relaxed(1, gi2c->base +
692 SE_DMA_TX_FSM_RST);
693 else
694 writel_relaxed(1, gi2c->base +
695 SE_DMA_RX_FSM_RST);
696 wait_for_completion_timeout(&gi2c->xfer, HZ);
697 }
698 geni_se_rx_dma_unprep(gi2c->wrapper_dev, rx_dma,
699 msgs[i].len);
700 geni_se_tx_dma_unprep(gi2c->wrapper_dev, tx_dma,
701 msgs[i].len);
702 }
703 ret = gi2c->err;
Sagar Dharia7c927c02016-11-23 11:51:43 -0700704 if (gi2c->err) {
705 dev_err(gi2c->dev, "i2c error :%d\n", gi2c->err);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700706 break;
707 }
708 }
Sagar Dharia673a4502017-04-14 14:20:21 -0600709geni_i2c_txn_ret:
Sagar Dharia7c927c02016-11-23 11:51:43 -0700710 if (ret == 0)
Sagar Dharia673a4502017-04-14 14:20:21 -0600711 ret = num;
Sagar Dhariab44003b2017-03-10 15:34:26 -0700712 pm_runtime_put_sync(gi2c->dev);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700713 gi2c->cur = NULL;
714 gi2c->err = 0;
715 dev_dbg(gi2c->dev, "i2c txn ret:%d\n", ret);
716 return ret;
717}
718
719static u32 geni_i2c_func(struct i2c_adapter *adap)
720{
721 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
722}
723
724static const struct i2c_algorithm geni_i2c_algo = {
725 .master_xfer = geni_i2c_xfer,
726 .functionality = geni_i2c_func,
727};
728
729static int geni_i2c_probe(struct platform_device *pdev)
730{
731 struct geni_i2c_dev *gi2c;
732 struct resource *res;
Karthikeyan Ramasubramanian0d578b72017-04-26 10:44:02 -0600733 struct platform_device *wrapper_pdev;
734 struct device_node *wrapper_ph_node;
Sagar Dharia7c927c02016-11-23 11:51:43 -0700735 int ret;
736
737 gi2c = devm_kzalloc(&pdev->dev, sizeof(*gi2c), GFP_KERNEL);
738 if (!gi2c)
739 return -ENOMEM;
740
741 gi2c->dev = &pdev->dev;
742
743 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
744 if (!res)
745 return -EINVAL;
746
Karthikeyan Ramasubramanian0d578b72017-04-26 10:44:02 -0600747 wrapper_ph_node = of_parse_phandle(pdev->dev.of_node,
748 "qcom,wrapper-core", 0);
749 if (IS_ERR_OR_NULL(wrapper_ph_node)) {
750 ret = PTR_ERR(wrapper_ph_node);
751 dev_err(&pdev->dev, "No wrapper core defined\n");
752 return ret;
753 }
754 wrapper_pdev = of_find_device_by_node(wrapper_ph_node);
755 of_node_put(wrapper_ph_node);
756 if (IS_ERR_OR_NULL(wrapper_pdev)) {
757 ret = PTR_ERR(wrapper_pdev);
758 dev_err(&pdev->dev, "Cannot retrieve wrapper device\n");
759 return ret;
760 }
761 gi2c->wrapper_dev = &wrapper_pdev->dev;
762 gi2c->i2c_rsc.wrapper_dev = &wrapper_pdev->dev;
763 ret = geni_se_resources_init(&gi2c->i2c_rsc, I2C_CORE2X_VOTE,
764 (DEFAULT_SE_CLK * DEFAULT_BUS_WIDTH));
765 if (ret) {
766 dev_err(gi2c->dev, "geni_se_resources_init\n");
767 return ret;
768 }
769
Sagar Dhariab44003b2017-03-10 15:34:26 -0700770 gi2c->i2c_rsc.se_clk = devm_clk_get(&pdev->dev, "se-clk");
771 if (IS_ERR(gi2c->i2c_rsc.se_clk)) {
772 ret = PTR_ERR(gi2c->i2c_rsc.se_clk);
773 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
774 return ret;
775 }
776
777 gi2c->i2c_rsc.m_ahb_clk = devm_clk_get(&pdev->dev, "m-ahb");
778 if (IS_ERR(gi2c->i2c_rsc.m_ahb_clk)) {
779 ret = PTR_ERR(gi2c->i2c_rsc.m_ahb_clk);
780 dev_err(&pdev->dev, "Err getting M AHB clk %d\n", ret);
781 return ret;
782 }
783
784 gi2c->i2c_rsc.s_ahb_clk = devm_clk_get(&pdev->dev, "s-ahb");
785 if (IS_ERR(gi2c->i2c_rsc.s_ahb_clk)) {
786 ret = PTR_ERR(gi2c->i2c_rsc.s_ahb_clk);
787 dev_err(&pdev->dev, "Err getting S AHB clk %d\n", ret);
788 return ret;
789 }
790
Sagar Dharia7c927c02016-11-23 11:51:43 -0700791 gi2c->base = devm_ioremap_resource(gi2c->dev, res);
792 if (IS_ERR(gi2c->base))
793 return PTR_ERR(gi2c->base);
794
Sagar Dhariab44003b2017-03-10 15:34:26 -0700795 gi2c->i2c_rsc.geni_pinctrl = devm_pinctrl_get(&pdev->dev);
796 if (IS_ERR_OR_NULL(gi2c->i2c_rsc.geni_pinctrl)) {
797 dev_err(&pdev->dev, "No pinctrl config specified\n");
798 ret = PTR_ERR(gi2c->i2c_rsc.geni_pinctrl);
799 return ret;
800 }
801 gi2c->i2c_rsc.geni_gpio_active =
802 pinctrl_lookup_state(gi2c->i2c_rsc.geni_pinctrl,
803 PINCTRL_DEFAULT);
804 if (IS_ERR_OR_NULL(gi2c->i2c_rsc.geni_gpio_active)) {
805 dev_err(&pdev->dev, "No default config specified\n");
806 ret = PTR_ERR(gi2c->i2c_rsc.geni_gpio_active);
807 return ret;
808 }
809 gi2c->i2c_rsc.geni_gpio_sleep =
810 pinctrl_lookup_state(gi2c->i2c_rsc.geni_pinctrl,
811 PINCTRL_SLEEP);
812 if (IS_ERR_OR_NULL(gi2c->i2c_rsc.geni_gpio_sleep)) {
813 dev_err(&pdev->dev, "No sleep config specified\n");
814 ret = PTR_ERR(gi2c->i2c_rsc.geni_gpio_sleep);
815 return ret;
816 }
817
Shrey Vijay6f231202017-07-11 11:16:16 +0530818 if (of_property_read_u32(pdev->dev.of_node, "qcom,clk-freq-out",
819 &gi2c->i2c_rsc.clk_freq_out)) {
820 dev_info(&pdev->dev,
821 "Bus frequency not specified, default to 400KHz.\n");
822 gi2c->i2c_rsc.clk_freq_out = KHz(400);
823 }
824
Sagar Dharia7c927c02016-11-23 11:51:43 -0700825 gi2c->irq = platform_get_irq(pdev, 0);
826 if (gi2c->irq < 0) {
827 dev_err(gi2c->dev, "IRQ error for i2c-geni\n");
828 return gi2c->irq;
829 }
830
Shrey Vijay6f231202017-07-11 11:16:16 +0530831 ret = geni_i2c_clk_map_idx(gi2c);
832 if (ret) {
833 dev_err(gi2c->dev, "Invalid clk frequency %d KHz: %d\n",
834 gi2c->i2c_rsc.clk_freq_out, ret);
835 return ret;
836 }
837
Sagar Dharia7c927c02016-11-23 11:51:43 -0700838 gi2c->adap.algo = &geni_i2c_algo;
839 init_completion(&gi2c->xfer);
840 platform_set_drvdata(pdev, gi2c);
841 ret = devm_request_irq(gi2c->dev, gi2c->irq, geni_i2c_irq,
842 IRQF_TRIGGER_HIGH, "i2c_geni", gi2c);
843 if (ret) {
844 dev_err(gi2c->dev, "Request_irq failed:%d: err:%d\n",
845 gi2c->irq, ret);
846 return ret;
847 }
848 disable_irq(gi2c->irq);
849 i2c_set_adapdata(&gi2c->adap, gi2c);
850 gi2c->adap.dev.parent = gi2c->dev;
851 gi2c->adap.dev.of_node = pdev->dev.of_node;
852
853 strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
854
Sagar Dhariab44003b2017-03-10 15:34:26 -0700855 pm_runtime_set_suspended(gi2c->dev);
856 pm_runtime_enable(gi2c->dev);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700857 i2c_add_adapter(&gi2c->adap);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700858
Karthikeyan Ramasubramaniana5766572017-04-19 11:31:42 -0600859 dev_dbg(gi2c->dev, "I2C probed\n");
Sagar Dharia7c927c02016-11-23 11:51:43 -0700860 return 0;
861}
862
863static int geni_i2c_remove(struct platform_device *pdev)
864{
865 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
866
Sagar Dhariab44003b2017-03-10 15:34:26 -0700867 pm_runtime_disable(gi2c->dev);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700868 i2c_del_adapter(&gi2c->adap);
Sagar Dharia818623c2017-04-27 13:13:29 -0600869 if (gi2c->ipcl)
870 ipc_log_context_destroy(gi2c->ipcl);
Sagar Dharia7c927c02016-11-23 11:51:43 -0700871 return 0;
872}
873
Sagar Dhariab44003b2017-03-10 15:34:26 -0700874static int geni_i2c_resume_noirq(struct device *device)
Sagar Dharia7c927c02016-11-23 11:51:43 -0700875{
876 return 0;
877}
878
Sagar Dhariab44003b2017-03-10 15:34:26 -0700879#ifdef CONFIG_PM
880static int geni_i2c_runtime_suspend(struct device *dev)
881{
882 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
883
Sagar Dharia673a4502017-04-14 14:20:21 -0600884 if (gi2c->se_mode == FIFO_SE_DMA)
885 disable_irq(gi2c->irq);
886
Sagar Dhariab44003b2017-03-10 15:34:26 -0700887 se_geni_resources_off(&gi2c->i2c_rsc);
888 return 0;
889}
890
891static int geni_i2c_runtime_resume(struct device *dev)
892{
893 int ret;
894 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
895
Sagar Dharia818623c2017-04-27 13:13:29 -0600896 if (!gi2c->ipcl) {
897 char ipc_name[I2C_NAME_SIZE];
898
899 snprintf(ipc_name, I2C_NAME_SIZE, "i2c-%d", gi2c->adap.nr);
900 gi2c->ipcl = ipc_log_context_create(2, ipc_name, 0);
901 }
Sagar Dhariab44003b2017-03-10 15:34:26 -0700902 ret = se_geni_resources_on(&gi2c->i2c_rsc);
903 if (ret)
904 return ret;
905
Sagar Dharia673a4502017-04-14 14:20:21 -0600906 if (gi2c->se_mode == UNINITIALIZED) {
Girish Mahadevanaf5f2bc2017-08-15 12:05:40 -0600907 u32 se_mode = readl_relaxed(gi2c->base +
908 GENI_IF_FIFO_DISABLE_RO);
Karthikeyan Ramasubramanian0d578b72017-04-26 10:44:02 -0600909
Sagar Dharia673a4502017-04-14 14:20:21 -0600910 if (se_mode) {
911 gi2c->se_mode = GSI_ONLY;
912 geni_se_select_mode(gi2c->base, GSI_DMA);
913 GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev,
914 "i2c in GSI ONLY mode\n");
915 } else {
916 int gi2c_tx_depth = get_tx_fifo_depth(gi2c->base);
917
918 gi2c->se_mode = FIFO_SE_DMA;
919
920 gi2c->tx_wm = gi2c_tx_depth - 1;
921 geni_se_init(gi2c->base, gi2c->tx_wm, gi2c_tx_depth);
922 se_config_packing(gi2c->base, 8, 4, true);
923 GENI_SE_DBG(gi2c->ipcl, false, gi2c->dev,
924 "i2c fifo/se-dma mode. fifo depth:%d\n",
925 gi2c_tx_depth);
926 }
Karthikeyan Ramasubramanian0d578b72017-04-26 10:44:02 -0600927 }
Sagar Dharia673a4502017-04-14 14:20:21 -0600928 if (gi2c->se_mode == FIFO_SE_DMA)
929 enable_irq(gi2c->irq);
930
Sagar Dhariab44003b2017-03-10 15:34:26 -0700931 return 0;
932}
933
934static int geni_i2c_suspend_noirq(struct device *device)
935{
936 if (!pm_runtime_status_suspended(device))
937 return -EBUSY;
938 return 0;
939}
940#else
941static int geni_i2c_runtime_suspend(struct device *dev)
942{
943 return 0;
944}
945
946static int geni_i2c_runtime_resume(struct device *dev)
947{
948 return 0;
949}
950
951static int geni_i2c_suspend_noirq(struct device *device)
Sagar Dharia7c927c02016-11-23 11:51:43 -0700952{
953 return 0;
954}
955#endif
956
957static const struct dev_pm_ops geni_i2c_pm_ops = {
Sagar Dhariab44003b2017-03-10 15:34:26 -0700958 .suspend_noirq = geni_i2c_suspend_noirq,
959 .resume_noirq = geni_i2c_resume_noirq,
960 .runtime_suspend = geni_i2c_runtime_suspend,
961 .runtime_resume = geni_i2c_runtime_resume,
Sagar Dharia7c927c02016-11-23 11:51:43 -0700962};
963
964static const struct of_device_id geni_i2c_dt_match[] = {
965 { .compatible = "qcom,i2c-geni" },
966 {}
967};
968MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
969
970static struct platform_driver geni_i2c_driver = {
971 .probe = geni_i2c_probe,
972 .remove = geni_i2c_remove,
973 .driver = {
974 .name = "i2c_geni",
975 .pm = &geni_i2c_pm_ops,
976 .of_match_table = geni_i2c_dt_match,
977 },
978};
979
980module_platform_driver(geni_i2c_driver);
981
982MODULE_LICENSE("GPL v2");
983MODULE_ALIAS("platform:i2c_geni");