blob: e326ac9730cf9c557a80d31dbf58706bca9e0b62 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
Tvrtko Ursulin93b81f52015-02-10 17:16:05 +000034#include <uapi/drm/drm_fourcc.h>
Chris Wilsone9b73c62012-12-03 21:03:14 +000035
Jesse Barnes585fb112008-07-29 11:54:06 -070036#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080037#include "intel_bios.h"
Zou Nan hai8187a2b2010-05-21 09:08:55 +080038#include "intel_ringbuffer.h"
Oscar Mateob20385f2014-07-24 17:04:10 +010039#include "intel_lrc.h"
Ben Widawsky0260c422014-03-22 22:47:21 -070040#include "i915_gem_gtt.h"
Oscar Mateo564ddb22014-08-21 11:40:54 +010041#include "i915_gem_render_state.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070042#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070043#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010044#include <linux/i2c-algo-bit.h>
Daniel Vetter0ade6382010-08-24 22:18:41 +020045#include <drm/intel-gtt.h>
Daniel Vetterba8286f2014-09-11 07:43:25 +020046#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
Daniel Vetterd9fc9412014-09-23 15:46:53 +020047#include <drm/drm_gem.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020048#include <linux/backlight.h>
Chris Wilson5cc9ed42014-05-16 14:22:37 +010049#include <linux/hashtable.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070050#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020051#include <linux/kref.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010052#include <linux/pm_qos.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070053
Linus Torvalds1da177e2005-04-16 15:20:36 -070054/* General customization:
55 */
56
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#define DRIVER_NAME "i915"
58#define DRIVER_DESC "Intel Graphics"
Daniel Vetter1ff27a32015-03-27 20:21:01 +010059#define DRIVER_DATE "20150327"
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
Mika Kuoppalac883ef12014-10-28 17:32:30 +020061#undef WARN_ON
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010062/* Many gcc seem to no see through this and fall over :( */
63#if 0
64#define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
69#else
70#define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
71#endif
72
Jani Nikulacd9bfac2015-03-12 13:01:12 +020073#undef WARN_ON_ONCE
74#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
75
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010076#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
Mika Kuoppalac883ef12014-10-28 17:32:30 +020078
Rob Clarke2c719b2014-12-15 13:56:32 -050079/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
84 * spam.
85 */
86#define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
Jani Nikula2f3408c2015-01-12 15:45:31 +020090 WARN(1, format); \
Rob Clarke2c719b2014-12-15 13:56:32 -050091 else \
92 DRM_ERROR(format); \
93 } \
94 unlikely(__ret_warn_on); \
95})
96
97#define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
Jani Nikula2f3408c2015-01-12 15:45:31 +0200101 WARN(1, "WARN_ON(" #condition ")\n"); \
Rob Clarke2c719b2014-12-15 13:56:32 -0500102 else \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
104 } \
105 unlikely(__ret_warn_on); \
106})
Jesse Barnes317c35d2008-08-25 15:11:06 -0700107
108enum pipe {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800109 INVALID_PIPE = -1,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200110 PIPE_A = 0,
111 PIPE_B,
Jesse Barnes317c35d2008-08-25 15:11:06 -0700112 PIPE_C,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800113 _PIPE_EDP,
Jesse Barnes317c35d2008-08-25 15:11:06 -0700114 I915_MAX_PIPES = _PIPE_EDP
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200115};
116#define pipe_name(p) ((p) + 'A')
117
118enum transcoder {
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200119 TRANSCODER_A = 0,
120 TRANSCODER_B,
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200121 TRANSCODER_C,
122 TRANSCODER_EDP,
123 I915_MAX_TRANSCODERS
Damien Lespiau84139d12014-03-28 00:18:32 +0530124};
125#define transcoder_name(t) ((t) + 'A')
126
127/*
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
130 *
131 * This value doesn't count the cursor plane.
Jesse Barnes80824002009-09-10 15:28:06 -0700132 */
133#define I915_MAX_PLANES 3
134
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800135enum plane {
Jesse Barnes80824002009-09-10 15:28:06 -0700136 PLANE_A = 0,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800137 PLANE_B,
Keith Packard52440212008-11-18 09:30:25 -0800138 PLANE_C,
Damien Lespiaud615a162014-03-03 17:31:48 +0000139};
Ville Syrjälä06da8da2013-04-17 17:48:51 +0300140#define plane_name(p) ((p) + 'A')
Eugeni Dodonov2b139522012-03-29 12:32:22 -0300141
142#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
143
144enum port {
145 PORT_A = 0,
146 PORT_B,
147 PORT_C,
148 PORT_D,
149 PORT_E,
150 I915_MAX_PORTS
Chon Ming Leea09cadd2014-04-09 13:28:14 +0300151};
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800152#define port_name(p) ((p) + 'A')
153
154#define I915_NUM_PHYS_VLV 2
155
156enum dpio_channel {
157 DPIO_CH0,
158 DPIO_CH1
159};
160
161enum dpio_phy {
162 DPIO_PHY0,
Paulo Zanonib97186f2013-05-03 12:15:36 -0300163 DPIO_PHY1
164};
165
166enum intel_display_power_domain {
167 POWER_DOMAIN_PIPE_A,
168 POWER_DOMAIN_PIPE_B,
169 POWER_DOMAIN_PIPE_C,
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
Imre Deakf52e3532013-10-16 17:25:48 +0300173 POWER_DOMAIN_TRANSCODER_A,
Imre Deak319be8a2014-03-04 19:22:57 +0200174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
176 POWER_DOMAIN_TRANSCODER_EDP,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
Ville Syrjäläcdf8dd72013-09-16 17:38:30 +0300185 POWER_DOMAIN_PORT_DSI,
Imre Deakfbeeaa22013-11-25 17:15:28 +0200186 POWER_DOMAIN_PORT_CRT,
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -0300187 POWER_DOMAIN_PORT_OTHER,
Imre Deakbaa70702013-10-25 17:36:48 +0300188 POWER_DOMAIN_VGA,
Imre Deakbddc7642013-10-16 17:25:49 +0300189 POWER_DOMAIN_AUDIO,
190 POWER_DOMAIN_PLLS,
Satheeshakrishna M14071212015-01-16 15:57:51 +0000191 POWER_DOMAIN_AUX_A,
192 POWER_DOMAIN_AUX_B,
193 POWER_DOMAIN_AUX_C,
194 POWER_DOMAIN_AUX_D,
Paulo Zanonib97186f2013-05-03 12:15:36 -0300195 POWER_DOMAIN_INIT,
196
197 POWER_DOMAIN_NUM,
198};
199
200#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
Imre Deakf52e3532013-10-16 17:25:48 +0300203#define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
Paulo Zanonib97186f2013-05-03 12:15:36 -0300206
Egbert Eich1d843f92013-02-25 12:06:49 -0500207enum hpd_pin {
208 HPD_NONE = 0,
209 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
211 HPD_CRT,
212 HPD_SDVO_B,
213 HPD_SDVO_C,
214 HPD_PORT_B,
215 HPD_PORT_C,
216 HPD_PORT_D,
217 HPD_NUM_PINS
218};
219
Chris Wilson2a2d5482012-12-03 11:49:06 +0000220#define I915_GEM_GPU_DOMAINS \
221 (I915_GEM_DOMAIN_RENDER | \
222 I915_GEM_DOMAIN_SAMPLER | \
223 I915_GEM_DOMAIN_COMMAND | \
224 I915_GEM_DOMAIN_INSTRUCTION | \
225 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700226
Damien Lespiau055e3932014-08-18 13:49:10 +0100227#define for_each_pipe(__dev_priv, __p) \
228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
Damien Lespiaudd740782015-02-28 14:54:08 +0000229#define for_each_plane(__dev_priv, __pipe, __p) \
230 for ((__p) = 0; \
231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
232 (__p)++)
Damien Lespiau3bdcfc02015-02-28 14:54:09 +0000233#define for_each_sprite(__dev_priv, __p, __s) \
234 for ((__s) = 0; \
235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
236 (__s)++)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800237
Damien Lespiaud79b8142014-05-13 23:32:23 +0100238#define for_each_crtc(dev, crtc) \
239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
240
Damien Lespiaud063ae42014-05-13 23:32:21 +0100241#define for_each_intel_crtc(dev, intel_crtc) \
242 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
243
Damien Lespiaub2784e12014-08-05 11:29:37 +0100244#define for_each_intel_encoder(dev, intel_encoder) \
245 list_for_each_entry(intel_encoder, \
246 &(dev)->mode_config.encoder_list, \
247 base.head)
248
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +0200249#define for_each_intel_connector(dev, intel_connector) \
250 list_for_each_entry(intel_connector, \
251 &dev->mode_config.connector_list, \
252 base.head)
253
254
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200255#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
256 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
257 if ((intel_encoder)->base.crtc == (__crtc))
258
Jesse Barnes53f5e3c2014-02-07 12:48:15 -0800259#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
260 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
261 if ((intel_connector)->base.encoder == (__encoder))
262
Borun Fub04c5bd2014-07-12 10:02:27 +0530263#define for_each_power_domain(domain, mask) \
264 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
265 if ((1 << (domain)) & (mask))
266
Daniel Vettere7b903d2013-06-05 13:34:14 +0200267struct drm_i915_private;
Chris Wilsonad46cb52014-08-07 14:20:40 +0100268struct i915_mm_struct;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100269struct i915_mmu_object;
Daniel Vettere7b903d2013-06-05 13:34:14 +0200270
Daniel Vettere2b78262013-06-07 23:10:03 +0200271enum intel_dpll_id {
272 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
273 /* real shared dpll ids must be >= 0 */
Daniel Vetter9cd86932014-06-25 22:01:57 +0300274 DPLL_ID_PCH_PLL_A = 0,
275 DPLL_ID_PCH_PLL_B = 1,
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000276 /* hsw/bdw */
Daniel Vetter9cd86932014-06-25 22:01:57 +0300277 DPLL_ID_WRPLL1 = 0,
278 DPLL_ID_WRPLL2 = 1,
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000279 /* skl */
280 DPLL_ID_SKL_DPLL1 = 0,
281 DPLL_ID_SKL_DPLL2 = 1,
282 DPLL_ID_SKL_DPLL3 = 2,
Daniel Vettere2b78262013-06-07 23:10:03 +0200283};
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000284#define I915_NUM_PLLS 3
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100285
Daniel Vetter53589012013-06-05 13:34:16 +0200286struct intel_dpll_hw_state {
Damien Lespiaudcfc3552014-07-29 18:06:16 +0100287 /* i9xx, pch plls */
Daniel Vetter66e985c2013-06-05 13:34:20 +0200288 uint32_t dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +0200289 uint32_t dpll_md;
Daniel Vetter66e985c2013-06-05 13:34:20 +0200290 uint32_t fp0;
291 uint32_t fp1;
Damien Lespiaudcfc3552014-07-29 18:06:16 +0100292
293 /* hsw, bdw */
Daniel Vetterd452c5b2014-07-04 11:27:39 -0300294 uint32_t wrpll;
Satheeshakrishna Md1a2dc72014-11-13 14:55:18 +0000295
296 /* skl */
297 /*
298 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
299 * lower part of crtl1 and they get shifted into position when writing
300 * the register. This allows us to easily compare the state to share
301 * the DPLL.
302 */
303 uint32_t ctrl1;
304 /* HDMI only, 0 when used for DP */
305 uint32_t cfgcr1, cfgcr2;
Daniel Vetter53589012013-06-05 13:34:16 +0200306};
307
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +0200308struct intel_shared_dpll_config {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +0200309 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +0200310 struct intel_dpll_hw_state hw_state;
311};
312
313struct intel_shared_dpll {
314 struct intel_shared_dpll_config config;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +0200315 struct intel_shared_dpll_config *new_config;
316
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317 int active; /* count of number of active CRTCs (i.e. DPMS on) */
318 bool on; /* is the PLL actually active? Disabled during modeset */
Daniel Vetter46edb022013-06-05 13:34:12 +0200319 const char *name;
320 /* should match the index in the dev_priv->shared_dplls array */
321 enum intel_dpll_id id;
Daniel Vetter96f61282014-06-25 22:01:58 +0300322 /* The mode_set hook is optional and should be used together with the
323 * intel_prepare_shared_dpll function. */
Daniel Vetter15bdd4c2013-06-05 13:34:23 +0200324 void (*mode_set)(struct drm_i915_private *dev_priv,
325 struct intel_shared_dpll *pll);
Daniel Vettere7b903d2013-06-05 13:34:14 +0200326 void (*enable)(struct drm_i915_private *dev_priv,
327 struct intel_shared_dpll *pll);
328 void (*disable)(struct drm_i915_private *dev_priv,
329 struct intel_shared_dpll *pll);
Daniel Vetter53589012013-06-05 13:34:16 +0200330 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
331 struct intel_shared_dpll *pll,
332 struct intel_dpll_hw_state *hw_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334
Satheeshakrishna M429d47d2014-11-13 14:55:14 +0000335#define SKL_DPLL0 0
336#define SKL_DPLL1 1
337#define SKL_DPLL2 2
338#define SKL_DPLL3 3
339
Daniel Vettere69d0bc2012-11-29 15:59:36 +0100340/* Used by dp and fdi links */
341struct intel_link_m_n {
342 uint32_t tu;
343 uint32_t gmch_m;
344 uint32_t gmch_n;
345 uint32_t link_m;
346 uint32_t link_n;
347};
348
349void intel_link_compute_m_n(int bpp, int nlanes,
350 int pixel_clock, int link_clock,
351 struct intel_link_m_n *m_n);
352
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353/* Interface history:
354 *
355 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100356 * 1.2: Add Power Management
357 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100358 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000359 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000360 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
361 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 */
363#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000364#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365#define DRIVER_PATCHLEVEL 0
366
Chris Wilson23bc5982010-09-29 16:10:57 +0100367#define WATCH_LISTS 0
Eric Anholt673a3942008-07-30 12:06:12 -0700368
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700369struct opregion_header;
370struct opregion_acpi;
371struct opregion_swsci;
372struct opregion_asle;
373
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100374struct intel_opregion {
Ben Widawsky5bc44182012-04-16 14:07:42 -0700375 struct opregion_header __iomem *header;
376 struct opregion_acpi __iomem *acpi;
377 struct opregion_swsci __iomem *swsci;
Jani Nikulaebde53c2013-09-02 10:38:59 +0300378 u32 swsci_gbda_sub_functions;
379 u32 swsci_sbcb_sub_functions;
Ben Widawsky5bc44182012-04-16 14:07:42 -0700380 struct opregion_asle __iomem *asle;
381 void __iomem *vbt;
Chris Wilson01fe9db2011-01-16 19:37:30 +0000382 u32 __iomem *lid_state;
Jani Nikula91a60f22013-10-31 18:55:48 +0200383 struct work_struct asle_work;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100384};
Chris Wilson44834a62010-08-19 16:09:23 +0100385#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100386
Chris Wilson6ef3d422010-08-04 20:26:07 +0100387struct intel_overlay;
388struct intel_overlay_error_state;
389
Jesse Barnesde151cf2008-11-12 10:03:55 -0800390#define I915_FENCE_REG_NONE -1
Ville Syrjälä42b5aea2013-04-09 13:02:47 +0300391#define I915_MAX_NUM_FENCES 32
392/* 32 fences + sign bit for FENCE_REG_NONE */
393#define I915_MAX_NUM_FENCE_BITS 6
Jesse Barnesde151cf2008-11-12 10:03:55 -0800394
395struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200396 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000397 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100398 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800399};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000400
yakui_zhao9b9d1722009-05-31 17:17:17 +0800401struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100402 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800403 u8 dvo_port;
404 u8 slave_addr;
405 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100406 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400407 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800408};
409
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000410struct intel_display_error_state;
411
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700412struct drm_i915_error_state {
Daniel Vetter742cbee2012-04-27 15:17:39 +0200413 struct kref ref;
Ben Widawsky585b0282014-01-30 00:19:37 -0800414 struct timeval time;
415
Mika Kuoppalacb383002014-02-25 17:11:25 +0200416 char error_msg[128];
Mika Kuoppala48b031e2014-02-25 17:11:27 +0200417 u32 reset_count;
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200418 u32 suspend_count;
Mika Kuoppalacb383002014-02-25 17:11:25 +0200419
Ben Widawsky585b0282014-01-30 00:19:37 -0800420 /* Generic register state */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700421 u32 eir;
422 u32 pgtbl_er;
Ben Widawskybe998e22012-04-26 16:03:00 -0700423 u32 ier;
Rodrigo Vivi885ea5a2014-08-05 10:07:13 -0700424 u32 gtier[4];
Ben Widawskyb9a39062012-06-04 14:42:52 -0700425 u32 ccid;
Chris Wilson0f3b6842013-01-15 12:05:55 +0000426 u32 derrmr;
427 u32 forcewake;
Ben Widawsky585b0282014-01-30 00:19:37 -0800428 u32 error; /* gen6+ */
429 u32 err_int; /* gen7 */
Mika Kuoppala6c826f32015-03-24 14:54:19 +0200430 u32 fault_data0; /* gen8, gen9 */
431 u32 fault_data1; /* gen8, gen9 */
Ben Widawsky585b0282014-01-30 00:19:37 -0800432 u32 done_reg;
Ben Widawsky91ec5d12014-01-30 00:19:39 -0800433 u32 gac_eco;
434 u32 gam_ecochk;
435 u32 gab_ctl;
436 u32 gfx_mode;
Ben Widawsky585b0282014-01-30 00:19:37 -0800437 u32 extra_instdone[I915_NUM_INSTDONE_REG];
Ben Widawsky585b0282014-01-30 00:19:37 -0800438 u64 fence[I915_MAX_NUM_FENCES];
439 struct intel_overlay_error_state *overlay;
440 struct intel_display_error_state *display;
Ben Widawsky0ca36d72014-06-30 09:53:41 -0700441 struct drm_i915_error_object *semaphore_obj;
Ben Widawsky585b0282014-01-30 00:19:37 -0800442
Chris Wilson52d39a22012-02-15 11:25:37 +0000443 struct drm_i915_error_ring {
Chris Wilson372fbb82014-01-27 13:52:34 +0000444 bool valid;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800445 /* Software tracked state */
446 bool waiting;
447 int hangcheck_score;
448 enum intel_ring_hangcheck_action hangcheck_action;
449 int num_requests;
450
451 /* our own tracking of ring head and tail */
452 u32 cpu_ring_head;
453 u32 cpu_ring_tail;
454
455 u32 semaphore_seqno[I915_NUM_RINGS - 1];
456
457 /* Register state */
458 u32 tail;
459 u32 head;
460 u32 ctl;
461 u32 hws;
462 u32 ipeir;
463 u32 ipehr;
464 u32 instdone;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800465 u32 bbstate;
466 u32 instpm;
467 u32 instps;
468 u32 seqno;
469 u64 bbaddr;
Chris Wilson50877442014-03-21 12:41:53 +0000470 u64 acthd;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800471 u32 fault_reg;
Ben Widawsky13ffadd2014-04-01 16:31:07 -0700472 u64 faddr;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800473 u32 rc_psmi; /* sleep state */
474 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
475
Chris Wilson52d39a22012-02-15 11:25:37 +0000476 struct drm_i915_error_object {
477 int page_count;
478 u32 gtt_offset;
479 u32 *pages[0];
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200480 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800481
Chris Wilson52d39a22012-02-15 11:25:37 +0000482 struct drm_i915_error_request {
483 long jiffies;
484 u32 seqno;
Chris Wilsonee4f42b2012-02-15 11:25:38 +0000485 u32 tail;
Chris Wilson52d39a22012-02-15 11:25:37 +0000486 } *requests;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800487
488 struct {
489 u32 gfx_mode;
490 union {
491 u64 pdp[4];
492 u32 pp_dir_base;
493 };
494 } vm_info;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200495
496 pid_t pid;
497 char comm[TASK_COMM_LEN];
Chris Wilson52d39a22012-02-15 11:25:37 +0000498 } ring[I915_NUM_RINGS];
Chris Wilson3a448732014-08-12 20:05:47 +0100499
Chris Wilson9df30792010-02-18 10:24:56 +0000500 struct drm_i915_error_buffer {
Chris Wilsona779e5a2011-01-09 21:07:49 +0000501 u32 size;
Chris Wilson9df30792010-02-18 10:24:56 +0000502 u32 name;
Chris Wilson0201f1e2012-07-20 12:41:01 +0100503 u32 rseqno, wseqno;
Chris Wilson9df30792010-02-18 10:24:56 +0000504 u32 gtt_offset;
505 u32 read_domains;
506 u32 write_domain;
Daniel Vetter4b9de732011-10-09 21:52:02 +0200507 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
Chris Wilson9df30792010-02-18 10:24:56 +0000508 s32 pinned:2;
509 u32 tiling:2;
510 u32 dirty:1;
511 u32 purgeable:1;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100512 u32 userptr:1;
Daniel Vetter5d1333f2012-02-16 11:03:29 +0100513 s32 ring:4;
Chris Wilsonf56383c2013-09-25 10:23:19 +0100514 u32 cache_level:3;
Ben Widawsky95f53012013-07-31 17:00:15 -0700515 } **active_bo, **pinned_bo;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800516
Ben Widawsky95f53012013-07-31 17:00:15 -0700517 u32 *active_bo_count, *pinned_bo_count;
Chris Wilson3a448732014-08-12 20:05:47 +0100518 u32 vm_count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700519};
520
Jani Nikula7bd688c2013-11-08 16:48:56 +0200521struct intel_connector;
Jani Nikula820d2d72014-10-27 16:26:47 +0200522struct intel_encoder;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200523struct intel_crtc_state;
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000524struct intel_initial_plane_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100525struct intel_crtc;
Daniel Vetteree9300b2013-06-03 22:40:22 +0200526struct intel_limit;
527struct dpll;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100528
Jesse Barnese70236a2009-09-21 10:42:27 -0700529struct drm_i915_display_funcs {
Adam Jacksonee5382a2010-04-23 11:17:39 -0400530 bool (*fbc_enabled)(struct drm_device *dev);
Ville Syrjälä993495a2013-12-12 17:27:40 +0200531 void (*enable_fbc)(struct drm_crtc *crtc);
Jesse Barnese70236a2009-09-21 10:42:27 -0700532 void (*disable_fbc)(struct drm_device *dev);
533 int (*get_display_clock_speed)(struct drm_device *dev);
534 int (*get_fifo_size)(struct drm_device *dev, int plane);
Daniel Vetteree9300b2013-06-03 22:40:22 +0200535 /**
536 * find_dpll() - Find the best values for the PLL
537 * @limit: limits for the PLL
538 * @crtc: current CRTC
539 * @target: target frequency in kHz
540 * @refclk: reference clock frequency in kHz
541 * @match_clock: if provided, @best_clock P divider must
542 * match the P divider from @match_clock
543 * used for LVDS downclocking
544 * @best_clock: best PLL values found
545 *
546 * Returns true on success, false on failure.
547 */
548 bool (*find_dpll)(const struct intel_limit *limit,
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200549 struct intel_crtc_state *crtc_state,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200550 int target, int refclk,
551 struct dpll *match_clock,
552 struct dpll *best_clock);
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300553 void (*update_wm)(struct drm_crtc *crtc);
Ville Syrjäläadf3d352013-08-06 22:24:11 +0300554 void (*update_sprite_wm)(struct drm_plane *plane,
555 struct drm_crtc *crtc,
Damien Lespiaued57cb82014-07-15 09:21:24 +0200556 uint32_t sprite_width, uint32_t sprite_height,
557 int pixel_size, bool enable, bool scaled);
Ander Conselvan de Oliveira679dacd2015-03-20 16:18:15 +0200558 void (*modeset_global_resources)(struct drm_atomic_state *state);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100559 /* Returns the active state of the crtc, and if the crtc is active,
560 * fills out the pipe-config with the hw state. */
561 bool (*get_pipe_config)(struct intel_crtc *,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200562 struct intel_crtc_state *);
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000563 void (*get_initial_plane_config)(struct intel_crtc *,
564 struct intel_initial_plane_config *);
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +0200565 int (*crtc_compute_clock)(struct intel_crtc *crtc,
566 struct intel_crtc_state *crtc_state);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200567 void (*crtc_enable)(struct drm_crtc *crtc);
568 void (*crtc_disable)(struct drm_crtc *crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100569 void (*off)(struct drm_crtc *crtc);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200570 void (*audio_codec_enable)(struct drm_connector *connector,
571 struct intel_encoder *encoder,
572 struct drm_display_mode *mode);
573 void (*audio_codec_disable)(struct intel_encoder *encoder);
Jesse Barnes674cf962011-04-28 14:27:04 -0700574 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700575 void (*init_clock_gating)(struct drm_device *dev);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -0700576 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
577 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -0700578 struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +0100579 struct intel_engine_cs *ring,
Keith Packarded8d1972013-07-22 18:49:58 -0700580 uint32_t flags);
Daniel Vetter29b9bde2014-04-24 23:55:01 +0200581 void (*update_primary_plane)(struct drm_crtc *crtc,
582 struct drm_framebuffer *fb,
583 int x, int y);
Daniel Vetter20afbda2012-12-11 14:05:07 +0100584 void (*hpd_irq_setup)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700585 /* clock updates for mode set */
586 /* cursor updates */
587 /* render clock increase/decrease */
588 /* display clock increase/decrease */
589 /* pll clock increase/decrease */
Jani Nikula7bd688c2013-11-08 16:48:56 +0200590
Ville Syrjälä6517d272014-11-07 11:16:02 +0200591 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
Jani Nikula7bd688c2013-11-08 16:48:56 +0200592 uint32_t (*get_backlight)(struct intel_connector *connector);
593 void (*set_backlight)(struct intel_connector *connector,
594 uint32_t level);
595 void (*disable_backlight)(struct intel_connector *connector);
596 void (*enable_backlight)(struct intel_connector *connector);
Jesse Barnese70236a2009-09-21 10:42:27 -0700597};
598
Mika Kuoppala48c10262015-01-16 11:34:41 +0200599enum forcewake_domain_id {
600 FW_DOMAIN_ID_RENDER = 0,
601 FW_DOMAIN_ID_BLITTER,
602 FW_DOMAIN_ID_MEDIA,
603
604 FW_DOMAIN_ID_COUNT
605};
606
607enum forcewake_domains {
608 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
609 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
610 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
611 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
612 FORCEWAKE_BLITTER |
613 FORCEWAKE_MEDIA)
614};
615
Chris Wilson907b28c2013-07-19 20:36:52 +0100616struct intel_uncore_funcs {
Deepak Sc8d9a592013-11-23 14:55:42 +0530617 void (*force_wake_get)(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +0200618 enum forcewake_domains domains);
Deepak Sc8d9a592013-11-23 14:55:42 +0530619 void (*force_wake_put)(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +0200620 enum forcewake_domains domains);
Ben Widawsky0b274482013-10-04 21:22:51 -0700621
622 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
623 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
624 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
625 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
626
627 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
628 uint8_t val, bool trace);
629 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
630 uint16_t val, bool trace);
631 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
632 uint32_t val, bool trace);
633 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
634 uint64_t val, bool trace);
Chris Wilson990bbda2012-07-02 11:51:02 -0300635};
636
Chris Wilson907b28c2013-07-19 20:36:52 +0100637struct intel_uncore {
638 spinlock_t lock; /** lock is also taken in irq contexts. */
639
640 struct intel_uncore_funcs funcs;
641
642 unsigned fifo_count;
Mika Kuoppala48c10262015-01-16 11:34:41 +0200643 enum forcewake_domains fw_domains;
Chris Wilsonaec347a2013-08-26 13:46:09 +0100644
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200645 struct intel_uncore_forcewake_domain {
646 struct drm_i915_private *i915;
Mika Kuoppala48c10262015-01-16 11:34:41 +0200647 enum forcewake_domain_id id;
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200648 unsigned wake_count;
649 struct timer_list timer;
Mika Kuoppala05a2fb12015-01-19 16:20:43 +0200650 u32 reg_set;
651 u32 val_set;
652 u32 val_clear;
653 u32 reg_ack;
654 u32 reg_post;
655 u32 val_reset;
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200656 } fw_domain[FW_DOMAIN_ID_COUNT];
Chris Wilson907b28c2013-07-19 20:36:52 +0100657};
658
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200659/* Iterate over initialised fw domains */
660#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
661 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
662 (i__) < FW_DOMAIN_ID_COUNT; \
663 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
664 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
665
666#define for_each_fw_domain(domain__, dev_priv__, i__) \
667 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
668
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100669#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
670 func(is_mobile) sep \
671 func(is_i85x) sep \
672 func(is_i915g) sep \
673 func(is_i945gm) sep \
674 func(is_g33) sep \
675 func(need_gfx_hws) sep \
676 func(is_g4x) sep \
677 func(is_pineview) sep \
678 func(is_broadwater) sep \
679 func(is_crestline) sep \
680 func(is_ivybridge) sep \
681 func(is_valleyview) sep \
682 func(is_haswell) sep \
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +0530683 func(is_skylake) sep \
Ben Widawskyb833d682013-08-23 16:00:07 -0700684 func(is_preliminary) sep \
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100685 func(has_fbc) sep \
686 func(has_pipe_cxsr) sep \
687 func(has_hotplug) sep \
688 func(cursor_needs_physical) sep \
689 func(has_overlay) sep \
690 func(overlay_needs_physical) sep \
691 func(supports_tv) sep \
Damien Lespiaudd93be52013-04-22 18:40:39 +0100692 func(has_llc) sep \
Damien Lespiau30568c42013-04-22 18:40:41 +0100693 func(has_ddi) sep \
694 func(has_fpga_dbg)
Daniel Vetterc96ea642012-08-08 22:01:51 +0200695
Damien Lespiaua587f772013-04-22 18:40:38 +0100696#define DEFINE_FLAG(name) u8 name:1
697#define SEP_SEMICOLON ;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200698
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500699struct intel_device_info {
Ville Syrjälä10fce672013-01-24 15:29:28 +0200700 u32 display_mmio_offset;
Chris Wilson87f1f462014-08-09 19:18:42 +0100701 u16 device_id;
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700702 u8 num_pipes:3;
Damien Lespiaud615a162014-03-03 17:31:48 +0000703 u8 num_sprites[I915_MAX_PIPES];
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000704 u8 gen;
Ben Widawsky73ae4782013-10-15 10:02:57 -0700705 u8 ring_mask; /* Rings supported by the HW */
Damien Lespiaua587f772013-04-22 18:40:38 +0100706 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200707 /* Register offsets for the various display pipes and transcoders */
708 int pipe_offsets[I915_MAX_TRANSCODERS];
709 int trans_offsets[I915_MAX_TRANSCODERS];
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200710 int palette_offsets[I915_MAX_PIPES];
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300711 int cursor_offsets[I915_MAX_PIPES];
Jeff McGee38732182015-02-13 10:27:54 -0600712
713 /* Slice/subslice/EU info */
714 u8 slice_total;
715 u8 subslice_total;
716 u8 subslice_per_slice;
717 u8 eu_total;
718 u8 eu_per_subslice;
Damien Lespiaub7668792015-02-14 18:30:29 +0000719 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
720 u8 subslice_7eu[3];
Jeff McGee38732182015-02-13 10:27:54 -0600721 u8 has_slice_pg:1;
722 u8 has_subslice_pg:1;
723 u8 has_eu_pg:1;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500724};
725
Damien Lespiaua587f772013-04-22 18:40:38 +0100726#undef DEFINE_FLAG
727#undef SEP_SEMICOLON
728
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800729enum i915_cache_level {
730 I915_CACHE_NONE = 0,
Chris Wilson350ec882013-08-06 13:17:02 +0100731 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
732 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
733 caches, eg sampler/render caches, and the
734 large Last-Level-Cache. LLC is coherent with
735 the CPU, but L3 is only visible to the GPU. */
Chris Wilson651d7942013-08-08 14:41:10 +0100736 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800737};
738
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300739struct i915_ctx_hang_stats {
740 /* This context had batch pending when hang was declared */
741 unsigned batch_pending;
742
743 /* This context had batch active when hang was declared */
744 unsigned batch_active;
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300745
746 /* Time when this context was last blamed for a GPU reset */
747 unsigned long guilty_ts;
748
Chris Wilson676fa572014-12-24 08:13:39 -0800749 /* If the contexts causes a second GPU hang within this time,
750 * it is permanently banned from submitting any more work.
751 */
752 unsigned long ban_period_seconds;
753
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300754 /* This context is banned to submit more work */
755 bool banned;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300756};
Ben Widawsky40521052012-06-04 14:42:43 -0700757
758/* This must match up with the value previously used for execbuf2.rsvd1. */
Oscar Mateo821d66d2014-07-03 16:28:00 +0100759#define DEFAULT_CONTEXT_HANDLE 0
Oscar Mateo31b7a882014-07-03 16:28:01 +0100760/**
761 * struct intel_context - as the name implies, represents a context.
762 * @ref: reference count.
763 * @user_handle: userspace tracking identity for this context.
764 * @remap_slice: l3 row remapping information.
765 * @file_priv: filp associated with this context (NULL for global default
766 * context).
767 * @hang_stats: information about the role of this context in possible GPU
768 * hangs.
769 * @vm: virtual memory space used by this context.
770 * @legacy_hw_ctx: render context backing object and whether it is correctly
771 * initialized (legacy ring submission mechanism only).
772 * @link: link in the global list of contexts.
773 *
774 * Contexts are memory images used by the hardware to store copies of their
775 * internal state.
776 */
Oscar Mateo273497e2014-05-22 14:13:37 +0100777struct intel_context {
Mika Kuoppaladce32712013-04-30 13:30:33 +0300778 struct kref ref;
Oscar Mateo821d66d2014-07-03 16:28:00 +0100779 int user_handle;
Ben Widawsky3ccfd192013-09-18 19:03:18 -0700780 uint8_t remap_slice;
Ben Widawsky40521052012-06-04 14:42:43 -0700781 struct drm_i915_file_private *file_priv;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300782 struct i915_ctx_hang_stats hang_stats;
Daniel Vetterae6c4802014-08-06 15:04:53 +0200783 struct i915_hw_ppgtt *ppgtt;
Ben Widawskya33afea2013-09-17 21:12:45 -0700784
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100785 /* Legacy ring buffer submission */
Oscar Mateoea0c76f2014-07-03 16:27:59 +0100786 struct {
787 struct drm_i915_gem_object *rcs_state;
788 bool initialized;
789 } legacy_hw_ctx;
790
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100791 /* Execlists */
Oscar Mateo564ddb22014-08-21 11:40:54 +0100792 bool rcs_initialized;
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100793 struct {
794 struct drm_i915_gem_object *state;
Oscar Mateo84c23772014-07-24 17:04:15 +0100795 struct intel_ringbuffer *ringbuf;
Mika Kuoppalaa7cbede2015-01-13 11:32:25 +0200796 int pin_count;
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100797 } engine[I915_NUM_RINGS];
798
Ben Widawskya33afea2013-09-17 21:12:45 -0700799 struct list_head link;
Ben Widawsky40521052012-06-04 14:42:43 -0700800};
801
Paulo Zanonia4001f12015-02-13 17:23:44 -0200802enum fb_op_origin {
803 ORIGIN_GTT,
804 ORIGIN_CPU,
805 ORIGIN_CS,
806 ORIGIN_FLIP,
807};
808
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700809struct i915_fbc {
Jani Nikula60ee5cd2015-02-05 12:04:27 +0200810 unsigned long uncompressed_size;
Ben Widawsky5e59f712014-06-30 10:41:24 -0700811 unsigned threshold;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700812 unsigned int fb_id;
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200813 unsigned int possible_framebuffer_bits;
814 unsigned int busy_bits;
Paulo Zanonie35fef22015-02-09 14:46:29 -0200815 struct intel_crtc *crtc;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700816 int y;
817
Ben Widawskyc4213882014-06-19 12:06:10 -0700818 struct drm_mm_node compressed_fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700819 struct drm_mm_node *compressed_llb;
820
Rodrigo Vivida46f932014-08-01 02:04:45 -0700821 bool false_color;
822
Paulo Zanoni9adccc62014-09-19 16:04:55 -0300823 /* Tracks whether the HW is actually enabled, not whether the feature is
824 * possible. */
825 bool enabled;
826
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700827 struct intel_fbc_work {
828 struct delayed_work work;
829 struct drm_crtc *crtc;
830 struct drm_framebuffer *fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700831 } *fbc_work;
832
Chris Wilson29ebf902013-07-27 17:23:55 +0100833 enum no_fbc_reason {
834 FBC_OK, /* FBC is enabled */
835 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700836 FBC_NO_OUTPUT, /* no outputs enabled to compress */
837 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
838 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
839 FBC_MODE_TOO_LARGE, /* mode too large for compression */
840 FBC_BAD_PLANE, /* fbc not supported on plane */
841 FBC_NOT_TILED, /* buffer not tiled */
842 FBC_MULTIPLE_PIPES, /* more than one pipe active */
843 FBC_MODULE_PARAM,
844 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
845 } no_fbc_reason;
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800846};
847
Vandana Kannan96178ee2015-01-10 02:25:56 +0530848/**
849 * HIGH_RR is the highest eDP panel refresh rate read from EDID
850 * LOW_RR is the lowest eDP panel refresh rate found from EDID
851 * parsing for same resolution.
852 */
853enum drrs_refresh_rate_type {
854 DRRS_HIGH_RR,
855 DRRS_LOW_RR,
856 DRRS_MAX_RR, /* RR count */
857};
858
859enum drrs_support_type {
860 DRRS_NOT_SUPPORTED = 0,
861 STATIC_DRRS_SUPPORT = 1,
862 SEAMLESS_DRRS_SUPPORT = 2
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530863};
864
Daniel Vetter2807cf62014-07-11 10:30:11 -0700865struct intel_dp;
Vandana Kannan96178ee2015-01-10 02:25:56 +0530866struct i915_drrs {
867 struct mutex mutex;
868 struct delayed_work work;
869 struct intel_dp *dp;
870 unsigned busy_frontbuffer_bits;
871 enum drrs_refresh_rate_type refresh_rate_type;
872 enum drrs_support_type type;
873};
874
Rodrigo Vivia031d702013-10-03 16:15:06 -0300875struct i915_psr {
Daniel Vetterf0355c42014-07-11 10:30:15 -0700876 struct mutex lock;
Rodrigo Vivia031d702013-10-03 16:15:06 -0300877 bool sink_support;
878 bool source_ok;
Daniel Vetter2807cf62014-07-11 10:30:11 -0700879 struct intel_dp *enabled;
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -0700880 bool active;
881 struct delayed_work work;
Daniel Vetter9ca15302014-07-11 10:30:16 -0700882 unsigned busy_frontbuffer_bits;
Rodrigo Vivi0243f7b2015-01-12 10:14:32 -0800883 bool link_standby;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -0300884};
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700885
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800886enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300887 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800888 PCH_IBX, /* Ibexpeak PCH */
889 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300890 PCH_LPT, /* Lynxpoint PCH */
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530891 PCH_SPT, /* Sunrisepoint PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -0700892 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800893};
894
Paulo Zanoni988d6ee2012-12-01 12:04:24 -0200895enum intel_sbi_destination {
896 SBI_ICLK,
897 SBI_MPHY,
898};
899
Jesse Barnesb690e962010-07-19 13:53:12 -0700900#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -0700901#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +0100902#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Scot Doyle9c72cc62014-07-03 23:27:50 +0000903#define QUIRK_BACKLIGHT_PRESENT (1<<3)
Ville Syrjäläb6b5d042014-08-15 01:22:07 +0300904#define QUIRK_PIPEB_FORCE (1<<4)
Daniel Vetter656bfa32014-11-20 09:26:30 +0100905#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
Jesse Barnesb690e962010-07-19 13:53:12 -0700906
Dave Airlie8be48d92010-03-30 05:34:14 +0000907struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +0100908struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +0000909
Daniel Vetterc2b91522012-02-14 22:37:19 +0100910struct intel_gmbus {
911 struct i2c_adapter adapter;
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000912 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100913 u32 reg0;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100914 u32 gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100915 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100916 struct drm_i915_private *dev_priv;
917};
918
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100919struct i915_suspend_saved_registers {
Keith Packarde948e992008-05-07 12:27:53 +1000920 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000921 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700922 u32 savePP_ON_DELAYS;
923 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000924 u32 savePP_ON;
925 u32 savePP_OFF;
926 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700927 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000928 u32 saveFBC_CONTROL;
Keith Packard1f84e552008-02-16 19:19:29 -0800929 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -0800930 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000931 u32 saveSWF0[16];
932 u32 saveSWF1[16];
933 u32 saveSWF2[3];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200934 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Adam Jacksoncda2bb72011-07-26 16:53:06 -0400935 u32 savePCH_PORT_HOTPLUG;
Jesse Barnes9f49c372014-12-10 12:16:05 -0800936 u16 saveGCDGMBUS;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100937};
Daniel Vetterc85aa882012-11-02 19:55:03 +0100938
Imre Deakddeea5b2014-05-05 15:19:56 +0300939struct vlv_s0ix_state {
940 /* GAM */
941 u32 wr_watermark;
942 u32 gfx_prio_ctrl;
943 u32 arb_mode;
944 u32 gfx_pend_tlb0;
945 u32 gfx_pend_tlb1;
946 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
947 u32 media_max_req_count;
948 u32 gfx_max_req_count;
949 u32 render_hwsp;
950 u32 ecochk;
951 u32 bsd_hwsp;
952 u32 blt_hwsp;
953 u32 tlb_rd_addr;
954
955 /* MBC */
956 u32 g3dctl;
957 u32 gsckgctl;
958 u32 mbctl;
959
960 /* GCP */
961 u32 ucgctl1;
962 u32 ucgctl3;
963 u32 rcgctl1;
964 u32 rcgctl2;
965 u32 rstctl;
966 u32 misccpctl;
967
968 /* GPM */
969 u32 gfxpause;
970 u32 rpdeuhwtc;
971 u32 rpdeuc;
972 u32 ecobus;
973 u32 pwrdwnupctl;
974 u32 rp_down_timeout;
975 u32 rp_deucsw;
976 u32 rcubmabdtmr;
977 u32 rcedata;
978 u32 spare2gh;
979
980 /* Display 1 CZ domain */
981 u32 gt_imr;
982 u32 gt_ier;
983 u32 pm_imr;
984 u32 pm_ier;
985 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
986
987 /* GT SA CZ domain */
988 u32 tilectl;
989 u32 gt_fifoctl;
990 u32 gtlc_wake_ctrl;
991 u32 gtlc_survive;
992 u32 pmwgicz;
993
994 /* Display 2 CZ domain */
995 u32 gu_ctl0;
996 u32 gu_ctl1;
997 u32 clock_gate_dis2;
998};
999
Chris Wilsonbf225f22014-07-10 20:31:18 +01001000struct intel_rps_ei {
1001 u32 cz_clock;
1002 u32 render_c0;
1003 u32 media_c0;
Deepak S31685c22014-07-03 17:33:01 -04001004};
1005
Daniel Vetterc85aa882012-11-02 19:55:03 +01001006struct intel_gen6_power_mgmt {
Imre Deakd4d70aa2014-11-19 15:30:04 +02001007 /*
1008 * work, interrupts_enabled and pm_iir are protected by
1009 * dev_priv->irq_lock
1010 */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001011 struct work_struct work;
Imre Deakd4d70aa2014-11-19 15:30:04 +02001012 bool interrupts_enabled;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001013 u32 pm_iir;
Daniel Vetter59cdb632013-07-04 23:35:28 +02001014
Ben Widawskyb39fb292014-03-19 18:31:11 -07001015 /* Frequencies are stored in potentially platform dependent multiples.
1016 * In other words, *_freq needs to be multiplied by X to be interesting.
1017 * Soft limits are those which are used for the dynamic reclocking done
1018 * by the driver (raise frequencies under heavy loads, and lower for
1019 * lighter loads). Hard limits are those imposed by the hardware.
1020 *
1021 * A distinction is made for overclocking, which is never enabled by
1022 * default, and is considered to be above the hard limit if it's
1023 * possible at all.
1024 */
1025 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1026 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1027 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1028 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1029 u8 min_freq; /* AKA RPn. Minimum frequency */
Chris Wilsonaed242f2015-03-18 09:48:21 +00001030 u8 idle_freq; /* Frequency to request when we are idle */
Ben Widawskyb39fb292014-03-19 18:31:11 -07001031 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1032 u8 rp1_freq; /* "less than" RP0 power/freqency */
1033 u8 rp0_freq; /* Non-overclocked max frequency. */
Deepak S67c3bf62014-07-10 13:16:24 +05301034 u32 cz_freq;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001035
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001036 int last_adj;
1037 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1038
Chris Wilsonc0951f02013-10-10 21:58:50 +01001039 bool enabled;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001040 struct delayed_work delayed_resume_work;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001041
Chris Wilsonbf225f22014-07-10 20:31:18 +01001042 /* manual wa residency calculations */
1043 struct intel_rps_ei up_ei, down_ei;
1044
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001045 /*
1046 * Protects RPS/RC6 register access and PCU communication.
1047 * Must be taken after struct_mutex if nested.
1048 */
1049 struct mutex hw_lock;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001050};
1051
Daniel Vetter1a240d42012-11-29 22:18:51 +01001052/* defined intel_pm.c */
1053extern spinlock_t mchdev_lock;
1054
Daniel Vetterc85aa882012-11-02 19:55:03 +01001055struct intel_ilk_power_mgmt {
1056 u8 cur_delay;
1057 u8 min_delay;
1058 u8 max_delay;
1059 u8 fmax;
1060 u8 fstart;
1061
1062 u64 last_count1;
1063 unsigned long last_time1;
1064 unsigned long chipset_power;
1065 u64 last_count2;
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001066 u64 last_time2;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001067 unsigned long gfx_power;
1068 u8 corr;
1069
1070 int c_m;
1071 int r_t;
1072};
1073
Imre Deakc6cb5822014-03-04 19:22:55 +02001074struct drm_i915_private;
1075struct i915_power_well;
1076
1077struct i915_power_well_ops {
1078 /*
1079 * Synchronize the well's hw state to match the current sw state, for
1080 * example enable/disable it based on the current refcount. Called
1081 * during driver init and resume time, possibly after first calling
1082 * the enable/disable handlers.
1083 */
1084 void (*sync_hw)(struct drm_i915_private *dev_priv,
1085 struct i915_power_well *power_well);
1086 /*
1087 * Enable the well and resources that depend on it (for example
1088 * interrupts located on the well). Called after the 0->1 refcount
1089 * transition.
1090 */
1091 void (*enable)(struct drm_i915_private *dev_priv,
1092 struct i915_power_well *power_well);
1093 /*
1094 * Disable the well and resources that depend on it. Called after
1095 * the 1->0 refcount transition.
1096 */
1097 void (*disable)(struct drm_i915_private *dev_priv,
1098 struct i915_power_well *power_well);
1099 /* Returns the hw enabled state. */
1100 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1101 struct i915_power_well *power_well);
1102};
1103
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001104/* Power well structure for haswell */
1105struct i915_power_well {
Imre Deakc1ca7272013-11-25 17:15:29 +02001106 const char *name;
Imre Deak6f3ef5d2013-11-25 17:15:30 +02001107 bool always_on;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001108 /* power well enable/disable usage count */
1109 int count;
Imre Deakbfafe932014-06-05 20:31:47 +03001110 /* cached hw enabled state */
1111 bool hw_enabled;
Imre Deakc1ca7272013-11-25 17:15:29 +02001112 unsigned long domains;
Imre Deak77961eb2014-03-05 16:20:56 +02001113 unsigned long data;
Imre Deakc6cb5822014-03-04 19:22:55 +02001114 const struct i915_power_well_ops *ops;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001115};
1116
Imre Deak83c00f552013-10-25 17:36:47 +03001117struct i915_power_domains {
Imre Deakbaa70702013-10-25 17:36:48 +03001118 /*
1119 * Power wells needed for initialization at driver init and suspend
1120 * time are on. They are kept on until after the first modeset.
1121 */
1122 bool init_power_on;
Imre Deak0d116a22014-04-25 13:19:05 +03001123 bool initializing;
Imre Deakc1ca7272013-11-25 17:15:29 +02001124 int power_well_count;
Imre Deakbaa70702013-10-25 17:36:48 +03001125
Imre Deak83c00f552013-10-25 17:36:47 +03001126 struct mutex lock;
Imre Deak1da51582013-11-25 17:15:35 +02001127 int domain_use_count[POWER_DOMAIN_NUM];
Imre Deakc1ca7272013-11-25 17:15:29 +02001128 struct i915_power_well *power_wells;
Imre Deak83c00f552013-10-25 17:36:47 +03001129};
1130
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001131#define MAX_L3_SLICES 2
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001132struct intel_l3_parity {
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001133 u32 *remap_info[MAX_L3_SLICES];
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001134 struct work_struct error_work;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001135 int which_slice;
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001136};
1137
Brad Volkin493018d2014-12-11 12:13:08 -08001138struct i915_gem_batch_pool {
1139 struct drm_device *dev;
1140 struct list_head cache_list;
1141};
1142
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001143struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001144 /** Memory allocator for GTT stolen memory */
1145 struct drm_mm stolen;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001146 /** List of all objects in gtt_space. Used to restore gtt
1147 * mappings on resume */
1148 struct list_head bound_list;
1149 /**
1150 * List of objects which are not bound to the GTT (thus
1151 * are idle and not used by the GPU) but still have
1152 * (presumably uncached) pages still attached.
1153 */
1154 struct list_head unbound_list;
1155
Brad Volkin493018d2014-12-11 12:13:08 -08001156 /*
1157 * A pool of objects to use as shadow copies of client batch buffers
1158 * when the command parser is enabled. Prevents the client from
1159 * modifying the batch contents after software parsing.
1160 */
1161 struct i915_gem_batch_pool batch_pool;
1162
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001163 /** Usable portion of the GTT for GEM */
1164 unsigned long stolen_base; /* limited to low memory (32-bit) */
1165
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001166 /** PPGTT used for aliasing the PPGTT with the GTT */
1167 struct i915_hw_ppgtt *aliasing_ppgtt;
1168
Chris Wilson2cfcd322014-05-20 08:28:43 +01001169 struct notifier_block oom_notifier;
Chris Wilsonceabbba52014-03-25 13:23:04 +00001170 struct shrinker shrinker;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001171 bool shrinker_no_lock_stealing;
1172
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001173 /** LRU list of objects with fence regs on them. */
1174 struct list_head fence_list;
1175
1176 /**
1177 * We leave the user IRQ off as much as possible,
1178 * but this means that requests will finish and never
1179 * be retired once the system goes idle. Set a timer to
1180 * fire periodically while the ring is running. When it
1181 * fires, go retire requests.
1182 */
1183 struct delayed_work retire_work;
1184
1185 /**
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001186 * When we detect an idle GPU, we want to turn on
1187 * powersaving features. So once we see that there
1188 * are no more requests outstanding and no more
1189 * arrive within a small period of time, we fire
1190 * off the idle_work.
1191 */
1192 struct delayed_work idle_work;
1193
1194 /**
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001195 * Are we in a non-interruptible section of code like
1196 * modesetting?
1197 */
1198 bool interruptible;
1199
Chris Wilsonf62a0072014-02-21 17:55:39 +00001200 /**
1201 * Is the GPU currently considered idle, or busy executing userspace
1202 * requests? Whilst idle, we attempt to power down the hardware and
1203 * display clocks. In order to reduce the effect on performance, there
1204 * is a slight delay before we do so.
1205 */
1206 bool busy;
1207
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001208 /* the indicator for dispatch video commands on two BSD rings */
1209 int bsd_ring_dispatch_index;
1210
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001211 /** Bit 6 swizzling required for X tiling */
1212 uint32_t bit_6_swizzle_x;
1213 /** Bit 6 swizzling required for Y tiling */
1214 uint32_t bit_6_swizzle_y;
1215
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001216 /* accounting, useful for userland debugging */
Daniel Vetterc20e8352013-07-24 22:40:23 +02001217 spinlock_t object_stat_lock;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001218 size_t object_memory;
1219 u32 object_count;
1220};
1221
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001222struct drm_i915_error_state_buf {
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01001223 struct drm_i915_private *i915;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001224 unsigned bytes;
1225 unsigned size;
1226 int err;
1227 u8 *buf;
1228 loff_t start;
1229 loff_t pos;
1230};
1231
Mika Kuoppalafc16b482013-06-06 15:18:39 +03001232struct i915_error_state_file_priv {
1233 struct drm_device *dev;
1234 struct drm_i915_error_state *error;
1235};
1236
Daniel Vetter99584db2012-11-14 17:14:04 +01001237struct i915_gpu_error {
1238 /* For hangcheck timer */
1239#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1240#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03001241 /* Hang gpu twice in this window and your context gets banned */
1242#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1243
Chris Wilson737b1502015-01-26 18:03:03 +02001244 struct workqueue_struct *hangcheck_wq;
1245 struct delayed_work hangcheck_work;
Daniel Vetter99584db2012-11-14 17:14:04 +01001246
1247 /* For reset and error_state handling. */
1248 spinlock_t lock;
1249 /* Protected by the above dev->gpu_error.lock. */
1250 struct drm_i915_error_state *first_error;
Chris Wilson094f9a52013-09-25 17:34:55 +01001251
1252 unsigned long missed_irq_rings;
1253
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001254 /**
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001255 * State variable controlling the reset flow and count
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001256 *
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001257 * This is a counter which gets incremented when reset is triggered,
1258 * and again when reset has been handled. So odd values (lowest bit set)
1259 * means that reset is in progress and even values that
1260 * (reset_counter >> 1):th reset was successfully completed.
1261 *
1262 * If reset is not completed succesfully, the I915_WEDGE bit is
1263 * set meaning that hardware is terminally sour and there is no
1264 * recovery. All waiters on the reset_queue will be woken when
1265 * that happens.
1266 *
1267 * This counter is used by the wait_seqno code to notice that reset
1268 * event happened and it needs to restart the entire ioctl (since most
1269 * likely the seqno it waited for won't ever signal anytime soon).
Daniel Vetterf69061b2012-12-06 09:01:42 +01001270 *
1271 * This is important for lock-free wait paths, where no contended lock
1272 * naturally enforces the correct ordering between the bail-out of the
1273 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001274 */
1275 atomic_t reset_counter;
1276
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001277#define I915_RESET_IN_PROGRESS_FLAG 1
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001278#define I915_WEDGED (1 << 31)
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001279
1280 /**
1281 * Waitqueue to signal when the reset has completed. Used by clients
1282 * that wait for dev_priv->mm.wedged to settle.
1283 */
1284 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +01001285
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02001286 /* Userspace knobs for gpu hang simulation;
1287 * combines both a ring mask, and extra flags
1288 */
1289 u32 stop_rings;
1290#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1291#define I915_STOP_RING_ALLOW_WARN (1 << 30)
Chris Wilson094f9a52013-09-25 17:34:55 +01001292
1293 /* For missed irq/seqno simulation. */
1294 unsigned int test_irq_rings;
McAulay, Alistair6689c162014-08-15 18:51:35 +01001295
1296 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1297 bool reload_in_reset;
Daniel Vetter99584db2012-11-14 17:14:04 +01001298};
1299
Zhang Ruib8efb172013-02-05 15:41:53 +08001300enum modeset_restore {
1301 MODESET_ON_LID_OPEN,
1302 MODESET_DONE,
1303 MODESET_SUSPENDED,
1304};
1305
Paulo Zanoni6acab152013-09-12 17:06:24 -03001306struct ddi_vbt_port_info {
Damien Lespiauce4dd492014-08-01 11:07:54 +01001307 /*
1308 * This is an index in the HDMI/DVI DDI buffer translation table.
1309 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1310 * populate this field.
1311 */
1312#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
Paulo Zanoni6acab152013-09-12 17:06:24 -03001313 uint8_t hdmi_level_shift;
Paulo Zanoni311a2092013-09-12 17:12:18 -03001314
1315 uint8_t supports_dvi:1;
1316 uint8_t supports_hdmi:1;
1317 uint8_t supports_dp:1;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001318};
1319
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001320enum psr_lines_to_wait {
1321 PSR_0_LINES_TO_WAIT = 0,
1322 PSR_1_LINE_TO_WAIT,
1323 PSR_4_LINES_TO_WAIT,
1324 PSR_8_LINES_TO_WAIT
Pradeep Bhat83a72802014-03-28 10:14:57 +05301325};
1326
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001327struct intel_vbt_data {
1328 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1329 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1330
1331 /* Feature bits */
1332 unsigned int int_tv_support:1;
1333 unsigned int lvds_dither:1;
1334 unsigned int lvds_vbt:1;
1335 unsigned int int_crt_support:1;
1336 unsigned int lvds_use_ssc:1;
1337 unsigned int display_clock_mode:1;
1338 unsigned int fdi_rx_polarity_inverted:1;
Shobhit Kumar3e6bd012014-05-27 19:33:59 +05301339 unsigned int has_mipi:1;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001340 int lvds_ssc_freq;
1341 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1342
Pradeep Bhat83a72802014-03-28 10:14:57 +05301343 enum drrs_support_type drrs_type;
1344
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001345 /* eDP */
1346 int edp_rate;
1347 int edp_lanes;
1348 int edp_preemphasis;
1349 int edp_vswing;
1350 bool edp_initialized;
1351 bool edp_support;
1352 int edp_bpp;
Sonika Jindal9a57f5b2015-02-25 10:29:11 +05301353 bool edp_low_vswing;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001354 struct edp_power_seq edp_pps;
1355
Jani Nikulaf00076d2013-12-14 20:38:29 -02001356 struct {
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001357 bool full_link;
1358 bool require_aux_wakeup;
1359 int idle_frames;
1360 enum psr_lines_to_wait lines_to_wait;
1361 int tp1_wakeup_time;
1362 int tp2_tp3_wakeup_time;
1363 } psr;
1364
1365 struct {
Jani Nikulaf00076d2013-12-14 20:38:29 -02001366 u16 pwm_freq_hz;
Jani Nikula39fbc9c2014-04-09 11:22:06 +03001367 bool present;
Jani Nikulaf00076d2013-12-14 20:38:29 -02001368 bool active_low_pwm;
Jani Nikula1de60682014-06-24 18:27:39 +03001369 u8 min_brightness; /* min_brightness/255 of max */
Jani Nikulaf00076d2013-12-14 20:38:29 -02001370 } backlight;
1371
Shobhit Kumard17c5442013-08-27 15:12:25 +03001372 /* MIPI DSI */
1373 struct {
Shobhit Kumar3e6bd012014-05-27 19:33:59 +05301374 u16 port;
Shobhit Kumard17c5442013-08-27 15:12:25 +03001375 u16 panel_id;
Shobhit Kumard3b542f2014-04-14 11:00:34 +05301376 struct mipi_config *config;
1377 struct mipi_pps_data *pps;
1378 u8 seq_version;
1379 u32 size;
1380 u8 *data;
1381 u8 *sequence[MIPI_SEQ_MAX];
Shobhit Kumard17c5442013-08-27 15:12:25 +03001382 } dsi;
1383
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001384 int crt_ddc_pin;
1385
1386 int child_dev_num;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03001387 union child_device_config *child_dev;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001388
1389 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001390};
1391
Ville Syrjälä77c122b2013-08-06 22:24:04 +03001392enum intel_ddb_partitioning {
1393 INTEL_DDB_PART_1_2,
1394 INTEL_DDB_PART_5_6, /* IVB+ */
1395};
1396
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03001397struct intel_wm_level {
1398 bool enable;
1399 uint32_t pri_val;
1400 uint32_t spr_val;
1401 uint32_t cur_val;
1402 uint32_t fbc_val;
1403};
1404
Imre Deak820c1982013-12-17 14:46:36 +02001405struct ilk_wm_values {
Ville Syrjälä609cede2013-10-09 19:18:03 +03001406 uint32_t wm_pipe[3];
1407 uint32_t wm_lp[3];
1408 uint32_t wm_lp_spr[3];
1409 uint32_t wm_linetime[3];
1410 bool enable_fbc_wm;
1411 enum intel_ddb_partitioning partitioning;
1412};
1413
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001414struct vlv_wm_values {
1415 struct {
Ville Syrjäläae801522015-03-05 21:19:49 +02001416 uint16_t primary;
1417 uint16_t sprite[2];
1418 uint8_t cursor;
1419 } pipe[3];
1420
1421 struct {
1422 uint16_t plane;
1423 uint8_t cursor;
1424 } sr;
1425
1426 struct {
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001427 uint8_t cursor;
1428 uint8_t sprite[2];
1429 uint8_t primary;
1430 } ddl[3];
1431};
1432
Damien Lespiauc1939242014-11-04 17:06:41 +00001433struct skl_ddb_entry {
Damien Lespiau16160e32014-11-04 17:06:53 +00001434 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
Damien Lespiauc1939242014-11-04 17:06:41 +00001435};
1436
1437static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1438{
Damien Lespiau16160e32014-11-04 17:06:53 +00001439 return entry->end - entry->start;
Damien Lespiauc1939242014-11-04 17:06:41 +00001440}
1441
Damien Lespiau08db6652014-11-04 17:06:52 +00001442static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1443 const struct skl_ddb_entry *e2)
1444{
1445 if (e1->start == e2->start && e1->end == e2->end)
1446 return true;
1447
1448 return false;
1449}
1450
Damien Lespiauc1939242014-11-04 17:06:41 +00001451struct skl_ddb_allocation {
Damien Lespiau34bb56a2014-11-04 17:07:01 +00001452 struct skl_ddb_entry pipe[I915_MAX_PIPES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001453 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1454 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1455};
1456
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001457struct skl_wm_values {
1458 bool dirty[I915_MAX_PIPES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001459 struct skl_ddb_allocation ddb;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001460 uint32_t wm_linetime[I915_MAX_PIPES];
1461 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1462 uint32_t cursor[I915_MAX_PIPES][8];
1463 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1464 uint32_t cursor_trans[I915_MAX_PIPES];
1465};
1466
1467struct skl_wm_level {
1468 bool plane_en[I915_MAX_PLANES];
Damien Lespiaub99f58d2014-11-04 17:06:56 +00001469 bool cursor_en;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001470 uint16_t plane_res_b[I915_MAX_PLANES];
1471 uint8_t plane_res_l[I915_MAX_PLANES];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001472 uint16_t cursor_res_b;
1473 uint8_t cursor_res_l;
1474};
1475
Paulo Zanonic67a4702013-08-19 13:18:09 -03001476/*
Paulo Zanoni765dab62014-03-07 20:08:18 -03001477 * This struct helps tracking the state needed for runtime PM, which puts the
1478 * device in PCI D3 state. Notice that when this happens, nothing on the
1479 * graphics device works, even register access, so we don't get interrupts nor
1480 * anything else.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001481 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001482 * Every piece of our code that needs to actually touch the hardware needs to
1483 * either call intel_runtime_pm_get or call intel_display_power_get with the
1484 * appropriate power domain.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001485 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001486 * Our driver uses the autosuspend delay feature, which means we'll only really
1487 * suspend if we stay with zero refcount for a certain amount of time. The
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001488 * default value is currently very conservative (see intel_runtime_pm_enable), but
Paulo Zanoni765dab62014-03-07 20:08:18 -03001489 * it can be changed with the standard runtime PM files from sysfs.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001490 *
1491 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1492 * goes back to false exactly before we reenable the IRQs. We use this variable
1493 * to check if someone is trying to enable/disable IRQs while they're supposed
1494 * to be disabled. This shouldn't happen and we'll print some error messages in
Paulo Zanoni730488b2014-03-07 20:12:32 -03001495 * case it happens.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001496 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001497 * For more, read the Documentation/power/runtime_pm.txt.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001498 */
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001499struct i915_runtime_pm {
1500 bool suspended;
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02001501 bool irqs_enabled;
Paulo Zanonic67a4702013-08-19 13:18:09 -03001502};
1503
Daniel Vetter926321d2013-10-16 13:30:34 +02001504enum intel_pipe_crc_source {
1505 INTEL_PIPE_CRC_SOURCE_NONE,
1506 INTEL_PIPE_CRC_SOURCE_PLANE1,
1507 INTEL_PIPE_CRC_SOURCE_PLANE2,
1508 INTEL_PIPE_CRC_SOURCE_PF,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001509 INTEL_PIPE_CRC_SOURCE_PIPE,
Daniel Vetter3d099a02013-10-16 22:55:58 +02001510 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1511 INTEL_PIPE_CRC_SOURCE_TV,
1512 INTEL_PIPE_CRC_SOURCE_DP_B,
1513 INTEL_PIPE_CRC_SOURCE_DP_C,
1514 INTEL_PIPE_CRC_SOURCE_DP_D,
Daniel Vetter46a19182013-11-01 10:50:20 +01001515 INTEL_PIPE_CRC_SOURCE_AUTO,
Daniel Vetter926321d2013-10-16 13:30:34 +02001516 INTEL_PIPE_CRC_SOURCE_MAX,
1517};
1518
Shuang He8bf1e9f2013-10-15 18:55:27 +01001519struct intel_pipe_crc_entry {
Damien Lespiauac2300d2013-10-15 18:55:30 +01001520 uint32_t frame;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001521 uint32_t crc[5];
1522};
1523
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001524#define INTEL_PIPE_CRC_ENTRIES_NR 128
Shuang He8bf1e9f2013-10-15 18:55:27 +01001525struct intel_pipe_crc {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001526 spinlock_t lock;
1527 bool opened; /* exclusive access to the result file */
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01001528 struct intel_pipe_crc_entry *entries;
Daniel Vetter926321d2013-10-16 13:30:34 +02001529 enum intel_pipe_crc_source source;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001530 int head, tail;
Damien Lespiau07144422013-10-15 18:55:40 +01001531 wait_queue_head_t wq;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001532};
1533
Daniel Vetterf99d7062014-06-19 16:01:59 +02001534struct i915_frontbuffer_tracking {
1535 struct mutex lock;
1536
1537 /*
1538 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1539 * scheduled flips.
1540 */
1541 unsigned busy_bits;
1542 unsigned flip_bits;
1543};
1544
Mika Kuoppala72253422014-10-07 17:21:26 +03001545struct i915_wa_reg {
1546 u32 addr;
1547 u32 value;
1548 /* bitmask representing WA bits */
1549 u32 mask;
1550};
1551
1552#define I915_MAX_WA_REGS 16
1553
1554struct i915_workarounds {
1555 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1556 u32 count;
1557};
1558
Yu Zhangcf9d2892015-02-10 19:05:47 +08001559struct i915_virtual_gpu {
1560 bool active;
1561};
1562
Jani Nikula77fec552014-03-31 14:27:22 +03001563struct drm_i915_private {
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001564 struct drm_device *dev;
Chris Wilson42dcedd2012-11-15 11:32:30 +00001565 struct kmem_cache *slab;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001566
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001567 const struct intel_device_info info;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001568
1569 int relative_constants_mode;
1570
1571 void __iomem *regs;
1572
Chris Wilson907b28c2013-07-19 20:36:52 +01001573 struct intel_uncore uncore;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001574
Yu Zhangcf9d2892015-02-10 19:05:47 +08001575 struct i915_virtual_gpu vgpu;
1576
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001577 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1578
Daniel Vetter28c70f12012-12-01 13:53:45 +01001579
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001580 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1581 * controller on different i2c buses. */
1582 struct mutex gmbus_mutex;
1583
1584 /**
1585 * Base address of the gmbus and gpio block.
1586 */
1587 uint32_t gpio_mmio_base;
1588
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301589 /* MMIO base address for MIPI regs */
1590 uint32_t mipi_mmio_base;
1591
Daniel Vetter28c70f12012-12-01 13:53:45 +01001592 wait_queue_head_t gmbus_wait_queue;
1593
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001594 struct pci_dev *bridge_dev;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001595 struct intel_engine_cs ring[I915_NUM_RINGS];
Ben Widawsky3e789982014-06-30 09:53:37 -07001596 struct drm_i915_gem_object *semaphore_obj;
Mika Kuoppalaf72b3432012-12-10 15:41:48 +02001597 uint32_t last_seqno, next_seqno;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001598
Daniel Vetterba8286f2014-09-11 07:43:25 +02001599 struct drm_dma_handle *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001600 struct resource mch_res;
1601
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001602 /* protects the irq masks */
1603 spinlock_t irq_lock;
1604
Sourab Gupta84c33a62014-06-02 16:47:17 +05301605 /* protects the mmio flip data */
1606 spinlock_t mmio_flip_lock;
1607
Imre Deakf8b79e52014-03-04 19:23:07 +02001608 bool display_irqs_enabled;
1609
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001610 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1611 struct pm_qos_request pm_qos;
1612
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001613 /* DPIO indirect register protection */
Daniel Vetter09153002012-12-12 14:06:44 +01001614 struct mutex dpio_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001615
1616 /** Cached value of IMR to avoid reads in updating the bitfield */
Ben Widawskyabd58f02013-11-02 21:07:09 -07001617 union {
1618 u32 irq_mask;
1619 u32 de_irq_mask[I915_MAX_PIPES];
1620 };
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001621 u32 gt_irq_mask;
Paulo Zanoni605cd252013-08-06 18:57:15 -03001622 u32 pm_irq_mask;
Deepak Sa6706b42014-03-15 20:23:22 +05301623 u32 pm_rps_events;
Imre Deak91d181d2014-02-10 18:42:49 +02001624 u32 pipestat_irq_mask[I915_MAX_PIPES];
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001625
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001626 struct work_struct hotplug_work;
Egbert Eichb543fb02013-04-16 13:36:54 +02001627 struct {
1628 unsigned long hpd_last_jiffies;
1629 int hpd_cnt;
1630 enum {
1631 HPD_ENABLED = 0,
1632 HPD_DISABLED = 1,
1633 HPD_MARK_DISABLED = 2
1634 } hpd_mark;
1635 } hpd_stats[HPD_NUM_PINS];
Egbert Eich142e2392013-04-11 15:57:57 +02001636 u32 hpd_event_bits;
Imre Deak63237512014-08-18 15:37:02 +03001637 struct delayed_work hotplug_reenable_work;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001638
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07001639 struct i915_fbc fbc;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05301640 struct i915_drrs drrs;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001641 struct intel_opregion opregion;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001642 struct intel_vbt_data vbt;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001643
Jesse Barnesd9ceb812014-10-09 12:57:43 -07001644 bool preserve_bios_swizzle;
1645
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001646 /* overlay */
1647 struct intel_overlay *overlay;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001648
Jani Nikula58c68772013-11-08 16:48:54 +02001649 /* backlight registers and fields in struct intel_panel */
Daniel Vetter07f11d42014-09-15 14:35:09 +02001650 struct mutex backlight_lock;
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001651
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001652 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001653 bool no_aux_handshake;
1654
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001655 /* protects panel power sequencer state */
1656 struct mutex pps_mutex;
1657
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001658 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1659 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1660 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1661
1662 unsigned int fsb_freq, mem_freq, is_ddr3;
Imre Deakd60c4472014-03-27 17:45:10 +02001663 unsigned int vlv_cdclk_freq;
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03001664 unsigned int hpll_freq;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001665
Daniel Vetter645416f2013-09-02 16:22:25 +02001666 /**
1667 * wq - Driver workqueue for GEM.
1668 *
1669 * NOTE: Work items scheduled here are not allowed to grab any modeset
1670 * locks, for otherwise the flushing done in the pageflip code will
1671 * result in deadlocks.
1672 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001673 struct workqueue_struct *wq;
1674
1675 /* Display functions */
1676 struct drm_i915_display_funcs display;
1677
1678 /* PCH chipset type */
1679 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001680 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001681
1682 unsigned long quirks;
1683
Zhang Ruib8efb172013-02-05 15:41:53 +08001684 enum modeset_restore modeset_restore;
1685 struct mutex modeset_restore_lock;
Eric Anholt673a3942008-07-30 12:06:12 -07001686
Ben Widawskya7bbbd62013-07-16 16:50:07 -07001687 struct list_head vm_list; /* Global list of all address spaces */
Ben Widawsky0260c422014-03-22 22:47:21 -07001688 struct i915_gtt gtt; /* VM representing the global address space */
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001689
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001690 struct i915_gem_mm mm;
Chris Wilsonad46cb52014-08-07 14:20:40 +01001691 DECLARE_HASHTABLE(mm_structs, 7);
1692 struct mutex mm_lock;
Daniel Vetter87813422012-05-02 11:49:32 +02001693
Daniel Vetter87813422012-05-02 11:49:32 +02001694 /* Kernel Modesetting */
1695
yakui_zhao9b9d1722009-05-31 17:17:17 +08001696 struct sdvo_device_mapping sdvo_mappings[2];
Jesse Barnes652c3932009-08-17 13:31:43 -07001697
Damien Lespiau76c4ac02014-02-07 19:12:52 +00001698 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1699 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001700 wait_queue_head_t pending_flip_queue;
1701
Daniel Vetterc4597872013-10-21 21:04:07 +02001702#ifdef CONFIG_DEBUG_FS
1703 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1704#endif
1705
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001706 int num_shared_dpll;
1707 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001708 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001709
Mika Kuoppala72253422014-10-07 17:21:26 +03001710 struct i915_workarounds workarounds;
Arun Siluvery888b5992014-08-26 14:44:51 +01001711
Jesse Barnes652c3932009-08-17 13:31:43 -07001712 /* Reclocking support */
1713 bool render_reclock_avail;
1714 bool lvds_downclock_avail;
Zhao Yakui18f9ed12009-11-20 03:24:16 +00001715 /* indicates the reduced downclock for LVDS*/
1716 int lvds_downclock;
Daniel Vetterf99d7062014-06-19 16:01:59 +02001717
1718 struct i915_frontbuffer_tracking fb_tracking;
1719
Jesse Barnes652c3932009-08-17 13:31:43 -07001720 u16 orig_clock;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001721
Zhenyu Wangc48044112009-12-17 14:48:43 +08001722 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001723
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001724 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001725
Ben Widawsky59124502013-07-04 11:02:05 -07001726 /* Cannot be determined by PCIID. You must always read a register. */
1727 size_t ellc_size;
1728
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001729 /* gen6+ rps state */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001730 struct intel_gen6_power_mgmt rps;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001731
Daniel Vetter20e4d402012-08-08 23:35:39 +02001732 /* ilk-only ips/rps state. Everything in here is protected by the global
1733 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001734 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001735
Imre Deak83c00f552013-10-25 17:36:47 +03001736 struct i915_power_domains power_domains;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001737
Rodrigo Vivia031d702013-10-03 16:15:06 -03001738 struct i915_psr psr;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001739
Daniel Vetter99584db2012-11-14 17:14:04 +01001740 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01001741
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001742 struct drm_i915_gem_object *vlv_pctx;
1743
Daniel Vetter4520f532013-10-09 09:18:51 +02001744#ifdef CONFIG_DRM_I915_FBDEV
Dave Airlie8be48d92010-03-30 05:34:14 +00001745 /* list of fbdev register on this device */
1746 struct intel_fbdev *fbdev;
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001747 struct work_struct fbdev_suspend_work;
Daniel Vetter4520f532013-10-09 09:18:51 +02001748#endif
Chris Wilsone953fd72011-02-21 22:23:52 +00001749
1750 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01001751 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07001752
Imre Deak58fddc22015-01-08 17:54:14 +02001753 /* hda/i915 audio component */
1754 bool audio_component_registered;
1755
Ben Widawsky254f9652012-06-04 14:42:42 -07001756 uint32_t hw_context_size;
Ben Widawskya33afea2013-09-17 21:12:45 -07001757 struct list_head context_list;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001758
Damien Lespiau3e683202012-12-11 18:48:29 +00001759 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02001760
Daniel Vetter842f1c82014-03-10 10:01:44 +01001761 u32 suspend_count;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001762 struct i915_suspend_saved_registers regfile;
Imre Deakddeea5b2014-05-05 15:19:56 +03001763 struct vlv_s0ix_state vlv_s0ix_state;
Daniel Vetter231f42a2012-11-02 19:55:05 +01001764
Ville Syrjälä53615a52013-08-01 16:18:50 +03001765 struct {
1766 /*
1767 * Raw watermark latency values:
1768 * in 0.1us units for WM0,
1769 * in 0.5us units for WM1+.
1770 */
1771 /* primary */
1772 uint16_t pri_latency[5];
1773 /* sprite */
1774 uint16_t spr_latency[5];
1775 /* cursor */
1776 uint16_t cur_latency[5];
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001777 /*
1778 * Raw watermark memory latency values
1779 * for SKL for all 8 levels
1780 * in 1us units.
1781 */
1782 uint16_t skl_latency[8];
Ville Syrjälä609cede2013-10-09 19:18:03 +03001783
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001784 /*
1785 * The skl_wm_values structure is a bit too big for stack
1786 * allocation, so we keep the staging struct where we store
1787 * intermediate results here instead.
1788 */
1789 struct skl_wm_values skl_results;
1790
Ville Syrjälä609cede2013-10-09 19:18:03 +03001791 /* current hardware state */
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001792 union {
1793 struct ilk_wm_values hw;
1794 struct skl_wm_values skl_hw;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001795 struct vlv_wm_values vlv;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001796 };
Ville Syrjälä53615a52013-08-01 16:18:50 +03001797 } wm;
1798
Paulo Zanoni8a187452013-12-06 20:32:13 -02001799 struct i915_runtime_pm pm;
1800
Dave Airlie13cf5502014-06-18 11:29:35 +10001801 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1802 u32 long_hpd_port_mask;
1803 u32 short_hpd_port_mask;
1804 struct work_struct dig_port_work;
1805
Dave Airlie0e32b392014-05-02 14:02:48 +10001806 /*
1807 * if we get a HPD irq from DP and a HPD irq from non-DP
1808 * the non-DP HPD could block the workqueue on a mode config
1809 * mutex getting, that userspace may have taken. However
1810 * userspace is waiting on the DP workqueue to run which is
1811 * blocked behind the non-DP one.
1812 */
1813 struct workqueue_struct *dp_wq;
1814
Oscar Mateoa83014d2014-07-24 17:04:21 +01001815 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1816 struct {
1817 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1818 struct intel_engine_cs *ring,
1819 struct intel_context *ctx,
1820 struct drm_i915_gem_execbuffer2 *args,
1821 struct list_head *vmas,
1822 struct drm_i915_gem_object *batch_obj,
1823 u64 exec_start, u32 flags);
1824 int (*init_rings)(struct drm_device *dev);
1825 void (*cleanup_ring)(struct intel_engine_cs *ring);
1826 void (*stop_ring)(struct intel_engine_cs *ring);
1827 } gt;
1828
John Harrison67e29372014-12-05 13:49:35 +00001829 uint32_t request_uniq;
1830
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001831 /*
1832 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1833 * will be rejected. Instead look for a better place.
1834 */
Jani Nikula77fec552014-03-31 14:27:22 +03001835};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001836
Chris Wilson2c1792a2013-08-01 18:39:55 +01001837static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1838{
1839 return dev->dev_private;
1840}
1841
Imre Deak888d0d42015-01-08 17:54:13 +02001842static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1843{
1844 return to_i915(dev_get_drvdata(dev));
1845}
1846
Chris Wilsonb4519512012-05-11 14:29:30 +01001847/* Iterate over initialised rings */
1848#define for_each_ring(ring__, dev_priv__, i__) \
1849 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1850 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1851
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001852enum hdmi_force_audio {
1853 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1854 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1855 HDMI_AUDIO_AUTO, /* trust EDID */
1856 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1857};
1858
Daniel Vetter190d6cd2013-07-04 13:06:28 +02001859#define I915_GTT_OFFSET_NONE ((u32)-1)
Chris Wilsoned2f3452012-11-15 11:32:19 +00001860
Chris Wilson37e680a2012-06-07 15:38:42 +01001861struct drm_i915_gem_object_ops {
1862 /* Interface between the GEM object and its backing storage.
1863 * get_pages() is called once prior to the use of the associated set
1864 * of pages before to binding them into the GTT, and put_pages() is
1865 * called after we no longer need them. As we expect there to be
1866 * associated cost with migrating pages between the backing storage
1867 * and making them available for the GPU (e.g. clflush), we may hold
1868 * onto the pages after they are no longer referenced by the GPU
1869 * in case they may be used again shortly (for example migrating the
1870 * pages to a different memory domain within the GTT). put_pages()
1871 * will therefore most likely be called when the object itself is
1872 * being released or under memory pressure (where we attempt to
1873 * reap pages for the shrinker).
1874 */
1875 int (*get_pages)(struct drm_i915_gem_object *);
1876 void (*put_pages)(struct drm_i915_gem_object *);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01001877 int (*dmabuf_export)(struct drm_i915_gem_object *);
1878 void (*release)(struct drm_i915_gem_object *);
Chris Wilson37e680a2012-06-07 15:38:42 +01001879};
1880
Daniel Vettera071fa02014-06-18 23:28:09 +02001881/*
1882 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1883 * considered to be the frontbuffer for the given plane interface-vise. This
1884 * doesn't mean that the hw necessarily already scans it out, but that any
1885 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1886 *
1887 * We have one bit per pipe and per scanout plane type.
1888 */
1889#define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1890#define INTEL_FRONTBUFFER_BITS \
1891 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1892#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1893 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1894#define INTEL_FRONTBUFFER_CURSOR(pipe) \
1895 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1896#define INTEL_FRONTBUFFER_SPRITE(pipe) \
1897 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1898#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1899 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettercc365132014-06-18 13:59:13 +02001900#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1901 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
Daniel Vettera071fa02014-06-18 23:28:09 +02001902
Eric Anholt673a3942008-07-30 12:06:12 -07001903struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +00001904 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -07001905
Chris Wilson37e680a2012-06-07 15:38:42 +01001906 const struct drm_i915_gem_object_ops *ops;
1907
Ben Widawsky2f633152013-07-17 12:19:03 -07001908 /** List of VMAs backed by this object */
1909 struct list_head vma_list;
1910
Chris Wilsonc1ad11f2012-11-15 11:32:21 +00001911 /** Stolen memory for this object, instead of being backed by shmem. */
1912 struct drm_mm_node *stolen;
Ben Widawsky35c20a62013-05-31 11:28:48 -07001913 struct list_head global_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001914
Chris Wilson69dc4982010-10-19 10:36:51 +01001915 struct list_head ring_list;
Ben Widawskyb25cb2f2013-08-14 11:38:33 +02001916 /** Used in execbuf to temporarily hold a ref */
1917 struct list_head obj_exec_link;
Eric Anholt673a3942008-07-30 12:06:12 -07001918
Brad Volkin493018d2014-12-11 12:13:08 -08001919 struct list_head batch_pool_list;
1920
Eric Anholt673a3942008-07-30 12:06:12 -07001921 /**
Chris Wilson65ce3022012-07-20 12:41:02 +01001922 * This is set if the object is on the active lists (has pending
1923 * rendering and so a non-zero seqno), and is not set if it i s on
1924 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -07001925 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001926 unsigned int active:1;
Eric Anholt673a3942008-07-30 12:06:12 -07001927
1928 /**
1929 * This is set if the object has been written to since last bound
1930 * to the GTT
1931 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001932 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001933
1934 /**
1935 * Fence register bits (if any) for this object. Will be set
1936 * as needed when mapped into the GTT.
1937 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +02001938 */
Daniel Vetter4b9de732011-10-09 21:52:02 +02001939 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +02001940
1941 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001942 * Advice: are the backing pages purgeable?
1943 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001944 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +02001945
1946 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001947 * Current tiling mode for the object.
1948 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001949 unsigned int tiling_mode:2;
Chris Wilson5d82e3e2012-04-21 16:23:23 +01001950 /**
1951 * Whether the tiling parameters for the currently associated fence
1952 * register have changed. Note that for the purposes of tracking
1953 * tiling changes we also treat the unfenced register, the register
1954 * slot that the object occupies whilst it executes a fenced
1955 * command (such as BLT on gen2/3), as a "fence".
1956 */
1957 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001958
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001959 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +01001960 * Is the object at the current location in the gtt mappable and
1961 * fenceable? Used to avoid costly recalculations.
1962 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001963 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +01001964
1965 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001966 * Whether the current gtt mapping needs to be mappable (and isn't just
1967 * mappable by accident). Track pin and fault separate for a more
1968 * accurate mappable working set.
1969 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001970 unsigned int fault_mappable:1;
1971 unsigned int pin_mappable:1;
Chris Wilsoncc98b412013-08-09 12:25:09 +01001972 unsigned int pin_display:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001973
Chris Wilsoncaea7472010-11-12 13:53:37 +00001974 /*
Akash Goel24f3a8c2014-06-17 10:59:42 +05301975 * Is the object to be mapped as read-only to the GPU
1976 * Only honoured if hardware has relevant pte bit
1977 */
1978 unsigned long gt_ro:1;
Chris Wilson651d7942013-08-08 14:41:10 +01001979 unsigned int cache_level:3;
Chris Wilson0f719792015-01-13 13:32:52 +00001980 unsigned int cache_dirty:1;
Chris Wilson93dfb402011-03-29 16:59:50 -07001981
Chris Wilson9da3da62012-06-01 15:20:22 +01001982 unsigned int has_dma_mapping:1;
Daniel Vetter7bddb012012-02-09 17:15:47 +01001983
Daniel Vettera071fa02014-06-18 23:28:09 +02001984 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1985
Chris Wilson9da3da62012-06-01 15:20:22 +01001986 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01001987 int pages_pin_count;
Eric Anholt673a3942008-07-30 12:06:12 -07001988
Daniel Vetter1286ff72012-05-10 15:25:09 +02001989 /* prime dma-buf support */
Dave Airlie9a70cc22012-05-22 13:09:21 +01001990 void *dma_buf_vmapping;
1991 int vmapping_count;
1992
Chris Wilson1c293ea2012-04-17 15:31:27 +01001993 /** Breadcrumb of last rendering to the buffer. */
John Harrison97b2a6a2014-11-24 18:49:26 +00001994 struct drm_i915_gem_request *last_read_req;
1995 struct drm_i915_gem_request *last_write_req;
Chris Wilsoncaea7472010-11-12 13:53:37 +00001996 /** Breadcrumb of last fenced GPU access to the buffer. */
John Harrison97b2a6a2014-11-24 18:49:26 +00001997 struct drm_i915_gem_request *last_fenced_req;
Eric Anholt673a3942008-07-30 12:06:12 -07001998
Daniel Vetter778c3542010-05-13 11:49:44 +02001999 /** Current tiling stride for the object, if it's tiled. */
Jesse Barnesde151cf2008-11-12 10:03:55 -08002000 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -07002001
Daniel Vetter80075d42013-10-09 21:23:52 +02002002 /** References from framebuffers, locks out tiling changes. */
2003 unsigned long framebuffer_references;
2004
Eric Anholt280b7132009-03-12 16:56:27 -07002005 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01002006 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07002007
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002008 union {
Chris Wilson6a2c4232014-11-04 04:51:40 -08002009 /** for phy allocated objects */
2010 struct drm_dma_handle *phys_handle;
2011
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002012 struct i915_gem_userptr {
2013 uintptr_t ptr;
2014 unsigned read_only :1;
2015 unsigned workers :4;
2016#define I915_GEM_USERPTR_MAX_WORKERS 15
2017
Chris Wilsonad46cb52014-08-07 14:20:40 +01002018 struct i915_mm_struct *mm;
2019 struct i915_mmu_object *mmu_object;
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002020 struct work_struct *work;
2021 } userptr;
2022 };
2023};
Daniel Vetter62b8b212010-04-09 19:05:08 +00002024#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +01002025
Daniel Vettera071fa02014-06-18 23:28:09 +02002026void i915_gem_track_fb(struct drm_i915_gem_object *old,
2027 struct drm_i915_gem_object *new,
2028 unsigned frontbuffer_bits);
2029
Eric Anholt673a3942008-07-30 12:06:12 -07002030/**
2031 * Request queue structure.
2032 *
2033 * The request queue allows us to note sequence numbers that have been emitted
2034 * and may be associated with active buffers to be retired.
2035 *
John Harrison97b2a6a2014-11-24 18:49:26 +00002036 * By keeping this list, we can avoid having to do questionable sequence
2037 * number comparisons on buffer last_read|write_seqno. It also allows an
2038 * emission time to be associated with the request for tracking how far ahead
2039 * of the GPU the submission is.
Nick Hoathb3a38992015-02-19 16:30:47 +00002040 *
2041 * The requests are reference counted, so upon creation they should have an
2042 * initial reference taken using kref_init
Eric Anholt673a3942008-07-30 12:06:12 -07002043 */
2044struct drm_i915_gem_request {
John Harrisonabfe2622014-11-24 18:49:24 +00002045 struct kref ref;
2046
Zou Nan hai852835f2010-05-21 09:08:56 +08002047 /** On Which ring this request was generated */
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002048 struct intel_engine_cs *ring;
Zou Nan hai852835f2010-05-21 09:08:56 +08002049
Eric Anholt673a3942008-07-30 12:06:12 -07002050 /** GEM sequence number associated with this request. */
2051 uint32_t seqno;
2052
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002053 /** Position in the ringbuffer of the start of the request */
2054 u32 head;
2055
Nick Hoath72f95af2015-01-15 13:10:37 +00002056 /**
2057 * Position in the ringbuffer of the start of the postfix.
2058 * This is required to calculate the maximum available ringbuffer
2059 * space without overwriting the postfix.
2060 */
2061 u32 postfix;
2062
2063 /** Position in the ringbuffer of the end of the whole request */
Chris Wilsona71d8d92012-02-15 11:25:36 +00002064 u32 tail;
2065
Nick Hoathb3a38992015-02-19 16:30:47 +00002066 /**
Dave Airliea8c6ecb2015-03-09 19:58:30 +10002067 * Context and ring buffer related to this request
Nick Hoathb3a38992015-02-19 16:30:47 +00002068 * Contexts are refcounted, so when this request is associated with a
2069 * context, we must increment the context's refcount, to guarantee that
2070 * it persists while any request is linked to it. Requests themselves
2071 * are also refcounted, so the request will only be freed when the last
2072 * reference to it is dismissed, and the code in
2073 * i915_gem_request_free() will then decrement the refcount on the
2074 * context.
2075 */
Oscar Mateo273497e2014-05-22 14:13:37 +01002076 struct intel_context *ctx;
John Harrison98e1bd42015-02-13 11:48:12 +00002077 struct intel_ringbuffer *ringbuf;
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002078
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002079 /** Batch buffer related to this request if any */
2080 struct drm_i915_gem_object *batch_obj;
2081
Eric Anholt673a3942008-07-30 12:06:12 -07002082 /** Time at which this request was emitted, in jiffies. */
2083 unsigned long emitted_jiffies;
2084
Eric Anholtb9624422009-06-03 07:27:35 +00002085 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -07002086 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +00002087
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002088 struct drm_i915_file_private *file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00002089 /** file_priv list entry for this request */
2090 struct list_head client_list;
John Harrison67e29372014-12-05 13:49:35 +00002091
Mika Kuoppala071c92d2015-02-12 10:26:02 +02002092 /** process identifier submitting this request */
2093 struct pid *pid;
2094
John Harrison67e29372014-12-05 13:49:35 +00002095 uint32_t uniq;
Nick Hoath6d3d8272015-01-15 13:10:39 +00002096
2097 /**
2098 * The ELSP only accepts two elements at a time, so we queue
2099 * context/tail pairs on a given queue (ring->execlist_queue) until the
2100 * hardware is available. The queue serves a double purpose: we also use
2101 * it to keep track of the up to 2 contexts currently in the hardware
2102 * (usually one in execution and the other queued up by the GPU): We
2103 * only remove elements from the head of the queue when the hardware
2104 * informs us that an element has been completed.
2105 *
2106 * All accesses to the queue are mediated by a spinlock
2107 * (ring->execlist_lock).
2108 */
2109
2110 /** Execlist link in the submission queue.*/
2111 struct list_head execlist_link;
2112
2113 /** Execlists no. of times this request has been sent to the ELSP */
2114 int elsp_submitted;
2115
Eric Anholt673a3942008-07-30 12:06:12 -07002116};
2117
John Harrisonabfe2622014-11-24 18:49:24 +00002118void i915_gem_request_free(struct kref *req_ref);
2119
John Harrisonb793a002014-11-24 18:49:25 +00002120static inline uint32_t
2121i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2122{
2123 return req ? req->seqno : 0;
2124}
2125
2126static inline struct intel_engine_cs *
2127i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2128{
2129 return req ? req->ring : NULL;
2130}
2131
John Harrisonabfe2622014-11-24 18:49:24 +00002132static inline void
2133i915_gem_request_reference(struct drm_i915_gem_request *req)
2134{
2135 kref_get(&req->ref);
2136}
2137
2138static inline void
2139i915_gem_request_unreference(struct drm_i915_gem_request *req)
2140{
Daniel Vetterf2458602014-11-26 10:26:05 +01002141 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
John Harrisonabfe2622014-11-24 18:49:24 +00002142 kref_put(&req->ref, i915_gem_request_free);
2143}
2144
2145static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2146 struct drm_i915_gem_request *src)
2147{
2148 if (src)
2149 i915_gem_request_reference(src);
2150
2151 if (*pdst)
2152 i915_gem_request_unreference(*pdst);
2153
2154 *pdst = src;
2155}
2156
John Harrison1b5a4332014-11-24 18:49:42 +00002157/*
2158 * XXX: i915_gem_request_completed should be here but currently needs the
2159 * definition of i915_seqno_passed() which is below. It will be moved in
2160 * a later patch when the call to i915_seqno_passed() is obsoleted...
2161 */
2162
Eric Anholt673a3942008-07-30 12:06:12 -07002163struct drm_i915_file_private {
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002164 struct drm_i915_private *dev_priv;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +02002165 struct drm_file *file;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002166
Eric Anholt673a3942008-07-30 12:06:12 -07002167 struct {
Luis R. Rodriguez99057c82012-11-29 12:45:06 -08002168 spinlock_t lock;
Eric Anholtb9624422009-06-03 07:27:35 +00002169 struct list_head request_list;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002170 struct delayed_work idle_work;
Eric Anholt673a3942008-07-30 12:06:12 -07002171 } mm;
Ben Widawsky40521052012-06-04 14:42:43 -07002172 struct idr context_idr;
Mika Kuoppalae59ec132013-06-12 12:35:28 +03002173
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002174 atomic_t rps_wait_boost;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002175 struct intel_engine_cs *bsd_ring;
Eric Anholt673a3942008-07-30 12:06:12 -07002176};
2177
Brad Volkin351e3db2014-02-18 10:15:46 -08002178/*
2179 * A command that requires special handling by the command parser.
2180 */
2181struct drm_i915_cmd_descriptor {
2182 /*
2183 * Flags describing how the command parser processes the command.
2184 *
2185 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2186 * a length mask if not set
2187 * CMD_DESC_SKIP: The command is allowed but does not follow the
2188 * standard length encoding for the opcode range in
2189 * which it falls
2190 * CMD_DESC_REJECT: The command is never allowed
2191 * CMD_DESC_REGISTER: The command should be checked against the
2192 * register whitelist for the appropriate ring
2193 * CMD_DESC_MASTER: The command is allowed if the submitting process
2194 * is the DRM master
2195 */
2196 u32 flags;
2197#define CMD_DESC_FIXED (1<<0)
2198#define CMD_DESC_SKIP (1<<1)
2199#define CMD_DESC_REJECT (1<<2)
2200#define CMD_DESC_REGISTER (1<<3)
2201#define CMD_DESC_BITMASK (1<<4)
2202#define CMD_DESC_MASTER (1<<5)
2203
2204 /*
2205 * The command's unique identification bits and the bitmask to get them.
2206 * This isn't strictly the opcode field as defined in the spec and may
2207 * also include type, subtype, and/or subop fields.
2208 */
2209 struct {
2210 u32 value;
2211 u32 mask;
2212 } cmd;
2213
2214 /*
2215 * The command's length. The command is either fixed length (i.e. does
2216 * not include a length field) or has a length field mask. The flag
2217 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2218 * a length mask. All command entries in a command table must include
2219 * length information.
2220 */
2221 union {
2222 u32 fixed;
2223 u32 mask;
2224 } length;
2225
2226 /*
2227 * Describes where to find a register address in the command to check
2228 * against the ring's register whitelist. Only valid if flags has the
2229 * CMD_DESC_REGISTER bit set.
2230 */
2231 struct {
2232 u32 offset;
2233 u32 mask;
2234 } reg;
2235
2236#define MAX_CMD_DESC_BITMASKS 3
2237 /*
2238 * Describes command checks where a particular dword is masked and
2239 * compared against an expected value. If the command does not match
2240 * the expected value, the parser rejects it. Only valid if flags has
2241 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2242 * are valid.
Brad Volkind4d48032014-02-18 10:15:54 -08002243 *
2244 * If the check specifies a non-zero condition_mask then the parser
2245 * only performs the check when the bits specified by condition_mask
2246 * are non-zero.
Brad Volkin351e3db2014-02-18 10:15:46 -08002247 */
2248 struct {
2249 u32 offset;
2250 u32 mask;
2251 u32 expected;
Brad Volkind4d48032014-02-18 10:15:54 -08002252 u32 condition_offset;
2253 u32 condition_mask;
Brad Volkin351e3db2014-02-18 10:15:46 -08002254 } bits[MAX_CMD_DESC_BITMASKS];
2255};
2256
2257/*
2258 * A table of commands requiring special handling by the command parser.
2259 *
2260 * Each ring has an array of tables. Each table consists of an array of command
2261 * descriptors, which must be sorted with command opcodes in ascending order.
2262 */
2263struct drm_i915_cmd_table {
2264 const struct drm_i915_cmd_descriptor *table;
2265 int count;
2266};
2267
Chris Wilsondbbe9122014-08-09 19:18:43 +01002268/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
Chris Wilson7312e2d2014-08-13 12:14:12 +01002269#define __I915__(p) ({ \
2270 struct drm_i915_private *__p; \
2271 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2272 __p = (struct drm_i915_private *)p; \
2273 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2274 __p = to_i915((struct drm_device *)p); \
2275 else \
2276 BUILD_BUG(); \
2277 __p; \
2278})
Chris Wilsondbbe9122014-08-09 19:18:43 +01002279#define INTEL_INFO(p) (&__I915__(p)->info)
Chris Wilson87f1f462014-08-09 19:18:42 +01002280#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002281#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
Zou Nan haicae58522010-11-09 17:17:32 +08002282
Chris Wilson87f1f462014-08-09 19:18:42 +01002283#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2284#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
Zou Nan haicae58522010-11-09 17:17:32 +08002285#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002286#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
Zou Nan haicae58522010-11-09 17:17:32 +08002287#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
Chris Wilson87f1f462014-08-09 19:18:42 +01002288#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2289#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
Zou Nan haicae58522010-11-09 17:17:32 +08002290#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2291#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2292#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
Chris Wilson87f1f462014-08-09 19:18:42 +01002293#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
Zou Nan haicae58522010-11-09 17:17:32 +08002294#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002295#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2296#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
Zou Nan haicae58522010-11-09 17:17:32 +08002297#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2298#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
Chris Wilson87f1f462014-08-09 19:18:42 +01002299#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07002300#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Chris Wilson87f1f462014-08-09 19:18:42 +01002301#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2302 INTEL_DEVID(dev) == 0x0152 || \
2303 INTEL_DEVID(dev) == 0x015a)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07002304#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Ville Syrjälä6df40272014-04-09 13:28:00 +03002305#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03002306#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Ville Syrjälä8179f1f2014-04-09 13:27:59 +03002307#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +05302308#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
Zou Nan haicae58522010-11-09 17:17:32 +08002309#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Paulo Zanonied1c9e22013-08-12 14:34:08 -03002310#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002311 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002312#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
Rodrigo Vivi6b96d702015-01-19 16:16:15 -08002313 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
Rodrigo Vivi0dc6f202015-01-21 11:46:32 -08002314 (INTEL_DEVID(dev) & 0xf) == 0xb || \
Chris Wilson87f1f462014-08-09 19:18:42 +01002315 (INTEL_DEVID(dev) & 0xf) == 0xe))
Rodrigo Vivia0fcbd92014-09-19 20:16:26 -04002316#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2317 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002318#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002319 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
Rodrigo Vivi94353732013-08-28 16:45:46 -03002320#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002321 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Paulo Zanoni9bbfd202014-04-29 11:00:22 -03002322/* ULX machines are also considered ULT. */
Chris Wilson87f1f462014-08-09 19:18:42 +01002323#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2324 INTEL_DEVID(dev) == 0x0A1E)
Ben Widawskyb833d682013-08-23 16:00:07 -07002325#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
Zou Nan haicae58522010-11-09 17:17:32 +08002326
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002327#define SKL_REVID_A0 (0x0)
2328#define SKL_REVID_B0 (0x1)
2329#define SKL_REVID_C0 (0x2)
2330#define SKL_REVID_D0 (0x3)
Damien Lespiau8bc0ccf2015-02-09 19:33:18 +00002331#define SKL_REVID_E0 (0x4)
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002332
Jesse Barnes85436692011-04-06 12:11:14 -07002333/*
2334 * The genX designation typically refers to the render engine, so render
2335 * capability related checks should use IS_GEN, while display and other checks
2336 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2337 * chips, etc.).
2338 */
Zou Nan haicae58522010-11-09 17:17:32 +08002339#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2340#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2341#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2342#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2343#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
Jesse Barnes85436692011-04-06 12:11:14 -07002344#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
Ben Widawskyd2980842013-11-02 21:06:59 -07002345#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
Damien Lespiaub71252d2013-02-13 15:27:24 +00002346#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
Zou Nan haicae58522010-11-09 17:17:32 +08002347
Ben Widawsky73ae4782013-10-15 10:02:57 -07002348#define RENDER_RING (1<<RCS)
2349#define BSD_RING (1<<VCS)
2350#define BLT_RING (1<<BCS)
2351#define VEBOX_RING (1<<VECS)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002352#define BSD2_RING (1<<VCS2)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002353#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002354#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002355#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2356#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2357#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2358#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002359 __I915__(dev)->ellc_size)
Zou Nan haicae58522010-11-09 17:17:32 +08002360#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2361
Ben Widawsky254f9652012-06-04 14:42:42 -07002362#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Oscar Mateod7f621e2014-07-24 17:04:49 +01002363#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
Jesse Barnes692ef702014-08-05 07:51:18 -07002364#define USES_PPGTT(dev) (i915.enable_ppgtt)
2365#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01002366
Chris Wilson05394f32010-11-08 19:18:58 +00002367#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08002368#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2369
Daniel Vetterb45305f2012-12-17 16:21:27 +01002370/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2371#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
Daniel Vetter4e6b7882014-02-07 16:33:20 +01002372/*
2373 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2374 * even when in MSI mode. This results in spurious interrupt warnings if the
2375 * legacy irq no. is shared with another device. The kernel then disables that
2376 * interrupt source and so prevents the other device from working properly.
2377 */
2378#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2379#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
Daniel Vetterb45305f2012-12-17 16:21:27 +01002380
Zou Nan haicae58522010-11-09 17:17:32 +08002381/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2382 * rows, which changed the alignment requirements and fence programming.
2383 */
2384#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2385 IS_I915GM(dev)))
2386#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2387#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2388#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
Zou Nan haicae58522010-11-09 17:17:32 +08002389#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2390#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
Zou Nan haicae58522010-11-09 17:17:32 +08002391
2392#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2393#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01002394#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08002395
Damien Lespiaudbf77862014-10-01 20:04:14 +01002396#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
Damien Lespiauf5adf942013-06-24 18:29:34 +01002397
Damien Lespiaudd93be52013-04-22 18:40:39 +01002398#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
Damien Lespiau30568c42013-04-22 18:40:41 +01002399#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
Rodrigo Vivib32c6f42014-11-20 03:44:37 -08002400#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
Sonika Jindale3d99842015-01-22 14:30:54 +05302401 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2402 IS_SKYLAKE(dev))
Paulo Zanoni6157d3c2014-03-07 20:12:37 -03002403#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
Imre Deakfd7f8cc2014-04-14 20:41:30 +03002404 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
Rodrigo Vivi58abf1d2014-10-07 07:06:50 -07002405#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2406#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002407
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002408#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2409#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2410#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2411#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2412#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2413#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302414#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2415#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002416
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002417#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302418#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03002419#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Zou Nan haicae58522010-11-09 17:17:32 +08002420#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2421#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Ben Widawsky40c7ead2013-04-05 13:12:40 -07002422#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03002423#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08002424
Sonika Jindal5fafe292014-07-21 15:23:38 +05302425#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2426
Ben Widawsky040d2ba2013-09-19 11:01:40 -07002427/* DPF == dynamic parity feature */
2428#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2429#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07002430
Ben Widawskyc8735b02012-09-07 19:43:39 -07002431#define GT_FREQUENCY_MULTIPLIER 50
Akash Goelde43ae92015-03-06 11:07:14 +05302432#define GEN9_FREQ_SCALER 3
Ben Widawskyc8735b02012-09-07 19:43:39 -07002433
Chris Wilson05394f32010-11-08 19:18:58 +00002434#include "i915_trace.h"
2435
Rob Clarkbaa70942013-08-02 13:27:49 -04002436extern const struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +10002437extern int i915_max_ioctl;
2438
Imre Deakfc49b3d2014-10-23 19:23:27 +03002439extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2440extern int i915_resume_legacy(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10002441
Jani Nikulad330a952014-01-21 11:24:25 +02002442/* i915_params.c */
2443struct i915_params {
2444 int modeset;
2445 int panel_ignore_lid;
Jani Nikulad330a952014-01-21 11:24:25 +02002446 int semaphores;
2447 unsigned int lvds_downclock;
2448 int lvds_channel_mode;
2449 int panel_use_ssc;
2450 int vbt_sdvo_panel_type;
2451 int enable_rc6;
2452 int enable_fbc;
Jani Nikulad330a952014-01-21 11:24:25 +02002453 int enable_ppgtt;
Oscar Mateo127f1002014-07-24 17:04:11 +01002454 int enable_execlists;
Jani Nikulad330a952014-01-21 11:24:25 +02002455 int enable_psr;
2456 unsigned int preliminary_hw_support;
2457 int disable_power_well;
2458 int enable_ips;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00002459 int invert_brightness;
Brad Volkin351e3db2014-02-18 10:15:46 -08002460 int enable_cmd_parser;
Damien Lespiaue5aa6542014-02-07 19:12:53 +00002461 /* leave bools at the end to not create holes */
2462 bool enable_hangcheck;
2463 bool fastboot;
Jani Nikulad330a952014-01-21 11:24:25 +02002464 bool prefault_disable;
Daniel Vetter5bedeb22015-03-03 18:03:47 +01002465 bool load_detect_test;
Jani Nikulad330a952014-01-21 11:24:25 +02002466 bool reset;
Damien Lespiaua0bae572014-02-10 17:20:55 +00002467 bool disable_display;
Daniel Vetter7a10dfa2014-04-01 09:33:47 +02002468 bool disable_vtd_wa;
Sourab Gupta84c33a62014-06-02 16:47:17 +05302469 int use_mmio_flip;
Chris Wilson48572ed2014-12-18 10:55:50 +00002470 int mmio_debug;
Rob Clarke2c719b2014-12-15 13:56:32 -05002471 bool verbose_state_checks;
Matt Roperb2e77232015-01-22 16:53:12 -08002472 bool nuclear_pageflip;
Jani Nikulad330a952014-01-21 11:24:25 +02002473};
2474extern struct i915_params i915 __read_mostly;
2475
Linus Torvalds1da177e2005-04-16 15:20:36 -07002476 /* i915_dma.c */
Dave Airlie22eae942005-11-10 22:16:34 +11002477extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002478extern int i915_driver_unload(struct drm_device *);
John Harrison2885f6a2014-06-26 18:23:52 +01002479extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
Dave Airlie84b1fd12007-07-11 15:53:27 +10002480extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +10002481extern void i915_driver_preclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002482 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002483extern void i915_driver_postclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002484 struct drm_file *file);
Dave Airlie84b1fd12007-07-11 15:53:27 +10002485extern int i915_driver_device_is_agp(struct drm_device * dev);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002486#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11002487extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2488 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002489#endif
Ben Widawsky8e96d9c2012-06-04 14:42:56 -07002490extern int intel_gpu_reset(struct drm_device *dev);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +02002491extern int i915_reset(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002492extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2493extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2494extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2495extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
Imre Deak650ad972014-04-18 16:35:02 +03002496int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
Imre Deak1d0d3432014-08-18 14:42:44 +03002497void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002498
Linus Torvalds1da177e2005-04-16 15:20:36 -07002499/* i915_irq.c */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03002500void i915_queue_hangcheck(struct drm_device *dev);
Mika Kuoppala58174462014-02-25 17:11:26 +02002501__printf(3, 4)
2502void i915_handle_error(struct drm_device *dev, bool wedged,
2503 const char *fmt, ...);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002504
Daniel Vetterb9632912014-09-30 10:56:44 +02002505extern void intel_irq_init(struct drm_i915_private *dev_priv);
2506extern void intel_hpd_init(struct drm_i915_private *dev_priv);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02002507int intel_irq_install(struct drm_i915_private *dev_priv);
2508void intel_irq_uninstall(struct drm_i915_private *dev_priv);
Chris Wilson907b28c2013-07-19 20:36:52 +01002509
2510extern void intel_uncore_sanitize(struct drm_device *dev);
Imre Deak10018602014-06-06 12:59:39 +03002511extern void intel_uncore_early_sanitize(struct drm_device *dev,
2512 bool restore_forcewake);
Chris Wilson907b28c2013-07-19 20:36:52 +01002513extern void intel_uncore_init(struct drm_device *dev);
Chris Wilson907b28c2013-07-19 20:36:52 +01002514extern void intel_uncore_check_errors(struct drm_device *dev);
Chris Wilsonaec347a2013-08-26 13:46:09 +01002515extern void intel_uncore_fini(struct drm_device *dev);
Jesse Barnes156c7ca2014-06-12 08:35:45 -07002516extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
Mika Kuoppala48c10262015-01-16 11:34:41 +02002517const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002518void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +02002519 enum forcewake_domains domains);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002520void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +02002521 enum forcewake_domains domains);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002522void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
Yu Zhangcf9d2892015-02-10 19:05:47 +08002523static inline bool intel_vgpu_active(struct drm_device *dev)
2524{
2525 return to_i915(dev)->vgpu.active;
2526}
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002527
Keith Packard7c463582008-11-04 02:03:27 -08002528void
Jani Nikula50227e12014-03-31 14:27:21 +03002529i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002530 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002531
2532void
Jani Nikula50227e12014-03-31 14:27:21 +03002533i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002534 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002535
Imre Deakf8b79e52014-03-04 19:23:07 +02002536void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2537void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
Daniel Vetter47339cd2014-09-30 10:56:46 +02002538void
2539ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2540void
2541ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2542void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2543 uint32_t interrupt_mask,
2544 uint32_t enabled_irq_mask);
2545#define ibx_enable_display_interrupt(dev_priv, bits) \
2546 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2547#define ibx_disable_display_interrupt(dev_priv, bits) \
2548 ibx_display_interrupt_update((dev_priv), (bits), 0)
Imre Deakf8b79e52014-03-04 19:23:07 +02002549
Eric Anholt673a3942008-07-30 12:06:12 -07002550/* i915_gem.c */
Eric Anholt673a3942008-07-30 12:06:12 -07002551int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2552 struct drm_file *file_priv);
2553int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2554 struct drm_file *file_priv);
2555int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2556 struct drm_file *file_priv);
2557int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2558 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002559int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2560 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002561int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2562 struct drm_file *file_priv);
2563int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2564 struct drm_file *file_priv);
Oscar Mateoba8b7cc2014-07-24 17:04:33 +01002565void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2566 struct intel_engine_cs *ring);
2567void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2568 struct drm_file *file,
2569 struct intel_engine_cs *ring,
2570 struct drm_i915_gem_object *obj);
Oscar Mateoa83014d2014-07-24 17:04:21 +01002571int i915_gem_ringbuffer_submission(struct drm_device *dev,
2572 struct drm_file *file,
2573 struct intel_engine_cs *ring,
2574 struct intel_context *ctx,
2575 struct drm_i915_gem_execbuffer2 *args,
2576 struct list_head *vmas,
2577 struct drm_i915_gem_object *batch_obj,
2578 u64 exec_start, u32 flags);
Eric Anholt673a3942008-07-30 12:06:12 -07002579int i915_gem_execbuffer(struct drm_device *dev, void *data,
2580 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05002581int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2582 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002583int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2584 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07002585int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2586 struct drm_file *file);
2587int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2588 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002589int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2590 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01002591int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2592 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002593int i915_gem_set_tiling(struct drm_device *dev, void *data,
2594 struct drm_file *file_priv);
2595int i915_gem_get_tiling(struct drm_device *dev, void *data,
2596 struct drm_file *file_priv);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002597int i915_gem_init_userptr(struct drm_device *dev);
2598int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2599 struct drm_file *file);
Eric Anholt5a125c32008-10-22 21:40:13 -07002600int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2601 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002602int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2603 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002604void i915_gem_load(struct drm_device *dev);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002605void *i915_gem_object_alloc(struct drm_device *dev);
2606void i915_gem_object_free(struct drm_i915_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01002607void i915_gem_object_init(struct drm_i915_gem_object *obj,
2608 const struct drm_i915_gem_object_ops *ops);
Chris Wilson05394f32010-11-08 19:18:58 +00002609struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2610 size_t size);
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08002611void i915_init_vm(struct drm_i915_private *dev_priv,
2612 struct i915_address_space *vm);
Eric Anholt673a3942008-07-30 12:06:12 -07002613void i915_gem_free_object(struct drm_gem_object *obj);
Ben Widawsky2f633152013-07-17 12:19:03 -07002614void i915_gem_vma_destroy(struct i915_vma *vma);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002615
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002616#define PIN_MAPPABLE 0x1
2617#define PIN_NONBLOCK 0x2
Daniel Vetterbf3d1492014-02-14 14:01:12 +01002618#define PIN_GLOBAL 0x4
Chris Wilsond23db882014-05-23 08:48:08 +02002619#define PIN_OFFSET_BIAS 0x8
2620#define PIN_OFFSET_MASK (~4095)
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002621int __must_check
2622i915_gem_object_pin(struct drm_i915_gem_object *obj,
2623 struct i915_address_space *vm,
2624 uint32_t alignment,
2625 uint64_t flags);
2626int __must_check
2627i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2628 const struct i915_ggtt_view *view,
2629 uint32_t alignment,
2630 uint64_t flags);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002631
2632int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2633 u32 flags);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07002634int __must_check i915_vma_unbind(struct i915_vma *vma);
Chris Wilsondd624af2013-01-15 12:39:35 +00002635int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
Paulo Zanoni48018a52013-12-13 15:22:31 -02002636void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
Chris Wilson05394f32010-11-08 19:18:58 +00002637void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002638
Brad Volkin4c914c02014-02-18 10:15:45 -08002639int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2640 int *needs_clflush);
2641
Chris Wilson37e680a2012-06-07 15:38:42 +01002642int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilson9da3da62012-06-01 15:20:22 +01002643static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2644{
Imre Deak67d5a502013-02-18 19:28:02 +02002645 struct sg_page_iter sg_iter;
Chris Wilson1cf83782012-10-10 12:11:52 +01002646
Imre Deak67d5a502013-02-18 19:28:02 +02002647 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
Imre Deak2db76d72013-03-26 15:14:18 +02002648 return sg_page_iter_page(&sg_iter);
Imre Deak67d5a502013-02-18 19:28:02 +02002649
2650 return NULL;
Chris Wilson9da3da62012-06-01 15:20:22 +01002651}
Chris Wilsona5570172012-09-04 21:02:54 +01002652static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2653{
2654 BUG_ON(obj->pages == NULL);
2655 obj->pages_pin_count++;
2656}
2657static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2658{
2659 BUG_ON(obj->pages_pin_count == 0);
2660 obj->pages_pin_count--;
2661}
2662
Chris Wilson54cf91d2010-11-25 18:00:26 +00002663int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07002664int i915_gem_object_sync(struct drm_i915_gem_object *obj,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002665 struct intel_engine_cs *to);
Ben Widawskye2d05a82013-09-24 09:57:58 -07002666void i915_vma_move_to_active(struct i915_vma *vma,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002667 struct intel_engine_cs *ring);
Dave Airlieff72145b2011-02-07 12:16:14 +10002668int i915_gem_dumb_create(struct drm_file *file_priv,
2669 struct drm_device *dev,
2670 struct drm_mode_create_dumb *args);
Dave Airlieda6b51d2014-12-24 13:11:17 +10002671int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2672 uint32_t handle, uint64_t *offset);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002673/**
2674 * Returns true if seq1 is later than seq2.
2675 */
2676static inline bool
2677i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2678{
2679 return (int32_t)(seq1 - seq2) >= 0;
2680}
2681
John Harrison1b5a4332014-11-24 18:49:42 +00002682static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2683 bool lazy_coherency)
2684{
2685 u32 seqno;
2686
2687 BUG_ON(req == NULL);
2688
2689 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2690
2691 return i915_seqno_passed(seqno, req->seqno);
2692}
2693
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002694int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2695int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson06d98132012-04-17 15:31:24 +01002696int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
Chris Wilsond9e86c02010-11-10 16:40:20 +00002697int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00002698
Daniel Vetterd8ffa602014-05-13 12:11:26 +02002699bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2700void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002701
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002702struct drm_i915_gem_request *
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002703i915_gem_find_active_request(struct intel_engine_cs *ring);
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002704
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002705bool i915_gem_retire_requests(struct drm_device *dev);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002706void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
Daniel Vetter33196de2012-11-14 17:14:05 +01002707int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
Daniel Vetterd6b2c792012-07-04 22:54:13 +02002708 bool interruptible);
John Harrisonb6660d52014-11-24 18:49:30 +00002709int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
Sourab Gupta84c33a62014-06-02 16:47:17 +05302710
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002711static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2712{
2713 return unlikely(atomic_read(&error->reset_counter)
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002714 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002715}
2716
2717static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2718{
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002719 return atomic_read(&error->reset_counter) & I915_WEDGED;
2720}
2721
2722static inline u32 i915_reset_count(struct i915_gpu_error *error)
2723{
2724 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002725}
Chris Wilsona71d8d92012-02-15 11:25:36 +00002726
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02002727static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2728{
2729 return dev_priv->gpu_error.stop_rings == 0 ||
2730 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2731}
2732
2733static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2734{
2735 return dev_priv->gpu_error.stop_rings == 0 ||
2736 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2737}
2738
Chris Wilson069efc12010-09-30 16:53:18 +01002739void i915_gem_reset(struct drm_device *dev);
Chris Wilson000433b2013-08-08 14:41:09 +01002740bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
Chris Wilsona8198ee2011-04-13 22:04:09 +01002741int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
Chris Wilson1070a422012-04-24 15:47:41 +01002742int __must_check i915_gem_init(struct drm_device *dev);
Oscar Mateoa83014d2014-07-24 17:04:21 +01002743int i915_gem_init_rings(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002744int __must_check i915_gem_init_hw(struct drm_device *dev);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002745int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002746void i915_gem_init_swizzling(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002747void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07002748int __must_check i915_gpu_idle(struct drm_device *dev);
Chris Wilson45c5f202013-10-16 11:50:01 +01002749int __must_check i915_gem_suspend(struct drm_device *dev);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002750int __i915_add_request(struct intel_engine_cs *ring,
Mika Kuoppala0025c072013-06-12 12:35:30 +03002751 struct drm_file *file,
John Harrison9400ae52014-11-24 18:49:36 +00002752 struct drm_i915_gem_object *batch_obj);
2753#define i915_add_request(ring) \
2754 __i915_add_request(ring, NULL, NULL)
John Harrison9c654812014-11-24 18:49:35 +00002755int __i915_wait_request(struct drm_i915_gem_request *req,
Ander Conselvan de Oliveira16e9a212014-11-06 09:26:38 +02002756 unsigned reset_counter,
2757 bool interruptible,
2758 s64 *timeout,
2759 struct drm_i915_file_private *file_priv);
Daniel Vettera4b3a572014-11-26 14:17:05 +01002760int __must_check i915_wait_request(struct drm_i915_gem_request *req);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002761int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00002762int __must_check
2763i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2764 bool write);
2765int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02002766i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2767int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002768i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2769 u32 alignment,
Tvrtko Ursuline6617332015-03-23 11:10:33 +00002770 struct intel_engine_cs *pipelined,
2771 const struct i915_ggtt_view *view);
2772void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2773 const struct i915_ggtt_view *view);
Chris Wilson00731152014-05-21 12:42:56 +01002774int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01002775 int align);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002776int i915_gem_open(struct drm_device *dev, struct drm_file *file);
Chris Wilson05394f32010-11-08 19:18:58 +00002777void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002778
Chris Wilson467cffb2011-03-07 10:42:03 +00002779uint32_t
Imre Deak0fa87792013-01-07 21:47:35 +02002780i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2781uint32_t
Imre Deakd8651102013-01-07 21:47:33 +02002782i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2783 int tiling_mode, bool fenced);
Chris Wilson467cffb2011-03-07 10:42:03 +00002784
Chris Wilsone4ffd172011-04-04 09:44:39 +01002785int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2786 enum i915_cache_level cache_level);
2787
Daniel Vetter1286ff72012-05-10 15:25:09 +02002788struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2789 struct dma_buf *dma_buf);
2790
2791struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2792 struct drm_gem_object *gem_obj, int flags);
2793
Chris Wilson19b2dbd2013-06-12 10:15:12 +01002794void i915_gem_restore_fences(struct drm_device *dev);
2795
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002796unsigned long
2797i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02002798 const struct i915_ggtt_view *view);
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002799unsigned long
2800i915_gem_obj_offset(struct drm_i915_gem_object *o,
2801 struct i915_address_space *vm);
2802static inline unsigned long
2803i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002804{
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02002805 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002806}
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002807
Ben Widawskya70a3142013-07-31 16:59:56 -07002808bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002809bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02002810 const struct i915_ggtt_view *view);
Ben Widawskya70a3142013-07-31 16:59:56 -07002811bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002812 struct i915_address_space *vm);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002813
Ben Widawskya70a3142013-07-31 16:59:56 -07002814unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2815 struct i915_address_space *vm);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002816struct i915_vma *
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002817i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2818 struct i915_address_space *vm);
2819struct i915_vma *
2820i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
2821 const struct i915_ggtt_view *view);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002822
Ben Widawskyaccfef22013-08-14 11:38:35 +02002823struct i915_vma *
2824i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002825 struct i915_address_space *vm);
2826struct i915_vma *
2827i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2828 const struct i915_ggtt_view *view);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07002829
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002830static inline struct i915_vma *
2831i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
2832{
2833 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08002834}
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002835bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07002836
Ben Widawskya70a3142013-07-31 16:59:56 -07002837/* Some GGTT VM helpers */
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002838#define i915_obj_to_ggtt(obj) \
Ben Widawskya70a3142013-07-31 16:59:56 -07002839 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2840static inline bool i915_is_ggtt(struct i915_address_space *vm)
2841{
2842 struct i915_address_space *ggtt =
2843 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2844 return vm == ggtt;
2845}
2846
Daniel Vetter841cd772014-08-06 15:04:48 +02002847static inline struct i915_hw_ppgtt *
2848i915_vm_to_ppgtt(struct i915_address_space *vm)
2849{
2850 WARN_ON(i915_is_ggtt(vm));
2851
2852 return container_of(vm, struct i915_hw_ppgtt, base);
2853}
2854
2855
Ben Widawskya70a3142013-07-31 16:59:56 -07002856static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2857{
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02002858 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
Ben Widawskya70a3142013-07-31 16:59:56 -07002859}
2860
2861static inline unsigned long
2862i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2863{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002864 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
Ben Widawskya70a3142013-07-31 16:59:56 -07002865}
Ben Widawskyc37e2202013-07-31 16:59:58 -07002866
2867static inline int __must_check
2868i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2869 uint32_t alignment,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002870 unsigned flags)
Ben Widawskyc37e2202013-07-31 16:59:58 -07002871{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02002872 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2873 alignment, flags | PIN_GLOBAL);
Ben Widawskyc37e2202013-07-31 16:59:58 -07002874}
Ben Widawskya70a3142013-07-31 16:59:56 -07002875
Daniel Vetterb2871102014-02-14 14:01:19 +01002876static inline int
2877i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2878{
2879 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2880}
2881
Tvrtko Ursuline6617332015-03-23 11:10:33 +00002882void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
2883 const struct i915_ggtt_view *view);
2884static inline void
2885i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
2886{
2887 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
2888}
Daniel Vetterb2871102014-02-14 14:01:19 +01002889
Ben Widawsky254f9652012-06-04 14:42:42 -07002890/* i915_gem_context.c */
Ben Widawsky8245be32013-11-06 13:56:29 -02002891int __must_check i915_gem_context_init(struct drm_device *dev);
Ben Widawsky254f9652012-06-04 14:42:42 -07002892void i915_gem_context_fini(struct drm_device *dev);
Ben Widawskyacce9ff2013-12-06 14:11:03 -08002893void i915_gem_context_reset(struct drm_device *dev);
Ben Widawskye422b882013-12-06 14:10:58 -08002894int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
Ben Widawsky2fa48d82013-12-06 14:11:04 -08002895int i915_gem_context_enable(struct drm_i915_private *dev_priv);
Ben Widawsky254f9652012-06-04 14:42:42 -07002896void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002897int i915_switch_context(struct intel_engine_cs *ring,
Oscar Mateo273497e2014-05-22 14:13:37 +01002898 struct intel_context *to);
2899struct intel_context *
Ben Widawsky41bde552013-12-06 14:11:21 -08002900i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002901void i915_gem_context_free(struct kref *ctx_ref);
Oscar Mateo8c8579172014-07-24 17:04:14 +01002902struct drm_i915_gem_object *
2903i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
Oscar Mateo273497e2014-05-22 14:13:37 +01002904static inline void i915_gem_context_reference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03002905{
Chris Wilson691e6412014-04-09 09:07:36 +01002906 kref_get(&ctx->ref);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002907}
2908
Oscar Mateo273497e2014-05-22 14:13:37 +01002909static inline void i915_gem_context_unreference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03002910{
Chris Wilson691e6412014-04-09 09:07:36 +01002911 kref_put(&ctx->ref, i915_gem_context_free);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002912}
2913
Oscar Mateo273497e2014-05-22 14:13:37 +01002914static inline bool i915_gem_context_is_default(const struct intel_context *c)
Mika Kuoppala3fac8972014-01-30 16:05:48 +02002915{
Oscar Mateo821d66d2014-07-03 16:28:00 +01002916 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
Mika Kuoppala3fac8972014-01-30 16:05:48 +02002917}
2918
Ben Widawsky84624812012-06-04 14:42:54 -07002919int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2920 struct drm_file *file);
2921int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2922 struct drm_file *file);
Chris Wilsonc9dc0f32014-12-24 08:13:40 -08002923int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2924 struct drm_file *file_priv);
2925int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2926 struct drm_file *file_priv);
Daniel Vetter1286ff72012-05-10 15:25:09 +02002927
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002928/* i915_gem_evict.c */
Ben Widawskyf6cd1f12013-07-31 17:00:11 -07002929int __must_check i915_gem_evict_something(struct drm_device *dev,
2930 struct i915_address_space *vm,
2931 int min_size,
Chris Wilson42d6ab42012-07-26 11:49:32 +01002932 unsigned alignment,
2933 unsigned cache_level,
Chris Wilsond23db882014-05-23 08:48:08 +02002934 unsigned long start,
2935 unsigned long end,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01002936 unsigned flags);
Ben Widawsky68c8c172013-09-11 14:57:50 -07002937int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
Chris Wilson6c085a72012-08-20 11:40:46 +02002938int i915_gem_evict_everything(struct drm_device *dev);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002939
Ben Widawsky0260c422014-03-22 22:47:21 -07002940/* belongs in i915_gem_gtt.h */
Eric Anholt673a3942008-07-30 12:06:12 -07002941static inline void i915_gem_chipset_flush(struct drm_device *dev)
2942{
Chris Wilson05394f32010-11-08 19:18:58 +00002943 if (INTEL_INFO(dev)->gen < 6)
2944 intel_gtt_chipset_flush();
Chris Wilson9797fbf2012-04-24 15:47:39 +01002945}
Ben Widawsky246cbfb2013-12-06 14:11:14 -08002946
Chris Wilson9797fbf2012-04-24 15:47:39 +01002947/* i915_gem_stolen.c */
2948int i915_gem_init_stolen(struct drm_device *dev);
Ben Widawsky5e59f712014-06-30 10:41:24 -07002949int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
Chris Wilson11be49e2012-11-15 11:32:20 +00002950void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
Chris Wilson9797fbf2012-04-24 15:47:39 +01002951void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00002952struct drm_i915_gem_object *
2953i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
Chris Wilson866d12b2013-02-19 13:31:37 -08002954struct drm_i915_gem_object *
2955i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2956 u32 stolen_offset,
2957 u32 gtt_offset,
2958 u32 size);
Chris Wilson9797fbf2012-04-24 15:47:39 +01002959
Daniel Vetterbe6a0372015-03-18 10:46:04 +01002960/* i915_gem_shrinker.c */
2961unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2962 long target,
2963 unsigned flags);
2964#define I915_SHRINK_PURGEABLE 0x1
2965#define I915_SHRINK_UNBOUND 0x2
2966#define I915_SHRINK_BOUND 0x4
2967unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
2968void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
2969
2970
Eric Anholt673a3942008-07-30 12:06:12 -07002971/* i915_gem_tiling.c */
Chris Wilson2c1792a2013-08-01 18:39:55 +01002972static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
Chris Wilsone9b73c62012-12-03 21:03:14 +00002973{
Jani Nikula50227e12014-03-31 14:27:21 +03002974 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsone9b73c62012-12-03 21:03:14 +00002975
2976 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2977 obj->tiling_mode != I915_TILING_NONE;
2978}
2979
Eric Anholt673a3942008-07-30 12:06:12 -07002980void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Eric Anholt280b7132009-03-12 16:56:27 -07002981void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2982void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002983
2984/* i915_gem_debug.c */
Chris Wilson23bc5982010-09-29 16:10:57 +01002985#if WATCH_LISTS
2986int i915_verify_lists(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07002987#else
Chris Wilson23bc5982010-09-29 16:10:57 +01002988#define i915_verify_lists(dev) 0
Eric Anholt673a3942008-07-30 12:06:12 -07002989#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002990
Ben Gamari20172632009-02-17 20:08:50 -05002991/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -04002992int i915_debugfs_init(struct drm_minor *minor);
2993void i915_debugfs_cleanup(struct drm_minor *minor);
Daniel Vetterf8c168f2013-10-16 11:49:58 +02002994#ifdef CONFIG_DEBUG_FS
Damien Lespiau07144422013-10-15 18:55:40 +01002995void intel_display_crc_init(struct drm_device *dev);
2996#else
Daniel Vetterf8c168f2013-10-16 11:49:58 +02002997static inline void intel_display_crc_init(struct drm_device *dev) {}
Damien Lespiau07144422013-10-15 18:55:40 +01002998#endif
Mika Kuoppala84734a02013-07-12 16:50:57 +03002999
3000/* i915_gpu_error.c */
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003001__printf(2, 3)
3002void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
Mika Kuoppalafc16b482013-06-06 15:18:39 +03003003int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3004 const struct i915_error_state_file_priv *error);
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003005int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003006 struct drm_i915_private *i915,
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003007 size_t count, loff_t pos);
3008static inline void i915_error_state_buf_release(
3009 struct drm_i915_error_state_buf *eb)
3010{
3011 kfree(eb->buf);
3012}
Mika Kuoppala58174462014-02-25 17:11:26 +02003013void i915_capture_error_state(struct drm_device *dev, bool wedge,
3014 const char *error_msg);
Mika Kuoppala84734a02013-07-12 16:50:57 +03003015void i915_error_state_get(struct drm_device *dev,
3016 struct i915_error_state_file_priv *error_priv);
3017void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3018void i915_destroy_error_state(struct drm_device *dev);
3019
3020void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003021const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
Ben Gamari20172632009-02-17 20:08:50 -05003022
Brad Volkin493018d2014-12-11 12:13:08 -08003023/* i915_gem_batch_pool.c */
3024void i915_gem_batch_pool_init(struct drm_device *dev,
3025 struct i915_gem_batch_pool *pool);
3026void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool);
3027struct drm_i915_gem_object*
3028i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size);
3029
Brad Volkin351e3db2014-02-18 10:15:46 -08003030/* i915_cmd_parser.c */
Brad Volkind728c8e2014-02-18 10:15:56 -08003031int i915_cmd_parser_get_version(void);
Oscar Mateoa4872ba2014-05-22 14:13:33 +01003032int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3033void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3034bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3035int i915_parse_cmds(struct intel_engine_cs *ring,
Brad Volkin351e3db2014-02-18 10:15:46 -08003036 struct drm_i915_gem_object *batch_obj,
Brad Volkin78a42372014-12-11 12:13:09 -08003037 struct drm_i915_gem_object *shadow_batch_obj,
Brad Volkin351e3db2014-02-18 10:15:46 -08003038 u32 batch_start_offset,
Brad Volkinb9ffd802014-12-11 12:13:10 -08003039 u32 batch_len,
Brad Volkin351e3db2014-02-18 10:15:46 -08003040 bool is_master);
3041
Jesse Barnes317c35d2008-08-25 15:11:06 -07003042/* i915_suspend.c */
3043extern int i915_save_state(struct drm_device *dev);
3044extern int i915_restore_state(struct drm_device *dev);
3045
Ben Widawsky0136db582012-04-10 21:17:01 -07003046/* i915_sysfs.c */
3047void i915_setup_sysfs(struct drm_device *dev_priv);
3048void i915_teardown_sysfs(struct drm_device *dev_priv);
3049
Chris Wilsonf899fc62010-07-20 15:44:45 -07003050/* intel_i2c.c */
3051extern int intel_setup_gmbus(struct drm_device *dev);
3052extern void intel_teardown_gmbus(struct drm_device *dev);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02003053static inline bool intel_gmbus_is_port_valid(unsigned port)
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08003054{
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08003055 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08003056}
3057
3058extern struct i2c_adapter *intel_gmbus_get_adapter(
3059 struct drm_i915_private *dev_priv, unsigned port);
Chris Wilsone957d772010-09-24 12:52:03 +01003060extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3061extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02003062static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
Chris Wilsonb8232e92010-09-28 16:41:32 +01003063{
3064 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3065}
Chris Wilsonf899fc62010-07-20 15:44:45 -07003066extern void intel_i2c_reset(struct drm_device *dev);
3067
Chris Wilson3b617962010-08-24 09:02:58 +01003068/* intel_opregion.c */
Chris Wilson44834a62010-08-19 16:09:23 +01003069#ifdef CONFIG_ACPI
Lv Zheng27d50c82013-12-06 16:52:05 +08003070extern int intel_opregion_setup(struct drm_device *dev);
Chris Wilson44834a62010-08-19 16:09:23 +01003071extern void intel_opregion_init(struct drm_device *dev);
3072extern void intel_opregion_fini(struct drm_device *dev);
Chris Wilson3b617962010-08-24 09:02:58 +01003073extern void intel_opregion_asle_intr(struct drm_device *dev);
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003074extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3075 bool enable);
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003076extern int intel_opregion_notify_adapter(struct drm_device *dev,
3077 pci_power_t state);
Len Brown65e082c2008-10-24 17:18:10 -04003078#else
Lv Zheng27d50c82013-12-06 16:52:05 +08003079static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
Chris Wilson44834a62010-08-19 16:09:23 +01003080static inline void intel_opregion_init(struct drm_device *dev) { return; }
3081static inline void intel_opregion_fini(struct drm_device *dev) { return; }
Chris Wilson3b617962010-08-24 09:02:58 +01003082static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003083static inline int
3084intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3085{
3086 return 0;
3087}
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003088static inline int
3089intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3090{
3091 return 0;
3092}
Len Brown65e082c2008-10-24 17:18:10 -04003093#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01003094
Jesse Barnes723bfd72010-10-07 16:01:13 -07003095/* intel_acpi.c */
3096#ifdef CONFIG_ACPI
3097extern void intel_register_dsm_handler(void);
3098extern void intel_unregister_dsm_handler(void);
3099#else
3100static inline void intel_register_dsm_handler(void) { return; }
3101static inline void intel_unregister_dsm_handler(void) { return; }
3102#endif /* CONFIG_ACPI */
3103
Jesse Barnes79e53942008-11-07 14:24:08 -08003104/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02003105extern void intel_modeset_init_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003106extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01003107extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003108extern void intel_modeset_cleanup(struct drm_device *dev);
Imre Deak4932e2c2014-02-11 17:12:48 +02003109extern void intel_connector_unregister(struct intel_connector *);
Dave Airlie28d52042009-09-21 14:33:58 +10003110extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01003111extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3112 bool force_restore);
Daniel Vetter44cec742013-01-25 17:53:21 +01003113extern void i915_redisable_vga(struct drm_device *dev);
Imre Deak04098752014-02-18 00:02:16 +02003114extern void i915_redisable_vga_power_on(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07003115extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
Paulo Zanonidde86e22012-12-01 12:04:25 -02003116extern void intel_init_pch_refclk(struct drm_device *dev);
Ville Syrjäläffe02b42015-02-02 19:09:50 +02003117extern void intel_set_rps(struct drm_device *dev, u8 val);
Imre Deak5209b1f2014-07-01 12:36:17 +03003118extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3119 bool enable);
Akshay Joshi0206e352011-08-16 15:34:10 -04003120extern void intel_detect_pch(struct drm_device *dev);
3121extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
Ben Widawsky0136db582012-04-10 21:17:01 -07003122extern int intel_enable_rc6(const struct drm_device *dev);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08003123
Ben Widawsky2911a352012-04-05 14:47:36 -07003124extern bool i915_semaphore_is_enabled(struct drm_device *dev);
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07003125int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3126 struct drm_file *file);
Mika Kuoppalab6359912013-10-30 15:44:16 +02003127int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3128 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07003129
Chris Wilson6ef3d422010-08-04 20:26:07 +01003130/* overlay */
3131extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003132extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3133 struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003134
3135extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003136extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003137 struct drm_device *dev,
3138 struct intel_display_error_state *error);
Chris Wilson6ef3d422010-08-04 20:26:07 +01003139
Tom O'Rourke151a49d2014-11-13 18:50:10 -08003140int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3141int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003142
3143/* intel_sideband.c */
Deepak S707b6e32015-01-16 20:42:17 +05303144u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3145void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
Jani Nikula64936252013-05-22 15:36:20 +03003146u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
Jani Nikulae9f882a2013-08-27 15:12:14 +03003147u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3148void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3149u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3150void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3151u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3152void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnesf3419152013-11-04 11:52:44 -08003153u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3154void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jani Nikulae9f882a2013-08-27 15:12:14 +03003155u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3156void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08003157u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3158void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003159u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3160 enum intel_sbi_destination destination);
3161void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3162 enum intel_sbi_destination destination);
Shobhit Kumare9fe51c2013-12-10 12:14:55 +05303163u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3164void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003165
Ville Syrjälä616bc822015-01-23 21:04:25 +02003166int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3167int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
Deepak Sc8d9a592013-11-23 14:55:42 +05303168
Ben Widawsky0b274482013-10-04 21:22:51 -07003169#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3170#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
Keith Packard5f753772010-11-22 09:24:22 +00003171
Ben Widawsky0b274482013-10-04 21:22:51 -07003172#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3173#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3174#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3175#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003176
Ben Widawsky0b274482013-10-04 21:22:51 -07003177#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3178#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3179#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3180#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003181
Chris Wilson698b3132014-03-21 13:16:43 +00003182/* Be very careful with read/write 64-bit values. On 32-bit machines, they
3183 * will be implemented using 2 32-bit writes in an arbitrary order with
3184 * an arbitrary delay between them. This can cause the hardware to
3185 * act upon the intermediate value, possibly leading to corruption and
3186 * machine death. You have been warned.
3187 */
Ben Widawsky0b274482013-10-04 21:22:51 -07003188#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3189#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
Zou Nan haicae58522010-11-09 17:17:32 +08003190
Chris Wilson50877442014-03-21 12:41:53 +00003191#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3192 u32 upper = I915_READ(upper_reg); \
3193 u32 lower = I915_READ(lower_reg); \
3194 u32 tmp = I915_READ(upper_reg); \
3195 if (upper != tmp) { \
3196 upper = tmp; \
3197 lower = I915_READ(lower_reg); \
3198 WARN_ON(I915_READ(upper_reg) != upper); \
3199 } \
3200 (u64)upper << 32 | lower; })
3201
Zou Nan haicae58522010-11-09 17:17:32 +08003202#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3203#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3204
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003205/* "Broadcast RGB" property */
3206#define INTEL_BROADCAST_RGB_AUTO 0
3207#define INTEL_BROADCAST_RGB_FULL 1
3208#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08003209
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003210static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3211{
Sonika Jindal92e23b92014-07-21 15:23:40 +05303212 if (IS_VALLEYVIEW(dev))
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003213 return VLV_VGACNTRL;
Sonika Jindal92e23b92014-07-21 15:23:40 +05303214 else if (INTEL_INFO(dev)->gen >= 5)
3215 return CPU_VGACNTRL;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003216 else
3217 return VGACNTRL;
3218}
3219
Ville Syrjälä2bb46292013-02-22 16:12:51 +02003220static inline void __user *to_user_ptr(u64 address)
3221{
3222 return (void __user *)(uintptr_t)address;
3223}
3224
Imre Deakdf977292013-05-21 20:03:17 +03003225static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3226{
3227 unsigned long j = msecs_to_jiffies(m);
3228
3229 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3230}
3231
Daniel Vetter7bd0e222014-12-04 11:12:54 +01003232static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3233{
3234 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3235}
3236
Imre Deakdf977292013-05-21 20:03:17 +03003237static inline unsigned long
3238timespec_to_jiffies_timeout(const struct timespec *value)
3239{
3240 unsigned long j = timespec_to_jiffies(value);
3241
3242 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3243}
3244
Paulo Zanonidce56b32013-12-19 14:29:40 -02003245/*
3246 * If you need to wait X milliseconds between events A and B, but event B
3247 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3248 * when event A happened, then just before event B you call this function and
3249 * pass the timestamp as the first argument, and X as the second argument.
3250 */
3251static inline void
3252wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3253{
Imre Deakec5e0cf2014-01-29 13:25:40 +02003254 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
Paulo Zanonidce56b32013-12-19 14:29:40 -02003255
3256 /*
3257 * Don't re-read the value of "jiffies" every time since it may change
3258 * behind our back and break the math.
3259 */
3260 tmp_jiffies = jiffies;
3261 target_jiffies = timestamp_jiffies +
3262 msecs_to_jiffies_timeout(to_wait_ms);
3263
3264 if (time_after(target_jiffies, tmp_jiffies)) {
Imre Deakec5e0cf2014-01-29 13:25:40 +02003265 remaining_jiffies = target_jiffies - tmp_jiffies;
3266 while (remaining_jiffies)
3267 remaining_jiffies =
3268 schedule_timeout_uninterruptible(remaining_jiffies);
Paulo Zanonidce56b32013-12-19 14:29:40 -02003269 }
3270}
3271
John Harrison581c26e82014-11-24 18:49:39 +00003272static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3273 struct drm_i915_gem_request *req)
3274{
3275 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3276 i915_gem_request_assign(&ring->trace_irq_req, req);
3277}
3278
Linus Torvalds1da177e2005-04-16 15:20:36 -07003279#endif