Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator |
| 3 | * |
| 4 | * MIPS floating point support |
| 5 | * Copyright (C) 1994-2000 Algorithmics Ltd. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
| 7 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com |
| 8 | * Copyright (C) 2000 MIPS Technologies, Inc. |
| 9 | * |
| 10 | * This program is free software; you can distribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License (Version 2) as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 17 | * for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along |
| 20 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 21 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 22 | * |
| 23 | * A complete emulator for MIPS coprocessor 1 instructions. This is |
| 24 | * required for #float(switch) or #float(trap), where it catches all |
| 25 | * COP1 instructions via the "CoProcessor Unusable" exception. |
| 26 | * |
| 27 | * More surprisingly it is also required for #float(ieee), to help out |
| 28 | * the hardware fpu at the boundaries of the IEEE-754 representation |
| 29 | * (denormalised values, infinities, underflow, etc). It is made |
| 30 | * quite nasty because emulation of some non-COP1 instructions is |
| 31 | * required, e.g. in branch delay slots. |
| 32 | * |
| 33 | * Note if you know that you won't have an fpu, then you'll get much |
| 34 | * better performance by compiling with -msoft-float! |
| 35 | */ |
| 36 | #include <linux/sched.h> |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 37 | #include <linux/module.h> |
Atsushi Nemoto | 83fd38c | 2007-07-07 23:21:49 +0900 | [diff] [blame] | 38 | #include <linux/debugfs.h> |
Deng-Cheng Zhu | 7f788d2 | 2010-10-12 19:37:21 +0800 | [diff] [blame] | 39 | #include <linux/perf_event.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | |
| 41 | #include <asm/inst.h> |
| 42 | #include <asm/bootinfo.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | #include <asm/processor.h> |
| 44 | #include <asm/ptrace.h> |
| 45 | #include <asm/signal.h> |
| 46 | #include <asm/mipsregs.h> |
| 47 | #include <asm/fpu_emulator.h> |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 48 | #include <asm/fpu.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | #include <asm/uaccess.h> |
| 50 | #include <asm/branch.h> |
| 51 | |
| 52 | #include "ieee754.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | |
| 54 | /* Strap kernel emulator for full MIPS IV emulation */ |
| 55 | |
| 56 | #ifdef __mips |
| 57 | #undef __mips |
| 58 | #endif |
| 59 | #define __mips 4 |
| 60 | |
| 61 | /* Function which emulates a floating point instruction. */ |
| 62 | |
Atsushi Nemoto | eae8907 | 2006-05-16 01:26:03 +0900 | [diff] [blame] | 63 | static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | mips_instruction); |
| 65 | |
| 66 | #if __mips >= 4 && __mips != 32 |
| 67 | static int fpux_emu(struct pt_regs *, |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 68 | struct mips_fpu_struct *, mips_instruction, void *__user *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | #endif |
| 70 | |
Atsushi Nemoto | eae8907 | 2006-05-16 01:26:03 +0900 | [diff] [blame] | 71 | /* Further private data for which no space exists in mips_fpu_struct */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 73 | #ifdef CONFIG_DEBUG_FS |
| 74 | DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); |
| 75 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | |
| 77 | /* Control registers */ |
| 78 | |
| 79 | #define FPCREG_RID 0 /* $0 = revision id */ |
| 80 | #define FPCREG_CSR 31 /* $31 = csr */ |
| 81 | |
Shane McDonald | 95e8f63 | 2010-05-06 23:26:57 -0600 | [diff] [blame] | 82 | /* Determine rounding mode from the RM bits of the FCSR */ |
| 83 | #define modeindex(v) ((v) & FPU_CSR_RM) |
| 84 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 85 | /* microMIPS bitfields */ |
| 86 | #define MM_POOL32A_MINOR_MASK 0x3f |
| 87 | #define MM_POOL32A_MINOR_SHIFT 0x6 |
| 88 | #define MM_MIPS32_COND_FC 0x30 |
| 89 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | /* Convert Mips rounding mode (0..3) to IEEE library modes. */ |
| 91 | static const unsigned char ieee_rm[4] = { |
Ralf Baechle | cd21dfc | 2005-04-28 13:39:10 +0000 | [diff] [blame] | 92 | [FPU_CSR_RN] = IEEE754_RN, |
| 93 | [FPU_CSR_RZ] = IEEE754_RZ, |
| 94 | [FPU_CSR_RU] = IEEE754_RU, |
| 95 | [FPU_CSR_RD] = IEEE754_RD, |
| 96 | }; |
| 97 | /* Convert IEEE library modes to Mips rounding mode (0..3). */ |
| 98 | static const unsigned char mips_rm[4] = { |
| 99 | [IEEE754_RN] = FPU_CSR_RN, |
| 100 | [IEEE754_RZ] = FPU_CSR_RZ, |
| 101 | [IEEE754_RD] = FPU_CSR_RD, |
| 102 | [IEEE754_RU] = FPU_CSR_RU, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | }; |
| 104 | |
| 105 | #if __mips >= 4 |
| 106 | /* convert condition code register number to csr bit */ |
| 107 | static const unsigned int fpucondbit[8] = { |
| 108 | FPU_CSR_COND0, |
| 109 | FPU_CSR_COND1, |
| 110 | FPU_CSR_COND2, |
| 111 | FPU_CSR_COND3, |
| 112 | FPU_CSR_COND4, |
| 113 | FPU_CSR_COND5, |
| 114 | FPU_CSR_COND6, |
| 115 | FPU_CSR_COND7 |
| 116 | }; |
| 117 | #endif |
| 118 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 119 | /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */ |
| 120 | static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7}; |
| 121 | |
| 122 | /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ |
| 123 | static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; |
| 124 | static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; |
| 125 | static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; |
| 126 | static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; |
| 127 | |
| 128 | /* |
| 129 | * This functions translates a 32-bit microMIPS instruction |
| 130 | * into a 32-bit MIPS32 instruction. Returns 0 on success |
| 131 | * and SIGILL otherwise. |
| 132 | */ |
| 133 | static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) |
| 134 | { |
| 135 | union mips_instruction insn = *insn_ptr; |
| 136 | union mips_instruction mips32_insn = insn; |
| 137 | int func, fmt, op; |
| 138 | |
| 139 | switch (insn.mm_i_format.opcode) { |
| 140 | case mm_ldc132_op: |
| 141 | mips32_insn.mm_i_format.opcode = ldc1_op; |
| 142 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; |
| 143 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; |
| 144 | break; |
| 145 | case mm_lwc132_op: |
| 146 | mips32_insn.mm_i_format.opcode = lwc1_op; |
| 147 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; |
| 148 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; |
| 149 | break; |
| 150 | case mm_sdc132_op: |
| 151 | mips32_insn.mm_i_format.opcode = sdc1_op; |
| 152 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; |
| 153 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; |
| 154 | break; |
| 155 | case mm_swc132_op: |
| 156 | mips32_insn.mm_i_format.opcode = swc1_op; |
| 157 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; |
| 158 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; |
| 159 | break; |
| 160 | case mm_pool32i_op: |
| 161 | /* NOTE: offset is << by 1 if in microMIPS mode. */ |
| 162 | if ((insn.mm_i_format.rt == mm_bc1f_op) || |
| 163 | (insn.mm_i_format.rt == mm_bc1t_op)) { |
| 164 | mips32_insn.fb_format.opcode = cop1_op; |
| 165 | mips32_insn.fb_format.bc = bc_op; |
| 166 | mips32_insn.fb_format.flag = |
| 167 | (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; |
| 168 | } else |
| 169 | return SIGILL; |
| 170 | break; |
| 171 | case mm_pool32f_op: |
| 172 | switch (insn.mm_fp0_format.func) { |
| 173 | case mm_32f_01_op: |
| 174 | case mm_32f_11_op: |
| 175 | case mm_32f_02_op: |
| 176 | case mm_32f_12_op: |
| 177 | case mm_32f_41_op: |
| 178 | case mm_32f_51_op: |
| 179 | case mm_32f_42_op: |
| 180 | case mm_32f_52_op: |
| 181 | op = insn.mm_fp0_format.func; |
| 182 | if (op == mm_32f_01_op) |
| 183 | func = madd_s_op; |
| 184 | else if (op == mm_32f_11_op) |
| 185 | func = madd_d_op; |
| 186 | else if (op == mm_32f_02_op) |
| 187 | func = nmadd_s_op; |
| 188 | else if (op == mm_32f_12_op) |
| 189 | func = nmadd_d_op; |
| 190 | else if (op == mm_32f_41_op) |
| 191 | func = msub_s_op; |
| 192 | else if (op == mm_32f_51_op) |
| 193 | func = msub_d_op; |
| 194 | else if (op == mm_32f_42_op) |
| 195 | func = nmsub_s_op; |
| 196 | else |
| 197 | func = nmsub_d_op; |
| 198 | mips32_insn.fp6_format.opcode = cop1x_op; |
| 199 | mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; |
| 200 | mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; |
| 201 | mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; |
| 202 | mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; |
| 203 | mips32_insn.fp6_format.func = func; |
| 204 | break; |
| 205 | case mm_32f_10_op: |
| 206 | func = -1; /* Invalid */ |
| 207 | op = insn.mm_fp5_format.op & 0x7; |
| 208 | if (op == mm_ldxc1_op) |
| 209 | func = ldxc1_op; |
| 210 | else if (op == mm_sdxc1_op) |
| 211 | func = sdxc1_op; |
| 212 | else if (op == mm_lwxc1_op) |
| 213 | func = lwxc1_op; |
| 214 | else if (op == mm_swxc1_op) |
| 215 | func = swxc1_op; |
| 216 | |
| 217 | if (func != -1) { |
| 218 | mips32_insn.r_format.opcode = cop1x_op; |
| 219 | mips32_insn.r_format.rs = |
| 220 | insn.mm_fp5_format.base; |
| 221 | mips32_insn.r_format.rt = |
| 222 | insn.mm_fp5_format.index; |
| 223 | mips32_insn.r_format.rd = 0; |
| 224 | mips32_insn.r_format.re = insn.mm_fp5_format.fd; |
| 225 | mips32_insn.r_format.func = func; |
| 226 | } else |
| 227 | return SIGILL; |
| 228 | break; |
| 229 | case mm_32f_40_op: |
| 230 | op = -1; /* Invalid */ |
| 231 | if (insn.mm_fp2_format.op == mm_fmovt_op) |
| 232 | op = 1; |
| 233 | else if (insn.mm_fp2_format.op == mm_fmovf_op) |
| 234 | op = 0; |
| 235 | if (op != -1) { |
| 236 | mips32_insn.fp0_format.opcode = cop1_op; |
| 237 | mips32_insn.fp0_format.fmt = |
| 238 | sdps_format[insn.mm_fp2_format.fmt]; |
| 239 | mips32_insn.fp0_format.ft = |
| 240 | (insn.mm_fp2_format.cc<<2) + op; |
| 241 | mips32_insn.fp0_format.fs = |
| 242 | insn.mm_fp2_format.fs; |
| 243 | mips32_insn.fp0_format.fd = |
| 244 | insn.mm_fp2_format.fd; |
| 245 | mips32_insn.fp0_format.func = fmovc_op; |
| 246 | } else |
| 247 | return SIGILL; |
| 248 | break; |
| 249 | case mm_32f_60_op: |
| 250 | func = -1; /* Invalid */ |
| 251 | if (insn.mm_fp0_format.op == mm_fadd_op) |
| 252 | func = fadd_op; |
| 253 | else if (insn.mm_fp0_format.op == mm_fsub_op) |
| 254 | func = fsub_op; |
| 255 | else if (insn.mm_fp0_format.op == mm_fmul_op) |
| 256 | func = fmul_op; |
| 257 | else if (insn.mm_fp0_format.op == mm_fdiv_op) |
| 258 | func = fdiv_op; |
| 259 | if (func != -1) { |
| 260 | mips32_insn.fp0_format.opcode = cop1_op; |
| 261 | mips32_insn.fp0_format.fmt = |
| 262 | sdps_format[insn.mm_fp0_format.fmt]; |
| 263 | mips32_insn.fp0_format.ft = |
| 264 | insn.mm_fp0_format.ft; |
| 265 | mips32_insn.fp0_format.fs = |
| 266 | insn.mm_fp0_format.fs; |
| 267 | mips32_insn.fp0_format.fd = |
| 268 | insn.mm_fp0_format.fd; |
| 269 | mips32_insn.fp0_format.func = func; |
| 270 | } else |
| 271 | return SIGILL; |
| 272 | break; |
| 273 | case mm_32f_70_op: |
| 274 | func = -1; /* Invalid */ |
| 275 | if (insn.mm_fp0_format.op == mm_fmovn_op) |
| 276 | func = fmovn_op; |
| 277 | else if (insn.mm_fp0_format.op == mm_fmovz_op) |
| 278 | func = fmovz_op; |
| 279 | if (func != -1) { |
| 280 | mips32_insn.fp0_format.opcode = cop1_op; |
| 281 | mips32_insn.fp0_format.fmt = |
| 282 | sdps_format[insn.mm_fp0_format.fmt]; |
| 283 | mips32_insn.fp0_format.ft = |
| 284 | insn.mm_fp0_format.ft; |
| 285 | mips32_insn.fp0_format.fs = |
| 286 | insn.mm_fp0_format.fs; |
| 287 | mips32_insn.fp0_format.fd = |
| 288 | insn.mm_fp0_format.fd; |
| 289 | mips32_insn.fp0_format.func = func; |
| 290 | } else |
| 291 | return SIGILL; |
| 292 | break; |
| 293 | case mm_32f_73_op: /* POOL32FXF */ |
| 294 | switch (insn.mm_fp1_format.op) { |
| 295 | case mm_movf0_op: |
| 296 | case mm_movf1_op: |
| 297 | case mm_movt0_op: |
| 298 | case mm_movt1_op: |
| 299 | if ((insn.mm_fp1_format.op & 0x7f) == |
| 300 | mm_movf0_op) |
| 301 | op = 0; |
| 302 | else |
| 303 | op = 1; |
| 304 | mips32_insn.r_format.opcode = spec_op; |
| 305 | mips32_insn.r_format.rs = insn.mm_fp4_format.fs; |
| 306 | mips32_insn.r_format.rt = |
| 307 | (insn.mm_fp4_format.cc << 2) + op; |
| 308 | mips32_insn.r_format.rd = insn.mm_fp4_format.rt; |
| 309 | mips32_insn.r_format.re = 0; |
| 310 | mips32_insn.r_format.func = movc_op; |
| 311 | break; |
| 312 | case mm_fcvtd0_op: |
| 313 | case mm_fcvtd1_op: |
| 314 | case mm_fcvts0_op: |
| 315 | case mm_fcvts1_op: |
| 316 | if ((insn.mm_fp1_format.op & 0x7f) == |
| 317 | mm_fcvtd0_op) { |
| 318 | func = fcvtd_op; |
| 319 | fmt = swl_format[insn.mm_fp3_format.fmt]; |
| 320 | } else { |
| 321 | func = fcvts_op; |
| 322 | fmt = dwl_format[insn.mm_fp3_format.fmt]; |
| 323 | } |
| 324 | mips32_insn.fp0_format.opcode = cop1_op; |
| 325 | mips32_insn.fp0_format.fmt = fmt; |
| 326 | mips32_insn.fp0_format.ft = 0; |
| 327 | mips32_insn.fp0_format.fs = |
| 328 | insn.mm_fp3_format.fs; |
| 329 | mips32_insn.fp0_format.fd = |
| 330 | insn.mm_fp3_format.rt; |
| 331 | mips32_insn.fp0_format.func = func; |
| 332 | break; |
| 333 | case mm_fmov0_op: |
| 334 | case mm_fmov1_op: |
| 335 | case mm_fabs0_op: |
| 336 | case mm_fabs1_op: |
| 337 | case mm_fneg0_op: |
| 338 | case mm_fneg1_op: |
| 339 | if ((insn.mm_fp1_format.op & 0x7f) == |
| 340 | mm_fmov0_op) |
| 341 | func = fmov_op; |
| 342 | else if ((insn.mm_fp1_format.op & 0x7f) == |
| 343 | mm_fabs0_op) |
| 344 | func = fabs_op; |
| 345 | else |
| 346 | func = fneg_op; |
| 347 | mips32_insn.fp0_format.opcode = cop1_op; |
| 348 | mips32_insn.fp0_format.fmt = |
| 349 | sdps_format[insn.mm_fp3_format.fmt]; |
| 350 | mips32_insn.fp0_format.ft = 0; |
| 351 | mips32_insn.fp0_format.fs = |
| 352 | insn.mm_fp3_format.fs; |
| 353 | mips32_insn.fp0_format.fd = |
| 354 | insn.mm_fp3_format.rt; |
| 355 | mips32_insn.fp0_format.func = func; |
| 356 | break; |
| 357 | case mm_ffloorl_op: |
| 358 | case mm_ffloorw_op: |
| 359 | case mm_fceill_op: |
| 360 | case mm_fceilw_op: |
| 361 | case mm_ftruncl_op: |
| 362 | case mm_ftruncw_op: |
| 363 | case mm_froundl_op: |
| 364 | case mm_froundw_op: |
| 365 | case mm_fcvtl_op: |
| 366 | case mm_fcvtw_op: |
| 367 | if (insn.mm_fp1_format.op == mm_ffloorl_op) |
| 368 | func = ffloorl_op; |
| 369 | else if (insn.mm_fp1_format.op == mm_ffloorw_op) |
| 370 | func = ffloor_op; |
| 371 | else if (insn.mm_fp1_format.op == mm_fceill_op) |
| 372 | func = fceill_op; |
| 373 | else if (insn.mm_fp1_format.op == mm_fceilw_op) |
| 374 | func = fceil_op; |
| 375 | else if (insn.mm_fp1_format.op == mm_ftruncl_op) |
| 376 | func = ftruncl_op; |
| 377 | else if (insn.mm_fp1_format.op == mm_ftruncw_op) |
| 378 | func = ftrunc_op; |
| 379 | else if (insn.mm_fp1_format.op == mm_froundl_op) |
| 380 | func = froundl_op; |
| 381 | else if (insn.mm_fp1_format.op == mm_froundw_op) |
| 382 | func = fround_op; |
| 383 | else if (insn.mm_fp1_format.op == mm_fcvtl_op) |
| 384 | func = fcvtl_op; |
| 385 | else |
| 386 | func = fcvtw_op; |
| 387 | mips32_insn.fp0_format.opcode = cop1_op; |
| 388 | mips32_insn.fp0_format.fmt = |
| 389 | sd_format[insn.mm_fp1_format.fmt]; |
| 390 | mips32_insn.fp0_format.ft = 0; |
| 391 | mips32_insn.fp0_format.fs = |
| 392 | insn.mm_fp1_format.fs; |
| 393 | mips32_insn.fp0_format.fd = |
| 394 | insn.mm_fp1_format.rt; |
| 395 | mips32_insn.fp0_format.func = func; |
| 396 | break; |
| 397 | case mm_frsqrt_op: |
| 398 | case mm_fsqrt_op: |
| 399 | case mm_frecip_op: |
| 400 | if (insn.mm_fp1_format.op == mm_frsqrt_op) |
| 401 | func = frsqrt_op; |
| 402 | else if (insn.mm_fp1_format.op == mm_fsqrt_op) |
| 403 | func = fsqrt_op; |
| 404 | else |
| 405 | func = frecip_op; |
| 406 | mips32_insn.fp0_format.opcode = cop1_op; |
| 407 | mips32_insn.fp0_format.fmt = |
| 408 | sdps_format[insn.mm_fp1_format.fmt]; |
| 409 | mips32_insn.fp0_format.ft = 0; |
| 410 | mips32_insn.fp0_format.fs = |
| 411 | insn.mm_fp1_format.fs; |
| 412 | mips32_insn.fp0_format.fd = |
| 413 | insn.mm_fp1_format.rt; |
| 414 | mips32_insn.fp0_format.func = func; |
| 415 | break; |
| 416 | case mm_mfc1_op: |
| 417 | case mm_mtc1_op: |
| 418 | case mm_cfc1_op: |
| 419 | case mm_ctc1_op: |
| 420 | if (insn.mm_fp1_format.op == mm_mfc1_op) |
| 421 | op = mfc_op; |
| 422 | else if (insn.mm_fp1_format.op == mm_mtc1_op) |
| 423 | op = mtc_op; |
| 424 | else if (insn.mm_fp1_format.op == mm_cfc1_op) |
| 425 | op = cfc_op; |
| 426 | else |
| 427 | op = ctc_op; |
| 428 | mips32_insn.fp1_format.opcode = cop1_op; |
| 429 | mips32_insn.fp1_format.op = op; |
| 430 | mips32_insn.fp1_format.rt = |
| 431 | insn.mm_fp1_format.rt; |
| 432 | mips32_insn.fp1_format.fs = |
| 433 | insn.mm_fp1_format.fs; |
| 434 | mips32_insn.fp1_format.fd = 0; |
| 435 | mips32_insn.fp1_format.func = 0; |
| 436 | break; |
| 437 | default: |
| 438 | return SIGILL; |
| 439 | break; |
| 440 | } |
| 441 | break; |
| 442 | case mm_32f_74_op: /* c.cond.fmt */ |
| 443 | mips32_insn.fp0_format.opcode = cop1_op; |
| 444 | mips32_insn.fp0_format.fmt = |
| 445 | sdps_format[insn.mm_fp4_format.fmt]; |
| 446 | mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; |
| 447 | mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; |
| 448 | mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; |
| 449 | mips32_insn.fp0_format.func = |
| 450 | insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; |
| 451 | break; |
| 452 | default: |
| 453 | return SIGILL; |
| 454 | break; |
| 455 | } |
| 456 | break; |
| 457 | default: |
| 458 | return SIGILL; |
| 459 | break; |
| 460 | } |
| 461 | |
| 462 | *insn_ptr = mips32_insn; |
| 463 | return 0; |
| 464 | } |
| 465 | |
| 466 | int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, |
| 467 | unsigned long *contpc) |
| 468 | { |
| 469 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; |
| 470 | int bc_false = 0; |
| 471 | unsigned int fcr31; |
| 472 | unsigned int bit; |
| 473 | |
David Daney | fe6d290 | 2013-05-24 20:54:09 +0000 | [diff] [blame] | 474 | if (!cpu_has_mmips) |
| 475 | return 0; |
| 476 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 477 | switch (insn.mm_i_format.opcode) { |
| 478 | case mm_pool32a_op: |
| 479 | if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) == |
| 480 | mm_pool32axf_op) { |
| 481 | switch (insn.mm_i_format.simmediate >> |
| 482 | MM_POOL32A_MINOR_SHIFT) { |
| 483 | case mm_jalr_op: |
| 484 | case mm_jalrhb_op: |
| 485 | case mm_jalrs_op: |
| 486 | case mm_jalrshb_op: |
| 487 | if (insn.mm_i_format.rt != 0) /* Not mm_jr */ |
| 488 | regs->regs[insn.mm_i_format.rt] = |
| 489 | regs->cp0_epc + |
| 490 | dec_insn.pc_inc + |
| 491 | dec_insn.next_pc_inc; |
| 492 | *contpc = regs->regs[insn.mm_i_format.rs]; |
| 493 | return 1; |
| 494 | break; |
| 495 | } |
| 496 | } |
| 497 | break; |
| 498 | case mm_pool32i_op: |
| 499 | switch (insn.mm_i_format.rt) { |
| 500 | case mm_bltzals_op: |
| 501 | case mm_bltzal_op: |
| 502 | regs->regs[31] = regs->cp0_epc + |
| 503 | dec_insn.pc_inc + |
| 504 | dec_insn.next_pc_inc; |
| 505 | /* Fall through */ |
| 506 | case mm_bltz_op: |
| 507 | if ((long)regs->regs[insn.mm_i_format.rs] < 0) |
| 508 | *contpc = regs->cp0_epc + |
| 509 | dec_insn.pc_inc + |
| 510 | (insn.mm_i_format.simmediate << 1); |
| 511 | else |
| 512 | *contpc = regs->cp0_epc + |
| 513 | dec_insn.pc_inc + |
| 514 | dec_insn.next_pc_inc; |
| 515 | return 1; |
| 516 | break; |
| 517 | case mm_bgezals_op: |
| 518 | case mm_bgezal_op: |
| 519 | regs->regs[31] = regs->cp0_epc + |
| 520 | dec_insn.pc_inc + |
| 521 | dec_insn.next_pc_inc; |
| 522 | /* Fall through */ |
| 523 | case mm_bgez_op: |
| 524 | if ((long)regs->regs[insn.mm_i_format.rs] >= 0) |
| 525 | *contpc = regs->cp0_epc + |
| 526 | dec_insn.pc_inc + |
| 527 | (insn.mm_i_format.simmediate << 1); |
| 528 | else |
| 529 | *contpc = regs->cp0_epc + |
| 530 | dec_insn.pc_inc + |
| 531 | dec_insn.next_pc_inc; |
| 532 | return 1; |
| 533 | break; |
| 534 | case mm_blez_op: |
| 535 | if ((long)regs->regs[insn.mm_i_format.rs] <= 0) |
| 536 | *contpc = regs->cp0_epc + |
| 537 | dec_insn.pc_inc + |
| 538 | (insn.mm_i_format.simmediate << 1); |
| 539 | else |
| 540 | *contpc = regs->cp0_epc + |
| 541 | dec_insn.pc_inc + |
| 542 | dec_insn.next_pc_inc; |
| 543 | return 1; |
| 544 | break; |
| 545 | case mm_bgtz_op: |
| 546 | if ((long)regs->regs[insn.mm_i_format.rs] <= 0) |
| 547 | *contpc = regs->cp0_epc + |
| 548 | dec_insn.pc_inc + |
| 549 | (insn.mm_i_format.simmediate << 1); |
| 550 | else |
| 551 | *contpc = regs->cp0_epc + |
| 552 | dec_insn.pc_inc + |
| 553 | dec_insn.next_pc_inc; |
| 554 | return 1; |
| 555 | break; |
| 556 | case mm_bc2f_op: |
| 557 | case mm_bc1f_op: |
| 558 | bc_false = 1; |
| 559 | /* Fall through */ |
| 560 | case mm_bc2t_op: |
| 561 | case mm_bc1t_op: |
| 562 | preempt_disable(); |
| 563 | if (is_fpu_owner()) |
| 564 | asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); |
| 565 | else |
| 566 | fcr31 = current->thread.fpu.fcr31; |
| 567 | preempt_enable(); |
| 568 | |
| 569 | if (bc_false) |
| 570 | fcr31 = ~fcr31; |
| 571 | |
| 572 | bit = (insn.mm_i_format.rs >> 2); |
| 573 | bit += (bit != 0); |
| 574 | bit += 23; |
| 575 | if (fcr31 & (1 << bit)) |
| 576 | *contpc = regs->cp0_epc + |
| 577 | dec_insn.pc_inc + |
| 578 | (insn.mm_i_format.simmediate << 1); |
| 579 | else |
| 580 | *contpc = regs->cp0_epc + |
| 581 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 582 | return 1; |
| 583 | break; |
| 584 | } |
| 585 | break; |
| 586 | case mm_pool16c_op: |
| 587 | switch (insn.mm_i_format.rt) { |
| 588 | case mm_jalr16_op: |
| 589 | case mm_jalrs16_op: |
| 590 | regs->regs[31] = regs->cp0_epc + |
| 591 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 592 | /* Fall through */ |
| 593 | case mm_jr16_op: |
| 594 | *contpc = regs->regs[insn.mm_i_format.rs]; |
| 595 | return 1; |
| 596 | break; |
| 597 | } |
| 598 | break; |
| 599 | case mm_beqz16_op: |
| 600 | if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0) |
| 601 | *contpc = regs->cp0_epc + |
| 602 | dec_insn.pc_inc + |
| 603 | (insn.mm_b1_format.simmediate << 1); |
| 604 | else |
| 605 | *contpc = regs->cp0_epc + |
| 606 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 607 | return 1; |
| 608 | break; |
| 609 | case mm_bnez16_op: |
| 610 | if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) |
| 611 | *contpc = regs->cp0_epc + |
| 612 | dec_insn.pc_inc + |
| 613 | (insn.mm_b1_format.simmediate << 1); |
| 614 | else |
| 615 | *contpc = regs->cp0_epc + |
| 616 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 617 | return 1; |
| 618 | break; |
| 619 | case mm_b16_op: |
| 620 | *contpc = regs->cp0_epc + dec_insn.pc_inc + |
| 621 | (insn.mm_b0_format.simmediate << 1); |
| 622 | return 1; |
| 623 | break; |
| 624 | case mm_beq32_op: |
| 625 | if (regs->regs[insn.mm_i_format.rs] == |
| 626 | regs->regs[insn.mm_i_format.rt]) |
| 627 | *contpc = regs->cp0_epc + |
| 628 | dec_insn.pc_inc + |
| 629 | (insn.mm_i_format.simmediate << 1); |
| 630 | else |
| 631 | *contpc = regs->cp0_epc + |
| 632 | dec_insn.pc_inc + |
| 633 | dec_insn.next_pc_inc; |
| 634 | return 1; |
| 635 | break; |
| 636 | case mm_bne32_op: |
| 637 | if (regs->regs[insn.mm_i_format.rs] != |
| 638 | regs->regs[insn.mm_i_format.rt]) |
| 639 | *contpc = regs->cp0_epc + |
| 640 | dec_insn.pc_inc + |
| 641 | (insn.mm_i_format.simmediate << 1); |
| 642 | else |
| 643 | *contpc = regs->cp0_epc + |
| 644 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 645 | return 1; |
| 646 | break; |
| 647 | case mm_jalx32_op: |
| 648 | regs->regs[31] = regs->cp0_epc + |
| 649 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 650 | *contpc = regs->cp0_epc + dec_insn.pc_inc; |
| 651 | *contpc >>= 28; |
| 652 | *contpc <<= 28; |
| 653 | *contpc |= (insn.j_format.target << 2); |
| 654 | return 1; |
| 655 | break; |
| 656 | case mm_jals32_op: |
| 657 | case mm_jal32_op: |
| 658 | regs->regs[31] = regs->cp0_epc + |
| 659 | dec_insn.pc_inc + dec_insn.next_pc_inc; |
| 660 | /* Fall through */ |
| 661 | case mm_j32_op: |
| 662 | *contpc = regs->cp0_epc + dec_insn.pc_inc; |
| 663 | *contpc >>= 27; |
| 664 | *contpc <<= 27; |
| 665 | *contpc |= (insn.j_format.target << 1); |
| 666 | set_isa16_mode(*contpc); |
| 667 | return 1; |
| 668 | break; |
| 669 | } |
| 670 | return 0; |
| 671 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 672 | |
| 673 | /* |
| 674 | * Redundant with logic already in kernel/branch.c, |
| 675 | * embedded in compute_return_epc. At some point, |
| 676 | * a single subroutine should be used across both |
| 677 | * modules. |
| 678 | */ |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 679 | static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, |
| 680 | unsigned long *contpc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 681 | { |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 682 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; |
| 683 | unsigned int fcr31; |
| 684 | unsigned int bit = 0; |
| 685 | |
| 686 | switch (insn.i_format.opcode) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 687 | case spec_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 688 | switch (insn.r_format.func) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 689 | case jalr_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 690 | regs->regs[insn.r_format.rd] = |
| 691 | regs->cp0_epc + dec_insn.pc_inc + |
| 692 | dec_insn.next_pc_inc; |
| 693 | /* Fall through */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 694 | case jr_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 695 | *contpc = regs->regs[insn.r_format.rs]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 696 | return 1; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 697 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 698 | } |
| 699 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 700 | case bcond_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 701 | switch (insn.i_format.rt) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 702 | case bltzal_op: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 703 | case bltzall_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 704 | regs->regs[31] = regs->cp0_epc + |
| 705 | dec_insn.pc_inc + |
| 706 | dec_insn.next_pc_inc; |
| 707 | /* Fall through */ |
| 708 | case bltz_op: |
| 709 | case bltzl_op: |
| 710 | if ((long)regs->regs[insn.i_format.rs] < 0) |
| 711 | *contpc = regs->cp0_epc + |
| 712 | dec_insn.pc_inc + |
| 713 | (insn.i_format.simmediate << 2); |
| 714 | else |
| 715 | *contpc = regs->cp0_epc + |
| 716 | dec_insn.pc_inc + |
| 717 | dec_insn.next_pc_inc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 718 | return 1; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 719 | break; |
| 720 | case bgezal_op: |
| 721 | case bgezall_op: |
| 722 | regs->regs[31] = regs->cp0_epc + |
| 723 | dec_insn.pc_inc + |
| 724 | dec_insn.next_pc_inc; |
| 725 | /* Fall through */ |
| 726 | case bgez_op: |
| 727 | case bgezl_op: |
| 728 | if ((long)regs->regs[insn.i_format.rs] >= 0) |
| 729 | *contpc = regs->cp0_epc + |
| 730 | dec_insn.pc_inc + |
| 731 | (insn.i_format.simmediate << 2); |
| 732 | else |
| 733 | *contpc = regs->cp0_epc + |
| 734 | dec_insn.pc_inc + |
| 735 | dec_insn.next_pc_inc; |
| 736 | return 1; |
| 737 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 738 | } |
| 739 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 740 | case jalx_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 741 | set_isa16_mode(bit); |
| 742 | case jal_op: |
| 743 | regs->regs[31] = regs->cp0_epc + |
| 744 | dec_insn.pc_inc + |
| 745 | dec_insn.next_pc_inc; |
| 746 | /* Fall through */ |
| 747 | case j_op: |
| 748 | *contpc = regs->cp0_epc + dec_insn.pc_inc; |
| 749 | *contpc >>= 28; |
| 750 | *contpc <<= 28; |
| 751 | *contpc |= (insn.j_format.target << 2); |
| 752 | /* Set microMIPS mode bit: XOR for jalx. */ |
| 753 | *contpc ^= bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 754 | return 1; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 755 | break; |
| 756 | case beq_op: |
| 757 | case beql_op: |
| 758 | if (regs->regs[insn.i_format.rs] == |
| 759 | regs->regs[insn.i_format.rt]) |
| 760 | *contpc = regs->cp0_epc + |
| 761 | dec_insn.pc_inc + |
| 762 | (insn.i_format.simmediate << 2); |
| 763 | else |
| 764 | *contpc = regs->cp0_epc + |
| 765 | dec_insn.pc_inc + |
| 766 | dec_insn.next_pc_inc; |
| 767 | return 1; |
| 768 | break; |
| 769 | case bne_op: |
| 770 | case bnel_op: |
| 771 | if (regs->regs[insn.i_format.rs] != |
| 772 | regs->regs[insn.i_format.rt]) |
| 773 | *contpc = regs->cp0_epc + |
| 774 | dec_insn.pc_inc + |
| 775 | (insn.i_format.simmediate << 2); |
| 776 | else |
| 777 | *contpc = regs->cp0_epc + |
| 778 | dec_insn.pc_inc + |
| 779 | dec_insn.next_pc_inc; |
| 780 | return 1; |
| 781 | break; |
| 782 | case blez_op: |
| 783 | case blezl_op: |
| 784 | if ((long)regs->regs[insn.i_format.rs] <= 0) |
| 785 | *contpc = regs->cp0_epc + |
| 786 | dec_insn.pc_inc + |
| 787 | (insn.i_format.simmediate << 2); |
| 788 | else |
| 789 | *contpc = regs->cp0_epc + |
| 790 | dec_insn.pc_inc + |
| 791 | dec_insn.next_pc_inc; |
| 792 | return 1; |
| 793 | break; |
| 794 | case bgtz_op: |
| 795 | case bgtzl_op: |
| 796 | if ((long)regs->regs[insn.i_format.rs] > 0) |
| 797 | *contpc = regs->cp0_epc + |
| 798 | dec_insn.pc_inc + |
| 799 | (insn.i_format.simmediate << 2); |
| 800 | else |
| 801 | *contpc = regs->cp0_epc + |
| 802 | dec_insn.pc_inc + |
| 803 | dec_insn.next_pc_inc; |
| 804 | return 1; |
| 805 | break; |
David Daney | c26d421 | 2013-08-19 12:10:34 -0700 | [diff] [blame] | 806 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
| 807 | case lwc2_op: /* This is bbit0 on Octeon */ |
| 808 | if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) |
| 809 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); |
| 810 | else |
| 811 | *contpc = regs->cp0_epc + 8; |
| 812 | return 1; |
| 813 | case ldc2_op: /* This is bbit032 on Octeon */ |
| 814 | if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) |
| 815 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); |
| 816 | else |
| 817 | *contpc = regs->cp0_epc + 8; |
| 818 | return 1; |
| 819 | case swc2_op: /* This is bbit1 on Octeon */ |
| 820 | if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) |
| 821 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); |
| 822 | else |
| 823 | *contpc = regs->cp0_epc + 8; |
| 824 | return 1; |
| 825 | case sdc2_op: /* This is bbit132 on Octeon */ |
| 826 | if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) |
| 827 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); |
| 828 | else |
| 829 | *contpc = regs->cp0_epc + 8; |
| 830 | return 1; |
| 831 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 832 | case cop0_op: |
| 833 | case cop1_op: |
| 834 | case cop2_op: |
| 835 | case cop1x_op: |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 836 | if (insn.i_format.rs == bc_op) { |
| 837 | preempt_disable(); |
| 838 | if (is_fpu_owner()) |
| 839 | asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); |
| 840 | else |
| 841 | fcr31 = current->thread.fpu.fcr31; |
| 842 | preempt_enable(); |
| 843 | |
| 844 | bit = (insn.i_format.rt >> 2); |
| 845 | bit += (bit != 0); |
| 846 | bit += 23; |
| 847 | switch (insn.i_format.rt & 3) { |
| 848 | case 0: /* bc1f */ |
| 849 | case 2: /* bc1fl */ |
| 850 | if (~fcr31 & (1 << bit)) |
| 851 | *contpc = regs->cp0_epc + |
| 852 | dec_insn.pc_inc + |
| 853 | (insn.i_format.simmediate << 2); |
| 854 | else |
| 855 | *contpc = regs->cp0_epc + |
| 856 | dec_insn.pc_inc + |
| 857 | dec_insn.next_pc_inc; |
| 858 | return 1; |
| 859 | break; |
| 860 | case 1: /* bc1t */ |
| 861 | case 3: /* bc1tl */ |
| 862 | if (fcr31 & (1 << bit)) |
| 863 | *contpc = regs->cp0_epc + |
| 864 | dec_insn.pc_inc + |
| 865 | (insn.i_format.simmediate << 2); |
| 866 | else |
| 867 | *contpc = regs->cp0_epc + |
| 868 | dec_insn.pc_inc + |
| 869 | dec_insn.next_pc_inc; |
| 870 | return 1; |
| 871 | break; |
| 872 | } |
| 873 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 874 | break; |
| 875 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 876 | return 0; |
| 877 | } |
| 878 | |
| 879 | /* |
| 880 | * In the Linux kernel, we support selection of FPR format on the |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 881 | * basis of the Status.FR bit. If an FPU is not present, the FR bit |
David Daney | da0bac3 | 2009-11-02 11:33:46 -0800 | [diff] [blame] | 882 | * is hardwired to zero, which would imply a 32-bit FPU even for |
Ralf Baechle | 51d943f | 2012-08-15 19:42:19 +0200 | [diff] [blame] | 883 | * 64-bit CPUs so we rather look at TIF_32BIT_REGS. |
| 884 | * FPU emu is slow and bulky and optimizing this function offers fairly |
| 885 | * sizeable benefits so we try to be clever and make this function return |
| 886 | * a constant whenever possible, that is on 64-bit kernels without O32 |
| 887 | * compatibility enabled and on 32-bit kernels. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 888 | */ |
David Daney | da0bac3 | 2009-11-02 11:33:46 -0800 | [diff] [blame] | 889 | static inline int cop1_64bit(struct pt_regs *xcp) |
| 890 | { |
Ralf Baechle | 51d943f | 2012-08-15 19:42:19 +0200 | [diff] [blame] | 891 | #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32) |
| 892 | return 1; |
| 893 | #elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32) |
David Daney | da0bac3 | 2009-11-02 11:33:46 -0800 | [diff] [blame] | 894 | return !test_thread_flag(TIF_32BIT_REGS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 895 | #else |
David Daney | da0bac3 | 2009-11-02 11:33:46 -0800 | [diff] [blame] | 896 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 897 | #endif |
David Daney | da0bac3 | 2009-11-02 11:33:46 -0800 | [diff] [blame] | 898 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 899 | |
David Daney | da0bac3 | 2009-11-02 11:33:46 -0800 | [diff] [blame] | 900 | #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \ |
| 901 | (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32)) |
| 902 | |
| 903 | #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \ |
| 904 | cop1_64bit(xcp) || !(x & 1) ? \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 905 | ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ |
| 906 | ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) |
| 907 | |
David Daney | da0bac3 | 2009-11-02 11:33:46 -0800 | [diff] [blame] | 908 | #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)]) |
| 909 | #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 910 | |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 911 | #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) |
| 912 | #define SPTOREG(sp, x) SITOREG((sp).bits, x) |
| 913 | #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) |
| 914 | #define DPTOREG(dp, x) DITOREG((dp).bits, x) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 915 | |
| 916 | /* |
| 917 | * Emulate the single floating point instruction pointed at by EPC. |
| 918 | * Two instructions if the instruction is in a branch delay slot. |
| 919 | */ |
| 920 | |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 921 | static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 922 | struct mm_decoded_insn dec_insn, void *__user *fault_addr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 923 | { |
| 924 | mips_instruction ir; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 925 | unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 926 | unsigned int cond; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 927 | int pc_inc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 928 | |
| 929 | /* XXX NEC Vr54xx bug workaround */ |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 930 | if (xcp->cp0_cause & CAUSEF_BD) { |
| 931 | if (dec_insn.micro_mips_mode) { |
| 932 | if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) |
| 933 | xcp->cp0_cause &= ~CAUSEF_BD; |
| 934 | } else { |
| 935 | if (!isBranchInstr(xcp, dec_insn, &contpc)) |
| 936 | xcp->cp0_cause &= ~CAUSEF_BD; |
| 937 | } |
| 938 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 939 | |
| 940 | if (xcp->cp0_cause & CAUSEF_BD) { |
| 941 | /* |
| 942 | * The instruction to be emulated is in a branch delay slot |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 943 | * which means that we have to emulate the branch instruction |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 944 | * BEFORE we do the cop1 instruction. |
| 945 | * |
| 946 | * This branch could be a COP1 branch, but in that case we |
| 947 | * would have had a trap for that instruction, and would not |
| 948 | * come through this route. |
| 949 | * |
| 950 | * Linux MIPS branch emulator operates on context, updating the |
| 951 | * cp0_epc. |
| 952 | */ |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 953 | ir = dec_insn.next_insn; /* process delay slot instr */ |
| 954 | pc_inc = dec_insn.next_pc_inc; |
Ralf Baechle | 333d1f6 | 2005-02-28 17:55:57 +0000 | [diff] [blame] | 955 | } else { |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 956 | ir = dec_insn.insn; /* process current instr */ |
| 957 | pc_inc = dec_insn.pc_inc; |
| 958 | } |
| 959 | |
| 960 | /* |
| 961 | * Since microMIPS FPU instructios are a subset of MIPS32 FPU |
| 962 | * instructions, we want to convert microMIPS FPU instructions |
| 963 | * into MIPS32 instructions so that we could reuse all of the |
| 964 | * FPU emulation code. |
| 965 | * |
| 966 | * NOTE: We cannot do this for branch instructions since they |
| 967 | * are not a subset. Example: Cannot emulate a 16-bit |
| 968 | * aligned target address with a MIPS32 instruction. |
| 969 | */ |
| 970 | if (dec_insn.micro_mips_mode) { |
| 971 | /* |
| 972 | * If next instruction is a 16-bit instruction, then it |
| 973 | * it cannot be a FPU instruction. This could happen |
| 974 | * since we can be called for non-FPU instructions. |
| 975 | */ |
| 976 | if ((pc_inc == 2) || |
| 977 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) |
| 978 | == SIGILL)) |
| 979 | return SIGILL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 980 | } |
| 981 | |
| 982 | emul: |
Peter Zijlstra | a8b0ca1 | 2011-06-27 14:41:57 +0200 | [diff] [blame] | 983 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 984 | MIPS_FPU_EMU_INC_STATS(emulated); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 985 | switch (MIPSInst_OPCODE(ir)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | case ldc1_op:{ |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 987 | u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 988 | MIPSInst_SIMM(ir)); |
| 989 | u64 val; |
| 990 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 991 | MIPS_FPU_EMU_INC_STATS(loads); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 992 | |
| 993 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 994 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 995 | *fault_addr = va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 996 | return SIGBUS; |
| 997 | } |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 998 | if (__get_user(val, va)) { |
| 999 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1000 | *fault_addr = va; |
| 1001 | return SIGSEGV; |
| 1002 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1003 | DITOREG(val, MIPSInst_RT(ir)); |
| 1004 | break; |
| 1005 | } |
| 1006 | |
| 1007 | case sdc1_op:{ |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1008 | u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1009 | MIPSInst_SIMM(ir)); |
| 1010 | u64 val; |
| 1011 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1012 | MIPS_FPU_EMU_INC_STATS(stores); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1013 | DIFROMREG(val, MIPSInst_RT(ir)); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1014 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1015 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1016 | *fault_addr = va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1017 | return SIGBUS; |
| 1018 | } |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1019 | if (__put_user(val, va)) { |
| 1020 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1021 | *fault_addr = va; |
| 1022 | return SIGSEGV; |
| 1023 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1024 | break; |
| 1025 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1026 | |
| 1027 | case lwc1_op:{ |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1028 | u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1029 | MIPSInst_SIMM(ir)); |
| 1030 | u32 val; |
| 1031 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1032 | MIPS_FPU_EMU_INC_STATS(loads); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1033 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1034 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1035 | *fault_addr = va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1036 | return SIGBUS; |
| 1037 | } |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1038 | if (__get_user(val, va)) { |
| 1039 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1040 | *fault_addr = va; |
| 1041 | return SIGSEGV; |
| 1042 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1043 | SITOREG(val, MIPSInst_RT(ir)); |
| 1044 | break; |
| 1045 | } |
| 1046 | |
| 1047 | case swc1_op:{ |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1048 | u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1049 | MIPSInst_SIMM(ir)); |
| 1050 | u32 val; |
| 1051 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1052 | MIPS_FPU_EMU_INC_STATS(stores); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1053 | SIFROMREG(val, MIPSInst_RT(ir)); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1054 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1055 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1056 | *fault_addr = va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1057 | return SIGBUS; |
| 1058 | } |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1059 | if (__put_user(val, va)) { |
| 1060 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1061 | *fault_addr = va; |
| 1062 | return SIGSEGV; |
| 1063 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1064 | break; |
| 1065 | } |
| 1066 | |
| 1067 | case cop1_op: |
| 1068 | switch (MIPSInst_RS(ir)) { |
| 1069 | |
Ralf Baechle | 4b724ef | 2005-10-23 15:05:47 +0100 | [diff] [blame] | 1070 | #if defined(__mips64) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1071 | case dmfc_op: |
| 1072 | /* copregister fs -> gpr[rt] */ |
| 1073 | if (MIPSInst_RT(ir) != 0) { |
| 1074 | DIFROMREG(xcp->regs[MIPSInst_RT(ir)], |
| 1075 | MIPSInst_RD(ir)); |
| 1076 | } |
| 1077 | break; |
| 1078 | |
| 1079 | case dmtc_op: |
| 1080 | /* copregister fs <- rt */ |
| 1081 | DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
| 1082 | break; |
| 1083 | #endif |
| 1084 | |
| 1085 | case mfc_op: |
| 1086 | /* copregister rd -> gpr[rt] */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1087 | if (MIPSInst_RT(ir) != 0) { |
| 1088 | SIFROMREG(xcp->regs[MIPSInst_RT(ir)], |
| 1089 | MIPSInst_RD(ir)); |
| 1090 | } |
| 1091 | break; |
| 1092 | |
| 1093 | case mtc_op: |
| 1094 | /* copregister rd <- rt */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1095 | SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
| 1096 | break; |
| 1097 | |
| 1098 | case cfc_op:{ |
| 1099 | /* cop control register rd -> gpr[rt] */ |
| 1100 | u32 value; |
| 1101 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1102 | if (MIPSInst_RD(ir) == FPCREG_CSR) { |
| 1103 | value = ctx->fcr31; |
Shane McDonald | 3f13553 | 2010-05-07 00:02:09 -0600 | [diff] [blame] | 1104 | value = (value & ~FPU_CSR_RM) | |
| 1105 | mips_rm[modeindex(value)]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1106 | #ifdef CSRTRACE |
| 1107 | printk("%p gpr[%d]<-csr=%08x\n", |
Ralf Baechle | 333d1f6 | 2005-02-28 17:55:57 +0000 | [diff] [blame] | 1108 | (void *) (xcp->cp0_epc), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1109 | MIPSInst_RT(ir), value); |
| 1110 | #endif |
| 1111 | } |
| 1112 | else if (MIPSInst_RD(ir) == FPCREG_RID) |
| 1113 | value = 0; |
| 1114 | else |
| 1115 | value = 0; |
| 1116 | if (MIPSInst_RT(ir)) |
| 1117 | xcp->regs[MIPSInst_RT(ir)] = value; |
| 1118 | break; |
| 1119 | } |
| 1120 | |
| 1121 | case ctc_op:{ |
| 1122 | /* copregister rd <- rt */ |
| 1123 | u32 value; |
| 1124 | |
| 1125 | if (MIPSInst_RT(ir) == 0) |
| 1126 | value = 0; |
| 1127 | else |
| 1128 | value = xcp->regs[MIPSInst_RT(ir)]; |
| 1129 | |
| 1130 | /* we only have one writable control reg |
| 1131 | */ |
| 1132 | if (MIPSInst_RD(ir) == FPCREG_CSR) { |
| 1133 | #ifdef CSRTRACE |
| 1134 | printk("%p gpr[%d]->csr=%08x\n", |
Ralf Baechle | 333d1f6 | 2005-02-28 17:55:57 +0000 | [diff] [blame] | 1135 | (void *) (xcp->cp0_epc), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1136 | MIPSInst_RT(ir), value); |
| 1137 | #endif |
Shane McDonald | 95e8f63 | 2010-05-06 23:26:57 -0600 | [diff] [blame] | 1138 | |
| 1139 | /* |
| 1140 | * Don't write reserved bits, |
| 1141 | * and convert to ieee library modes |
| 1142 | */ |
| 1143 | ctx->fcr31 = (value & |
| 1144 | ~(FPU_CSR_RSVD | FPU_CSR_RM)) | |
| 1145 | ieee_rm[modeindex(value)]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1146 | } |
| 1147 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
| 1148 | return SIGFPE; |
| 1149 | } |
| 1150 | break; |
| 1151 | } |
| 1152 | |
| 1153 | case bc_op:{ |
| 1154 | int likely = 0; |
| 1155 | |
| 1156 | if (xcp->cp0_cause & CAUSEF_BD) |
| 1157 | return SIGILL; |
| 1158 | |
| 1159 | #if __mips >= 4 |
| 1160 | cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2]; |
| 1161 | #else |
| 1162 | cond = ctx->fcr31 & FPU_CSR_COND; |
| 1163 | #endif |
| 1164 | switch (MIPSInst_RT(ir) & 3) { |
| 1165 | case bcfl_op: |
| 1166 | likely = 1; |
| 1167 | case bcf_op: |
| 1168 | cond = !cond; |
| 1169 | break; |
| 1170 | case bctl_op: |
| 1171 | likely = 1; |
| 1172 | case bct_op: |
| 1173 | break; |
| 1174 | default: |
| 1175 | /* thats an illegal instruction */ |
| 1176 | return SIGILL; |
| 1177 | } |
| 1178 | |
| 1179 | xcp->cp0_cause |= CAUSEF_BD; |
| 1180 | if (cond) { |
| 1181 | /* branch taken: emulate dslot |
| 1182 | * instruction |
| 1183 | */ |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 1184 | xcp->cp0_epc += dec_insn.pc_inc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1185 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 1186 | contpc = MIPSInst_SIMM(ir); |
| 1187 | ir = dec_insn.next_insn; |
| 1188 | if (dec_insn.micro_mips_mode) { |
| 1189 | contpc = (xcp->cp0_epc + (contpc << 1)); |
| 1190 | |
| 1191 | /* If 16-bit instruction, not FPU. */ |
| 1192 | if ((dec_insn.next_pc_inc == 2) || |
| 1193 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { |
| 1194 | |
| 1195 | /* |
| 1196 | * Since this instruction will |
| 1197 | * be put on the stack with |
| 1198 | * 32-bit words, get around |
| 1199 | * this problem by putting a |
| 1200 | * NOP16 as the second one. |
| 1201 | */ |
| 1202 | if (dec_insn.next_pc_inc == 2) |
| 1203 | ir = (ir & (~0xffff)) | MM_NOP16; |
| 1204 | |
| 1205 | /* |
| 1206 | * Single step the non-CP1 |
| 1207 | * instruction in the dslot. |
| 1208 | */ |
| 1209 | return mips_dsemul(xcp, ir, contpc); |
| 1210 | } |
| 1211 | } else |
| 1212 | contpc = (xcp->cp0_epc + (contpc << 2)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1213 | |
| 1214 | switch (MIPSInst_OPCODE(ir)) { |
| 1215 | case lwc1_op: |
| 1216 | case swc1_op: |
Ralf Baechle | 4b724ef | 2005-10-23 15:05:47 +0100 | [diff] [blame] | 1217 | #if (__mips >= 2 || defined(__mips64)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1218 | case ldc1_op: |
| 1219 | case sdc1_op: |
| 1220 | #endif |
| 1221 | case cop1_op: |
| 1222 | #if __mips >= 4 && __mips != 32 |
| 1223 | case cop1x_op: |
| 1224 | #endif |
| 1225 | /* its one of ours */ |
| 1226 | goto emul; |
| 1227 | #if __mips >= 4 |
| 1228 | case spec_op: |
| 1229 | if (MIPSInst_FUNC(ir) == movc_op) |
| 1230 | goto emul; |
| 1231 | break; |
| 1232 | #endif |
| 1233 | } |
| 1234 | |
| 1235 | /* |
| 1236 | * Single step the non-cp1 |
| 1237 | * instruction in the dslot |
| 1238 | */ |
Atsushi Nemoto | e70dfc1 | 2007-07-13 23:02:29 +0900 | [diff] [blame] | 1239 | return mips_dsemul(xcp, ir, contpc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1240 | } |
| 1241 | else { |
| 1242 | /* branch not taken */ |
| 1243 | if (likely) { |
| 1244 | /* |
| 1245 | * branch likely nullifies |
| 1246 | * dslot if not taken |
| 1247 | */ |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 1248 | xcp->cp0_epc += dec_insn.pc_inc; |
| 1249 | contpc += dec_insn.pc_inc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1250 | /* |
| 1251 | * else continue & execute |
| 1252 | * dslot as normal insn |
| 1253 | */ |
| 1254 | } |
| 1255 | } |
| 1256 | break; |
| 1257 | } |
| 1258 | |
| 1259 | default: |
| 1260 | if (!(MIPSInst_RS(ir) & 0x10)) |
| 1261 | return SIGILL; |
| 1262 | { |
| 1263 | int sig; |
| 1264 | |
| 1265 | /* a real fpu computation instruction */ |
| 1266 | if ((sig = fpu_emu(xcp, ctx, ir))) |
| 1267 | return sig; |
| 1268 | } |
| 1269 | } |
| 1270 | break; |
| 1271 | |
| 1272 | #if __mips >= 4 && __mips != 32 |
| 1273 | case cop1x_op:{ |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1274 | int sig = fpux_emu(xcp, ctx, ir, fault_addr); |
| 1275 | if (sig) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1276 | return sig; |
| 1277 | break; |
| 1278 | } |
| 1279 | #endif |
| 1280 | |
| 1281 | #if __mips >= 4 |
| 1282 | case spec_op: |
| 1283 | if (MIPSInst_FUNC(ir) != movc_op) |
| 1284 | return SIGILL; |
| 1285 | cond = fpucondbit[MIPSInst_RT(ir) >> 2]; |
| 1286 | if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) |
| 1287 | xcp->regs[MIPSInst_RD(ir)] = |
| 1288 | xcp->regs[MIPSInst_RS(ir)]; |
| 1289 | break; |
| 1290 | #endif |
| 1291 | |
| 1292 | default: |
| 1293 | return SIGILL; |
| 1294 | } |
| 1295 | |
| 1296 | /* we did it !! */ |
Atsushi Nemoto | e70dfc1 | 2007-07-13 23:02:29 +0900 | [diff] [blame] | 1297 | xcp->cp0_epc = contpc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1298 | xcp->cp0_cause &= ~CAUSEF_BD; |
Ralf Baechle | 333d1f6 | 2005-02-28 17:55:57 +0000 | [diff] [blame] | 1299 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1300 | return 0; |
| 1301 | } |
| 1302 | |
| 1303 | /* |
| 1304 | * Conversion table from MIPS compare ops 48-63 |
| 1305 | * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); |
| 1306 | */ |
| 1307 | static const unsigned char cmptab[8] = { |
| 1308 | 0, /* cmp_0 (sig) cmp_sf */ |
| 1309 | IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ |
| 1310 | IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ |
| 1311 | IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ |
| 1312 | IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ |
| 1313 | IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ |
| 1314 | IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ |
| 1315 | IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ |
| 1316 | }; |
| 1317 | |
| 1318 | |
| 1319 | #if __mips >= 4 && __mips != 32 |
| 1320 | |
| 1321 | /* |
| 1322 | * Additional MIPS4 instructions |
| 1323 | */ |
| 1324 | |
| 1325 | #define DEF3OP(name, p, f1, f2, f3) \ |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1326 | static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1327 | ieee754##p t) \ |
| 1328 | { \ |
Ralf Baechle | cd21dfc | 2005-04-28 13:39:10 +0000 | [diff] [blame] | 1329 | struct _ieee754_csr ieee754_csr_save; \ |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1330 | s = f1(s, t); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1331 | ieee754_csr_save = ieee754_csr; \ |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1332 | s = f2(s, r); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1333 | ieee754_csr_save.cx |= ieee754_csr.cx; \ |
| 1334 | ieee754_csr_save.sx |= ieee754_csr.sx; \ |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1335 | s = f3(s); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1336 | ieee754_csr.cx |= ieee754_csr_save.cx; \ |
| 1337 | ieee754_csr.sx |= ieee754_csr_save.sx; \ |
| 1338 | return s; \ |
| 1339 | } |
| 1340 | |
| 1341 | static ieee754dp fpemu_dp_recip(ieee754dp d) |
| 1342 | { |
| 1343 | return ieee754dp_div(ieee754dp_one(0), d); |
| 1344 | } |
| 1345 | |
| 1346 | static ieee754dp fpemu_dp_rsqrt(ieee754dp d) |
| 1347 | { |
| 1348 | return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); |
| 1349 | } |
| 1350 | |
| 1351 | static ieee754sp fpemu_sp_recip(ieee754sp s) |
| 1352 | { |
| 1353 | return ieee754sp_div(ieee754sp_one(0), s); |
| 1354 | } |
| 1355 | |
| 1356 | static ieee754sp fpemu_sp_rsqrt(ieee754sp s) |
| 1357 | { |
| 1358 | return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); |
| 1359 | } |
| 1360 | |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1361 | DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); |
| 1362 | DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1363 | DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); |
| 1364 | DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 1365 | DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); |
| 1366 | DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1367 | DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); |
| 1368 | DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); |
| 1369 | |
Atsushi Nemoto | eae8907 | 2006-05-16 01:26:03 +0900 | [diff] [blame] | 1370 | static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1371 | mips_instruction ir, void *__user *fault_addr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1372 | { |
| 1373 | unsigned rcsr = 0; /* resulting csr */ |
| 1374 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1375 | MIPS_FPU_EMU_INC_STATS(cp1xops); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1376 | |
| 1377 | switch (MIPSInst_FMA_FFMT(ir)) { |
| 1378 | case s_fmt:{ /* 0 */ |
| 1379 | |
| 1380 | ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp); |
| 1381 | ieee754sp fd, fr, fs, ft; |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1382 | u32 __user *va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1383 | u32 val; |
| 1384 | |
| 1385 | switch (MIPSInst_FUNC(ir)) { |
| 1386 | case lwxc1_op: |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1387 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1388 | xcp->regs[MIPSInst_FT(ir)]); |
| 1389 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1390 | MIPS_FPU_EMU_INC_STATS(loads); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1391 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1392 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1393 | *fault_addr = va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1394 | return SIGBUS; |
| 1395 | } |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1396 | if (__get_user(val, va)) { |
| 1397 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1398 | *fault_addr = va; |
| 1399 | return SIGSEGV; |
| 1400 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1401 | SITOREG(val, MIPSInst_FD(ir)); |
| 1402 | break; |
| 1403 | |
| 1404 | case swxc1_op: |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1405 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1406 | xcp->regs[MIPSInst_FT(ir)]); |
| 1407 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1408 | MIPS_FPU_EMU_INC_STATS(stores); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1409 | |
| 1410 | SIFROMREG(val, MIPSInst_FS(ir)); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1411 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
| 1412 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1413 | *fault_addr = va; |
| 1414 | return SIGBUS; |
| 1415 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1416 | if (put_user(val, va)) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1417 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1418 | *fault_addr = va; |
| 1419 | return SIGSEGV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1420 | } |
| 1421 | break; |
| 1422 | |
| 1423 | case madd_s_op: |
| 1424 | handler = fpemu_sp_madd; |
| 1425 | goto scoptop; |
| 1426 | case msub_s_op: |
| 1427 | handler = fpemu_sp_msub; |
| 1428 | goto scoptop; |
| 1429 | case nmadd_s_op: |
| 1430 | handler = fpemu_sp_nmadd; |
| 1431 | goto scoptop; |
| 1432 | case nmsub_s_op: |
| 1433 | handler = fpemu_sp_nmsub; |
| 1434 | goto scoptop; |
| 1435 | |
| 1436 | scoptop: |
| 1437 | SPFROMREG(fr, MIPSInst_FR(ir)); |
| 1438 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1439 | SPFROMREG(ft, MIPSInst_FT(ir)); |
| 1440 | fd = (*handler) (fr, fs, ft); |
| 1441 | SPTOREG(fd, MIPSInst_FD(ir)); |
| 1442 | |
| 1443 | copcsr: |
| 1444 | if (ieee754_cxtest(IEEE754_INEXACT)) |
| 1445 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
| 1446 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) |
| 1447 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
| 1448 | if (ieee754_cxtest(IEEE754_OVERFLOW)) |
| 1449 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
| 1450 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) |
| 1451 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
| 1452 | |
| 1453 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1454 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
| 1455 | /*printk ("SIGFPE: fpu csr = %08x\n", |
| 1456 | ctx->fcr31); */ |
| 1457 | return SIGFPE; |
| 1458 | } |
| 1459 | |
| 1460 | break; |
| 1461 | |
| 1462 | default: |
| 1463 | return SIGILL; |
| 1464 | } |
| 1465 | break; |
| 1466 | } |
| 1467 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1468 | case d_fmt:{ /* 1 */ |
| 1469 | ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp); |
| 1470 | ieee754dp fd, fr, fs, ft; |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1471 | u64 __user *va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1472 | u64 val; |
| 1473 | |
| 1474 | switch (MIPSInst_FUNC(ir)) { |
| 1475 | case ldxc1_op: |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1476 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1477 | xcp->regs[MIPSInst_FT(ir)]); |
| 1478 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1479 | MIPS_FPU_EMU_INC_STATS(loads); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1480 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1481 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1482 | *fault_addr = va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1483 | return SIGBUS; |
| 1484 | } |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1485 | if (__get_user(val, va)) { |
| 1486 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1487 | *fault_addr = va; |
| 1488 | return SIGSEGV; |
| 1489 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1490 | DITOREG(val, MIPSInst_FD(ir)); |
| 1491 | break; |
| 1492 | |
| 1493 | case sdxc1_op: |
Ralf Baechle | 3fccc01 | 2005-10-23 13:58:21 +0100 | [diff] [blame] | 1494 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1495 | xcp->regs[MIPSInst_FT(ir)]); |
| 1496 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1497 | MIPS_FPU_EMU_INC_STATS(stores); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1498 | DIFROMREG(val, MIPSInst_FS(ir)); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1499 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1500 | MIPS_FPU_EMU_INC_STATS(errors); |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1501 | *fault_addr = va; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1502 | return SIGBUS; |
| 1503 | } |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 1504 | if (__put_user(val, va)) { |
| 1505 | MIPS_FPU_EMU_INC_STATS(errors); |
| 1506 | *fault_addr = va; |
| 1507 | return SIGSEGV; |
| 1508 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1509 | break; |
| 1510 | |
| 1511 | case madd_d_op: |
| 1512 | handler = fpemu_dp_madd; |
| 1513 | goto dcoptop; |
| 1514 | case msub_d_op: |
| 1515 | handler = fpemu_dp_msub; |
| 1516 | goto dcoptop; |
| 1517 | case nmadd_d_op: |
| 1518 | handler = fpemu_dp_nmadd; |
| 1519 | goto dcoptop; |
| 1520 | case nmsub_d_op: |
| 1521 | handler = fpemu_dp_nmsub; |
| 1522 | goto dcoptop; |
| 1523 | |
| 1524 | dcoptop: |
| 1525 | DPFROMREG(fr, MIPSInst_FR(ir)); |
| 1526 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1527 | DPFROMREG(ft, MIPSInst_FT(ir)); |
| 1528 | fd = (*handler) (fr, fs, ft); |
| 1529 | DPTOREG(fd, MIPSInst_FD(ir)); |
| 1530 | goto copcsr; |
| 1531 | |
| 1532 | default: |
| 1533 | return SIGILL; |
| 1534 | } |
| 1535 | break; |
| 1536 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1537 | |
| 1538 | case 0x7: /* 7 */ |
| 1539 | if (MIPSInst_FUNC(ir) != pfetch_op) { |
| 1540 | return SIGILL; |
| 1541 | } |
| 1542 | /* ignore prefx operation */ |
| 1543 | break; |
| 1544 | |
| 1545 | default: |
| 1546 | return SIGILL; |
| 1547 | } |
| 1548 | |
| 1549 | return 0; |
| 1550 | } |
| 1551 | #endif |
| 1552 | |
| 1553 | |
| 1554 | |
| 1555 | /* |
| 1556 | * Emulate a single COP1 arithmetic instruction. |
| 1557 | */ |
Atsushi Nemoto | eae8907 | 2006-05-16 01:26:03 +0900 | [diff] [blame] | 1558 | static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1559 | mips_instruction ir) |
| 1560 | { |
| 1561 | int rfmt; /* resulting format */ |
| 1562 | unsigned rcsr = 0; /* resulting csr */ |
| 1563 | unsigned cond; |
| 1564 | union { |
| 1565 | ieee754dp d; |
| 1566 | ieee754sp s; |
| 1567 | int w; |
Yoichi Yuasa | 766160c | 2005-09-03 15:56:22 -0700 | [diff] [blame] | 1568 | #ifdef __mips64 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1569 | s64 l; |
| 1570 | #endif |
| 1571 | } rv; /* resulting value */ |
| 1572 | |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 1573 | MIPS_FPU_EMU_INC_STATS(cp1ops); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1574 | switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { |
| 1575 | case s_fmt:{ /* 0 */ |
| 1576 | union { |
| 1577 | ieee754sp(*b) (ieee754sp, ieee754sp); |
| 1578 | ieee754sp(*u) (ieee754sp); |
| 1579 | } handler; |
| 1580 | |
| 1581 | switch (MIPSInst_FUNC(ir)) { |
| 1582 | /* binary ops */ |
| 1583 | case fadd_op: |
| 1584 | handler.b = ieee754sp_add; |
| 1585 | goto scopbop; |
| 1586 | case fsub_op: |
| 1587 | handler.b = ieee754sp_sub; |
| 1588 | goto scopbop; |
| 1589 | case fmul_op: |
| 1590 | handler.b = ieee754sp_mul; |
| 1591 | goto scopbop; |
| 1592 | case fdiv_op: |
| 1593 | handler.b = ieee754sp_div; |
| 1594 | goto scopbop; |
| 1595 | |
| 1596 | /* unary ops */ |
Ralf Baechle | 587cb98 | 2005-09-15 08:52:34 +0000 | [diff] [blame] | 1597 | #if __mips >= 2 || defined(__mips64) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1598 | case fsqrt_op: |
| 1599 | handler.u = ieee754sp_sqrt; |
| 1600 | goto scopuop; |
| 1601 | #endif |
| 1602 | #if __mips >= 4 && __mips != 32 |
| 1603 | case frsqrt_op: |
| 1604 | handler.u = fpemu_sp_rsqrt; |
| 1605 | goto scopuop; |
| 1606 | case frecip_op: |
| 1607 | handler.u = fpemu_sp_recip; |
| 1608 | goto scopuop; |
| 1609 | #endif |
| 1610 | #if __mips >= 4 |
| 1611 | case fmovc_op: |
| 1612 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
| 1613 | if (((ctx->fcr31 & cond) != 0) != |
| 1614 | ((MIPSInst_FT(ir) & 1) != 0)) |
| 1615 | return 0; |
| 1616 | SPFROMREG(rv.s, MIPSInst_FS(ir)); |
| 1617 | break; |
| 1618 | case fmovz_op: |
| 1619 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
| 1620 | return 0; |
| 1621 | SPFROMREG(rv.s, MIPSInst_FS(ir)); |
| 1622 | break; |
| 1623 | case fmovn_op: |
| 1624 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
| 1625 | return 0; |
| 1626 | SPFROMREG(rv.s, MIPSInst_FS(ir)); |
| 1627 | break; |
| 1628 | #endif |
| 1629 | case fabs_op: |
| 1630 | handler.u = ieee754sp_abs; |
| 1631 | goto scopuop; |
| 1632 | case fneg_op: |
| 1633 | handler.u = ieee754sp_neg; |
| 1634 | goto scopuop; |
| 1635 | case fmov_op: |
| 1636 | /* an easy one */ |
| 1637 | SPFROMREG(rv.s, MIPSInst_FS(ir)); |
| 1638 | goto copcsr; |
| 1639 | |
| 1640 | /* binary op on handler */ |
| 1641 | scopbop: |
| 1642 | { |
| 1643 | ieee754sp fs, ft; |
| 1644 | |
| 1645 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1646 | SPFROMREG(ft, MIPSInst_FT(ir)); |
| 1647 | |
| 1648 | rv.s = (*handler.b) (fs, ft); |
| 1649 | goto copcsr; |
| 1650 | } |
| 1651 | scopuop: |
| 1652 | { |
| 1653 | ieee754sp fs; |
| 1654 | |
| 1655 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1656 | rv.s = (*handler.u) (fs); |
| 1657 | goto copcsr; |
| 1658 | } |
| 1659 | copcsr: |
| 1660 | if (ieee754_cxtest(IEEE754_INEXACT)) |
| 1661 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
| 1662 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) |
| 1663 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
| 1664 | if (ieee754_cxtest(IEEE754_OVERFLOW)) |
| 1665 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
| 1666 | if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) |
| 1667 | rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; |
| 1668 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) |
| 1669 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
| 1670 | break; |
| 1671 | |
| 1672 | /* unary conv ops */ |
| 1673 | case fcvts_op: |
| 1674 | return SIGILL; /* not defined */ |
| 1675 | case fcvtd_op:{ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1676 | ieee754sp fs; |
| 1677 | |
| 1678 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1679 | rv.d = ieee754dp_fsp(fs); |
| 1680 | rfmt = d_fmt; |
| 1681 | goto copcsr; |
| 1682 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1683 | case fcvtw_op:{ |
| 1684 | ieee754sp fs; |
| 1685 | |
| 1686 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1687 | rv.w = ieee754sp_tint(fs); |
| 1688 | rfmt = w_fmt; |
| 1689 | goto copcsr; |
| 1690 | } |
| 1691 | |
Ralf Baechle | 587cb98 | 2005-09-15 08:52:34 +0000 | [diff] [blame] | 1692 | #if __mips >= 2 || defined(__mips64) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1693 | case fround_op: |
| 1694 | case ftrunc_op: |
| 1695 | case fceil_op: |
| 1696 | case ffloor_op:{ |
| 1697 | unsigned int oldrm = ieee754_csr.rm; |
| 1698 | ieee754sp fs; |
| 1699 | |
| 1700 | SPFROMREG(fs, MIPSInst_FS(ir)); |
Shane McDonald | 3f13553 | 2010-05-07 00:02:09 -0600 | [diff] [blame] | 1701 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1702 | rv.w = ieee754sp_tint(fs); |
| 1703 | ieee754_csr.rm = oldrm; |
| 1704 | rfmt = w_fmt; |
| 1705 | goto copcsr; |
| 1706 | } |
| 1707 | #endif /* __mips >= 2 */ |
| 1708 | |
Ralf Baechle | 4b724ef | 2005-10-23 15:05:47 +0100 | [diff] [blame] | 1709 | #if defined(__mips64) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1710 | case fcvtl_op:{ |
| 1711 | ieee754sp fs; |
| 1712 | |
| 1713 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1714 | rv.l = ieee754sp_tlong(fs); |
| 1715 | rfmt = l_fmt; |
| 1716 | goto copcsr; |
| 1717 | } |
| 1718 | |
| 1719 | case froundl_op: |
| 1720 | case ftruncl_op: |
| 1721 | case fceill_op: |
| 1722 | case ffloorl_op:{ |
| 1723 | unsigned int oldrm = ieee754_csr.rm; |
| 1724 | ieee754sp fs; |
| 1725 | |
| 1726 | SPFROMREG(fs, MIPSInst_FS(ir)); |
Shane McDonald | 3f13553 | 2010-05-07 00:02:09 -0600 | [diff] [blame] | 1727 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1728 | rv.l = ieee754sp_tlong(fs); |
| 1729 | ieee754_csr.rm = oldrm; |
| 1730 | rfmt = l_fmt; |
| 1731 | goto copcsr; |
| 1732 | } |
Ralf Baechle | 4b724ef | 2005-10-23 15:05:47 +0100 | [diff] [blame] | 1733 | #endif /* defined(__mips64) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1734 | |
| 1735 | default: |
| 1736 | if (MIPSInst_FUNC(ir) >= fcmp_op) { |
| 1737 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; |
| 1738 | ieee754sp fs, ft; |
| 1739 | |
| 1740 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1741 | SPFROMREG(ft, MIPSInst_FT(ir)); |
| 1742 | rv.w = ieee754sp_cmp(fs, ft, |
| 1743 | cmptab[cmpop & 0x7], cmpop & 0x8); |
| 1744 | rfmt = -1; |
| 1745 | if ((cmpop & 0x8) && ieee754_cxtest |
| 1746 | (IEEE754_INVALID_OPERATION)) |
| 1747 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; |
| 1748 | else |
| 1749 | goto copcsr; |
| 1750 | |
| 1751 | } |
| 1752 | else { |
| 1753 | return SIGILL; |
| 1754 | } |
| 1755 | break; |
| 1756 | } |
| 1757 | break; |
| 1758 | } |
| 1759 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1760 | case d_fmt:{ |
| 1761 | union { |
| 1762 | ieee754dp(*b) (ieee754dp, ieee754dp); |
| 1763 | ieee754dp(*u) (ieee754dp); |
| 1764 | } handler; |
| 1765 | |
| 1766 | switch (MIPSInst_FUNC(ir)) { |
| 1767 | /* binary ops */ |
| 1768 | case fadd_op: |
| 1769 | handler.b = ieee754dp_add; |
| 1770 | goto dcopbop; |
| 1771 | case fsub_op: |
| 1772 | handler.b = ieee754dp_sub; |
| 1773 | goto dcopbop; |
| 1774 | case fmul_op: |
| 1775 | handler.b = ieee754dp_mul; |
| 1776 | goto dcopbop; |
| 1777 | case fdiv_op: |
| 1778 | handler.b = ieee754dp_div; |
| 1779 | goto dcopbop; |
| 1780 | |
| 1781 | /* unary ops */ |
Ralf Baechle | 587cb98 | 2005-09-15 08:52:34 +0000 | [diff] [blame] | 1782 | #if __mips >= 2 || defined(__mips64) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1783 | case fsqrt_op: |
| 1784 | handler.u = ieee754dp_sqrt; |
| 1785 | goto dcopuop; |
| 1786 | #endif |
| 1787 | #if __mips >= 4 && __mips != 32 |
| 1788 | case frsqrt_op: |
| 1789 | handler.u = fpemu_dp_rsqrt; |
| 1790 | goto dcopuop; |
| 1791 | case frecip_op: |
| 1792 | handler.u = fpemu_dp_recip; |
| 1793 | goto dcopuop; |
| 1794 | #endif |
| 1795 | #if __mips >= 4 |
| 1796 | case fmovc_op: |
| 1797 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
| 1798 | if (((ctx->fcr31 & cond) != 0) != |
| 1799 | ((MIPSInst_FT(ir) & 1) != 0)) |
| 1800 | return 0; |
| 1801 | DPFROMREG(rv.d, MIPSInst_FS(ir)); |
| 1802 | break; |
| 1803 | case fmovz_op: |
| 1804 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
| 1805 | return 0; |
| 1806 | DPFROMREG(rv.d, MIPSInst_FS(ir)); |
| 1807 | break; |
| 1808 | case fmovn_op: |
| 1809 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
| 1810 | return 0; |
| 1811 | DPFROMREG(rv.d, MIPSInst_FS(ir)); |
| 1812 | break; |
| 1813 | #endif |
| 1814 | case fabs_op: |
| 1815 | handler.u = ieee754dp_abs; |
| 1816 | goto dcopuop; |
| 1817 | |
| 1818 | case fneg_op: |
| 1819 | handler.u = ieee754dp_neg; |
| 1820 | goto dcopuop; |
| 1821 | |
| 1822 | case fmov_op: |
| 1823 | /* an easy one */ |
| 1824 | DPFROMREG(rv.d, MIPSInst_FS(ir)); |
| 1825 | goto copcsr; |
| 1826 | |
| 1827 | /* binary op on handler */ |
| 1828 | dcopbop:{ |
| 1829 | ieee754dp fs, ft; |
| 1830 | |
| 1831 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1832 | DPFROMREG(ft, MIPSInst_FT(ir)); |
| 1833 | |
| 1834 | rv.d = (*handler.b) (fs, ft); |
| 1835 | goto copcsr; |
| 1836 | } |
| 1837 | dcopuop:{ |
| 1838 | ieee754dp fs; |
| 1839 | |
| 1840 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1841 | rv.d = (*handler.u) (fs); |
| 1842 | goto copcsr; |
| 1843 | } |
| 1844 | |
| 1845 | /* unary conv ops */ |
| 1846 | case fcvts_op:{ |
| 1847 | ieee754dp fs; |
| 1848 | |
| 1849 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1850 | rv.s = ieee754sp_fdp(fs); |
| 1851 | rfmt = s_fmt; |
| 1852 | goto copcsr; |
| 1853 | } |
| 1854 | case fcvtd_op: |
| 1855 | return SIGILL; /* not defined */ |
| 1856 | |
| 1857 | case fcvtw_op:{ |
| 1858 | ieee754dp fs; |
| 1859 | |
| 1860 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1861 | rv.w = ieee754dp_tint(fs); /* wrong */ |
| 1862 | rfmt = w_fmt; |
| 1863 | goto copcsr; |
| 1864 | } |
| 1865 | |
Ralf Baechle | 587cb98 | 2005-09-15 08:52:34 +0000 | [diff] [blame] | 1866 | #if __mips >= 2 || defined(__mips64) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1867 | case fround_op: |
| 1868 | case ftrunc_op: |
| 1869 | case fceil_op: |
| 1870 | case ffloor_op:{ |
| 1871 | unsigned int oldrm = ieee754_csr.rm; |
| 1872 | ieee754dp fs; |
| 1873 | |
| 1874 | DPFROMREG(fs, MIPSInst_FS(ir)); |
Shane McDonald | 3f13553 | 2010-05-07 00:02:09 -0600 | [diff] [blame] | 1875 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1876 | rv.w = ieee754dp_tint(fs); |
| 1877 | ieee754_csr.rm = oldrm; |
| 1878 | rfmt = w_fmt; |
| 1879 | goto copcsr; |
| 1880 | } |
| 1881 | #endif |
| 1882 | |
Ralf Baechle | 4b724ef | 2005-10-23 15:05:47 +0100 | [diff] [blame] | 1883 | #if defined(__mips64) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1884 | case fcvtl_op:{ |
| 1885 | ieee754dp fs; |
| 1886 | |
| 1887 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1888 | rv.l = ieee754dp_tlong(fs); |
| 1889 | rfmt = l_fmt; |
| 1890 | goto copcsr; |
| 1891 | } |
| 1892 | |
| 1893 | case froundl_op: |
| 1894 | case ftruncl_op: |
| 1895 | case fceill_op: |
| 1896 | case ffloorl_op:{ |
| 1897 | unsigned int oldrm = ieee754_csr.rm; |
| 1898 | ieee754dp fs; |
| 1899 | |
| 1900 | DPFROMREG(fs, MIPSInst_FS(ir)); |
Shane McDonald | 3f13553 | 2010-05-07 00:02:09 -0600 | [diff] [blame] | 1901 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1902 | rv.l = ieee754dp_tlong(fs); |
| 1903 | ieee754_csr.rm = oldrm; |
| 1904 | rfmt = l_fmt; |
| 1905 | goto copcsr; |
| 1906 | } |
Ralf Baechle | 4b724ef | 2005-10-23 15:05:47 +0100 | [diff] [blame] | 1907 | #endif /* __mips >= 3 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1908 | |
| 1909 | default: |
| 1910 | if (MIPSInst_FUNC(ir) >= fcmp_op) { |
| 1911 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; |
| 1912 | ieee754dp fs, ft; |
| 1913 | |
| 1914 | DPFROMREG(fs, MIPSInst_FS(ir)); |
| 1915 | DPFROMREG(ft, MIPSInst_FT(ir)); |
| 1916 | rv.w = ieee754dp_cmp(fs, ft, |
| 1917 | cmptab[cmpop & 0x7], cmpop & 0x8); |
| 1918 | rfmt = -1; |
| 1919 | if ((cmpop & 0x8) |
| 1920 | && |
| 1921 | ieee754_cxtest |
| 1922 | (IEEE754_INVALID_OPERATION)) |
| 1923 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; |
| 1924 | else |
| 1925 | goto copcsr; |
| 1926 | |
| 1927 | } |
| 1928 | else { |
| 1929 | return SIGILL; |
| 1930 | } |
| 1931 | break; |
| 1932 | } |
| 1933 | break; |
| 1934 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1935 | |
| 1936 | case w_fmt:{ |
| 1937 | ieee754sp fs; |
| 1938 | |
| 1939 | switch (MIPSInst_FUNC(ir)) { |
| 1940 | case fcvts_op: |
| 1941 | /* convert word to single precision real */ |
| 1942 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1943 | rv.s = ieee754sp_fint(fs.bits); |
| 1944 | rfmt = s_fmt; |
| 1945 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1946 | case fcvtd_op: |
| 1947 | /* convert word to double precision real */ |
| 1948 | SPFROMREG(fs, MIPSInst_FS(ir)); |
| 1949 | rv.d = ieee754dp_fint(fs.bits); |
| 1950 | rfmt = d_fmt; |
| 1951 | goto copcsr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1952 | default: |
| 1953 | return SIGILL; |
| 1954 | } |
| 1955 | break; |
| 1956 | } |
| 1957 | |
Ralf Baechle | 4b724ef | 2005-10-23 15:05:47 +0100 | [diff] [blame] | 1958 | #if defined(__mips64) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1959 | case l_fmt:{ |
| 1960 | switch (MIPSInst_FUNC(ir)) { |
| 1961 | case fcvts_op: |
| 1962 | /* convert long to single precision real */ |
| 1963 | rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]); |
| 1964 | rfmt = s_fmt; |
| 1965 | goto copcsr; |
| 1966 | case fcvtd_op: |
| 1967 | /* convert long to double precision real */ |
| 1968 | rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]); |
| 1969 | rfmt = d_fmt; |
| 1970 | goto copcsr; |
| 1971 | default: |
| 1972 | return SIGILL; |
| 1973 | } |
| 1974 | break; |
| 1975 | } |
| 1976 | #endif |
| 1977 | |
| 1978 | default: |
| 1979 | return SIGILL; |
| 1980 | } |
| 1981 | |
| 1982 | /* |
| 1983 | * Update the fpu CSR register for this operation. |
| 1984 | * If an exception is required, generate a tidy SIGFPE exception, |
| 1985 | * without updating the result register. |
| 1986 | * Note: cause exception bits do not accumulate, they are rewritten |
| 1987 | * for each op; only the flag/sticky bits accumulate. |
| 1988 | */ |
| 1989 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; |
| 1990 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
| 1991 | /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */ |
| 1992 | return SIGFPE; |
| 1993 | } |
| 1994 | |
| 1995 | /* |
| 1996 | * Now we can safely write the result back to the register file. |
| 1997 | */ |
| 1998 | switch (rfmt) { |
| 1999 | case -1:{ |
| 2000 | #if __mips >= 4 |
| 2001 | cond = fpucondbit[MIPSInst_FD(ir) >> 2]; |
| 2002 | #else |
| 2003 | cond = FPU_CSR_COND; |
| 2004 | #endif |
| 2005 | if (rv.w) |
| 2006 | ctx->fcr31 |= cond; |
| 2007 | else |
| 2008 | ctx->fcr31 &= ~cond; |
| 2009 | break; |
| 2010 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2011 | case d_fmt: |
| 2012 | DPTOREG(rv.d, MIPSInst_FD(ir)); |
| 2013 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2014 | case s_fmt: |
| 2015 | SPTOREG(rv.s, MIPSInst_FD(ir)); |
| 2016 | break; |
| 2017 | case w_fmt: |
| 2018 | SITOREG(rv.w, MIPSInst_FD(ir)); |
| 2019 | break; |
Ralf Baechle | 4b724ef | 2005-10-23 15:05:47 +0100 | [diff] [blame] | 2020 | #if defined(__mips64) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2021 | case l_fmt: |
| 2022 | DITOREG(rv.l, MIPSInst_FD(ir)); |
| 2023 | break; |
| 2024 | #endif |
| 2025 | default: |
| 2026 | return SIGILL; |
| 2027 | } |
| 2028 | |
| 2029 | return 0; |
| 2030 | } |
| 2031 | |
Atsushi Nemoto | e04582b | 2006-10-09 00:10:01 +0900 | [diff] [blame] | 2032 | int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
David Daney | 515b029 | 2010-10-21 16:32:26 -0700 | [diff] [blame] | 2033 | int has_fpu, void *__user *fault_addr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2034 | { |
Ralf Baechle | 333d1f6 | 2005-02-28 17:55:57 +0000 | [diff] [blame] | 2035 | unsigned long oldepc, prevepc; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 2036 | struct mm_decoded_insn dec_insn; |
| 2037 | u16 instr[4]; |
| 2038 | u16 *instr_ptr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2039 | int sig = 0; |
| 2040 | |
| 2041 | oldepc = xcp->cp0_epc; |
| 2042 | do { |
| 2043 | prevepc = xcp->cp0_epc; |
| 2044 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 2045 | if (get_isa16_mode(prevepc) && cpu_has_mmips) { |
| 2046 | /* |
| 2047 | * Get next 2 microMIPS instructions and convert them |
| 2048 | * into 32-bit instructions. |
| 2049 | */ |
| 2050 | if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || |
| 2051 | (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || |
| 2052 | (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || |
| 2053 | (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { |
| 2054 | MIPS_FPU_EMU_INC_STATS(errors); |
| 2055 | return SIGBUS; |
| 2056 | } |
| 2057 | instr_ptr = instr; |
| 2058 | |
| 2059 | /* Get first instruction. */ |
| 2060 | if (mm_insn_16bit(*instr_ptr)) { |
| 2061 | /* Duplicate the half-word. */ |
| 2062 | dec_insn.insn = (*instr_ptr << 16) | |
| 2063 | (*instr_ptr); |
| 2064 | /* 16-bit instruction. */ |
| 2065 | dec_insn.pc_inc = 2; |
| 2066 | instr_ptr += 1; |
| 2067 | } else { |
| 2068 | dec_insn.insn = (*instr_ptr << 16) | |
| 2069 | *(instr_ptr+1); |
| 2070 | /* 32-bit instruction. */ |
| 2071 | dec_insn.pc_inc = 4; |
| 2072 | instr_ptr += 2; |
| 2073 | } |
| 2074 | /* Get second instruction. */ |
| 2075 | if (mm_insn_16bit(*instr_ptr)) { |
| 2076 | /* Duplicate the half-word. */ |
| 2077 | dec_insn.next_insn = (*instr_ptr << 16) | |
| 2078 | (*instr_ptr); |
| 2079 | /* 16-bit instruction. */ |
| 2080 | dec_insn.next_pc_inc = 2; |
| 2081 | } else { |
| 2082 | dec_insn.next_insn = (*instr_ptr << 16) | |
| 2083 | *(instr_ptr+1); |
| 2084 | /* 32-bit instruction. */ |
| 2085 | dec_insn.next_pc_inc = 4; |
| 2086 | } |
| 2087 | dec_insn.micro_mips_mode = 1; |
| 2088 | } else { |
| 2089 | if ((get_user(dec_insn.insn, |
| 2090 | (mips_instruction __user *) xcp->cp0_epc)) || |
| 2091 | (get_user(dec_insn.next_insn, |
| 2092 | (mips_instruction __user *)(xcp->cp0_epc+4)))) { |
| 2093 | MIPS_FPU_EMU_INC_STATS(errors); |
| 2094 | return SIGBUS; |
| 2095 | } |
| 2096 | dec_insn.pc_inc = 4; |
| 2097 | dec_insn.next_pc_inc = 4; |
| 2098 | dec_insn.micro_mips_mode = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2099 | } |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 2100 | |
| 2101 | if ((dec_insn.insn == 0) || |
| 2102 | ((dec_insn.pc_inc == 2) && |
| 2103 | ((dec_insn.insn & 0xffff) == MM_NOP16))) |
| 2104 | xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2105 | else { |
Ralf Baechle | cd21dfc | 2005-04-28 13:39:10 +0000 | [diff] [blame] | 2106 | /* |
| 2107 | * The 'ieee754_csr' is an alias of |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 2108 | * ctx->fcr31. No need to copy ctx->fcr31 to |
| 2109 | * ieee754_csr. But ieee754_csr.rm is ieee |
Ralf Baechle | cd21dfc | 2005-04-28 13:39:10 +0000 | [diff] [blame] | 2110 | * library modes. (not mips rounding mode) |
| 2111 | */ |
| 2112 | /* convert to ieee library modes */ |
| 2113 | ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 2114 | sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); |
Ralf Baechle | cd21dfc | 2005-04-28 13:39:10 +0000 | [diff] [blame] | 2115 | /* revert to mips rounding mode */ |
| 2116 | ieee754_csr.rm = mips_rm[ieee754_csr.rm]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2117 | } |
| 2118 | |
Atsushi Nemoto | e04582b | 2006-10-09 00:10:01 +0900 | [diff] [blame] | 2119 | if (has_fpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2120 | break; |
| 2121 | if (sig) |
| 2122 | break; |
| 2123 | |
| 2124 | cond_resched(); |
| 2125 | } while (xcp->cp0_epc > prevepc); |
| 2126 | |
| 2127 | /* SIGILL indicates a non-fpu instruction */ |
| 2128 | if (sig == SIGILL && xcp->cp0_epc != oldepc) |
| 2129 | /* but if epc has advanced, then ignore it */ |
| 2130 | sig = 0; |
| 2131 | |
| 2132 | return sig; |
| 2133 | } |
Atsushi Nemoto | 83fd38c | 2007-07-07 23:21:49 +0900 | [diff] [blame] | 2134 | |
| 2135 | #ifdef CONFIG_DEBUG_FS |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 2136 | |
| 2137 | static int fpuemu_stat_get(void *data, u64 *val) |
| 2138 | { |
| 2139 | int cpu; |
| 2140 | unsigned long sum = 0; |
| 2141 | for_each_online_cpu(cpu) { |
| 2142 | struct mips_fpu_emulator_stats *ps; |
| 2143 | local_t *pv; |
| 2144 | ps = &per_cpu(fpuemustats, cpu); |
| 2145 | pv = (void *)ps + (unsigned long)data; |
| 2146 | sum += local_read(pv); |
| 2147 | } |
| 2148 | *val = sum; |
| 2149 | return 0; |
| 2150 | } |
| 2151 | DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n"); |
| 2152 | |
Atsushi Nemoto | 83fd38c | 2007-07-07 23:21:49 +0900 | [diff] [blame] | 2153 | extern struct dentry *mips_debugfs_dir; |
| 2154 | static int __init debugfs_fpuemu(void) |
| 2155 | { |
| 2156 | struct dentry *d, *dir; |
Atsushi Nemoto | 83fd38c | 2007-07-07 23:21:49 +0900 | [diff] [blame] | 2157 | |
| 2158 | if (!mips_debugfs_dir) |
| 2159 | return -ENODEV; |
| 2160 | dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); |
Zhaolei | ecab1f4 | 2008-10-17 19:12:30 +0800 | [diff] [blame] | 2161 | if (!dir) |
| 2162 | return -ENOMEM; |
David Daney | b6ee75e | 2009-11-05 11:34:26 -0800 | [diff] [blame] | 2163 | |
| 2164 | #define FPU_STAT_CREATE(M) \ |
| 2165 | do { \ |
| 2166 | d = debugfs_create_file(#M , S_IRUGO, dir, \ |
| 2167 | (void *)offsetof(struct mips_fpu_emulator_stats, M), \ |
| 2168 | &fops_fpuemu_stat); \ |
| 2169 | if (!d) \ |
| 2170 | return -ENOMEM; \ |
| 2171 | } while (0) |
| 2172 | |
| 2173 | FPU_STAT_CREATE(emulated); |
| 2174 | FPU_STAT_CREATE(loads); |
| 2175 | FPU_STAT_CREATE(stores); |
| 2176 | FPU_STAT_CREATE(cp1ops); |
| 2177 | FPU_STAT_CREATE(cp1xops); |
| 2178 | FPU_STAT_CREATE(errors); |
| 2179 | |
Atsushi Nemoto | 83fd38c | 2007-07-07 23:21:49 +0900 | [diff] [blame] | 2180 | return 0; |
| 2181 | } |
| 2182 | __initcall(debugfs_fpuemu); |
| 2183 | #endif |