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Michael Chanb6016b72005-05-26 13:03:09 -07001/* bnx2.c: Broadcom NX2 network driver.
2 *
Michael Chana6952b52009-02-12 16:54:48 -08003 * Copyright (c) 2004-2009 Broadcom Corporation
Michael Chanb6016b72005-05-26 13:03:09 -07004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
Michael Chanf2a4f052006-03-23 01:13:12 -080012
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
Jiri Slaby1977f032007-10-18 23:40:25 -070029#include <linux/bitops.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080030#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
Michael Chanc86a31f2006-06-13 15:03:47 -070034#include <asm/page.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080035#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080038#include <linux/if_vlan.h>
David S. Miller08013fa2008-08-15 19:46:01 -070039#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
Michael Chanf2a4f052006-03-23 01:13:12 -080040#define BCM_VLAN 1
41#endif
Michael Chanf2a4f052006-03-23 01:13:12 -080042#include <net/ip.h>
Linus Torvaldsde081fa2007-07-12 16:40:08 -070043#include <net/tcp.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080044#include <net/checksum.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080045#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
Michael Chan29b12172006-03-23 01:13:43 -080048#include <linux/cache.h>
Michael Chan57579f72009-04-04 16:51:14 -070049#include <linux/firmware.h>
Benjamin Li706bf242008-07-18 17:55:11 -070050#include <linux/log2.h>
Jiri Pirkoccffad252009-05-22 23:22:17 +000051#include <linux/list.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080052
Michael Chan4edd4732009-06-08 18:14:42 -070053#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54#define BCM_CNIC 1
55#include "cnic_if.h"
56#endif
Michael Chanb6016b72005-05-26 13:03:09 -070057#include "bnx2.h"
58#include "bnx2_fw.h"
Denys Vlasenkob3448b02007-09-30 17:55:51 -070059
Michael Chanb6016b72005-05-26 13:03:09 -070060#define DRV_MODULE_NAME "bnx2"
61#define PFX DRV_MODULE_NAME ": "
Michael Chan8fea0f02009-08-21 16:20:50 +000062#define DRV_MODULE_VERSION "2.0.2"
63#define DRV_MODULE_RELDATE "Aug 21, 2009"
Michael Chan078b0732009-08-29 00:02:46 -070064#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j3.fw"
65#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
66#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j3.fw"
67#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j3.fw"
68#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j3.fw"
Michael Chanb6016b72005-05-26 13:03:09 -070069
70#define RUN_AT(x) (jiffies + (x))
71
72/* Time in jiffies before concluding the transmitter is hung. */
73#define TX_TIMEOUT (5*HZ)
74
Andrew Mortonfefa8642008-02-09 23:17:15 -080075static char version[] __devinitdata =
Michael Chanb6016b72005-05-26 13:03:09 -070076 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
77
78MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
Benjamin Li453a9c62008-09-18 16:39:16 -070079MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
Michael Chanb6016b72005-05-26 13:03:09 -070080MODULE_LICENSE("GPL");
81MODULE_VERSION(DRV_MODULE_VERSION);
Michael Chan57579f72009-04-04 16:51:14 -070082MODULE_FIRMWARE(FW_MIPS_FILE_06);
83MODULE_FIRMWARE(FW_RV2P_FILE_06);
84MODULE_FIRMWARE(FW_MIPS_FILE_09);
85MODULE_FIRMWARE(FW_RV2P_FILE_09);
Michael Chan078b0732009-08-29 00:02:46 -070086MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
Michael Chanb6016b72005-05-26 13:03:09 -070087
88static int disable_msi = 0;
89
90module_param(disable_msi, int, 0);
91MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
92
93typedef enum {
94 BCM5706 = 0,
95 NC370T,
96 NC370I,
97 BCM5706S,
98 NC370F,
Michael Chan5b0c76a2005-11-04 08:45:49 -080099 BCM5708,
100 BCM5708S,
Michael Chanbac0dff2006-11-19 14:15:05 -0800101 BCM5709,
Michael Chan27a005b2007-05-03 13:23:41 -0700102 BCM5709S,
Michael Chan7bb0a042008-07-14 22:37:47 -0700103 BCM5716,
Michael Chan1caacec2008-11-12 16:01:12 -0800104 BCM5716S,
Michael Chanb6016b72005-05-26 13:03:09 -0700105} board_t;
106
107/* indexed by board_t, above */
Andrew Mortonfefa8642008-02-09 23:17:15 -0800108static struct {
Michael Chanb6016b72005-05-26 13:03:09 -0700109 char *name;
110} board_info[] __devinitdata = {
111 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
112 { "HP NC370T Multifunction Gigabit Server Adapter" },
113 { "HP NC370i Multifunction Gigabit Server Adapter" },
114 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
115 { "HP NC370F Multifunction Gigabit Server Adapter" },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800116 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
117 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
Michael Chanbac0dff2006-11-19 14:15:05 -0800118 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
Michael Chan27a005b2007-05-03 13:23:41 -0700119 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
Michael Chan7bb0a042008-07-14 22:37:47 -0700120 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
Michael Chan1caacec2008-11-12 16:01:12 -0800121 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
Michael Chanb6016b72005-05-26 13:03:09 -0700122 };
123
Michael Chan7bb0a042008-07-14 22:37:47 -0700124static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
Michael Chanb6016b72005-05-26 13:03:09 -0700125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
126 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
128 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
Michael Chanb6016b72005-05-26 13:03:09 -0700133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
134 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800137 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
Michael Chanbac0dff2006-11-19 14:15:05 -0800139 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
Michael Chan27a005b2007-05-03 13:23:41 -0700141 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
Michael Chan7bb0a042008-07-14 22:37:47 -0700143 { PCI_VENDOR_ID_BROADCOM, 0x163b,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
Michael Chan1caacec2008-11-12 16:01:12 -0800145 { PCI_VENDOR_ID_BROADCOM, 0x163c,
Michael Chan1f2435e2008-12-16 20:28:13 -0800146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
Michael Chanb6016b72005-05-26 13:03:09 -0700147 { 0, }
148};
149
Michael Chan0ced9d02009-08-21 16:20:49 +0000150static const struct flash_spec flash_table[] =
Michael Chanb6016b72005-05-26 13:03:09 -0700151{
Michael Chane30372c2007-07-16 18:26:23 -0700152#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
153#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
Michael Chanb6016b72005-05-26 13:03:09 -0700154 /* Slow EEPROM */
Michael Chan37137702005-11-04 08:49:17 -0800155 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700156 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700157 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
158 "EEPROM - slow"},
Michael Chan37137702005-11-04 08:49:17 -0800159 /* Expansion entry 0001 */
160 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700161 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800162 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
163 "Entry 0001"},
Michael Chanb6016b72005-05-26 13:03:09 -0700164 /* Saifun SA25F010 (non-buffered flash) */
165 /* strap, cfg1, & write1 need updates */
Michael Chan37137702005-11-04 08:49:17 -0800166 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700167 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700168 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
169 "Non-buffered flash (128kB)"},
170 /* Saifun SA25F020 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
Michael Chan37137702005-11-04 08:49:17 -0800172 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
175 "Non-buffered flash (256kB)"},
Michael Chan37137702005-11-04 08:49:17 -0800176 /* Expansion entry 0100 */
177 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700178 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800179 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
180 "Entry 0100"},
181 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400182 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700183 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800184 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
185 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
186 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
187 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700188 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800189 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
190 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
191 /* Saifun SA25F005 (non-buffered flash) */
192 /* strap, cfg1, & write1 need updates */
193 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800195 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
196 "Non-buffered flash (64kB)"},
197 /* Fast EEPROM */
198 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700199 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800200 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
201 "EEPROM - fast"},
202 /* Expansion entry 1001 */
203 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700204 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800205 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 "Entry 1001"},
207 /* Expansion entry 1010 */
208 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800210 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
211 "Entry 1010"},
212 /* ATMEL AT45DB011B (buffered flash) */
213 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700214 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800215 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
216 "Buffered flash (128kB)"},
217 /* Expansion entry 1100 */
218 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
221 "Entry 1100"},
222 /* Expansion entry 1101 */
223 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
226 "Entry 1101"},
227 /* Ateml Expansion entry 1110 */
228 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800230 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
231 "Entry 1110 (Atmel)"},
232 /* ATMEL AT45DB021B (buffered flash) */
233 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700234 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800235 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
236 "Buffered flash (256kB)"},
Michael Chanb6016b72005-05-26 13:03:09 -0700237};
238
Michael Chan0ced9d02009-08-21 16:20:49 +0000239static const struct flash_spec flash_5709 = {
Michael Chane30372c2007-07-16 18:26:23 -0700240 .flags = BNX2_NV_BUFFERED,
241 .page_bits = BCM5709_FLASH_PAGE_BITS,
242 .page_size = BCM5709_FLASH_PAGE_SIZE,
243 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
244 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
245 .name = "5709 Buffered flash (256kB)",
246};
247
Michael Chanb6016b72005-05-26 13:03:09 -0700248MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
249
Michael Chan35e90102008-06-19 16:37:42 -0700250static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
Michael Chane89bbf12005-08-25 15:36:58 -0700251{
Michael Chan2f8af122006-08-15 01:39:10 -0700252 u32 diff;
Michael Chane89bbf12005-08-25 15:36:58 -0700253
Michael Chan2f8af122006-08-15 01:39:10 -0700254 smp_mb();
Michael Chanfaac9c42006-12-14 15:56:32 -0800255
256 /* The ring uses 256 indices for 255 entries, one of them
257 * needs to be skipped.
258 */
Michael Chan35e90102008-06-19 16:37:42 -0700259 diff = txr->tx_prod - txr->tx_cons;
Michael Chanfaac9c42006-12-14 15:56:32 -0800260 if (unlikely(diff >= TX_DESC_CNT)) {
261 diff &= 0xffff;
262 if (diff == TX_DESC_CNT)
263 diff = MAX_TX_DESC_CNT;
264 }
Michael Chane89bbf12005-08-25 15:36:58 -0700265 return (bp->tx_ring_size - diff);
266}
267
Michael Chanb6016b72005-05-26 13:03:09 -0700268static u32
269bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
270{
Michael Chan1b8227c2007-05-03 13:24:05 -0700271 u32 val;
272
273 spin_lock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700274 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
Michael Chan1b8227c2007-05-03 13:24:05 -0700275 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
276 spin_unlock_bh(&bp->indirect_lock);
277 return val;
Michael Chanb6016b72005-05-26 13:03:09 -0700278}
279
280static void
281bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
282{
Michael Chan1b8227c2007-05-03 13:24:05 -0700283 spin_lock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700284 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
285 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
Michael Chan1b8227c2007-05-03 13:24:05 -0700286 spin_unlock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700287}
288
289static void
Michael Chan2726d6e2008-01-29 21:35:05 -0800290bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
291{
292 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
293}
294
295static u32
296bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
297{
298 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
299}
300
301static void
Michael Chanb6016b72005-05-26 13:03:09 -0700302bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
303{
304 offset += cid_addr;
Michael Chan1b8227c2007-05-03 13:24:05 -0700305 spin_lock_bh(&bp->indirect_lock);
Michael Chan59b47d82006-11-19 14:10:45 -0800306 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
307 int i;
308
309 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
310 REG_WR(bp, BNX2_CTX_CTX_CTRL,
311 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
312 for (i = 0; i < 5; i++) {
Michael Chan59b47d82006-11-19 14:10:45 -0800313 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
314 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
315 break;
316 udelay(5);
317 }
318 } else {
319 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
320 REG_WR(bp, BNX2_CTX_DATA, val);
321 }
Michael Chan1b8227c2007-05-03 13:24:05 -0700322 spin_unlock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700323}
324
Michael Chan4edd4732009-06-08 18:14:42 -0700325#ifdef BCM_CNIC
326static int
327bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
328{
329 struct bnx2 *bp = netdev_priv(dev);
330 struct drv_ctl_io *io = &info->data.io;
331
332 switch (info->cmd) {
333 case DRV_CTL_IO_WR_CMD:
334 bnx2_reg_wr_ind(bp, io->offset, io->data);
335 break;
336 case DRV_CTL_IO_RD_CMD:
337 io->data = bnx2_reg_rd_ind(bp, io->offset);
338 break;
339 case DRV_CTL_CTX_WR_CMD:
340 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
341 break;
342 default:
343 return -EINVAL;
344 }
345 return 0;
346}
347
348static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
349{
350 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
351 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
352 int sb_id;
353
354 if (bp->flags & BNX2_FLAG_USING_MSIX) {
355 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
356 bnapi->cnic_present = 0;
357 sb_id = bp->irq_nvecs;
358 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
359 } else {
360 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
361 bnapi->cnic_tag = bnapi->last_status_idx;
362 bnapi->cnic_present = 1;
363 sb_id = 0;
364 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
365 }
366
367 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
368 cp->irq_arr[0].status_blk = (void *)
369 ((unsigned long) bnapi->status_blk.msi +
370 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
371 cp->irq_arr[0].status_blk_num = sb_id;
372 cp->num_irq = 1;
373}
374
375static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
376 void *data)
377{
378 struct bnx2 *bp = netdev_priv(dev);
379 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
380
381 if (ops == NULL)
382 return -EINVAL;
383
384 if (cp->drv_state & CNIC_DRV_STATE_REGD)
385 return -EBUSY;
386
387 bp->cnic_data = data;
388 rcu_assign_pointer(bp->cnic_ops, ops);
389
390 cp->num_irq = 0;
391 cp->drv_state = CNIC_DRV_STATE_REGD;
392
393 bnx2_setup_cnic_irq_info(bp);
394
395 return 0;
396}
397
398static int bnx2_unregister_cnic(struct net_device *dev)
399{
400 struct bnx2 *bp = netdev_priv(dev);
401 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
402 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
403
Michael Chanc5a88952009-08-14 15:49:45 +0000404 mutex_lock(&bp->cnic_lock);
Michael Chan4edd4732009-06-08 18:14:42 -0700405 cp->drv_state = 0;
406 bnapi->cnic_present = 0;
407 rcu_assign_pointer(bp->cnic_ops, NULL);
Michael Chanc5a88952009-08-14 15:49:45 +0000408 mutex_unlock(&bp->cnic_lock);
Michael Chan4edd4732009-06-08 18:14:42 -0700409 synchronize_rcu();
410 return 0;
411}
412
413struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
414{
415 struct bnx2 *bp = netdev_priv(dev);
416 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
417
418 cp->drv_owner = THIS_MODULE;
419 cp->chip_id = bp->chip_id;
420 cp->pdev = bp->pdev;
421 cp->io_base = bp->regview;
422 cp->drv_ctl = bnx2_drv_ctl;
423 cp->drv_register_cnic = bnx2_register_cnic;
424 cp->drv_unregister_cnic = bnx2_unregister_cnic;
425
426 return cp;
427}
428EXPORT_SYMBOL(bnx2_cnic_probe);
429
430static void
431bnx2_cnic_stop(struct bnx2 *bp)
432{
433 struct cnic_ops *c_ops;
434 struct cnic_ctl_info info;
435
Michael Chanc5a88952009-08-14 15:49:45 +0000436 mutex_lock(&bp->cnic_lock);
437 c_ops = bp->cnic_ops;
Michael Chan4edd4732009-06-08 18:14:42 -0700438 if (c_ops) {
439 info.cmd = CNIC_CTL_STOP_CMD;
440 c_ops->cnic_ctl(bp->cnic_data, &info);
441 }
Michael Chanc5a88952009-08-14 15:49:45 +0000442 mutex_unlock(&bp->cnic_lock);
Michael Chan4edd4732009-06-08 18:14:42 -0700443}
444
445static void
446bnx2_cnic_start(struct bnx2 *bp)
447{
448 struct cnic_ops *c_ops;
449 struct cnic_ctl_info info;
450
Michael Chanc5a88952009-08-14 15:49:45 +0000451 mutex_lock(&bp->cnic_lock);
452 c_ops = bp->cnic_ops;
Michael Chan4edd4732009-06-08 18:14:42 -0700453 if (c_ops) {
454 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
455 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
456
457 bnapi->cnic_tag = bnapi->last_status_idx;
458 }
459 info.cmd = CNIC_CTL_START_CMD;
460 c_ops->cnic_ctl(bp->cnic_data, &info);
461 }
Michael Chanc5a88952009-08-14 15:49:45 +0000462 mutex_unlock(&bp->cnic_lock);
Michael Chan4edd4732009-06-08 18:14:42 -0700463}
464
465#else
466
467static void
468bnx2_cnic_stop(struct bnx2 *bp)
469{
470}
471
472static void
473bnx2_cnic_start(struct bnx2 *bp)
474{
475}
476
477#endif
478
Michael Chanb6016b72005-05-26 13:03:09 -0700479static int
480bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
481{
482 u32 val1;
483 int i, ret;
484
Michael Chan583c28e2008-01-21 19:51:35 -0800485 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700486 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
487 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
488
489 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
490 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
491
492 udelay(40);
493 }
494
495 val1 = (bp->phy_addr << 21) | (reg << 16) |
496 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
497 BNX2_EMAC_MDIO_COMM_START_BUSY;
498 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
499
500 for (i = 0; i < 50; i++) {
501 udelay(10);
502
503 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
504 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
505 udelay(5);
506
507 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
508 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
509
510 break;
511 }
512 }
513
514 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
515 *val = 0x0;
516 ret = -EBUSY;
517 }
518 else {
519 *val = val1;
520 ret = 0;
521 }
522
Michael Chan583c28e2008-01-21 19:51:35 -0800523 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700524 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
525 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
526
527 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
528 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
529
530 udelay(40);
531 }
532
533 return ret;
534}
535
536static int
537bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
538{
539 u32 val1;
540 int i, ret;
541
Michael Chan583c28e2008-01-21 19:51:35 -0800542 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700543 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
544 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
545
546 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
547 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
548
549 udelay(40);
550 }
551
552 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
553 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
554 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
555 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400556
Michael Chanb6016b72005-05-26 13:03:09 -0700557 for (i = 0; i < 50; i++) {
558 udelay(10);
559
560 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
561 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
562 udelay(5);
563 break;
564 }
565 }
566
567 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
568 ret = -EBUSY;
569 else
570 ret = 0;
571
Michael Chan583c28e2008-01-21 19:51:35 -0800572 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700573 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
574 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
575
576 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
577 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
578
579 udelay(40);
580 }
581
582 return ret;
583}
584
585static void
586bnx2_disable_int(struct bnx2 *bp)
587{
Michael Chanb4b36042007-12-20 19:59:30 -0800588 int i;
589 struct bnx2_napi *bnapi;
590
591 for (i = 0; i < bp->irq_nvecs; i++) {
592 bnapi = &bp->bnx2_napi[i];
593 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
594 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
595 }
Michael Chanb6016b72005-05-26 13:03:09 -0700596 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
597}
598
599static void
600bnx2_enable_int(struct bnx2 *bp)
601{
Michael Chanb4b36042007-12-20 19:59:30 -0800602 int i;
603 struct bnx2_napi *bnapi;
Michael Chan1269a8a2006-01-23 16:11:03 -0800604
Michael Chanb4b36042007-12-20 19:59:30 -0800605 for (i = 0; i < bp->irq_nvecs; i++) {
606 bnapi = &bp->bnx2_napi[i];
Michael Chan35efa7c2007-12-20 19:56:37 -0800607
Michael Chanb4b36042007-12-20 19:59:30 -0800608 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
609 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
610 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
611 bnapi->last_status_idx);
Michael Chanb6016b72005-05-26 13:03:09 -0700612
Michael Chanb4b36042007-12-20 19:59:30 -0800613 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
614 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
615 bnapi->last_status_idx);
616 }
Michael Chanbf5295b2006-03-23 01:11:56 -0800617 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
Michael Chanb6016b72005-05-26 13:03:09 -0700618}
619
620static void
621bnx2_disable_int_sync(struct bnx2 *bp)
622{
Michael Chanb4b36042007-12-20 19:59:30 -0800623 int i;
624
Michael Chanb6016b72005-05-26 13:03:09 -0700625 atomic_inc(&bp->intr_sem);
Michael Chan37675462009-08-21 16:20:44 +0000626 if (!netif_running(bp->dev))
627 return;
628
Michael Chanb6016b72005-05-26 13:03:09 -0700629 bnx2_disable_int(bp);
Michael Chanb4b36042007-12-20 19:59:30 -0800630 for (i = 0; i < bp->irq_nvecs; i++)
631 synchronize_irq(bp->irq_tbl[i].vector);
Michael Chanb6016b72005-05-26 13:03:09 -0700632}
633
634static void
Michael Chan35efa7c2007-12-20 19:56:37 -0800635bnx2_napi_disable(struct bnx2 *bp)
636{
Michael Chanb4b36042007-12-20 19:59:30 -0800637 int i;
638
639 for (i = 0; i < bp->irq_nvecs; i++)
640 napi_disable(&bp->bnx2_napi[i].napi);
Michael Chan35efa7c2007-12-20 19:56:37 -0800641}
642
643static void
644bnx2_napi_enable(struct bnx2 *bp)
645{
Michael Chanb4b36042007-12-20 19:59:30 -0800646 int i;
647
648 for (i = 0; i < bp->irq_nvecs; i++)
649 napi_enable(&bp->bnx2_napi[i].napi);
Michael Chan35efa7c2007-12-20 19:56:37 -0800650}
651
652static void
Michael Chanb6016b72005-05-26 13:03:09 -0700653bnx2_netif_stop(struct bnx2 *bp)
654{
Michael Chan4edd4732009-06-08 18:14:42 -0700655 bnx2_cnic_stop(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700656 bnx2_disable_int_sync(bp);
657 if (netif_running(bp->dev)) {
Michael Chan35efa7c2007-12-20 19:56:37 -0800658 bnx2_napi_disable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700659 netif_tx_disable(bp->dev);
660 bp->dev->trans_start = jiffies; /* prevent tx timeout */
661 }
662}
663
664static void
665bnx2_netif_start(struct bnx2 *bp)
666{
667 if (atomic_dec_and_test(&bp->intr_sem)) {
668 if (netif_running(bp->dev)) {
Benjamin Li706bf242008-07-18 17:55:11 -0700669 netif_tx_wake_all_queues(bp->dev);
Michael Chan35efa7c2007-12-20 19:56:37 -0800670 bnx2_napi_enable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700671 bnx2_enable_int(bp);
Michael Chan4edd4732009-06-08 18:14:42 -0700672 bnx2_cnic_start(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700673 }
674 }
675}
676
677static void
Michael Chan35e90102008-06-19 16:37:42 -0700678bnx2_free_tx_mem(struct bnx2 *bp)
679{
680 int i;
681
682 for (i = 0; i < bp->num_tx_rings; i++) {
683 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
684 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
685
686 if (txr->tx_desc_ring) {
687 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
688 txr->tx_desc_ring,
689 txr->tx_desc_mapping);
690 txr->tx_desc_ring = NULL;
691 }
692 kfree(txr->tx_buf_ring);
693 txr->tx_buf_ring = NULL;
694 }
695}
696
Michael Chanbb4f98a2008-06-19 16:38:19 -0700697static void
698bnx2_free_rx_mem(struct bnx2 *bp)
699{
700 int i;
701
702 for (i = 0; i < bp->num_rx_rings; i++) {
703 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
704 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
705 int j;
706
707 for (j = 0; j < bp->rx_max_ring; j++) {
708 if (rxr->rx_desc_ring[j])
709 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
710 rxr->rx_desc_ring[j],
711 rxr->rx_desc_mapping[j]);
712 rxr->rx_desc_ring[j] = NULL;
713 }
Breno Leitao25b0b992009-06-08 10:30:19 +0000714 vfree(rxr->rx_buf_ring);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700715 rxr->rx_buf_ring = NULL;
716
717 for (j = 0; j < bp->rx_max_pg_ring; j++) {
718 if (rxr->rx_pg_desc_ring[j])
719 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
Michael Chan3298a732008-12-17 19:06:08 -0800720 rxr->rx_pg_desc_ring[j],
721 rxr->rx_pg_desc_mapping[j]);
722 rxr->rx_pg_desc_ring[j] = NULL;
Michael Chanbb4f98a2008-06-19 16:38:19 -0700723 }
Breno Leitao25b0b992009-06-08 10:30:19 +0000724 vfree(rxr->rx_pg_ring);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700725 rxr->rx_pg_ring = NULL;
726 }
727}
728
Michael Chan35e90102008-06-19 16:37:42 -0700729static int
730bnx2_alloc_tx_mem(struct bnx2 *bp)
731{
732 int i;
733
734 for (i = 0; i < bp->num_tx_rings; i++) {
735 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
736 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
737
738 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
739 if (txr->tx_buf_ring == NULL)
740 return -ENOMEM;
741
742 txr->tx_desc_ring =
743 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
744 &txr->tx_desc_mapping);
745 if (txr->tx_desc_ring == NULL)
746 return -ENOMEM;
747 }
748 return 0;
749}
750
Michael Chanbb4f98a2008-06-19 16:38:19 -0700751static int
752bnx2_alloc_rx_mem(struct bnx2 *bp)
753{
754 int i;
755
756 for (i = 0; i < bp->num_rx_rings; i++) {
757 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
758 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
759 int j;
760
761 rxr->rx_buf_ring =
762 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
763 if (rxr->rx_buf_ring == NULL)
764 return -ENOMEM;
765
766 memset(rxr->rx_buf_ring, 0,
767 SW_RXBD_RING_SIZE * bp->rx_max_ring);
768
769 for (j = 0; j < bp->rx_max_ring; j++) {
770 rxr->rx_desc_ring[j] =
771 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
772 &rxr->rx_desc_mapping[j]);
773 if (rxr->rx_desc_ring[j] == NULL)
774 return -ENOMEM;
775
776 }
777
778 if (bp->rx_pg_ring_size) {
779 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
780 bp->rx_max_pg_ring);
781 if (rxr->rx_pg_ring == NULL)
782 return -ENOMEM;
783
784 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
785 bp->rx_max_pg_ring);
786 }
787
788 for (j = 0; j < bp->rx_max_pg_ring; j++) {
789 rxr->rx_pg_desc_ring[j] =
790 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
791 &rxr->rx_pg_desc_mapping[j]);
792 if (rxr->rx_pg_desc_ring[j] == NULL)
793 return -ENOMEM;
794
795 }
796 }
797 return 0;
798}
799
Michael Chan35e90102008-06-19 16:37:42 -0700800static void
Michael Chanb6016b72005-05-26 13:03:09 -0700801bnx2_free_mem(struct bnx2 *bp)
802{
Michael Chan13daffa2006-03-20 17:49:20 -0800803 int i;
Michael Chan43e80b82008-06-19 16:41:08 -0700804 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
Michael Chan13daffa2006-03-20 17:49:20 -0800805
Michael Chan35e90102008-06-19 16:37:42 -0700806 bnx2_free_tx_mem(bp);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700807 bnx2_free_rx_mem(bp);
Michael Chan35e90102008-06-19 16:37:42 -0700808
Michael Chan59b47d82006-11-19 14:10:45 -0800809 for (i = 0; i < bp->ctx_pages; i++) {
810 if (bp->ctx_blk[i]) {
811 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
812 bp->ctx_blk[i],
813 bp->ctx_blk_mapping[i]);
814 bp->ctx_blk[i] = NULL;
815 }
816 }
Michael Chan43e80b82008-06-19 16:41:08 -0700817 if (bnapi->status_blk.msi) {
Michael Chan0f31f992006-03-23 01:12:38 -0800818 pci_free_consistent(bp->pdev, bp->status_stats_size,
Michael Chan43e80b82008-06-19 16:41:08 -0700819 bnapi->status_blk.msi,
820 bp->status_blk_mapping);
821 bnapi->status_blk.msi = NULL;
Michael Chan0f31f992006-03-23 01:12:38 -0800822 bp->stats_blk = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -0700823 }
Michael Chanb6016b72005-05-26 13:03:09 -0700824}
825
826static int
827bnx2_alloc_mem(struct bnx2 *bp)
828{
Michael Chan35e90102008-06-19 16:37:42 -0700829 int i, status_blk_size, err;
Michael Chan43e80b82008-06-19 16:41:08 -0700830 struct bnx2_napi *bnapi;
831 void *status_blk;
Michael Chanb6016b72005-05-26 13:03:09 -0700832
Michael Chan0f31f992006-03-23 01:12:38 -0800833 /* Combine status and statistics blocks into one allocation. */
834 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
David S. Millerf86e82f2008-01-21 17:15:40 -0800835 if (bp->flags & BNX2_FLAG_MSIX_CAP)
Michael Chanb4b36042007-12-20 19:59:30 -0800836 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
837 BNX2_SBLK_MSIX_ALIGN_SIZE);
Michael Chan0f31f992006-03-23 01:12:38 -0800838 bp->status_stats_size = status_blk_size +
839 sizeof(struct statistics_block);
840
Michael Chan43e80b82008-06-19 16:41:08 -0700841 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
842 &bp->status_blk_mapping);
843 if (status_blk == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -0700844 goto alloc_mem_err;
845
Michael Chan43e80b82008-06-19 16:41:08 -0700846 memset(status_blk, 0, bp->status_stats_size);
Michael Chanb6016b72005-05-26 13:03:09 -0700847
Michael Chan43e80b82008-06-19 16:41:08 -0700848 bnapi = &bp->bnx2_napi[0];
849 bnapi->status_blk.msi = status_blk;
850 bnapi->hw_tx_cons_ptr =
851 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
852 bnapi->hw_rx_cons_ptr =
853 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
David S. Millerf86e82f2008-01-21 17:15:40 -0800854 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
Michael Chanb4b36042007-12-20 19:59:30 -0800855 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
Michael Chan43e80b82008-06-19 16:41:08 -0700856 struct status_block_msix *sblk;
Michael Chanb4b36042007-12-20 19:59:30 -0800857
Michael Chan43e80b82008-06-19 16:41:08 -0700858 bnapi = &bp->bnx2_napi[i];
859
860 sblk = (void *) (status_blk +
861 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
862 bnapi->status_blk.msix = sblk;
863 bnapi->hw_tx_cons_ptr =
864 &sblk->status_tx_quick_consumer_index;
865 bnapi->hw_rx_cons_ptr =
866 &sblk->status_rx_quick_consumer_index;
Michael Chanb4b36042007-12-20 19:59:30 -0800867 bnapi->int_num = i << 24;
868 }
869 }
Michael Chan35efa7c2007-12-20 19:56:37 -0800870
Michael Chan43e80b82008-06-19 16:41:08 -0700871 bp->stats_blk = status_blk + status_blk_size;
Michael Chanb6016b72005-05-26 13:03:09 -0700872
Michael Chan0f31f992006-03-23 01:12:38 -0800873 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
Michael Chanb6016b72005-05-26 13:03:09 -0700874
Michael Chan59b47d82006-11-19 14:10:45 -0800875 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
876 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
877 if (bp->ctx_pages == 0)
878 bp->ctx_pages = 1;
879 for (i = 0; i < bp->ctx_pages; i++) {
880 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
881 BCM_PAGE_SIZE,
882 &bp->ctx_blk_mapping[i]);
883 if (bp->ctx_blk[i] == NULL)
884 goto alloc_mem_err;
885 }
886 }
Michael Chan35e90102008-06-19 16:37:42 -0700887
Michael Chanbb4f98a2008-06-19 16:38:19 -0700888 err = bnx2_alloc_rx_mem(bp);
889 if (err)
890 goto alloc_mem_err;
891
Michael Chan35e90102008-06-19 16:37:42 -0700892 err = bnx2_alloc_tx_mem(bp);
893 if (err)
894 goto alloc_mem_err;
895
Michael Chanb6016b72005-05-26 13:03:09 -0700896 return 0;
897
898alloc_mem_err:
899 bnx2_free_mem(bp);
900 return -ENOMEM;
901}
902
903static void
Michael Chane3648b32005-11-04 08:51:21 -0800904bnx2_report_fw_link(struct bnx2 *bp)
905{
906 u32 fw_link_status = 0;
907
Michael Chan583c28e2008-01-21 19:51:35 -0800908 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -0700909 return;
910
Michael Chane3648b32005-11-04 08:51:21 -0800911 if (bp->link_up) {
912 u32 bmsr;
913
914 switch (bp->line_speed) {
915 case SPEED_10:
916 if (bp->duplex == DUPLEX_HALF)
917 fw_link_status = BNX2_LINK_STATUS_10HALF;
918 else
919 fw_link_status = BNX2_LINK_STATUS_10FULL;
920 break;
921 case SPEED_100:
922 if (bp->duplex == DUPLEX_HALF)
923 fw_link_status = BNX2_LINK_STATUS_100HALF;
924 else
925 fw_link_status = BNX2_LINK_STATUS_100FULL;
926 break;
927 case SPEED_1000:
928 if (bp->duplex == DUPLEX_HALF)
929 fw_link_status = BNX2_LINK_STATUS_1000HALF;
930 else
931 fw_link_status = BNX2_LINK_STATUS_1000FULL;
932 break;
933 case SPEED_2500:
934 if (bp->duplex == DUPLEX_HALF)
935 fw_link_status = BNX2_LINK_STATUS_2500HALF;
936 else
937 fw_link_status = BNX2_LINK_STATUS_2500FULL;
938 break;
939 }
940
941 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
942
943 if (bp->autoneg) {
944 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
945
Michael Chanca58c3a2007-05-03 13:22:52 -0700946 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
947 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Michael Chane3648b32005-11-04 08:51:21 -0800948
949 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
Michael Chan583c28e2008-01-21 19:51:35 -0800950 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
Michael Chane3648b32005-11-04 08:51:21 -0800951 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
952 else
953 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
954 }
955 }
956 else
957 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
958
Michael Chan2726d6e2008-01-29 21:35:05 -0800959 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
Michael Chane3648b32005-11-04 08:51:21 -0800960}
961
Michael Chan9b1084b2007-07-07 22:50:37 -0700962static char *
963bnx2_xceiver_str(struct bnx2 *bp)
964{
965 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
Michael Chan583c28e2008-01-21 19:51:35 -0800966 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
Michael Chan9b1084b2007-07-07 22:50:37 -0700967 "Copper"));
968}
969
Michael Chane3648b32005-11-04 08:51:21 -0800970static void
Michael Chanb6016b72005-05-26 13:03:09 -0700971bnx2_report_link(struct bnx2 *bp)
972{
973 if (bp->link_up) {
974 netif_carrier_on(bp->dev);
Michael Chan9b1084b2007-07-07 22:50:37 -0700975 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
976 bnx2_xceiver_str(bp));
Michael Chanb6016b72005-05-26 13:03:09 -0700977
978 printk("%d Mbps ", bp->line_speed);
979
980 if (bp->duplex == DUPLEX_FULL)
981 printk("full duplex");
982 else
983 printk("half duplex");
984
985 if (bp->flow_ctrl) {
986 if (bp->flow_ctrl & FLOW_CTRL_RX) {
987 printk(", receive ");
988 if (bp->flow_ctrl & FLOW_CTRL_TX)
989 printk("& transmit ");
990 }
991 else {
992 printk(", transmit ");
993 }
994 printk("flow control ON");
995 }
996 printk("\n");
997 }
998 else {
999 netif_carrier_off(bp->dev);
Michael Chan9b1084b2007-07-07 22:50:37 -07001000 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
1001 bnx2_xceiver_str(bp));
Michael Chanb6016b72005-05-26 13:03:09 -07001002 }
Michael Chane3648b32005-11-04 08:51:21 -08001003
1004 bnx2_report_fw_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001005}
1006
1007static void
1008bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1009{
1010 u32 local_adv, remote_adv;
1011
1012 bp->flow_ctrl = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001013 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
Michael Chanb6016b72005-05-26 13:03:09 -07001014 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1015
1016 if (bp->duplex == DUPLEX_FULL) {
1017 bp->flow_ctrl = bp->req_flow_ctrl;
1018 }
1019 return;
1020 }
1021
1022 if (bp->duplex != DUPLEX_FULL) {
1023 return;
1024 }
1025
Michael Chan583c28e2008-01-21 19:51:35 -08001026 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan5b0c76a2005-11-04 08:45:49 -08001027 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1028 u32 val;
1029
1030 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1031 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1032 bp->flow_ctrl |= FLOW_CTRL_TX;
1033 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1034 bp->flow_ctrl |= FLOW_CTRL_RX;
1035 return;
1036 }
1037
Michael Chanca58c3a2007-05-03 13:22:52 -07001038 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1039 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -07001040
Michael Chan583c28e2008-01-21 19:51:35 -08001041 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001042 u32 new_local_adv = 0;
1043 u32 new_remote_adv = 0;
1044
1045 if (local_adv & ADVERTISE_1000XPAUSE)
1046 new_local_adv |= ADVERTISE_PAUSE_CAP;
1047 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1048 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1049 if (remote_adv & ADVERTISE_1000XPAUSE)
1050 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1051 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1052 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1053
1054 local_adv = new_local_adv;
1055 remote_adv = new_remote_adv;
1056 }
1057
1058 /* See Table 28B-3 of 802.3ab-1999 spec. */
1059 if (local_adv & ADVERTISE_PAUSE_CAP) {
1060 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1061 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1062 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1063 }
1064 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1065 bp->flow_ctrl = FLOW_CTRL_RX;
1066 }
1067 }
1068 else {
1069 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1070 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1071 }
1072 }
1073 }
1074 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1075 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1076 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1077
1078 bp->flow_ctrl = FLOW_CTRL_TX;
1079 }
1080 }
1081}
1082
1083static int
Michael Chan27a005b2007-05-03 13:23:41 -07001084bnx2_5709s_linkup(struct bnx2 *bp)
1085{
1086 u32 val, speed;
1087
1088 bp->link_up = 1;
1089
1090 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1091 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1092 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1093
1094 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1095 bp->line_speed = bp->req_line_speed;
1096 bp->duplex = bp->req_duplex;
1097 return 0;
1098 }
1099 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1100 switch (speed) {
1101 case MII_BNX2_GP_TOP_AN_SPEED_10:
1102 bp->line_speed = SPEED_10;
1103 break;
1104 case MII_BNX2_GP_TOP_AN_SPEED_100:
1105 bp->line_speed = SPEED_100;
1106 break;
1107 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1108 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1109 bp->line_speed = SPEED_1000;
1110 break;
1111 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1112 bp->line_speed = SPEED_2500;
1113 break;
1114 }
1115 if (val & MII_BNX2_GP_TOP_AN_FD)
1116 bp->duplex = DUPLEX_FULL;
1117 else
1118 bp->duplex = DUPLEX_HALF;
1119 return 0;
1120}
1121
1122static int
Michael Chan5b0c76a2005-11-04 08:45:49 -08001123bnx2_5708s_linkup(struct bnx2 *bp)
1124{
1125 u32 val;
1126
1127 bp->link_up = 1;
1128 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1129 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1130 case BCM5708S_1000X_STAT1_SPEED_10:
1131 bp->line_speed = SPEED_10;
1132 break;
1133 case BCM5708S_1000X_STAT1_SPEED_100:
1134 bp->line_speed = SPEED_100;
1135 break;
1136 case BCM5708S_1000X_STAT1_SPEED_1G:
1137 bp->line_speed = SPEED_1000;
1138 break;
1139 case BCM5708S_1000X_STAT1_SPEED_2G5:
1140 bp->line_speed = SPEED_2500;
1141 break;
1142 }
1143 if (val & BCM5708S_1000X_STAT1_FD)
1144 bp->duplex = DUPLEX_FULL;
1145 else
1146 bp->duplex = DUPLEX_HALF;
1147
1148 return 0;
1149}
1150
1151static int
1152bnx2_5706s_linkup(struct bnx2 *bp)
Michael Chanb6016b72005-05-26 13:03:09 -07001153{
1154 u32 bmcr, local_adv, remote_adv, common;
1155
1156 bp->link_up = 1;
1157 bp->line_speed = SPEED_1000;
1158
Michael Chanca58c3a2007-05-03 13:22:52 -07001159 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001160 if (bmcr & BMCR_FULLDPLX) {
1161 bp->duplex = DUPLEX_FULL;
1162 }
1163 else {
1164 bp->duplex = DUPLEX_HALF;
1165 }
1166
1167 if (!(bmcr & BMCR_ANENABLE)) {
1168 return 0;
1169 }
1170
Michael Chanca58c3a2007-05-03 13:22:52 -07001171 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1172 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -07001173
1174 common = local_adv & remote_adv;
1175 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1176
1177 if (common & ADVERTISE_1000XFULL) {
1178 bp->duplex = DUPLEX_FULL;
1179 }
1180 else {
1181 bp->duplex = DUPLEX_HALF;
1182 }
1183 }
1184
1185 return 0;
1186}
1187
1188static int
1189bnx2_copper_linkup(struct bnx2 *bp)
1190{
1191 u32 bmcr;
1192
Michael Chanca58c3a2007-05-03 13:22:52 -07001193 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001194 if (bmcr & BMCR_ANENABLE) {
1195 u32 local_adv, remote_adv, common;
1196
1197 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1198 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1199
1200 common = local_adv & (remote_adv >> 2);
1201 if (common & ADVERTISE_1000FULL) {
1202 bp->line_speed = SPEED_1000;
1203 bp->duplex = DUPLEX_FULL;
1204 }
1205 else if (common & ADVERTISE_1000HALF) {
1206 bp->line_speed = SPEED_1000;
1207 bp->duplex = DUPLEX_HALF;
1208 }
1209 else {
Michael Chanca58c3a2007-05-03 13:22:52 -07001210 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1211 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -07001212
1213 common = local_adv & remote_adv;
1214 if (common & ADVERTISE_100FULL) {
1215 bp->line_speed = SPEED_100;
1216 bp->duplex = DUPLEX_FULL;
1217 }
1218 else if (common & ADVERTISE_100HALF) {
1219 bp->line_speed = SPEED_100;
1220 bp->duplex = DUPLEX_HALF;
1221 }
1222 else if (common & ADVERTISE_10FULL) {
1223 bp->line_speed = SPEED_10;
1224 bp->duplex = DUPLEX_FULL;
1225 }
1226 else if (common & ADVERTISE_10HALF) {
1227 bp->line_speed = SPEED_10;
1228 bp->duplex = DUPLEX_HALF;
1229 }
1230 else {
1231 bp->line_speed = 0;
1232 bp->link_up = 0;
1233 }
1234 }
1235 }
1236 else {
1237 if (bmcr & BMCR_SPEED100) {
1238 bp->line_speed = SPEED_100;
1239 }
1240 else {
1241 bp->line_speed = SPEED_10;
1242 }
1243 if (bmcr & BMCR_FULLDPLX) {
1244 bp->duplex = DUPLEX_FULL;
1245 }
1246 else {
1247 bp->duplex = DUPLEX_HALF;
1248 }
1249 }
1250
1251 return 0;
1252}
1253
Michael Chan83e3fc82008-01-29 21:37:17 -08001254static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07001255bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
Michael Chan83e3fc82008-01-29 21:37:17 -08001256{
Michael Chanbb4f98a2008-06-19 16:38:19 -07001257 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
Michael Chan83e3fc82008-01-29 21:37:17 -08001258
1259 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1260 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1261 val |= 0x02 << 8;
1262
1263 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1264 u32 lo_water, hi_water;
1265
1266 if (bp->flow_ctrl & FLOW_CTRL_TX)
1267 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1268 else
1269 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1270 if (lo_water >= bp->rx_ring_size)
1271 lo_water = 0;
1272
1273 hi_water = bp->rx_ring_size / 4;
1274
1275 if (hi_water <= lo_water)
1276 lo_water = 0;
1277
1278 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1279 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1280
1281 if (hi_water > 0xf)
1282 hi_water = 0xf;
1283 else if (hi_water == 0)
1284 lo_water = 0;
1285 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1286 }
1287 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1288}
1289
Michael Chanbb4f98a2008-06-19 16:38:19 -07001290static void
1291bnx2_init_all_rx_contexts(struct bnx2 *bp)
1292{
1293 int i;
1294 u32 cid;
1295
1296 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1297 if (i == 1)
1298 cid = RX_RSS_CID;
1299 bnx2_init_rx_context(bp, cid);
1300 }
1301}
1302
Benjamin Li344478d2008-09-18 16:38:24 -07001303static void
Michael Chanb6016b72005-05-26 13:03:09 -07001304bnx2_set_mac_link(struct bnx2 *bp)
1305{
1306 u32 val;
1307
1308 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1309 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1310 (bp->duplex == DUPLEX_HALF)) {
1311 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1312 }
1313
1314 /* Configure the EMAC mode register. */
1315 val = REG_RD(bp, BNX2_EMAC_MODE);
1316
1317 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
Michael Chan5b0c76a2005-11-04 08:45:49 -08001318 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
Michael Chan59b47d82006-11-19 14:10:45 -08001319 BNX2_EMAC_MODE_25G_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -07001320
1321 if (bp->link_up) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001322 switch (bp->line_speed) {
1323 case SPEED_10:
Michael Chan59b47d82006-11-19 14:10:45 -08001324 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1325 val |= BNX2_EMAC_MODE_PORT_MII_10M;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001326 break;
1327 }
1328 /* fall through */
1329 case SPEED_100:
1330 val |= BNX2_EMAC_MODE_PORT_MII;
1331 break;
1332 case SPEED_2500:
Michael Chan59b47d82006-11-19 14:10:45 -08001333 val |= BNX2_EMAC_MODE_25G_MODE;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001334 /* fall through */
1335 case SPEED_1000:
1336 val |= BNX2_EMAC_MODE_PORT_GMII;
1337 break;
1338 }
Michael Chanb6016b72005-05-26 13:03:09 -07001339 }
1340 else {
1341 val |= BNX2_EMAC_MODE_PORT_GMII;
1342 }
1343
1344 /* Set the MAC to operate in the appropriate duplex mode. */
1345 if (bp->duplex == DUPLEX_HALF)
1346 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1347 REG_WR(bp, BNX2_EMAC_MODE, val);
1348
1349 /* Enable/disable rx PAUSE. */
1350 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1351
1352 if (bp->flow_ctrl & FLOW_CTRL_RX)
1353 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1354 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1355
1356 /* Enable/disable tx PAUSE. */
1357 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1358 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1359
1360 if (bp->flow_ctrl & FLOW_CTRL_TX)
1361 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1362 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1363
1364 /* Acknowledge the interrupt. */
1365 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1366
Michael Chan83e3fc82008-01-29 21:37:17 -08001367 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chanbb4f98a2008-06-19 16:38:19 -07001368 bnx2_init_all_rx_contexts(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001369}
1370
Michael Chan27a005b2007-05-03 13:23:41 -07001371static void
1372bnx2_enable_bmsr1(struct bnx2 *bp)
1373{
Michael Chan583c28e2008-01-21 19:51:35 -08001374 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan27a005b2007-05-03 13:23:41 -07001375 (CHIP_NUM(bp) == CHIP_NUM_5709))
1376 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1377 MII_BNX2_BLK_ADDR_GP_STATUS);
1378}
1379
1380static void
1381bnx2_disable_bmsr1(struct bnx2 *bp)
1382{
Michael Chan583c28e2008-01-21 19:51:35 -08001383 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan27a005b2007-05-03 13:23:41 -07001384 (CHIP_NUM(bp) == CHIP_NUM_5709))
1385 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1386 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1387}
1388
Michael Chanb6016b72005-05-26 13:03:09 -07001389static int
Michael Chan605a9e22007-05-03 13:23:13 -07001390bnx2_test_and_enable_2g5(struct bnx2 *bp)
1391{
1392 u32 up1;
1393 int ret = 1;
1394
Michael Chan583c28e2008-01-21 19:51:35 -08001395 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001396 return 0;
1397
1398 if (bp->autoneg & AUTONEG_SPEED)
1399 bp->advertising |= ADVERTISED_2500baseX_Full;
1400
Michael Chan27a005b2007-05-03 13:23:41 -07001401 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1402 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1403
Michael Chan605a9e22007-05-03 13:23:13 -07001404 bnx2_read_phy(bp, bp->mii_up1, &up1);
1405 if (!(up1 & BCM5708S_UP1_2G5)) {
1406 up1 |= BCM5708S_UP1_2G5;
1407 bnx2_write_phy(bp, bp->mii_up1, up1);
1408 ret = 0;
1409 }
1410
Michael Chan27a005b2007-05-03 13:23:41 -07001411 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1412 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1413 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1414
Michael Chan605a9e22007-05-03 13:23:13 -07001415 return ret;
1416}
1417
1418static int
1419bnx2_test_and_disable_2g5(struct bnx2 *bp)
1420{
1421 u32 up1;
1422 int ret = 0;
1423
Michael Chan583c28e2008-01-21 19:51:35 -08001424 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001425 return 0;
1426
Michael Chan27a005b2007-05-03 13:23:41 -07001427 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1428 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1429
Michael Chan605a9e22007-05-03 13:23:13 -07001430 bnx2_read_phy(bp, bp->mii_up1, &up1);
1431 if (up1 & BCM5708S_UP1_2G5) {
1432 up1 &= ~BCM5708S_UP1_2G5;
1433 bnx2_write_phy(bp, bp->mii_up1, up1);
1434 ret = 1;
1435 }
1436
Michael Chan27a005b2007-05-03 13:23:41 -07001437 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1438 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1439 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1440
Michael Chan605a9e22007-05-03 13:23:13 -07001441 return ret;
1442}
1443
1444static void
1445bnx2_enable_forced_2g5(struct bnx2 *bp)
1446{
1447 u32 bmcr;
1448
Michael Chan583c28e2008-01-21 19:51:35 -08001449 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001450 return;
1451
Michael Chan27a005b2007-05-03 13:23:41 -07001452 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1453 u32 val;
1454
1455 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1456 MII_BNX2_BLK_ADDR_SERDES_DIG);
1457 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1458 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1459 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1460 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1461
1462 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1463 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1464 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1465
1466 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001467 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1468 bmcr |= BCM5708S_BMCR_FORCE_2500;
Eric Dumazetc7079852009-11-02 23:17:42 +00001469 } else {
1470 return;
Michael Chan605a9e22007-05-03 13:23:13 -07001471 }
1472
1473 if (bp->autoneg & AUTONEG_SPEED) {
1474 bmcr &= ~BMCR_ANENABLE;
1475 if (bp->req_duplex == DUPLEX_FULL)
1476 bmcr |= BMCR_FULLDPLX;
1477 }
1478 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1479}
1480
1481static void
1482bnx2_disable_forced_2g5(struct bnx2 *bp)
1483{
1484 u32 bmcr;
1485
Michael Chan583c28e2008-01-21 19:51:35 -08001486 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001487 return;
1488
Michael Chan27a005b2007-05-03 13:23:41 -07001489 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1490 u32 val;
1491
1492 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1493 MII_BNX2_BLK_ADDR_SERDES_DIG);
1494 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1495 val &= ~MII_BNX2_SD_MISC1_FORCE;
1496 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1497
1498 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1499 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1500 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1501
1502 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001503 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1504 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
Eric Dumazetc7079852009-11-02 23:17:42 +00001505 } else {
1506 return;
Michael Chan605a9e22007-05-03 13:23:13 -07001507 }
1508
1509 if (bp->autoneg & AUTONEG_SPEED)
1510 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1511 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1512}
1513
Michael Chanb2fadea2008-01-21 17:07:06 -08001514static void
1515bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1516{
1517 u32 val;
1518
1519 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1520 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1521 if (start)
1522 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1523 else
1524 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1525}
1526
Michael Chan605a9e22007-05-03 13:23:13 -07001527static int
Michael Chanb6016b72005-05-26 13:03:09 -07001528bnx2_set_link(struct bnx2 *bp)
1529{
1530 u32 bmsr;
1531 u8 link_up;
1532
Michael Chan80be4432006-11-19 14:07:28 -08001533 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
Michael Chanb6016b72005-05-26 13:03:09 -07001534 bp->link_up = 1;
1535 return 0;
1536 }
1537
Michael Chan583c28e2008-01-21 19:51:35 -08001538 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07001539 return 0;
1540
Michael Chanb6016b72005-05-26 13:03:09 -07001541 link_up = bp->link_up;
1542
Michael Chan27a005b2007-05-03 13:23:41 -07001543 bnx2_enable_bmsr1(bp);
1544 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1545 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1546 bnx2_disable_bmsr1(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001547
Michael Chan583c28e2008-01-21 19:51:35 -08001548 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chanb6016b72005-05-26 13:03:09 -07001549 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
Michael Chana2724e22008-02-23 19:47:44 -08001550 u32 val, an_dbg;
Michael Chanb6016b72005-05-26 13:03:09 -07001551
Michael Chan583c28e2008-01-21 19:51:35 -08001552 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
Michael Chanb2fadea2008-01-21 17:07:06 -08001553 bnx2_5706s_force_link_dn(bp, 0);
Michael Chan583c28e2008-01-21 19:51:35 -08001554 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
Michael Chanb2fadea2008-01-21 17:07:06 -08001555 }
Michael Chanb6016b72005-05-26 13:03:09 -07001556 val = REG_RD(bp, BNX2_EMAC_STATUS);
Michael Chana2724e22008-02-23 19:47:44 -08001557
1558 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1559 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1560 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1561
1562 if ((val & BNX2_EMAC_STATUS_LINK) &&
1563 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
Michael Chanb6016b72005-05-26 13:03:09 -07001564 bmsr |= BMSR_LSTATUS;
1565 else
1566 bmsr &= ~BMSR_LSTATUS;
1567 }
1568
1569 if (bmsr & BMSR_LSTATUS) {
1570 bp->link_up = 1;
1571
Michael Chan583c28e2008-01-21 19:51:35 -08001572 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001573 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1574 bnx2_5706s_linkup(bp);
1575 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1576 bnx2_5708s_linkup(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07001577 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1578 bnx2_5709s_linkup(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001579 }
1580 else {
1581 bnx2_copper_linkup(bp);
1582 }
1583 bnx2_resolve_flow_ctrl(bp);
1584 }
1585 else {
Michael Chan583c28e2008-01-21 19:51:35 -08001586 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan605a9e22007-05-03 13:23:13 -07001587 (bp->autoneg & AUTONEG_SPEED))
1588 bnx2_disable_forced_2g5(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001589
Michael Chan583c28e2008-01-21 19:51:35 -08001590 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
Michael Chanb2fadea2008-01-21 17:07:06 -08001591 u32 bmcr;
1592
1593 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1594 bmcr |= BMCR_ANENABLE;
1595 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1596
Michael Chan583c28e2008-01-21 19:51:35 -08001597 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chanb2fadea2008-01-21 17:07:06 -08001598 }
Michael Chanb6016b72005-05-26 13:03:09 -07001599 bp->link_up = 0;
1600 }
1601
1602 if (bp->link_up != link_up) {
1603 bnx2_report_link(bp);
1604 }
1605
1606 bnx2_set_mac_link(bp);
1607
1608 return 0;
1609}
1610
1611static int
1612bnx2_reset_phy(struct bnx2 *bp)
1613{
1614 int i;
1615 u32 reg;
1616
Michael Chanca58c3a2007-05-03 13:22:52 -07001617 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
Michael Chanb6016b72005-05-26 13:03:09 -07001618
1619#define PHY_RESET_MAX_WAIT 100
1620 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1621 udelay(10);
1622
Michael Chanca58c3a2007-05-03 13:22:52 -07001623 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
Michael Chanb6016b72005-05-26 13:03:09 -07001624 if (!(reg & BMCR_RESET)) {
1625 udelay(20);
1626 break;
1627 }
1628 }
1629 if (i == PHY_RESET_MAX_WAIT) {
1630 return -EBUSY;
1631 }
1632 return 0;
1633}
1634
1635static u32
1636bnx2_phy_get_pause_adv(struct bnx2 *bp)
1637{
1638 u32 adv = 0;
1639
1640 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1641 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1642
Michael Chan583c28e2008-01-21 19:51:35 -08001643 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001644 adv = ADVERTISE_1000XPAUSE;
1645 }
1646 else {
1647 adv = ADVERTISE_PAUSE_CAP;
1648 }
1649 }
1650 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
Michael Chan583c28e2008-01-21 19:51:35 -08001651 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001652 adv = ADVERTISE_1000XPSE_ASYM;
1653 }
1654 else {
1655 adv = ADVERTISE_PAUSE_ASYM;
1656 }
1657 }
1658 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
Michael Chan583c28e2008-01-21 19:51:35 -08001659 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001660 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1661 }
1662 else {
1663 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1664 }
1665 }
1666 return adv;
1667}
1668
Michael Chana2f13892008-07-14 22:38:23 -07001669static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
Michael Chan0d8a6572007-07-07 22:49:43 -07001670
Michael Chanb6016b72005-05-26 13:03:09 -07001671static int
Michael Chan0d8a6572007-07-07 22:49:43 -07001672bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
Harvey Harrison52d07b12009-01-19 17:27:06 -08001673__releases(&bp->phy_lock)
1674__acquires(&bp->phy_lock)
Michael Chan0d8a6572007-07-07 22:49:43 -07001675{
1676 u32 speed_arg = 0, pause_adv;
1677
1678 pause_adv = bnx2_phy_get_pause_adv(bp);
1679
1680 if (bp->autoneg & AUTONEG_SPEED) {
1681 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1682 if (bp->advertising & ADVERTISED_10baseT_Half)
1683 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1684 if (bp->advertising & ADVERTISED_10baseT_Full)
1685 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1686 if (bp->advertising & ADVERTISED_100baseT_Half)
1687 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1688 if (bp->advertising & ADVERTISED_100baseT_Full)
1689 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1690 if (bp->advertising & ADVERTISED_1000baseT_Full)
1691 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1692 if (bp->advertising & ADVERTISED_2500baseX_Full)
1693 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1694 } else {
1695 if (bp->req_line_speed == SPEED_2500)
1696 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1697 else if (bp->req_line_speed == SPEED_1000)
1698 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1699 else if (bp->req_line_speed == SPEED_100) {
1700 if (bp->req_duplex == DUPLEX_FULL)
1701 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1702 else
1703 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1704 } else if (bp->req_line_speed == SPEED_10) {
1705 if (bp->req_duplex == DUPLEX_FULL)
1706 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1707 else
1708 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1709 }
1710 }
1711
1712 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1713 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
Michael Chanc26736e2008-01-31 17:07:21 -08001714 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
Michael Chan0d8a6572007-07-07 22:49:43 -07001715 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1716
1717 if (port == PORT_TP)
1718 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1719 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1720
Michael Chan2726d6e2008-01-29 21:35:05 -08001721 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
Michael Chan0d8a6572007-07-07 22:49:43 -07001722
1723 spin_unlock_bh(&bp->phy_lock);
Michael Chana2f13892008-07-14 22:38:23 -07001724 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
Michael Chan0d8a6572007-07-07 22:49:43 -07001725 spin_lock_bh(&bp->phy_lock);
1726
1727 return 0;
1728}
1729
1730static int
1731bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
Harvey Harrison52d07b12009-01-19 17:27:06 -08001732__releases(&bp->phy_lock)
1733__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07001734{
Michael Chan605a9e22007-05-03 13:23:13 -07001735 u32 adv, bmcr;
Michael Chanb6016b72005-05-26 13:03:09 -07001736 u32 new_adv = 0;
1737
Michael Chan583c28e2008-01-21 19:51:35 -08001738 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07001739 return (bnx2_setup_remote_phy(bp, port));
1740
Michael Chanb6016b72005-05-26 13:03:09 -07001741 if (!(bp->autoneg & AUTONEG_SPEED)) {
1742 u32 new_bmcr;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001743 int force_link_down = 0;
1744
Michael Chan605a9e22007-05-03 13:23:13 -07001745 if (bp->req_line_speed == SPEED_2500) {
1746 if (!bnx2_test_and_enable_2g5(bp))
1747 force_link_down = 1;
1748 } else if (bp->req_line_speed == SPEED_1000) {
1749 if (bnx2_test_and_disable_2g5(bp))
1750 force_link_down = 1;
1751 }
Michael Chanca58c3a2007-05-03 13:22:52 -07001752 bnx2_read_phy(bp, bp->mii_adv, &adv);
Michael Chan80be4432006-11-19 14:07:28 -08001753 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1754
Michael Chanca58c3a2007-05-03 13:22:52 -07001755 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan605a9e22007-05-03 13:23:13 -07001756 new_bmcr = bmcr & ~BMCR_ANENABLE;
Michael Chan80be4432006-11-19 14:07:28 -08001757 new_bmcr |= BMCR_SPEED1000;
Michael Chan605a9e22007-05-03 13:23:13 -07001758
Michael Chan27a005b2007-05-03 13:23:41 -07001759 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1760 if (bp->req_line_speed == SPEED_2500)
1761 bnx2_enable_forced_2g5(bp);
1762 else if (bp->req_line_speed == SPEED_1000) {
1763 bnx2_disable_forced_2g5(bp);
1764 new_bmcr &= ~0x2000;
1765 }
1766
1767 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001768 if (bp->req_line_speed == SPEED_2500)
1769 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1770 else
1771 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001772 }
1773
Michael Chanb6016b72005-05-26 13:03:09 -07001774 if (bp->req_duplex == DUPLEX_FULL) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001775 adv |= ADVERTISE_1000XFULL;
Michael Chanb6016b72005-05-26 13:03:09 -07001776 new_bmcr |= BMCR_FULLDPLX;
1777 }
1778 else {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001779 adv |= ADVERTISE_1000XHALF;
Michael Chanb6016b72005-05-26 13:03:09 -07001780 new_bmcr &= ~BMCR_FULLDPLX;
1781 }
Michael Chan5b0c76a2005-11-04 08:45:49 -08001782 if ((new_bmcr != bmcr) || (force_link_down)) {
Michael Chanb6016b72005-05-26 13:03:09 -07001783 /* Force a link down visible on the other side */
1784 if (bp->link_up) {
Michael Chanca58c3a2007-05-03 13:22:52 -07001785 bnx2_write_phy(bp, bp->mii_adv, adv &
Michael Chan5b0c76a2005-11-04 08:45:49 -08001786 ~(ADVERTISE_1000XFULL |
1787 ADVERTISE_1000XHALF));
Michael Chanca58c3a2007-05-03 13:22:52 -07001788 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
Michael Chanb6016b72005-05-26 13:03:09 -07001789 BMCR_ANRESTART | BMCR_ANENABLE);
1790
1791 bp->link_up = 0;
1792 netif_carrier_off(bp->dev);
Michael Chanca58c3a2007-05-03 13:22:52 -07001793 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chan80be4432006-11-19 14:07:28 -08001794 bnx2_report_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001795 }
Michael Chanca58c3a2007-05-03 13:22:52 -07001796 bnx2_write_phy(bp, bp->mii_adv, adv);
1797 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chan605a9e22007-05-03 13:23:13 -07001798 } else {
1799 bnx2_resolve_flow_ctrl(bp);
1800 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001801 }
1802 return 0;
1803 }
1804
Michael Chan605a9e22007-05-03 13:23:13 -07001805 bnx2_test_and_enable_2g5(bp);
Michael Chan5b0c76a2005-11-04 08:45:49 -08001806
Michael Chanb6016b72005-05-26 13:03:09 -07001807 if (bp->advertising & ADVERTISED_1000baseT_Full)
1808 new_adv |= ADVERTISE_1000XFULL;
1809
1810 new_adv |= bnx2_phy_get_pause_adv(bp);
1811
Michael Chanca58c3a2007-05-03 13:22:52 -07001812 bnx2_read_phy(bp, bp->mii_adv, &adv);
1813 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001814
1815 bp->serdes_an_pending = 0;
1816 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1817 /* Force a link down visible on the other side */
1818 if (bp->link_up) {
Michael Chanca58c3a2007-05-03 13:22:52 -07001819 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chan80be4432006-11-19 14:07:28 -08001820 spin_unlock_bh(&bp->phy_lock);
1821 msleep(20);
1822 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07001823 }
1824
Michael Chanca58c3a2007-05-03 13:22:52 -07001825 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1826 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
Michael Chanb6016b72005-05-26 13:03:09 -07001827 BMCR_ANENABLE);
Michael Chanf8dd0642006-11-19 14:08:29 -08001828 /* Speed up link-up time when the link partner
1829 * does not autonegotiate which is very common
1830 * in blade servers. Some blade servers use
1831 * IPMI for kerboard input and it's important
1832 * to minimize link disruptions. Autoneg. involves
1833 * exchanging base pages plus 3 next pages and
1834 * normally completes in about 120 msec.
1835 */
Michael Chan40105c02008-11-12 16:02:45 -08001836 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
Michael Chanf8dd0642006-11-19 14:08:29 -08001837 bp->serdes_an_pending = 1;
1838 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chan605a9e22007-05-03 13:23:13 -07001839 } else {
1840 bnx2_resolve_flow_ctrl(bp);
1841 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001842 }
1843
1844 return 0;
1845}
1846
1847#define ETHTOOL_ALL_FIBRE_SPEED \
Michael Chan583c28e2008-01-21 19:51:35 -08001848 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
Michael Chandeaf3912007-07-07 22:48:00 -07001849 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1850 (ADVERTISED_1000baseT_Full)
Michael Chanb6016b72005-05-26 13:03:09 -07001851
1852#define ETHTOOL_ALL_COPPER_SPEED \
1853 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1854 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1855 ADVERTISED_1000baseT_Full)
1856
1857#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1858 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001859
Michael Chanb6016b72005-05-26 13:03:09 -07001860#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1861
Michael Chandeaf3912007-07-07 22:48:00 -07001862static void
Michael Chan0d8a6572007-07-07 22:49:43 -07001863bnx2_set_default_remote_link(struct bnx2 *bp)
1864{
1865 u32 link;
1866
1867 if (bp->phy_port == PORT_TP)
Michael Chan2726d6e2008-01-29 21:35:05 -08001868 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
Michael Chan0d8a6572007-07-07 22:49:43 -07001869 else
Michael Chan2726d6e2008-01-29 21:35:05 -08001870 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
Michael Chan0d8a6572007-07-07 22:49:43 -07001871
1872 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1873 bp->req_line_speed = 0;
1874 bp->autoneg |= AUTONEG_SPEED;
1875 bp->advertising = ADVERTISED_Autoneg;
1876 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1877 bp->advertising |= ADVERTISED_10baseT_Half;
1878 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1879 bp->advertising |= ADVERTISED_10baseT_Full;
1880 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1881 bp->advertising |= ADVERTISED_100baseT_Half;
1882 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1883 bp->advertising |= ADVERTISED_100baseT_Full;
1884 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1885 bp->advertising |= ADVERTISED_1000baseT_Full;
1886 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1887 bp->advertising |= ADVERTISED_2500baseX_Full;
1888 } else {
1889 bp->autoneg = 0;
1890 bp->advertising = 0;
1891 bp->req_duplex = DUPLEX_FULL;
1892 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1893 bp->req_line_speed = SPEED_10;
1894 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1895 bp->req_duplex = DUPLEX_HALF;
1896 }
1897 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1898 bp->req_line_speed = SPEED_100;
1899 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1900 bp->req_duplex = DUPLEX_HALF;
1901 }
1902 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1903 bp->req_line_speed = SPEED_1000;
1904 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1905 bp->req_line_speed = SPEED_2500;
1906 }
1907}
1908
1909static void
Michael Chandeaf3912007-07-07 22:48:00 -07001910bnx2_set_default_link(struct bnx2 *bp)
1911{
Harvey Harrisonab598592008-05-01 02:47:38 -07001912 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1913 bnx2_set_default_remote_link(bp);
1914 return;
1915 }
Michael Chan0d8a6572007-07-07 22:49:43 -07001916
Michael Chandeaf3912007-07-07 22:48:00 -07001917 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1918 bp->req_line_speed = 0;
Michael Chan583c28e2008-01-21 19:51:35 -08001919 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chandeaf3912007-07-07 22:48:00 -07001920 u32 reg;
1921
1922 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1923
Michael Chan2726d6e2008-01-29 21:35:05 -08001924 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
Michael Chandeaf3912007-07-07 22:48:00 -07001925 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1926 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1927 bp->autoneg = 0;
1928 bp->req_line_speed = bp->line_speed = SPEED_1000;
1929 bp->req_duplex = DUPLEX_FULL;
1930 }
1931 } else
1932 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1933}
1934
Michael Chan0d8a6572007-07-07 22:49:43 -07001935static void
Michael Chandf149d72007-07-07 22:51:36 -07001936bnx2_send_heart_beat(struct bnx2 *bp)
1937{
1938 u32 msg;
1939 u32 addr;
1940
1941 spin_lock(&bp->indirect_lock);
1942 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1943 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1944 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1945 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1946 spin_unlock(&bp->indirect_lock);
1947}
1948
1949static void
Michael Chan0d8a6572007-07-07 22:49:43 -07001950bnx2_remote_phy_event(struct bnx2 *bp)
1951{
1952 u32 msg;
1953 u8 link_up = bp->link_up;
1954 u8 old_port;
1955
Michael Chan2726d6e2008-01-29 21:35:05 -08001956 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
Michael Chan0d8a6572007-07-07 22:49:43 -07001957
Michael Chandf149d72007-07-07 22:51:36 -07001958 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1959 bnx2_send_heart_beat(bp);
1960
1961 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1962
Michael Chan0d8a6572007-07-07 22:49:43 -07001963 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1964 bp->link_up = 0;
1965 else {
1966 u32 speed;
1967
1968 bp->link_up = 1;
1969 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1970 bp->duplex = DUPLEX_FULL;
1971 switch (speed) {
1972 case BNX2_LINK_STATUS_10HALF:
1973 bp->duplex = DUPLEX_HALF;
1974 case BNX2_LINK_STATUS_10FULL:
1975 bp->line_speed = SPEED_10;
1976 break;
1977 case BNX2_LINK_STATUS_100HALF:
1978 bp->duplex = DUPLEX_HALF;
1979 case BNX2_LINK_STATUS_100BASE_T4:
1980 case BNX2_LINK_STATUS_100FULL:
1981 bp->line_speed = SPEED_100;
1982 break;
1983 case BNX2_LINK_STATUS_1000HALF:
1984 bp->duplex = DUPLEX_HALF;
1985 case BNX2_LINK_STATUS_1000FULL:
1986 bp->line_speed = SPEED_1000;
1987 break;
1988 case BNX2_LINK_STATUS_2500HALF:
1989 bp->duplex = DUPLEX_HALF;
1990 case BNX2_LINK_STATUS_2500FULL:
1991 bp->line_speed = SPEED_2500;
1992 break;
1993 default:
1994 bp->line_speed = 0;
1995 break;
1996 }
1997
Michael Chan0d8a6572007-07-07 22:49:43 -07001998 bp->flow_ctrl = 0;
1999 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2000 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2001 if (bp->duplex == DUPLEX_FULL)
2002 bp->flow_ctrl = bp->req_flow_ctrl;
2003 } else {
2004 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2005 bp->flow_ctrl |= FLOW_CTRL_TX;
2006 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2007 bp->flow_ctrl |= FLOW_CTRL_RX;
2008 }
2009
2010 old_port = bp->phy_port;
2011 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2012 bp->phy_port = PORT_FIBRE;
2013 else
2014 bp->phy_port = PORT_TP;
2015
2016 if (old_port != bp->phy_port)
2017 bnx2_set_default_link(bp);
2018
Michael Chan0d8a6572007-07-07 22:49:43 -07002019 }
2020 if (bp->link_up != link_up)
2021 bnx2_report_link(bp);
2022
2023 bnx2_set_mac_link(bp);
2024}
2025
2026static int
2027bnx2_set_remote_link(struct bnx2 *bp)
2028{
2029 u32 evt_code;
2030
Michael Chan2726d6e2008-01-29 21:35:05 -08002031 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
Michael Chan0d8a6572007-07-07 22:49:43 -07002032 switch (evt_code) {
2033 case BNX2_FW_EVT_CODE_LINK_EVENT:
2034 bnx2_remote_phy_event(bp);
2035 break;
2036 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2037 default:
Michael Chandf149d72007-07-07 22:51:36 -07002038 bnx2_send_heart_beat(bp);
Michael Chan0d8a6572007-07-07 22:49:43 -07002039 break;
2040 }
2041 return 0;
2042}
2043
Michael Chanb6016b72005-05-26 13:03:09 -07002044static int
2045bnx2_setup_copper_phy(struct bnx2 *bp)
Harvey Harrison52d07b12009-01-19 17:27:06 -08002046__releases(&bp->phy_lock)
2047__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07002048{
2049 u32 bmcr;
2050 u32 new_bmcr;
2051
Michael Chanca58c3a2007-05-03 13:22:52 -07002052 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07002053
2054 if (bp->autoneg & AUTONEG_SPEED) {
2055 u32 adv_reg, adv1000_reg;
2056 u32 new_adv_reg = 0;
2057 u32 new_adv1000_reg = 0;
2058
Michael Chanca58c3a2007-05-03 13:22:52 -07002059 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
Michael Chanb6016b72005-05-26 13:03:09 -07002060 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2061 ADVERTISE_PAUSE_ASYM);
2062
2063 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2064 adv1000_reg &= PHY_ALL_1000_SPEED;
2065
2066 if (bp->advertising & ADVERTISED_10baseT_Half)
2067 new_adv_reg |= ADVERTISE_10HALF;
2068 if (bp->advertising & ADVERTISED_10baseT_Full)
2069 new_adv_reg |= ADVERTISE_10FULL;
2070 if (bp->advertising & ADVERTISED_100baseT_Half)
2071 new_adv_reg |= ADVERTISE_100HALF;
2072 if (bp->advertising & ADVERTISED_100baseT_Full)
2073 new_adv_reg |= ADVERTISE_100FULL;
2074 if (bp->advertising & ADVERTISED_1000baseT_Full)
2075 new_adv1000_reg |= ADVERTISE_1000FULL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002076
Michael Chanb6016b72005-05-26 13:03:09 -07002077 new_adv_reg |= ADVERTISE_CSMA;
2078
2079 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2080
2081 if ((adv1000_reg != new_adv1000_reg) ||
2082 (adv_reg != new_adv_reg) ||
2083 ((bmcr & BMCR_ANENABLE) == 0)) {
2084
Michael Chanca58c3a2007-05-03 13:22:52 -07002085 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
Michael Chanb6016b72005-05-26 13:03:09 -07002086 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
Michael Chanca58c3a2007-05-03 13:22:52 -07002087 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
Michael Chanb6016b72005-05-26 13:03:09 -07002088 BMCR_ANENABLE);
2089 }
2090 else if (bp->link_up) {
2091 /* Flow ctrl may have changed from auto to forced */
2092 /* or vice-versa. */
2093
2094 bnx2_resolve_flow_ctrl(bp);
2095 bnx2_set_mac_link(bp);
2096 }
2097 return 0;
2098 }
2099
2100 new_bmcr = 0;
2101 if (bp->req_line_speed == SPEED_100) {
2102 new_bmcr |= BMCR_SPEED100;
2103 }
2104 if (bp->req_duplex == DUPLEX_FULL) {
2105 new_bmcr |= BMCR_FULLDPLX;
2106 }
2107 if (new_bmcr != bmcr) {
2108 u32 bmsr;
Michael Chanb6016b72005-05-26 13:03:09 -07002109
Michael Chanca58c3a2007-05-03 13:22:52 -07002110 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2111 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002112
Michael Chanb6016b72005-05-26 13:03:09 -07002113 if (bmsr & BMSR_LSTATUS) {
2114 /* Force link down */
Michael Chanca58c3a2007-05-03 13:22:52 -07002115 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chana16dda02006-11-19 14:08:56 -08002116 spin_unlock_bh(&bp->phy_lock);
2117 msleep(50);
2118 spin_lock_bh(&bp->phy_lock);
2119
Michael Chanca58c3a2007-05-03 13:22:52 -07002120 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2121 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Michael Chanb6016b72005-05-26 13:03:09 -07002122 }
2123
Michael Chanca58c3a2007-05-03 13:22:52 -07002124 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07002125
2126 /* Normally, the new speed is setup after the link has
2127 * gone down and up again. In some cases, link will not go
2128 * down so we need to set up the new speed here.
2129 */
2130 if (bmsr & BMSR_LSTATUS) {
2131 bp->line_speed = bp->req_line_speed;
2132 bp->duplex = bp->req_duplex;
2133 bnx2_resolve_flow_ctrl(bp);
2134 bnx2_set_mac_link(bp);
2135 }
Michael Chan27a005b2007-05-03 13:23:41 -07002136 } else {
2137 bnx2_resolve_flow_ctrl(bp);
2138 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07002139 }
2140 return 0;
2141}
2142
2143static int
Michael Chan0d8a6572007-07-07 22:49:43 -07002144bnx2_setup_phy(struct bnx2 *bp, u8 port)
Harvey Harrison52d07b12009-01-19 17:27:06 -08002145__releases(&bp->phy_lock)
2146__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07002147{
2148 if (bp->loopback == MAC_LOOPBACK)
2149 return 0;
2150
Michael Chan583c28e2008-01-21 19:51:35 -08002151 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan0d8a6572007-07-07 22:49:43 -07002152 return (bnx2_setup_serdes_phy(bp, port));
Michael Chanb6016b72005-05-26 13:03:09 -07002153 }
2154 else {
2155 return (bnx2_setup_copper_phy(bp));
2156 }
2157}
2158
2159static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002160bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
Michael Chan27a005b2007-05-03 13:23:41 -07002161{
2162 u32 val;
2163
2164 bp->mii_bmcr = MII_BMCR + 0x10;
2165 bp->mii_bmsr = MII_BMSR + 0x10;
2166 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2167 bp->mii_adv = MII_ADVERTISE + 0x10;
2168 bp->mii_lpa = MII_LPA + 0x10;
2169 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2170
2171 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2172 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2173
2174 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
Michael Chan9a120bc2008-05-16 22:17:45 -07002175 if (reset_phy)
2176 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002177
2178 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2179
2180 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2181 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2182 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2183 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2184
2185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2186 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
Michael Chan583c28e2008-01-21 19:51:35 -08002187 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
Michael Chan27a005b2007-05-03 13:23:41 -07002188 val |= BCM5708S_UP1_2G5;
2189 else
2190 val &= ~BCM5708S_UP1_2G5;
2191 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2192
2193 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2194 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2195 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2196 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2197
2198 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2199
2200 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2201 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2202 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2203
2204 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2205
2206 return 0;
2207}
2208
2209static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002210bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
Michael Chan5b0c76a2005-11-04 08:45:49 -08002211{
2212 u32 val;
2213
Michael Chan9a120bc2008-05-16 22:17:45 -07002214 if (reset_phy)
2215 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002216
2217 bp->mii_up1 = BCM5708S_UP1;
2218
Michael Chan5b0c76a2005-11-04 08:45:49 -08002219 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2220 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2221 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2222
2223 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2224 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2225 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2226
2227 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2228 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2229 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2230
Michael Chan583c28e2008-01-21 19:51:35 -08002231 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002232 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2233 val |= BCM5708S_UP1_2G5;
2234 bnx2_write_phy(bp, BCM5708S_UP1, val);
2235 }
2236
2237 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
Michael Chandda1e392006-01-23 16:08:14 -08002238 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2239 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002240 /* increase tx signal amplitude */
2241 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2242 BCM5708S_BLK_ADDR_TX_MISC);
2243 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2244 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2245 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2246 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2247 }
2248
Michael Chan2726d6e2008-01-29 21:35:05 -08002249 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
Michael Chan5b0c76a2005-11-04 08:45:49 -08002250 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2251
2252 if (val) {
2253 u32 is_backplane;
2254
Michael Chan2726d6e2008-01-29 21:35:05 -08002255 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
Michael Chan5b0c76a2005-11-04 08:45:49 -08002256 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2257 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2258 BCM5708S_BLK_ADDR_TX_MISC);
2259 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2260 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2261 BCM5708S_BLK_ADDR_DIG);
2262 }
2263 }
2264 return 0;
2265}
2266
2267static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002268bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07002269{
Michael Chan9a120bc2008-05-16 22:17:45 -07002270 if (reset_phy)
2271 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002272
Michael Chan583c28e2008-01-21 19:51:35 -08002273 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chanb6016b72005-05-26 13:03:09 -07002274
Michael Chan59b47d82006-11-19 14:10:45 -08002275 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2276 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
Michael Chanb6016b72005-05-26 13:03:09 -07002277
2278 if (bp->dev->mtu > 1500) {
2279 u32 val;
2280
2281 /* Set extended packet length bit */
2282 bnx2_write_phy(bp, 0x18, 0x7);
2283 bnx2_read_phy(bp, 0x18, &val);
2284 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2285
2286 bnx2_write_phy(bp, 0x1c, 0x6c00);
2287 bnx2_read_phy(bp, 0x1c, &val);
2288 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2289 }
2290 else {
2291 u32 val;
2292
2293 bnx2_write_phy(bp, 0x18, 0x7);
2294 bnx2_read_phy(bp, 0x18, &val);
2295 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2296
2297 bnx2_write_phy(bp, 0x1c, 0x6c00);
2298 bnx2_read_phy(bp, 0x1c, &val);
2299 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2300 }
2301
2302 return 0;
2303}
2304
2305static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002306bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07002307{
Michael Chan5b0c76a2005-11-04 08:45:49 -08002308 u32 val;
2309
Michael Chan9a120bc2008-05-16 22:17:45 -07002310 if (reset_phy)
2311 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002312
Michael Chan583c28e2008-01-21 19:51:35 -08002313 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
Michael Chanb6016b72005-05-26 13:03:09 -07002314 bnx2_write_phy(bp, 0x18, 0x0c00);
2315 bnx2_write_phy(bp, 0x17, 0x000a);
2316 bnx2_write_phy(bp, 0x15, 0x310b);
2317 bnx2_write_phy(bp, 0x17, 0x201f);
2318 bnx2_write_phy(bp, 0x15, 0x9506);
2319 bnx2_write_phy(bp, 0x17, 0x401f);
2320 bnx2_write_phy(bp, 0x15, 0x14e2);
2321 bnx2_write_phy(bp, 0x18, 0x0400);
2322 }
2323
Michael Chan583c28e2008-01-21 19:51:35 -08002324 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
Michael Chanb659f442007-02-02 00:46:35 -08002325 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2326 MII_BNX2_DSP_EXPAND_REG | 0x8);
2327 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2328 val &= ~(1 << 8);
2329 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2330 }
2331
Michael Chanb6016b72005-05-26 13:03:09 -07002332 if (bp->dev->mtu > 1500) {
Michael Chanb6016b72005-05-26 13:03:09 -07002333 /* Set extended packet length bit */
2334 bnx2_write_phy(bp, 0x18, 0x7);
2335 bnx2_read_phy(bp, 0x18, &val);
2336 bnx2_write_phy(bp, 0x18, val | 0x4000);
2337
2338 bnx2_read_phy(bp, 0x10, &val);
2339 bnx2_write_phy(bp, 0x10, val | 0x1);
2340 }
2341 else {
Michael Chanb6016b72005-05-26 13:03:09 -07002342 bnx2_write_phy(bp, 0x18, 0x7);
2343 bnx2_read_phy(bp, 0x18, &val);
2344 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2345
2346 bnx2_read_phy(bp, 0x10, &val);
2347 bnx2_write_phy(bp, 0x10, val & ~0x1);
2348 }
2349
Michael Chan5b0c76a2005-11-04 08:45:49 -08002350 /* ethernet@wirespeed */
2351 bnx2_write_phy(bp, 0x18, 0x7007);
2352 bnx2_read_phy(bp, 0x18, &val);
2353 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
Michael Chanb6016b72005-05-26 13:03:09 -07002354 return 0;
2355}
2356
2357
2358static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002359bnx2_init_phy(struct bnx2 *bp, int reset_phy)
Harvey Harrison52d07b12009-01-19 17:27:06 -08002360__releases(&bp->phy_lock)
2361__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07002362{
2363 u32 val;
2364 int rc = 0;
2365
Michael Chan583c28e2008-01-21 19:51:35 -08002366 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2367 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
Michael Chanb6016b72005-05-26 13:03:09 -07002368
Michael Chanca58c3a2007-05-03 13:22:52 -07002369 bp->mii_bmcr = MII_BMCR;
2370 bp->mii_bmsr = MII_BMSR;
Michael Chan27a005b2007-05-03 13:23:41 -07002371 bp->mii_bmsr1 = MII_BMSR;
Michael Chanca58c3a2007-05-03 13:22:52 -07002372 bp->mii_adv = MII_ADVERTISE;
2373 bp->mii_lpa = MII_LPA;
2374
Michael Chanb6016b72005-05-26 13:03:09 -07002375 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2376
Michael Chan583c28e2008-01-21 19:51:35 -08002377 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07002378 goto setup_phy;
2379
Michael Chanb6016b72005-05-26 13:03:09 -07002380 bnx2_read_phy(bp, MII_PHYSID1, &val);
2381 bp->phy_id = val << 16;
2382 bnx2_read_phy(bp, MII_PHYSID2, &val);
2383 bp->phy_id |= val & 0xffff;
2384
Michael Chan583c28e2008-01-21 19:51:35 -08002385 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002386 if (CHIP_NUM(bp) == CHIP_NUM_5706)
Michael Chan9a120bc2008-05-16 22:17:45 -07002387 rc = bnx2_init_5706s_phy(bp, reset_phy);
Michael Chan5b0c76a2005-11-04 08:45:49 -08002388 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
Michael Chan9a120bc2008-05-16 22:17:45 -07002389 rc = bnx2_init_5708s_phy(bp, reset_phy);
Michael Chan27a005b2007-05-03 13:23:41 -07002390 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chan9a120bc2008-05-16 22:17:45 -07002391 rc = bnx2_init_5709s_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07002392 }
2393 else {
Michael Chan9a120bc2008-05-16 22:17:45 -07002394 rc = bnx2_init_copper_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07002395 }
2396
Michael Chan0d8a6572007-07-07 22:49:43 -07002397setup_phy:
2398 if (!rc)
2399 rc = bnx2_setup_phy(bp, bp->phy_port);
Michael Chanb6016b72005-05-26 13:03:09 -07002400
2401 return rc;
2402}
2403
2404static int
2405bnx2_set_mac_loopback(struct bnx2 *bp)
2406{
2407 u32 mac_mode;
2408
2409 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2410 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2411 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2412 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2413 bp->link_up = 1;
2414 return 0;
2415}
2416
Michael Chanbc5a0692006-01-23 16:13:22 -08002417static int bnx2_test_link(struct bnx2 *);
2418
2419static int
2420bnx2_set_phy_loopback(struct bnx2 *bp)
2421{
2422 u32 mac_mode;
2423 int rc, i;
2424
2425 spin_lock_bh(&bp->phy_lock);
Michael Chanca58c3a2007-05-03 13:22:52 -07002426 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
Michael Chanbc5a0692006-01-23 16:13:22 -08002427 BMCR_SPEED1000);
2428 spin_unlock_bh(&bp->phy_lock);
2429 if (rc)
2430 return rc;
2431
2432 for (i = 0; i < 10; i++) {
2433 if (bnx2_test_link(bp) == 0)
2434 break;
Michael Chan80be4432006-11-19 14:07:28 -08002435 msleep(100);
Michael Chanbc5a0692006-01-23 16:13:22 -08002436 }
2437
2438 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2439 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2440 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
Michael Chan59b47d82006-11-19 14:10:45 -08002441 BNX2_EMAC_MODE_25G_MODE);
Michael Chanbc5a0692006-01-23 16:13:22 -08002442
2443 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2444 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2445 bp->link_up = 1;
2446 return 0;
2447}
2448
Michael Chanb6016b72005-05-26 13:03:09 -07002449static int
Michael Chana2f13892008-07-14 22:38:23 -07002450bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
Michael Chanb6016b72005-05-26 13:03:09 -07002451{
2452 int i;
2453 u32 val;
2454
Michael Chanb6016b72005-05-26 13:03:09 -07002455 bp->fw_wr_seq++;
2456 msg_data |= bp->fw_wr_seq;
2457
Michael Chan2726d6e2008-01-29 21:35:05 -08002458 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002459
Michael Chana2f13892008-07-14 22:38:23 -07002460 if (!ack)
2461 return 0;
2462
Michael Chanb6016b72005-05-26 13:03:09 -07002463 /* wait for an acknowledgement. */
Michael Chan40105c02008-11-12 16:02:45 -08002464 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
Michael Chanb090ae22006-01-23 16:07:10 -08002465 msleep(10);
Michael Chanb6016b72005-05-26 13:03:09 -07002466
Michael Chan2726d6e2008-01-29 21:35:05 -08002467 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
Michael Chanb6016b72005-05-26 13:03:09 -07002468
2469 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2470 break;
2471 }
Michael Chanb090ae22006-01-23 16:07:10 -08002472 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2473 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002474
2475 /* If we timed out, inform the firmware that this is the case. */
Michael Chanb090ae22006-01-23 16:07:10 -08002476 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2477 if (!silent)
2478 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2479 "%x\n", msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002480
2481 msg_data &= ~BNX2_DRV_MSG_CODE;
2482 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2483
Michael Chan2726d6e2008-01-29 21:35:05 -08002484 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002485
Michael Chanb6016b72005-05-26 13:03:09 -07002486 return -EBUSY;
2487 }
2488
Michael Chanb090ae22006-01-23 16:07:10 -08002489 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2490 return -EIO;
2491
Michael Chanb6016b72005-05-26 13:03:09 -07002492 return 0;
2493}
2494
Michael Chan59b47d82006-11-19 14:10:45 -08002495static int
2496bnx2_init_5709_context(struct bnx2 *bp)
2497{
2498 int i, ret = 0;
2499 u32 val;
2500
2501 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2502 val |= (BCM_PAGE_BITS - 8) << 16;
2503 REG_WR(bp, BNX2_CTX_COMMAND, val);
Michael Chan641bdcd2007-06-04 21:22:24 -07002504 for (i = 0; i < 10; i++) {
2505 val = REG_RD(bp, BNX2_CTX_COMMAND);
2506 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2507 break;
2508 udelay(2);
2509 }
2510 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2511 return -EBUSY;
2512
Michael Chan59b47d82006-11-19 14:10:45 -08002513 for (i = 0; i < bp->ctx_pages; i++) {
2514 int j;
2515
Michael Chan352f7682008-05-02 16:57:26 -07002516 if (bp->ctx_blk[i])
2517 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2518 else
2519 return -ENOMEM;
2520
Michael Chan59b47d82006-11-19 14:10:45 -08002521 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2522 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2523 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2524 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2525 (u64) bp->ctx_blk_mapping[i] >> 32);
2526 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2527 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2528 for (j = 0; j < 10; j++) {
2529
2530 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2531 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2532 break;
2533 udelay(5);
2534 }
2535 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2536 ret = -EBUSY;
2537 break;
2538 }
2539 }
2540 return ret;
2541}
2542
Michael Chanb6016b72005-05-26 13:03:09 -07002543static void
2544bnx2_init_context(struct bnx2 *bp)
2545{
2546 u32 vcid;
2547
2548 vcid = 96;
2549 while (vcid) {
2550 u32 vcid_addr, pcid_addr, offset;
Michael Chan7947b202007-06-04 21:17:10 -07002551 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07002552
2553 vcid--;
2554
2555 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2556 u32 new_vcid;
2557
2558 vcid_addr = GET_PCID_ADDR(vcid);
2559 if (vcid & 0x8) {
2560 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2561 }
2562 else {
2563 new_vcid = vcid;
2564 }
2565 pcid_addr = GET_PCID_ADDR(new_vcid);
2566 }
2567 else {
2568 vcid_addr = GET_CID_ADDR(vcid);
2569 pcid_addr = vcid_addr;
2570 }
2571
Michael Chan7947b202007-06-04 21:17:10 -07002572 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2573 vcid_addr += (i << PHY_CTX_SHIFT);
2574 pcid_addr += (i << PHY_CTX_SHIFT);
Michael Chanb6016b72005-05-26 13:03:09 -07002575
Michael Chan5d5d0012007-12-12 11:17:43 -08002576 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
Michael Chan7947b202007-06-04 21:17:10 -07002577 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2578
2579 /* Zero out the context. */
2580 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
Michael Chan62a83132008-01-29 21:35:40 -08002581 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07002582 }
Michael Chanb6016b72005-05-26 13:03:09 -07002583 }
2584}
2585
2586static int
2587bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2588{
2589 u16 *good_mbuf;
2590 u32 good_mbuf_cnt;
2591 u32 val;
2592
2593 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2594 if (good_mbuf == NULL) {
2595 printk(KERN_ERR PFX "Failed to allocate memory in "
2596 "bnx2_alloc_bad_rbuf\n");
2597 return -ENOMEM;
2598 }
2599
2600 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2601 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2602
2603 good_mbuf_cnt = 0;
2604
2605 /* Allocate a bunch of mbufs and save the good ones in an array. */
Michael Chan2726d6e2008-01-29 21:35:05 -08002606 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
Michael Chanb6016b72005-05-26 13:03:09 -07002607 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
Michael Chan2726d6e2008-01-29 21:35:05 -08002608 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2609 BNX2_RBUF_COMMAND_ALLOC_REQ);
Michael Chanb6016b72005-05-26 13:03:09 -07002610
Michael Chan2726d6e2008-01-29 21:35:05 -08002611 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
Michael Chanb6016b72005-05-26 13:03:09 -07002612
2613 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2614
2615 /* The addresses with Bit 9 set are bad memory blocks. */
2616 if (!(val & (1 << 9))) {
2617 good_mbuf[good_mbuf_cnt] = (u16) val;
2618 good_mbuf_cnt++;
2619 }
2620
Michael Chan2726d6e2008-01-29 21:35:05 -08002621 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
Michael Chanb6016b72005-05-26 13:03:09 -07002622 }
2623
2624 /* Free the good ones back to the mbuf pool thus discarding
2625 * all the bad ones. */
2626 while (good_mbuf_cnt) {
2627 good_mbuf_cnt--;
2628
2629 val = good_mbuf[good_mbuf_cnt];
2630 val = (val << 9) | val | 1;
2631
Michael Chan2726d6e2008-01-29 21:35:05 -08002632 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
Michael Chanb6016b72005-05-26 13:03:09 -07002633 }
2634 kfree(good_mbuf);
2635 return 0;
2636}
2637
2638static void
Benjamin Li5fcaed02008-07-14 22:39:52 -07002639bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
Michael Chanb6016b72005-05-26 13:03:09 -07002640{
2641 u32 val;
Michael Chanb6016b72005-05-26 13:03:09 -07002642
2643 val = (mac_addr[0] << 8) | mac_addr[1];
2644
Benjamin Li5fcaed02008-07-14 22:39:52 -07002645 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
Michael Chanb6016b72005-05-26 13:03:09 -07002646
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002647 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
Michael Chanb6016b72005-05-26 13:03:09 -07002648 (mac_addr[4] << 8) | mac_addr[5];
2649
Benjamin Li5fcaed02008-07-14 22:39:52 -07002650 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
Michael Chanb6016b72005-05-26 13:03:09 -07002651}
2652
2653static inline int
Michael Chanbb4f98a2008-06-19 16:38:19 -07002654bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
Michael Chan47bf4242007-12-12 11:19:12 -08002655{
2656 dma_addr_t mapping;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002657 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
Michael Chan47bf4242007-12-12 11:19:12 -08002658 struct rx_bd *rxbd =
Michael Chanbb4f98a2008-06-19 16:38:19 -07002659 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
Michael Chan47bf4242007-12-12 11:19:12 -08002660 struct page *page = alloc_page(GFP_ATOMIC);
2661
2662 if (!page)
2663 return -ENOMEM;
2664 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2665 PCI_DMA_FROMDEVICE);
Benjamin Li3d16af82008-10-09 12:26:41 -07002666 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2667 __free_page(page);
2668 return -EIO;
2669 }
2670
Michael Chan47bf4242007-12-12 11:19:12 -08002671 rx_pg->page = page;
2672 pci_unmap_addr_set(rx_pg, mapping, mapping);
2673 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2674 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2675 return 0;
2676}
2677
2678static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07002679bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
Michael Chan47bf4242007-12-12 11:19:12 -08002680{
Michael Chanbb4f98a2008-06-19 16:38:19 -07002681 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
Michael Chan47bf4242007-12-12 11:19:12 -08002682 struct page *page = rx_pg->page;
2683
2684 if (!page)
2685 return;
2686
2687 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2688 PCI_DMA_FROMDEVICE);
2689
2690 __free_page(page);
2691 rx_pg->page = NULL;
2692}
2693
2694static inline int
Michael Chanbb4f98a2008-06-19 16:38:19 -07002695bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
Michael Chanb6016b72005-05-26 13:03:09 -07002696{
2697 struct sk_buff *skb;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002698 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
Michael Chanb6016b72005-05-26 13:03:09 -07002699 dma_addr_t mapping;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002700 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
Michael Chanb6016b72005-05-26 13:03:09 -07002701 unsigned long align;
2702
Michael Chan932f3772006-08-15 01:39:36 -07002703 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
Michael Chanb6016b72005-05-26 13:03:09 -07002704 if (skb == NULL) {
2705 return -ENOMEM;
2706 }
2707
Michael Chan59b47d82006-11-19 14:10:45 -08002708 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2709 skb_reserve(skb, BNX2_RX_ALIGN - align);
Michael Chanb6016b72005-05-26 13:03:09 -07002710
Michael Chanb6016b72005-05-26 13:03:09 -07002711 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2712 PCI_DMA_FROMDEVICE);
Benjamin Li3d16af82008-10-09 12:26:41 -07002713 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2714 dev_kfree_skb(skb);
2715 return -EIO;
2716 }
Michael Chanb6016b72005-05-26 13:03:09 -07002717
2718 rx_buf->skb = skb;
2719 pci_unmap_addr_set(rx_buf, mapping, mapping);
2720
2721 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2722 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2723
Michael Chanbb4f98a2008-06-19 16:38:19 -07002724 rxr->rx_prod_bseq += bp->rx_buf_use_size;
Michael Chanb6016b72005-05-26 13:03:09 -07002725
2726 return 0;
2727}
2728
Michael Chanda3e4fb2007-05-03 13:24:23 -07002729static int
Michael Chan35efa7c2007-12-20 19:56:37 -08002730bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
Michael Chanda3e4fb2007-05-03 13:24:23 -07002731{
Michael Chan43e80b82008-06-19 16:41:08 -07002732 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanda3e4fb2007-05-03 13:24:23 -07002733 u32 new_link_state, old_link_state;
2734 int is_set = 1;
2735
2736 new_link_state = sblk->status_attn_bits & event;
2737 old_link_state = sblk->status_attn_bits_ack & event;
2738 if (new_link_state != old_link_state) {
2739 if (new_link_state)
2740 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2741 else
2742 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2743 } else
2744 is_set = 0;
2745
2746 return is_set;
2747}
2748
Michael Chanb6016b72005-05-26 13:03:09 -07002749static void
Michael Chan35efa7c2007-12-20 19:56:37 -08002750bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
Michael Chanb6016b72005-05-26 13:03:09 -07002751{
Michael Chan74ecc622008-05-02 16:56:16 -07002752 spin_lock(&bp->phy_lock);
2753
2754 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
Michael Chanb6016b72005-05-26 13:03:09 -07002755 bnx2_set_link(bp);
Michael Chan35efa7c2007-12-20 19:56:37 -08002756 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
Michael Chan0d8a6572007-07-07 22:49:43 -07002757 bnx2_set_remote_link(bp);
2758
Michael Chan74ecc622008-05-02 16:56:16 -07002759 spin_unlock(&bp->phy_lock);
2760
Michael Chanb6016b72005-05-26 13:03:09 -07002761}
2762
Michael Chanead72702007-12-20 19:55:39 -08002763static inline u16
Michael Chan35efa7c2007-12-20 19:56:37 -08002764bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
Michael Chanead72702007-12-20 19:55:39 -08002765{
2766 u16 cons;
2767
Michael Chan43e80b82008-06-19 16:41:08 -07002768 /* Tell compiler that status block fields can change. */
2769 barrier();
2770 cons = *bnapi->hw_tx_cons_ptr;
Michael Chan581daf72009-05-06 16:46:47 -07002771 barrier();
Michael Chanead72702007-12-20 19:55:39 -08002772 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2773 cons++;
2774 return cons;
2775}
2776
Michael Chan57851d82007-12-20 20:01:44 -08002777static int
2778bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
Michael Chanb6016b72005-05-26 13:03:09 -07002779{
Michael Chan35e90102008-06-19 16:37:42 -07002780 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07002781 u16 hw_cons, sw_cons, sw_ring_cons;
Benjamin Li706bf242008-07-18 17:55:11 -07002782 int tx_pkt = 0, index;
2783 struct netdev_queue *txq;
2784
2785 index = (bnapi - bp->bnx2_napi);
2786 txq = netdev_get_tx_queue(bp->dev, index);
Michael Chanb6016b72005-05-26 13:03:09 -07002787
Michael Chan35efa7c2007-12-20 19:56:37 -08002788 hw_cons = bnx2_get_hw_tx_cons(bnapi);
Michael Chan35e90102008-06-19 16:37:42 -07002789 sw_cons = txr->tx_cons;
Michael Chanb6016b72005-05-26 13:03:09 -07002790
2791 while (sw_cons != hw_cons) {
Benjamin Li3d16af82008-10-09 12:26:41 -07002792 struct sw_tx_bd *tx_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07002793 struct sk_buff *skb;
2794 int i, last;
2795
2796 sw_ring_cons = TX_RING_IDX(sw_cons);
2797
Michael Chan35e90102008-06-19 16:37:42 -07002798 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
Michael Chanb6016b72005-05-26 13:03:09 -07002799 skb = tx_buf->skb;
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002800
Eric Dumazetd62fda02009-05-12 20:48:02 +00002801 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2802 prefetch(&skb->end);
2803
Michael Chanb6016b72005-05-26 13:03:09 -07002804 /* partial BD completions possible with TSO packets */
Eric Dumazetd62fda02009-05-12 20:48:02 +00002805 if (tx_buf->is_gso) {
Michael Chanb6016b72005-05-26 13:03:09 -07002806 u16 last_idx, last_ring_idx;
2807
Eric Dumazetd62fda02009-05-12 20:48:02 +00002808 last_idx = sw_cons + tx_buf->nr_frags + 1;
2809 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
Michael Chanb6016b72005-05-26 13:03:09 -07002810 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2811 last_idx++;
2812 }
2813 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2814 break;
2815 }
2816 }
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002817
Alexander Duycke95524a2009-12-02 16:47:57 +00002818 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2819 skb_headlen(skb), PCI_DMA_TODEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07002820
2821 tx_buf->skb = NULL;
Eric Dumazetd62fda02009-05-12 20:48:02 +00002822 last = tx_buf->nr_frags;
Michael Chanb6016b72005-05-26 13:03:09 -07002823
2824 for (i = 0; i < last; i++) {
2825 sw_cons = NEXT_TX_BD(sw_cons);
Alexander Duycke95524a2009-12-02 16:47:57 +00002826
2827 pci_unmap_page(bp->pdev,
2828 pci_unmap_addr(
2829 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2830 mapping),
2831 skb_shinfo(skb)->frags[i].size,
2832 PCI_DMA_TODEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07002833 }
2834
2835 sw_cons = NEXT_TX_BD(sw_cons);
2836
Michael Chan745720e2006-06-29 12:37:41 -07002837 dev_kfree_skb(skb);
Michael Chan57851d82007-12-20 20:01:44 -08002838 tx_pkt++;
2839 if (tx_pkt == budget)
2840 break;
Michael Chanb6016b72005-05-26 13:03:09 -07002841
Eric Dumazetd62fda02009-05-12 20:48:02 +00002842 if (hw_cons == sw_cons)
2843 hw_cons = bnx2_get_hw_tx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07002844 }
2845
Michael Chan35e90102008-06-19 16:37:42 -07002846 txr->hw_tx_cons = hw_cons;
2847 txr->tx_cons = sw_cons;
Benjamin Li706bf242008-07-18 17:55:11 -07002848
Michael Chan2f8af122006-08-15 01:39:10 -07002849 /* Need to make the tx_cons update visible to bnx2_start_xmit()
Benjamin Li706bf242008-07-18 17:55:11 -07002850 * before checking for netif_tx_queue_stopped(). Without the
Michael Chan2f8af122006-08-15 01:39:10 -07002851 * memory barrier, there is a small possibility that bnx2_start_xmit()
2852 * will miss it and cause the queue to be stopped forever.
2853 */
2854 smp_mb();
Michael Chanb6016b72005-05-26 13:03:09 -07002855
Benjamin Li706bf242008-07-18 17:55:11 -07002856 if (unlikely(netif_tx_queue_stopped(txq)) &&
Michael Chan35e90102008-06-19 16:37:42 -07002857 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
Benjamin Li706bf242008-07-18 17:55:11 -07002858 __netif_tx_lock(txq, smp_processor_id());
2859 if ((netif_tx_queue_stopped(txq)) &&
Michael Chan35e90102008-06-19 16:37:42 -07002860 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
Benjamin Li706bf242008-07-18 17:55:11 -07002861 netif_tx_wake_queue(txq);
2862 __netif_tx_unlock(txq);
Michael Chanb6016b72005-05-26 13:03:09 -07002863 }
Benjamin Li706bf242008-07-18 17:55:11 -07002864
Michael Chan57851d82007-12-20 20:01:44 -08002865 return tx_pkt;
Michael Chanb6016b72005-05-26 13:03:09 -07002866}
2867
Michael Chan1db82f22007-12-12 11:19:35 -08002868static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07002869bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
Michael Chana1f60192007-12-20 19:57:19 -08002870 struct sk_buff *skb, int count)
Michael Chan1db82f22007-12-12 11:19:35 -08002871{
2872 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2873 struct rx_bd *cons_bd, *prod_bd;
Michael Chan1db82f22007-12-12 11:19:35 -08002874 int i;
Benjamin Li3d16af82008-10-09 12:26:41 -07002875 u16 hw_prod, prod;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002876 u16 cons = rxr->rx_pg_cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002877
Benjamin Li3d16af82008-10-09 12:26:41 -07002878 cons_rx_pg = &rxr->rx_pg_ring[cons];
2879
2880 /* The caller was unable to allocate a new page to replace the
2881 * last one in the frags array, so we need to recycle that page
2882 * and then free the skb.
2883 */
2884 if (skb) {
2885 struct page *page;
2886 struct skb_shared_info *shinfo;
2887
2888 shinfo = skb_shinfo(skb);
2889 shinfo->nr_frags--;
2890 page = shinfo->frags[shinfo->nr_frags].page;
2891 shinfo->frags[shinfo->nr_frags].page = NULL;
2892
2893 cons_rx_pg->page = page;
2894 dev_kfree_skb(skb);
2895 }
2896
2897 hw_prod = rxr->rx_pg_prod;
2898
Michael Chan1db82f22007-12-12 11:19:35 -08002899 for (i = 0; i < count; i++) {
2900 prod = RX_PG_RING_IDX(hw_prod);
2901
Michael Chanbb4f98a2008-06-19 16:38:19 -07002902 prod_rx_pg = &rxr->rx_pg_ring[prod];
2903 cons_rx_pg = &rxr->rx_pg_ring[cons];
2904 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2905 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
Michael Chan1db82f22007-12-12 11:19:35 -08002906
Michael Chan1db82f22007-12-12 11:19:35 -08002907 if (prod != cons) {
2908 prod_rx_pg->page = cons_rx_pg->page;
2909 cons_rx_pg->page = NULL;
2910 pci_unmap_addr_set(prod_rx_pg, mapping,
2911 pci_unmap_addr(cons_rx_pg, mapping));
2912
2913 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2914 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2915
2916 }
2917 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2918 hw_prod = NEXT_RX_BD(hw_prod);
2919 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07002920 rxr->rx_pg_prod = hw_prod;
2921 rxr->rx_pg_cons = cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002922}
2923
Michael Chanb6016b72005-05-26 13:03:09 -07002924static inline void
Michael Chanbb4f98a2008-06-19 16:38:19 -07002925bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2926 struct sk_buff *skb, u16 cons, u16 prod)
Michael Chanb6016b72005-05-26 13:03:09 -07002927{
Michael Chan236b6392006-03-20 17:49:02 -08002928 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2929 struct rx_bd *cons_bd, *prod_bd;
2930
Michael Chanbb4f98a2008-06-19 16:38:19 -07002931 cons_rx_buf = &rxr->rx_buf_ring[cons];
2932 prod_rx_buf = &rxr->rx_buf_ring[prod];
Michael Chanb6016b72005-05-26 13:03:09 -07002933
2934 pci_dma_sync_single_for_device(bp->pdev,
2935 pci_unmap_addr(cons_rx_buf, mapping),
Benjamin Li601d3d12008-05-16 22:19:35 -07002936 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07002937
Michael Chanbb4f98a2008-06-19 16:38:19 -07002938 rxr->rx_prod_bseq += bp->rx_buf_use_size;
Michael Chan236b6392006-03-20 17:49:02 -08002939
2940 prod_rx_buf->skb = skb;
2941
2942 if (cons == prod)
2943 return;
2944
Michael Chanb6016b72005-05-26 13:03:09 -07002945 pci_unmap_addr_set(prod_rx_buf, mapping,
2946 pci_unmap_addr(cons_rx_buf, mapping));
2947
Michael Chanbb4f98a2008-06-19 16:38:19 -07002948 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2949 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
Michael Chan236b6392006-03-20 17:49:02 -08002950 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2951 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
Michael Chanb6016b72005-05-26 13:03:09 -07002952}
2953
Michael Chan85833c62007-12-12 11:17:01 -08002954static int
Michael Chanbb4f98a2008-06-19 16:38:19 -07002955bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
Michael Chana1f60192007-12-20 19:57:19 -08002956 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2957 u32 ring_idx)
Michael Chan85833c62007-12-12 11:17:01 -08002958{
2959 int err;
2960 u16 prod = ring_idx & 0xffff;
2961
Michael Chanbb4f98a2008-06-19 16:38:19 -07002962 err = bnx2_alloc_rx_skb(bp, rxr, prod);
Michael Chan85833c62007-12-12 11:17:01 -08002963 if (unlikely(err)) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07002964 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
Michael Chan1db82f22007-12-12 11:19:35 -08002965 if (hdr_len) {
2966 unsigned int raw_len = len + 4;
2967 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2968
Michael Chanbb4f98a2008-06-19 16:38:19 -07002969 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
Michael Chan1db82f22007-12-12 11:19:35 -08002970 }
Michael Chan85833c62007-12-12 11:17:01 -08002971 return err;
2972 }
2973
Benjamin Lid89cb6a2008-05-16 22:18:57 -07002974 skb_reserve(skb, BNX2_RX_OFFSET);
Michael Chan85833c62007-12-12 11:17:01 -08002975 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2976 PCI_DMA_FROMDEVICE);
2977
Michael Chan1db82f22007-12-12 11:19:35 -08002978 if (hdr_len == 0) {
2979 skb_put(skb, len);
2980 return 0;
2981 } else {
2982 unsigned int i, frag_len, frag_size, pages;
2983 struct sw_pg *rx_pg;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002984 u16 pg_cons = rxr->rx_pg_cons;
2985 u16 pg_prod = rxr->rx_pg_prod;
Michael Chan1db82f22007-12-12 11:19:35 -08002986
2987 frag_size = len + 4 - hdr_len;
2988 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2989 skb_put(skb, hdr_len);
2990
2991 for (i = 0; i < pages; i++) {
Benjamin Li3d16af82008-10-09 12:26:41 -07002992 dma_addr_t mapping_old;
2993
Michael Chan1db82f22007-12-12 11:19:35 -08002994 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2995 if (unlikely(frag_len <= 4)) {
2996 unsigned int tail = 4 - frag_len;
2997
Michael Chanbb4f98a2008-06-19 16:38:19 -07002998 rxr->rx_pg_cons = pg_cons;
2999 rxr->rx_pg_prod = pg_prod;
3000 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
Michael Chana1f60192007-12-20 19:57:19 -08003001 pages - i);
Michael Chan1db82f22007-12-12 11:19:35 -08003002 skb->len -= tail;
3003 if (i == 0) {
3004 skb->tail -= tail;
3005 } else {
3006 skb_frag_t *frag =
3007 &skb_shinfo(skb)->frags[i - 1];
3008 frag->size -= tail;
3009 skb->data_len -= tail;
3010 skb->truesize -= tail;
3011 }
3012 return 0;
3013 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07003014 rx_pg = &rxr->rx_pg_ring[pg_cons];
Michael Chan1db82f22007-12-12 11:19:35 -08003015
Benjamin Li3d16af82008-10-09 12:26:41 -07003016 /* Don't unmap yet. If we're unable to allocate a new
3017 * page, we need to recycle the page and the DMA addr.
3018 */
3019 mapping_old = pci_unmap_addr(rx_pg, mapping);
Michael Chan1db82f22007-12-12 11:19:35 -08003020 if (i == pages - 1)
3021 frag_len -= 4;
3022
3023 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3024 rx_pg->page = NULL;
3025
Michael Chanbb4f98a2008-06-19 16:38:19 -07003026 err = bnx2_alloc_rx_page(bp, rxr,
3027 RX_PG_RING_IDX(pg_prod));
Michael Chan1db82f22007-12-12 11:19:35 -08003028 if (unlikely(err)) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07003029 rxr->rx_pg_cons = pg_cons;
3030 rxr->rx_pg_prod = pg_prod;
3031 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
Michael Chana1f60192007-12-20 19:57:19 -08003032 pages - i);
Michael Chan1db82f22007-12-12 11:19:35 -08003033 return err;
3034 }
3035
Benjamin Li3d16af82008-10-09 12:26:41 -07003036 pci_unmap_page(bp->pdev, mapping_old,
3037 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3038
Michael Chan1db82f22007-12-12 11:19:35 -08003039 frag_size -= frag_len;
3040 skb->data_len += frag_len;
3041 skb->truesize += frag_len;
3042 skb->len += frag_len;
3043
3044 pg_prod = NEXT_RX_BD(pg_prod);
3045 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3046 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07003047 rxr->rx_pg_prod = pg_prod;
3048 rxr->rx_pg_cons = pg_cons;
Michael Chan1db82f22007-12-12 11:19:35 -08003049 }
Michael Chan85833c62007-12-12 11:17:01 -08003050 return 0;
3051}
3052
Michael Chanc09c2622007-12-10 17:18:37 -08003053static inline u16
Michael Chan35efa7c2007-12-20 19:56:37 -08003054bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
Michael Chanc09c2622007-12-10 17:18:37 -08003055{
Michael Chanbb4f98a2008-06-19 16:38:19 -07003056 u16 cons;
3057
Michael Chan43e80b82008-06-19 16:41:08 -07003058 /* Tell compiler that status block fields can change. */
3059 barrier();
3060 cons = *bnapi->hw_rx_cons_ptr;
Michael Chan581daf72009-05-06 16:46:47 -07003061 barrier();
Michael Chanc09c2622007-12-10 17:18:37 -08003062 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3063 cons++;
3064 return cons;
3065}
3066
Michael Chanb6016b72005-05-26 13:03:09 -07003067static int
Michael Chan35efa7c2007-12-20 19:56:37 -08003068bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
Michael Chanb6016b72005-05-26 13:03:09 -07003069{
Michael Chanbb4f98a2008-06-19 16:38:19 -07003070 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07003071 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3072 struct l2_fhdr *rx_hdr;
Michael Chan1db82f22007-12-12 11:19:35 -08003073 int rx_pkt = 0, pg_ring_used = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003074
Michael Chan35efa7c2007-12-20 19:56:37 -08003075 hw_cons = bnx2_get_hw_rx_cons(bnapi);
Michael Chanbb4f98a2008-06-19 16:38:19 -07003076 sw_cons = rxr->rx_cons;
3077 sw_prod = rxr->rx_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07003078
3079 /* Memory barrier necessary as speculative reads of the rx
3080 * buffer can be ahead of the index in the status block
3081 */
3082 rmb();
3083 while (sw_cons != hw_cons) {
Michael Chan1db82f22007-12-12 11:19:35 -08003084 unsigned int len, hdr_len;
Michael Chanade2bfe2006-01-23 16:09:51 -08003085 u32 status;
Michael Chanb6016b72005-05-26 13:03:09 -07003086 struct sw_bd *rx_buf;
3087 struct sk_buff *skb;
Michael Chan236b6392006-03-20 17:49:02 -08003088 dma_addr_t dma_addr;
Michael Chanf22828e2008-08-14 15:30:14 -07003089 u16 vtag = 0;
3090 int hw_vlan __maybe_unused = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003091
3092 sw_ring_cons = RX_RING_IDX(sw_cons);
3093 sw_ring_prod = RX_RING_IDX(sw_prod);
3094
Michael Chanbb4f98a2008-06-19 16:38:19 -07003095 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
Michael Chanb6016b72005-05-26 13:03:09 -07003096 skb = rx_buf->skb;
Michael Chan236b6392006-03-20 17:49:02 -08003097
3098 rx_buf->skb = NULL;
3099
3100 dma_addr = pci_unmap_addr(rx_buf, mapping);
3101
3102 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
Benjamin Li601d3d12008-05-16 22:19:35 -07003103 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3104 PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07003105
3106 rx_hdr = (struct l2_fhdr *) skb->data;
Michael Chan1db82f22007-12-12 11:19:35 -08003107 len = rx_hdr->l2_fhdr_pkt_len;
Michael Chan990ec382009-02-12 16:54:13 -08003108 status = rx_hdr->l2_fhdr_status;
Michael Chanb6016b72005-05-26 13:03:09 -07003109
Michael Chan1db82f22007-12-12 11:19:35 -08003110 hdr_len = 0;
3111 if (status & L2_FHDR_STATUS_SPLIT) {
3112 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3113 pg_ring_used = 1;
3114 } else if (len > bp->rx_jumbo_thresh) {
3115 hdr_len = bp->rx_jumbo_thresh;
3116 pg_ring_used = 1;
3117 }
3118
Michael Chan990ec382009-02-12 16:54:13 -08003119 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3120 L2_FHDR_ERRORS_PHY_DECODE |
3121 L2_FHDR_ERRORS_ALIGNMENT |
3122 L2_FHDR_ERRORS_TOO_SHORT |
3123 L2_FHDR_ERRORS_GIANT_FRAME))) {
3124
3125 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3126 sw_ring_prod);
3127 if (pg_ring_used) {
3128 int pages;
3129
3130 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3131
3132 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3133 }
3134 goto next_rx;
3135 }
3136
Michael Chan1db82f22007-12-12 11:19:35 -08003137 len -= 4;
Michael Chanb6016b72005-05-26 13:03:09 -07003138
Michael Chan5d5d0012007-12-12 11:17:43 -08003139 if (len <= bp->rx_copy_thresh) {
Michael Chanb6016b72005-05-26 13:03:09 -07003140 struct sk_buff *new_skb;
3141
Michael Chanf22828e2008-08-14 15:30:14 -07003142 new_skb = netdev_alloc_skb(bp->dev, len + 6);
Michael Chan85833c62007-12-12 11:17:01 -08003143 if (new_skb == NULL) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07003144 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
Michael Chan85833c62007-12-12 11:17:01 -08003145 sw_ring_prod);
3146 goto next_rx;
3147 }
Michael Chanb6016b72005-05-26 13:03:09 -07003148
3149 /* aligned copy */
Benjamin Lid89cb6a2008-05-16 22:18:57 -07003150 skb_copy_from_linear_data_offset(skb,
Michael Chanf22828e2008-08-14 15:30:14 -07003151 BNX2_RX_OFFSET - 6,
3152 new_skb->data, len + 6);
3153 skb_reserve(new_skb, 6);
Michael Chanb6016b72005-05-26 13:03:09 -07003154 skb_put(new_skb, len);
Michael Chanb6016b72005-05-26 13:03:09 -07003155
Michael Chanbb4f98a2008-06-19 16:38:19 -07003156 bnx2_reuse_rx_skb(bp, rxr, skb,
Michael Chanb6016b72005-05-26 13:03:09 -07003157 sw_ring_cons, sw_ring_prod);
3158
3159 skb = new_skb;
Michael Chanbb4f98a2008-06-19 16:38:19 -07003160 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
Michael Chana1f60192007-12-20 19:57:19 -08003161 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
Michael Chanb6016b72005-05-26 13:03:09 -07003162 goto next_rx;
Michael Chanb6016b72005-05-26 13:03:09 -07003163
Michael Chanf22828e2008-08-14 15:30:14 -07003164 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3165 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3166 vtag = rx_hdr->l2_fhdr_vlan_tag;
3167#ifdef BCM_VLAN
3168 if (bp->vlgrp)
3169 hw_vlan = 1;
3170 else
3171#endif
3172 {
3173 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3174 __skb_push(skb, 4);
3175
3176 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3177 ve->h_vlan_proto = htons(ETH_P_8021Q);
3178 ve->h_vlan_TCI = htons(vtag);
3179 len += 4;
3180 }
3181 }
3182
Michael Chanb6016b72005-05-26 13:03:09 -07003183 skb->protocol = eth_type_trans(skb, bp->dev);
3184
3185 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
Alexey Dobriyand1e100b2006-06-11 20:57:17 -07003186 (ntohs(skb->protocol) != 0x8100)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003187
Michael Chan745720e2006-06-29 12:37:41 -07003188 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07003189 goto next_rx;
3190
3191 }
3192
Michael Chanb6016b72005-05-26 13:03:09 -07003193 skb->ip_summed = CHECKSUM_NONE;
3194 if (bp->rx_csum &&
3195 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3196 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3197
Michael Chanade2bfe2006-01-23 16:09:51 -08003198 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3199 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
Michael Chanb6016b72005-05-26 13:03:09 -07003200 skb->ip_summed = CHECKSUM_UNNECESSARY;
3201 }
3202
David S. Miller0c8dfc82009-01-27 16:22:32 -08003203 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3204
Michael Chanb6016b72005-05-26 13:03:09 -07003205#ifdef BCM_VLAN
Michael Chanf22828e2008-08-14 15:30:14 -07003206 if (hw_vlan)
3207 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
Michael Chanb6016b72005-05-26 13:03:09 -07003208 else
3209#endif
3210 netif_receive_skb(skb);
3211
Michael Chanb6016b72005-05-26 13:03:09 -07003212 rx_pkt++;
3213
3214next_rx:
Michael Chanb6016b72005-05-26 13:03:09 -07003215 sw_cons = NEXT_RX_BD(sw_cons);
3216 sw_prod = NEXT_RX_BD(sw_prod);
3217
3218 if ((rx_pkt == budget))
3219 break;
Michael Chanf4e418f2005-11-04 08:53:48 -08003220
3221 /* Refresh hw_cons to see if there is new work */
3222 if (sw_cons == hw_cons) {
Michael Chan35efa7c2007-12-20 19:56:37 -08003223 hw_cons = bnx2_get_hw_rx_cons(bnapi);
Michael Chanf4e418f2005-11-04 08:53:48 -08003224 rmb();
3225 }
Michael Chanb6016b72005-05-26 13:03:09 -07003226 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07003227 rxr->rx_cons = sw_cons;
3228 rxr->rx_prod = sw_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07003229
Michael Chan1db82f22007-12-12 11:19:35 -08003230 if (pg_ring_used)
Michael Chanbb4f98a2008-06-19 16:38:19 -07003231 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
Michael Chan1db82f22007-12-12 11:19:35 -08003232
Michael Chanbb4f98a2008-06-19 16:38:19 -07003233 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
Michael Chanb6016b72005-05-26 13:03:09 -07003234
Michael Chanbb4f98a2008-06-19 16:38:19 -07003235 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07003236
3237 mmiowb();
3238
3239 return rx_pkt;
3240
3241}
3242
3243/* MSI ISR - The only difference between this and the INTx ISR
3244 * is that the MSI interrupt is always serviced.
3245 */
3246static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01003247bnx2_msi(int irq, void *dev_instance)
Michael Chanb6016b72005-05-26 13:03:09 -07003248{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003249 struct bnx2_napi *bnapi = dev_instance;
3250 struct bnx2 *bp = bnapi->bp;
Michael Chanb6016b72005-05-26 13:03:09 -07003251
Michael Chan43e80b82008-06-19 16:41:08 -07003252 prefetch(bnapi->status_blk.msi);
Michael Chanb6016b72005-05-26 13:03:09 -07003253 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3254 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3255 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3256
3257 /* Return here if interrupt is disabled. */
Michael Chan73eef4c2005-08-25 15:39:15 -07003258 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3259 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003260
Ben Hutchings288379f2009-01-19 16:43:59 -08003261 napi_schedule(&bnapi->napi);
Michael Chanb6016b72005-05-26 13:03:09 -07003262
Michael Chan73eef4c2005-08-25 15:39:15 -07003263 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003264}
3265
3266static irqreturn_t
Michael Chan8e6a72c2007-05-03 13:24:48 -07003267bnx2_msi_1shot(int irq, void *dev_instance)
3268{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003269 struct bnx2_napi *bnapi = dev_instance;
3270 struct bnx2 *bp = bnapi->bp;
Michael Chan8e6a72c2007-05-03 13:24:48 -07003271
Michael Chan43e80b82008-06-19 16:41:08 -07003272 prefetch(bnapi->status_blk.msi);
Michael Chan8e6a72c2007-05-03 13:24:48 -07003273
3274 /* Return here if interrupt is disabled. */
3275 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3276 return IRQ_HANDLED;
3277
Ben Hutchings288379f2009-01-19 16:43:59 -08003278 napi_schedule(&bnapi->napi);
Michael Chan8e6a72c2007-05-03 13:24:48 -07003279
3280 return IRQ_HANDLED;
3281}
3282
3283static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01003284bnx2_interrupt(int irq, void *dev_instance)
Michael Chanb6016b72005-05-26 13:03:09 -07003285{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003286 struct bnx2_napi *bnapi = dev_instance;
3287 struct bnx2 *bp = bnapi->bp;
Michael Chan43e80b82008-06-19 16:41:08 -07003288 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanb6016b72005-05-26 13:03:09 -07003289
3290 /* When using INTx, it is possible for the interrupt to arrive
3291 * at the CPU before the status block posted prior to the
3292 * interrupt. Reading a register will flush the status block.
3293 * When using MSI, the MSI message will always complete after
3294 * the status block write.
3295 */
Michael Chan35efa7c2007-12-20 19:56:37 -08003296 if ((sblk->status_idx == bnapi->last_status_idx) &&
Michael Chanb6016b72005-05-26 13:03:09 -07003297 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3298 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
Michael Chan73eef4c2005-08-25 15:39:15 -07003299 return IRQ_NONE;
Michael Chanb6016b72005-05-26 13:03:09 -07003300
3301 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3302 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3303 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3304
Michael Chanb8a7ce72007-07-07 22:51:03 -07003305 /* Read back to deassert IRQ immediately to avoid too many
3306 * spurious interrupts.
3307 */
3308 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3309
Michael Chanb6016b72005-05-26 13:03:09 -07003310 /* Return here if interrupt is shared and is disabled. */
Michael Chan73eef4c2005-08-25 15:39:15 -07003311 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3312 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003313
Ben Hutchings288379f2009-01-19 16:43:59 -08003314 if (napi_schedule_prep(&bnapi->napi)) {
Michael Chan35efa7c2007-12-20 19:56:37 -08003315 bnapi->last_status_idx = sblk->status_idx;
Ben Hutchings288379f2009-01-19 16:43:59 -08003316 __napi_schedule(&bnapi->napi);
Michael Chanb8a7ce72007-07-07 22:51:03 -07003317 }
Michael Chanb6016b72005-05-26 13:03:09 -07003318
Michael Chan73eef4c2005-08-25 15:39:15 -07003319 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003320}
3321
Michael Chan43e80b82008-06-19 16:41:08 -07003322static inline int
3323bnx2_has_fast_work(struct bnx2_napi *bnapi)
3324{
3325 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3326 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3327
3328 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3329 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3330 return 1;
3331 return 0;
3332}
3333
Michael Chan0d8a6572007-07-07 22:49:43 -07003334#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3335 STATUS_ATTN_BITS_TIMER_ABORT)
Michael Chanda3e4fb2007-05-03 13:24:23 -07003336
Michael Chanf4e418f2005-11-04 08:53:48 -08003337static inline int
Michael Chan35efa7c2007-12-20 19:56:37 -08003338bnx2_has_work(struct bnx2_napi *bnapi)
Michael Chanf4e418f2005-11-04 08:53:48 -08003339{
Michael Chan43e80b82008-06-19 16:41:08 -07003340 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanf4e418f2005-11-04 08:53:48 -08003341
Michael Chan43e80b82008-06-19 16:41:08 -07003342 if (bnx2_has_fast_work(bnapi))
Michael Chanf4e418f2005-11-04 08:53:48 -08003343 return 1;
3344
Michael Chan4edd4732009-06-08 18:14:42 -07003345#ifdef BCM_CNIC
3346 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3347 return 1;
3348#endif
3349
Michael Chanda3e4fb2007-05-03 13:24:23 -07003350 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3351 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
Michael Chanf4e418f2005-11-04 08:53:48 -08003352 return 1;
3353
3354 return 0;
3355}
3356
Michael Chanefba0182008-12-03 00:36:15 -08003357static void
3358bnx2_chk_missed_msi(struct bnx2 *bp)
3359{
3360 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3361 u32 msi_ctrl;
3362
3363 if (bnx2_has_work(bnapi)) {
3364 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3365 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3366 return;
3367
3368 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3369 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3370 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3371 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3372 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3373 }
3374 }
3375
3376 bp->idle_chk_status_idx = bnapi->last_status_idx;
3377}
3378
Michael Chan4edd4732009-06-08 18:14:42 -07003379#ifdef BCM_CNIC
3380static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3381{
3382 struct cnic_ops *c_ops;
3383
3384 if (!bnapi->cnic_present)
3385 return;
3386
3387 rcu_read_lock();
3388 c_ops = rcu_dereference(bp->cnic_ops);
3389 if (c_ops)
3390 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3391 bnapi->status_blk.msi);
3392 rcu_read_unlock();
3393}
3394#endif
3395
Michael Chan43e80b82008-06-19 16:41:08 -07003396static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
Michael Chanb6016b72005-05-26 13:03:09 -07003397{
Michael Chan43e80b82008-06-19 16:41:08 -07003398 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanda3e4fb2007-05-03 13:24:23 -07003399 u32 status_attn_bits = sblk->status_attn_bits;
3400 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
Michael Chanb6016b72005-05-26 13:03:09 -07003401
Michael Chanda3e4fb2007-05-03 13:24:23 -07003402 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3403 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003404
Michael Chan35efa7c2007-12-20 19:56:37 -08003405 bnx2_phy_int(bp, bnapi);
Michael Chanbf5295b2006-03-23 01:11:56 -08003406
3407 /* This is needed to take care of transient status
3408 * during link changes.
3409 */
3410 REG_WR(bp, BNX2_HC_COMMAND,
3411 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3412 REG_RD(bp, BNX2_HC_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07003413 }
Michael Chan43e80b82008-06-19 16:41:08 -07003414}
3415
3416static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3417 int work_done, int budget)
3418{
3419 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3420 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07003421
Michael Chan35e90102008-06-19 16:37:42 -07003422 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
Michael Chan57851d82007-12-20 20:01:44 -08003423 bnx2_tx_int(bp, bnapi, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003424
Michael Chanbb4f98a2008-06-19 16:38:19 -07003425 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
Michael Chan35efa7c2007-12-20 19:56:37 -08003426 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003427
David S. Miller6f535762007-10-11 18:08:29 -07003428 return work_done;
3429}
Michael Chanf4e418f2005-11-04 08:53:48 -08003430
Michael Chanf0ea2e62008-06-19 16:41:57 -07003431static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3432{
3433 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3434 struct bnx2 *bp = bnapi->bp;
3435 int work_done = 0;
3436 struct status_block_msix *sblk = bnapi->status_blk.msix;
3437
3438 while (1) {
3439 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3440 if (unlikely(work_done >= budget))
3441 break;
3442
3443 bnapi->last_status_idx = sblk->status_idx;
3444 /* status idx must be read before checking for more work. */
3445 rmb();
3446 if (likely(!bnx2_has_fast_work(bnapi))) {
3447
Ben Hutchings288379f2009-01-19 16:43:59 -08003448 napi_complete(napi);
Michael Chanf0ea2e62008-06-19 16:41:57 -07003449 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3450 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3451 bnapi->last_status_idx);
3452 break;
3453 }
3454 }
3455 return work_done;
3456}
3457
David S. Miller6f535762007-10-11 18:08:29 -07003458static int bnx2_poll(struct napi_struct *napi, int budget)
3459{
Michael Chan35efa7c2007-12-20 19:56:37 -08003460 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3461 struct bnx2 *bp = bnapi->bp;
David S. Miller6f535762007-10-11 18:08:29 -07003462 int work_done = 0;
Michael Chan43e80b82008-06-19 16:41:08 -07003463 struct status_block *sblk = bnapi->status_blk.msi;
David S. Miller6f535762007-10-11 18:08:29 -07003464
3465 while (1) {
Michael Chan43e80b82008-06-19 16:41:08 -07003466 bnx2_poll_link(bp, bnapi);
3467
Michael Chan35efa7c2007-12-20 19:56:37 -08003468 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
David S. Miller6f535762007-10-11 18:08:29 -07003469
Michael Chan4edd4732009-06-08 18:14:42 -07003470#ifdef BCM_CNIC
3471 bnx2_poll_cnic(bp, bnapi);
3472#endif
3473
Michael Chan35efa7c2007-12-20 19:56:37 -08003474 /* bnapi->last_status_idx is used below to tell the hw how
Michael Chan6dee6422007-10-12 01:40:38 -07003475 * much work has been processed, so we must read it before
3476 * checking for more work.
3477 */
Michael Chan35efa7c2007-12-20 19:56:37 -08003478 bnapi->last_status_idx = sblk->status_idx;
Michael Chanefba0182008-12-03 00:36:15 -08003479
3480 if (unlikely(work_done >= budget))
3481 break;
3482
Michael Chan6dee6422007-10-12 01:40:38 -07003483 rmb();
Michael Chan35efa7c2007-12-20 19:56:37 -08003484 if (likely(!bnx2_has_work(bnapi))) {
Ben Hutchings288379f2009-01-19 16:43:59 -08003485 napi_complete(napi);
David S. Millerf86e82f2008-01-21 17:15:40 -08003486 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
David S. Miller6f535762007-10-11 18:08:29 -07003487 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3488 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
Michael Chan35efa7c2007-12-20 19:56:37 -08003489 bnapi->last_status_idx);
Michael Chan6dee6422007-10-12 01:40:38 -07003490 break;
David S. Miller6f535762007-10-11 18:08:29 -07003491 }
3492 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3493 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3494 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
Michael Chan35efa7c2007-12-20 19:56:37 -08003495 bnapi->last_status_idx);
David S. Miller6f535762007-10-11 18:08:29 -07003496
Michael Chan1269a8a2006-01-23 16:11:03 -08003497 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3498 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
Michael Chan35efa7c2007-12-20 19:56:37 -08003499 bnapi->last_status_idx);
David S. Miller6f535762007-10-11 18:08:29 -07003500 break;
Michael Chan1269a8a2006-01-23 16:11:03 -08003501 }
Michael Chanb6016b72005-05-26 13:03:09 -07003502 }
3503
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003504 return work_done;
Michael Chanb6016b72005-05-26 13:03:09 -07003505}
3506
Herbert Xu932ff272006-06-09 12:20:56 -07003507/* Called with rtnl_lock from vlan functions and also netif_tx_lock
Michael Chanb6016b72005-05-26 13:03:09 -07003508 * from set_multicast.
3509 */
3510static void
3511bnx2_set_rx_mode(struct net_device *dev)
3512{
Michael Chan972ec0d2006-01-23 16:12:43 -08003513 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07003514 u32 rx_mode, sort_mode;
Jiri Pirkoccffad252009-05-22 23:22:17 +00003515 struct netdev_hw_addr *ha;
Michael Chanb6016b72005-05-26 13:03:09 -07003516 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07003517
Michael Chan9f52b562008-10-09 12:21:46 -07003518 if (!netif_running(dev))
3519 return;
3520
Michael Chanc770a652005-08-25 15:38:39 -07003521 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003522
3523 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3524 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3525 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3526#ifdef BCM_VLAN
Michael Chan7c6337a2008-08-14 15:29:09 -07003527 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
Michael Chanb6016b72005-05-26 13:03:09 -07003528 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
Michael Chanb6016b72005-05-26 13:03:09 -07003529#else
Michael Chan7c6337a2008-08-14 15:29:09 -07003530 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
Michael Chane29054f2006-01-23 16:06:06 -08003531 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
Michael Chanb6016b72005-05-26 13:03:09 -07003532#endif
3533 if (dev->flags & IFF_PROMISC) {
3534 /* Promiscuous mode. */
3535 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
Michael Chan75108732006-11-19 14:06:40 -08003536 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3537 BNX2_RPM_SORT_USER0_PROM_VLAN;
Michael Chanb6016b72005-05-26 13:03:09 -07003538 }
3539 else if (dev->flags & IFF_ALLMULTI) {
3540 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3541 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3542 0xffffffff);
3543 }
3544 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3545 }
3546 else {
3547 /* Accept one or more multicast(s). */
3548 struct dev_mc_list *mclist;
3549 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3550 u32 regidx;
3551 u32 bit;
3552 u32 crc;
3553
3554 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3555
3556 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3557 i++, mclist = mclist->next) {
3558
3559 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3560 bit = crc & 0xff;
3561 regidx = (bit & 0xe0) >> 5;
3562 bit &= 0x1f;
3563 mc_filter[regidx] |= (1 << bit);
3564 }
3565
3566 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3567 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3568 mc_filter[i]);
3569 }
3570
3571 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3572 }
3573
Jiri Pirko31278e72009-06-17 01:12:19 +00003574 if (dev->uc.count > BNX2_MAX_UNICAST_ADDRESSES) {
Benjamin Li5fcaed02008-07-14 22:39:52 -07003575 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3576 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3577 BNX2_RPM_SORT_USER0_PROM_VLAN;
3578 } else if (!(dev->flags & IFF_PROMISC)) {
Benjamin Li5fcaed02008-07-14 22:39:52 -07003579 /* Add all entries into to the match filter list */
Jiri Pirkoccffad252009-05-22 23:22:17 +00003580 i = 0;
Jiri Pirko31278e72009-06-17 01:12:19 +00003581 list_for_each_entry(ha, &dev->uc.list, list) {
Jiri Pirkoccffad252009-05-22 23:22:17 +00003582 bnx2_set_mac_addr(bp, ha->addr,
Benjamin Li5fcaed02008-07-14 22:39:52 -07003583 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3584 sort_mode |= (1 <<
3585 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
Jiri Pirkoccffad252009-05-22 23:22:17 +00003586 i++;
Benjamin Li5fcaed02008-07-14 22:39:52 -07003587 }
3588
3589 }
3590
Michael Chanb6016b72005-05-26 13:03:09 -07003591 if (rx_mode != bp->rx_mode) {
3592 bp->rx_mode = rx_mode;
3593 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3594 }
3595
3596 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3597 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3598 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3599
Michael Chanc770a652005-08-25 15:38:39 -07003600 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003601}
3602
Michael Chan57579f72009-04-04 16:51:14 -07003603static int __devinit
3604check_fw_section(const struct firmware *fw,
3605 const struct bnx2_fw_file_section *section,
3606 u32 alignment, bool non_empty)
Michael Chanb6016b72005-05-26 13:03:09 -07003607{
Michael Chan57579f72009-04-04 16:51:14 -07003608 u32 offset = be32_to_cpu(section->offset);
3609 u32 len = be32_to_cpu(section->len);
Michael Chanb6016b72005-05-26 13:03:09 -07003610
Michael Chan57579f72009-04-04 16:51:14 -07003611 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3612 return -EINVAL;
3613 if ((non_empty && len == 0) || len > fw->size - offset ||
3614 len & (alignment - 1))
3615 return -EINVAL;
3616 return 0;
3617}
3618
3619static int __devinit
3620check_mips_fw_entry(const struct firmware *fw,
3621 const struct bnx2_mips_fw_file_entry *entry)
3622{
3623 if (check_fw_section(fw, &entry->text, 4, true) ||
3624 check_fw_section(fw, &entry->data, 4, false) ||
3625 check_fw_section(fw, &entry->rodata, 4, false))
3626 return -EINVAL;
3627 return 0;
3628}
3629
3630static int __devinit
3631bnx2_request_firmware(struct bnx2 *bp)
3632{
3633 const char *mips_fw_file, *rv2p_fw_file;
Bastian Blank5ee1c322009-04-08 15:50:07 -07003634 const struct bnx2_mips_fw_file *mips_fw;
3635 const struct bnx2_rv2p_fw_file *rv2p_fw;
Michael Chan57579f72009-04-04 16:51:14 -07003636 int rc;
3637
3638 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3639 mips_fw_file = FW_MIPS_FILE_09;
Michael Chan078b0732009-08-29 00:02:46 -07003640 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3641 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3642 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3643 else
3644 rv2p_fw_file = FW_RV2P_FILE_09;
Michael Chan57579f72009-04-04 16:51:14 -07003645 } else {
3646 mips_fw_file = FW_MIPS_FILE_06;
3647 rv2p_fw_file = FW_RV2P_FILE_06;
3648 }
3649
3650 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3651 if (rc) {
3652 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3653 mips_fw_file);
3654 return rc;
3655 }
3656
3657 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3658 if (rc) {
3659 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3660 rv2p_fw_file);
3661 return rc;
3662 }
Bastian Blank5ee1c322009-04-08 15:50:07 -07003663 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3664 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3665 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3666 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3667 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3668 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3669 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3670 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
Michael Chan57579f72009-04-04 16:51:14 -07003671 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3672 mips_fw_file);
3673 return -EINVAL;
3674 }
Bastian Blank5ee1c322009-04-08 15:50:07 -07003675 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3676 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3677 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
Michael Chan57579f72009-04-04 16:51:14 -07003678 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3679 rv2p_fw_file);
3680 return -EINVAL;
3681 }
3682
3683 return 0;
3684}
3685
3686static u32
3687rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3688{
3689 switch (idx) {
3690 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3691 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3692 rv2p_code |= RV2P_BD_PAGE_SIZE;
3693 break;
3694 }
3695 return rv2p_code;
3696}
3697
3698static int
3699load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3700 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3701{
3702 u32 rv2p_code_len, file_offset;
3703 __be32 *rv2p_code;
3704 int i;
3705 u32 val, cmd, addr;
3706
3707 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3708 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3709
3710 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3711
3712 if (rv2p_proc == RV2P_PROC1) {
3713 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3714 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3715 } else {
3716 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3717 addr = BNX2_RV2P_PROC2_ADDR_CMD;
Michael Chand25be1d2008-05-02 16:57:59 -07003718 }
Michael Chanb6016b72005-05-26 13:03:09 -07003719
3720 for (i = 0; i < rv2p_code_len; i += 8) {
Michael Chan57579f72009-04-04 16:51:14 -07003721 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
Michael Chanb6016b72005-05-26 13:03:09 -07003722 rv2p_code++;
Michael Chan57579f72009-04-04 16:51:14 -07003723 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
Michael Chanb6016b72005-05-26 13:03:09 -07003724 rv2p_code++;
3725
Michael Chan57579f72009-04-04 16:51:14 -07003726 val = (i / 8) | cmd;
3727 REG_WR(bp, addr, val);
3728 }
3729
3730 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3731 for (i = 0; i < 8; i++) {
3732 u32 loc, code;
3733
3734 loc = be32_to_cpu(fw_entry->fixup[i]);
3735 if (loc && ((loc * 4) < rv2p_code_len)) {
3736 code = be32_to_cpu(*(rv2p_code + loc - 1));
3737 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3738 code = be32_to_cpu(*(rv2p_code + loc));
3739 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3740 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3741
3742 val = (loc / 2) | cmd;
3743 REG_WR(bp, addr, val);
Michael Chanb6016b72005-05-26 13:03:09 -07003744 }
3745 }
3746
3747 /* Reset the processor, un-stall is done later. */
3748 if (rv2p_proc == RV2P_PROC1) {
3749 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3750 }
3751 else {
3752 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3753 }
Michael Chan57579f72009-04-04 16:51:14 -07003754
3755 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003756}
3757
Michael Chanaf3ee512006-11-19 14:09:25 -08003758static int
Michael Chan57579f72009-04-04 16:51:14 -07003759load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3760 const struct bnx2_mips_fw_file_entry *fw_entry)
Michael Chanb6016b72005-05-26 13:03:09 -07003761{
Michael Chan57579f72009-04-04 16:51:14 -07003762 u32 addr, len, file_offset;
3763 __be32 *data;
Michael Chanb6016b72005-05-26 13:03:09 -07003764 u32 offset;
3765 u32 val;
3766
3767 /* Halt the CPU. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003768 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
Michael Chanb6016b72005-05-26 13:03:09 -07003769 val |= cpu_reg->mode_value_halt;
Michael Chan2726d6e2008-01-29 21:35:05 -08003770 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3771 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
Michael Chanb6016b72005-05-26 13:03:09 -07003772
3773 /* Load the Text area. */
Michael Chan57579f72009-04-04 16:51:14 -07003774 addr = be32_to_cpu(fw_entry->text.addr);
3775 len = be32_to_cpu(fw_entry->text.len);
3776 file_offset = be32_to_cpu(fw_entry->text.offset);
3777 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3778
3779 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3780 if (len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003781 int j;
3782
Michael Chan57579f72009-04-04 16:51:14 -07003783 for (j = 0; j < (len / 4); j++, offset += 4)
3784 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
Michael Chanb6016b72005-05-26 13:03:09 -07003785 }
3786
3787 /* Load the Data area. */
Michael Chan57579f72009-04-04 16:51:14 -07003788 addr = be32_to_cpu(fw_entry->data.addr);
3789 len = be32_to_cpu(fw_entry->data.len);
3790 file_offset = be32_to_cpu(fw_entry->data.offset);
3791 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3792
3793 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3794 if (len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003795 int j;
3796
Michael Chan57579f72009-04-04 16:51:14 -07003797 for (j = 0; j < (len / 4); j++, offset += 4)
3798 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
Michael Chanb6016b72005-05-26 13:03:09 -07003799 }
3800
3801 /* Load the Read-Only area. */
Michael Chan57579f72009-04-04 16:51:14 -07003802 addr = be32_to_cpu(fw_entry->rodata.addr);
3803 len = be32_to_cpu(fw_entry->rodata.len);
3804 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3805 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3806
3807 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3808 if (len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003809 int j;
3810
Michael Chan57579f72009-04-04 16:51:14 -07003811 for (j = 0; j < (len / 4); j++, offset += 4)
3812 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
Michael Chanb6016b72005-05-26 13:03:09 -07003813 }
3814
3815 /* Clear the pre-fetch instruction. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003816 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
Michael Chan57579f72009-04-04 16:51:14 -07003817
3818 val = be32_to_cpu(fw_entry->start_addr);
3819 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
Michael Chanb6016b72005-05-26 13:03:09 -07003820
3821 /* Start the CPU. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003822 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
Michael Chanb6016b72005-05-26 13:03:09 -07003823 val &= ~cpu_reg->mode_value_halt;
Michael Chan2726d6e2008-01-29 21:35:05 -08003824 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3825 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
Michael Chanaf3ee512006-11-19 14:09:25 -08003826
3827 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003828}
3829
Michael Chanfba9fe92006-06-12 22:21:25 -07003830static int
Michael Chanb6016b72005-05-26 13:03:09 -07003831bnx2_init_cpus(struct bnx2 *bp)
3832{
Michael Chan57579f72009-04-04 16:51:14 -07003833 const struct bnx2_mips_fw_file *mips_fw =
3834 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3835 const struct bnx2_rv2p_fw_file *rv2p_fw =
3836 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3837 int rc;
Michael Chanb6016b72005-05-26 13:03:09 -07003838
3839 /* Initialize the RV2P processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003840 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3841 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
Michael Chanb6016b72005-05-26 13:03:09 -07003842
3843 /* Initialize the RX Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003844 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
Michael Chanfba9fe92006-06-12 22:21:25 -07003845 if (rc)
3846 goto init_cpu_err;
3847
Michael Chanb6016b72005-05-26 13:03:09 -07003848 /* Initialize the TX Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003849 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
Michael Chanfba9fe92006-06-12 22:21:25 -07003850 if (rc)
3851 goto init_cpu_err;
3852
Michael Chanb6016b72005-05-26 13:03:09 -07003853 /* Initialize the TX Patch-up Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003854 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
Michael Chanfba9fe92006-06-12 22:21:25 -07003855 if (rc)
3856 goto init_cpu_err;
3857
Michael Chanb6016b72005-05-26 13:03:09 -07003858 /* Initialize the Completion Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003859 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
Michael Chanfba9fe92006-06-12 22:21:25 -07003860 if (rc)
3861 goto init_cpu_err;
3862
Michael Chand43584c2006-11-19 14:14:35 -08003863 /* Initialize the Command Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003864 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
Michael Chan110d0ef2007-12-12 11:18:34 -08003865
Michael Chanfba9fe92006-06-12 22:21:25 -07003866init_cpu_err:
Michael Chanfba9fe92006-06-12 22:21:25 -07003867 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07003868}
3869
3870static int
Pavel Machek829ca9a2005-09-03 15:56:56 -07003871bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
Michael Chanb6016b72005-05-26 13:03:09 -07003872{
3873 u16 pmcsr;
3874
3875 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3876
3877 switch (state) {
Pavel Machek829ca9a2005-09-03 15:56:56 -07003878 case PCI_D0: {
Michael Chanb6016b72005-05-26 13:03:09 -07003879 u32 val;
3880
3881 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3882 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3883 PCI_PM_CTRL_PME_STATUS);
3884
3885 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3886 /* delay required during transition out of D3hot */
3887 msleep(20);
3888
3889 val = REG_RD(bp, BNX2_EMAC_MODE);
3890 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3891 val &= ~BNX2_EMAC_MODE_MPKT;
3892 REG_WR(bp, BNX2_EMAC_MODE, val);
3893
3894 val = REG_RD(bp, BNX2_RPM_CONFIG);
3895 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3896 REG_WR(bp, BNX2_RPM_CONFIG, val);
3897 break;
3898 }
Pavel Machek829ca9a2005-09-03 15:56:56 -07003899 case PCI_D3hot: {
Michael Chanb6016b72005-05-26 13:03:09 -07003900 int i;
3901 u32 val, wol_msg;
3902
3903 if (bp->wol) {
3904 u32 advertising;
3905 u8 autoneg;
3906
3907 autoneg = bp->autoneg;
3908 advertising = bp->advertising;
3909
Michael Chan239cd342007-10-17 19:26:15 -07003910 if (bp->phy_port == PORT_TP) {
3911 bp->autoneg = AUTONEG_SPEED;
3912 bp->advertising = ADVERTISED_10baseT_Half |
3913 ADVERTISED_10baseT_Full |
3914 ADVERTISED_100baseT_Half |
3915 ADVERTISED_100baseT_Full |
3916 ADVERTISED_Autoneg;
3917 }
Michael Chanb6016b72005-05-26 13:03:09 -07003918
Michael Chan239cd342007-10-17 19:26:15 -07003919 spin_lock_bh(&bp->phy_lock);
3920 bnx2_setup_phy(bp, bp->phy_port);
3921 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003922
3923 bp->autoneg = autoneg;
3924 bp->advertising = advertising;
3925
Benjamin Li5fcaed02008-07-14 22:39:52 -07003926 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003927
3928 val = REG_RD(bp, BNX2_EMAC_MODE);
3929
3930 /* Enable port mode. */
3931 val &= ~BNX2_EMAC_MODE_PORT;
Michael Chan239cd342007-10-17 19:26:15 -07003932 val |= BNX2_EMAC_MODE_MPKT_RCVD |
Michael Chanb6016b72005-05-26 13:03:09 -07003933 BNX2_EMAC_MODE_ACPI_RCVD |
Michael Chanb6016b72005-05-26 13:03:09 -07003934 BNX2_EMAC_MODE_MPKT;
Michael Chan239cd342007-10-17 19:26:15 -07003935 if (bp->phy_port == PORT_TP)
3936 val |= BNX2_EMAC_MODE_PORT_MII;
3937 else {
3938 val |= BNX2_EMAC_MODE_PORT_GMII;
3939 if (bp->line_speed == SPEED_2500)
3940 val |= BNX2_EMAC_MODE_25G_MODE;
3941 }
Michael Chanb6016b72005-05-26 13:03:09 -07003942
3943 REG_WR(bp, BNX2_EMAC_MODE, val);
3944
3945 /* receive all multicast */
3946 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3947 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3948 0xffffffff);
3949 }
3950 REG_WR(bp, BNX2_EMAC_RX_MODE,
3951 BNX2_EMAC_RX_MODE_SORT_MODE);
3952
3953 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3954 BNX2_RPM_SORT_USER0_MC_EN;
3955 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3956 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3957 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3958 BNX2_RPM_SORT_USER0_ENA);
3959
3960 /* Need to enable EMAC and RPM for WOL. */
3961 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3962 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3963 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3964 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3965
3966 val = REG_RD(bp, BNX2_RPM_CONFIG);
3967 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3968 REG_WR(bp, BNX2_RPM_CONFIG, val);
3969
3970 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3971 }
3972 else {
3973 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3974 }
3975
David S. Millerf86e82f2008-01-21 17:15:40 -08003976 if (!(bp->flags & BNX2_FLAG_NO_WOL))
Michael Chana2f13892008-07-14 22:38:23 -07003977 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3978 1, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003979
3980 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3981 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3982 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3983
3984 if (bp->wol)
3985 pmcsr |= 3;
3986 }
3987 else {
3988 pmcsr |= 3;
3989 }
3990 if (bp->wol) {
3991 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3992 }
3993 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3994 pmcsr);
3995
3996 /* No more memory access after this point until
3997 * device is brought back to D0.
3998 */
3999 udelay(50);
4000 break;
4001 }
4002 default:
4003 return -EINVAL;
4004 }
4005 return 0;
4006}
4007
4008static int
4009bnx2_acquire_nvram_lock(struct bnx2 *bp)
4010{
4011 u32 val;
4012 int j;
4013
4014 /* Request access to the flash interface. */
4015 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4016 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4017 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4018 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4019 break;
4020
4021 udelay(5);
4022 }
4023
4024 if (j >= NVRAM_TIMEOUT_COUNT)
4025 return -EBUSY;
4026
4027 return 0;
4028}
4029
4030static int
4031bnx2_release_nvram_lock(struct bnx2 *bp)
4032{
4033 int j;
4034 u32 val;
4035
4036 /* Relinquish nvram interface. */
4037 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4038
4039 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4040 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4041 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4042 break;
4043
4044 udelay(5);
4045 }
4046
4047 if (j >= NVRAM_TIMEOUT_COUNT)
4048 return -EBUSY;
4049
4050 return 0;
4051}
4052
4053
4054static int
4055bnx2_enable_nvram_write(struct bnx2 *bp)
4056{
4057 u32 val;
4058
4059 val = REG_RD(bp, BNX2_MISC_CFG);
4060 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4061
Michael Chane30372c2007-07-16 18:26:23 -07004062 if (bp->flash_info->flags & BNX2_NV_WREN) {
Michael Chanb6016b72005-05-26 13:03:09 -07004063 int j;
4064
4065 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4066 REG_WR(bp, BNX2_NVM_COMMAND,
4067 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4068
4069 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4070 udelay(5);
4071
4072 val = REG_RD(bp, BNX2_NVM_COMMAND);
4073 if (val & BNX2_NVM_COMMAND_DONE)
4074 break;
4075 }
4076
4077 if (j >= NVRAM_TIMEOUT_COUNT)
4078 return -EBUSY;
4079 }
4080 return 0;
4081}
4082
4083static void
4084bnx2_disable_nvram_write(struct bnx2 *bp)
4085{
4086 u32 val;
4087
4088 val = REG_RD(bp, BNX2_MISC_CFG);
4089 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4090}
4091
4092
4093static void
4094bnx2_enable_nvram_access(struct bnx2 *bp)
4095{
4096 u32 val;
4097
4098 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4099 /* Enable both bits, even on read. */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004100 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
Michael Chanb6016b72005-05-26 13:03:09 -07004101 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4102}
4103
4104static void
4105bnx2_disable_nvram_access(struct bnx2 *bp)
4106{
4107 u32 val;
4108
4109 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4110 /* Disable both bits, even after read. */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004111 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
Michael Chanb6016b72005-05-26 13:03:09 -07004112 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4113 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4114}
4115
4116static int
4117bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4118{
4119 u32 cmd;
4120 int j;
4121
Michael Chane30372c2007-07-16 18:26:23 -07004122 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
Michael Chanb6016b72005-05-26 13:03:09 -07004123 /* Buffered flash, no erase needed */
4124 return 0;
4125
4126 /* Build an erase command */
4127 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4128 BNX2_NVM_COMMAND_DOIT;
4129
4130 /* Need to clear DONE bit separately. */
4131 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4132
4133 /* Address of the NVRAM to read from. */
4134 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4135
4136 /* Issue an erase command. */
4137 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4138
4139 /* Wait for completion. */
4140 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4141 u32 val;
4142
4143 udelay(5);
4144
4145 val = REG_RD(bp, BNX2_NVM_COMMAND);
4146 if (val & BNX2_NVM_COMMAND_DONE)
4147 break;
4148 }
4149
4150 if (j >= NVRAM_TIMEOUT_COUNT)
4151 return -EBUSY;
4152
4153 return 0;
4154}
4155
4156static int
4157bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4158{
4159 u32 cmd;
4160 int j;
4161
4162 /* Build the command word. */
4163 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4164
Michael Chane30372c2007-07-16 18:26:23 -07004165 /* Calculate an offset of a buffered flash, not needed for 5709. */
4166 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
Michael Chanb6016b72005-05-26 13:03:09 -07004167 offset = ((offset / bp->flash_info->page_size) <<
4168 bp->flash_info->page_bits) +
4169 (offset % bp->flash_info->page_size);
4170 }
4171
4172 /* Need to clear DONE bit separately. */
4173 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4174
4175 /* Address of the NVRAM to read from. */
4176 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4177
4178 /* Issue a read command. */
4179 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4180
4181 /* Wait for completion. */
4182 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4183 u32 val;
4184
4185 udelay(5);
4186
4187 val = REG_RD(bp, BNX2_NVM_COMMAND);
4188 if (val & BNX2_NVM_COMMAND_DONE) {
Al Virob491edd2007-12-22 19:44:51 +00004189 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4190 memcpy(ret_val, &v, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004191 break;
4192 }
4193 }
4194 if (j >= NVRAM_TIMEOUT_COUNT)
4195 return -EBUSY;
4196
4197 return 0;
4198}
4199
4200
4201static int
4202bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4203{
Al Virob491edd2007-12-22 19:44:51 +00004204 u32 cmd;
4205 __be32 val32;
Michael Chanb6016b72005-05-26 13:03:09 -07004206 int j;
4207
4208 /* Build the command word. */
4209 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4210
Michael Chane30372c2007-07-16 18:26:23 -07004211 /* Calculate an offset of a buffered flash, not needed for 5709. */
4212 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
Michael Chanb6016b72005-05-26 13:03:09 -07004213 offset = ((offset / bp->flash_info->page_size) <<
4214 bp->flash_info->page_bits) +
4215 (offset % bp->flash_info->page_size);
4216 }
4217
4218 /* Need to clear DONE bit separately. */
4219 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4220
4221 memcpy(&val32, val, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004222
4223 /* Write the data. */
Al Virob491edd2007-12-22 19:44:51 +00004224 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
Michael Chanb6016b72005-05-26 13:03:09 -07004225
4226 /* Address of the NVRAM to write to. */
4227 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4228
4229 /* Issue the write command. */
4230 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4231
4232 /* Wait for completion. */
4233 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4234 udelay(5);
4235
4236 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4237 break;
4238 }
4239 if (j >= NVRAM_TIMEOUT_COUNT)
4240 return -EBUSY;
4241
4242 return 0;
4243}
4244
4245static int
4246bnx2_init_nvram(struct bnx2 *bp)
4247{
4248 u32 val;
Michael Chane30372c2007-07-16 18:26:23 -07004249 int j, entry_count, rc = 0;
Michael Chan0ced9d02009-08-21 16:20:49 +00004250 const struct flash_spec *flash;
Michael Chanb6016b72005-05-26 13:03:09 -07004251
Michael Chane30372c2007-07-16 18:26:23 -07004252 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4253 bp->flash_info = &flash_5709;
4254 goto get_flash_size;
4255 }
4256
Michael Chanb6016b72005-05-26 13:03:09 -07004257 /* Determine the selected interface. */
4258 val = REG_RD(bp, BNX2_NVM_CFG1);
4259
Denis Chengff8ac602007-09-02 18:30:18 +08004260 entry_count = ARRAY_SIZE(flash_table);
Michael Chanb6016b72005-05-26 13:03:09 -07004261
Michael Chanb6016b72005-05-26 13:03:09 -07004262 if (val & 0x40000000) {
4263
4264 /* Flash interface has been reconfigured */
4265 for (j = 0, flash = &flash_table[0]; j < entry_count;
Michael Chan37137702005-11-04 08:49:17 -08004266 j++, flash++) {
4267 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4268 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004269 bp->flash_info = flash;
4270 break;
4271 }
4272 }
4273 }
4274 else {
Michael Chan37137702005-11-04 08:49:17 -08004275 u32 mask;
Michael Chanb6016b72005-05-26 13:03:09 -07004276 /* Not yet been reconfigured */
4277
Michael Chan37137702005-11-04 08:49:17 -08004278 if (val & (1 << 23))
4279 mask = FLASH_BACKUP_STRAP_MASK;
4280 else
4281 mask = FLASH_STRAP_MASK;
4282
Michael Chanb6016b72005-05-26 13:03:09 -07004283 for (j = 0, flash = &flash_table[0]; j < entry_count;
4284 j++, flash++) {
4285
Michael Chan37137702005-11-04 08:49:17 -08004286 if ((val & mask) == (flash->strapping & mask)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004287 bp->flash_info = flash;
4288
4289 /* Request access to the flash interface. */
4290 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4291 return rc;
4292
4293 /* Enable access to flash interface */
4294 bnx2_enable_nvram_access(bp);
4295
4296 /* Reconfigure the flash interface */
4297 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4298 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4299 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4300 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4301
4302 /* Disable access to flash interface */
4303 bnx2_disable_nvram_access(bp);
4304 bnx2_release_nvram_lock(bp);
4305
4306 break;
4307 }
4308 }
4309 } /* if (val & 0x40000000) */
4310
4311 if (j == entry_count) {
4312 bp->flash_info = NULL;
John W. Linville2f23c522005-11-10 12:57:33 -08004313 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
Michael Chan1122db72006-01-23 16:11:42 -08004314 return -ENODEV;
Michael Chanb6016b72005-05-26 13:03:09 -07004315 }
4316
Michael Chane30372c2007-07-16 18:26:23 -07004317get_flash_size:
Michael Chan2726d6e2008-01-29 21:35:05 -08004318 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
Michael Chan1122db72006-01-23 16:11:42 -08004319 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4320 if (val)
4321 bp->flash_size = val;
4322 else
4323 bp->flash_size = bp->flash_info->total_size;
4324
Michael Chanb6016b72005-05-26 13:03:09 -07004325 return rc;
4326}
4327
4328static int
4329bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4330 int buf_size)
4331{
4332 int rc = 0;
4333 u32 cmd_flags, offset32, len32, extra;
4334
4335 if (buf_size == 0)
4336 return 0;
4337
4338 /* Request access to the flash interface. */
4339 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4340 return rc;
4341
4342 /* Enable access to flash interface */
4343 bnx2_enable_nvram_access(bp);
4344
4345 len32 = buf_size;
4346 offset32 = offset;
4347 extra = 0;
4348
4349 cmd_flags = 0;
4350
4351 if (offset32 & 3) {
4352 u8 buf[4];
4353 u32 pre_len;
4354
4355 offset32 &= ~3;
4356 pre_len = 4 - (offset & 3);
4357
4358 if (pre_len >= len32) {
4359 pre_len = len32;
4360 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4361 BNX2_NVM_COMMAND_LAST;
4362 }
4363 else {
4364 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4365 }
4366
4367 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4368
4369 if (rc)
4370 return rc;
4371
4372 memcpy(ret_buf, buf + (offset & 3), pre_len);
4373
4374 offset32 += 4;
4375 ret_buf += pre_len;
4376 len32 -= pre_len;
4377 }
4378 if (len32 & 3) {
4379 extra = 4 - (len32 & 3);
4380 len32 = (len32 + 4) & ~3;
4381 }
4382
4383 if (len32 == 4) {
4384 u8 buf[4];
4385
4386 if (cmd_flags)
4387 cmd_flags = BNX2_NVM_COMMAND_LAST;
4388 else
4389 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4390 BNX2_NVM_COMMAND_LAST;
4391
4392 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4393
4394 memcpy(ret_buf, buf, 4 - extra);
4395 }
4396 else if (len32 > 0) {
4397 u8 buf[4];
4398
4399 /* Read the first word. */
4400 if (cmd_flags)
4401 cmd_flags = 0;
4402 else
4403 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4404
4405 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4406
4407 /* Advance to the next dword. */
4408 offset32 += 4;
4409 ret_buf += 4;
4410 len32 -= 4;
4411
4412 while (len32 > 4 && rc == 0) {
4413 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4414
4415 /* Advance to the next dword. */
4416 offset32 += 4;
4417 ret_buf += 4;
4418 len32 -= 4;
4419 }
4420
4421 if (rc)
4422 return rc;
4423
4424 cmd_flags = BNX2_NVM_COMMAND_LAST;
4425 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4426
4427 memcpy(ret_buf, buf, 4 - extra);
4428 }
4429
4430 /* Disable access to flash interface */
4431 bnx2_disable_nvram_access(bp);
4432
4433 bnx2_release_nvram_lock(bp);
4434
4435 return rc;
4436}
4437
4438static int
4439bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4440 int buf_size)
4441{
4442 u32 written, offset32, len32;
Michael Chane6be7632007-01-08 19:56:13 -08004443 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07004444 int rc = 0;
4445 int align_start, align_end;
4446
4447 buf = data_buf;
4448 offset32 = offset;
4449 len32 = buf_size;
4450 align_start = align_end = 0;
4451
4452 if ((align_start = (offset32 & 3))) {
4453 offset32 &= ~3;
Michael Chanc8738792007-03-30 14:53:06 -07004454 len32 += align_start;
4455 if (len32 < 4)
4456 len32 = 4;
Michael Chanb6016b72005-05-26 13:03:09 -07004457 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4458 return rc;
4459 }
4460
4461 if (len32 & 3) {
Michael Chanc8738792007-03-30 14:53:06 -07004462 align_end = 4 - (len32 & 3);
4463 len32 += align_end;
4464 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4465 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004466 }
4467
4468 if (align_start || align_end) {
Michael Chane6be7632007-01-08 19:56:13 -08004469 align_buf = kmalloc(len32, GFP_KERNEL);
4470 if (align_buf == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07004471 return -ENOMEM;
4472 if (align_start) {
Michael Chane6be7632007-01-08 19:56:13 -08004473 memcpy(align_buf, start, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004474 }
4475 if (align_end) {
Michael Chane6be7632007-01-08 19:56:13 -08004476 memcpy(align_buf + len32 - 4, end, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004477 }
Michael Chane6be7632007-01-08 19:56:13 -08004478 memcpy(align_buf + align_start, data_buf, buf_size);
4479 buf = align_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07004480 }
4481
Michael Chane30372c2007-07-16 18:26:23 -07004482 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanae181bc2006-05-22 16:39:20 -07004483 flash_buffer = kmalloc(264, GFP_KERNEL);
4484 if (flash_buffer == NULL) {
4485 rc = -ENOMEM;
4486 goto nvram_write_end;
4487 }
4488 }
4489
Michael Chanb6016b72005-05-26 13:03:09 -07004490 written = 0;
4491 while ((written < len32) && (rc == 0)) {
4492 u32 page_start, page_end, data_start, data_end;
4493 u32 addr, cmd_flags;
4494 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07004495
4496 /* Find the page_start addr */
4497 page_start = offset32 + written;
4498 page_start -= (page_start % bp->flash_info->page_size);
4499 /* Find the page_end addr */
4500 page_end = page_start + bp->flash_info->page_size;
4501 /* Find the data_start addr */
4502 data_start = (written == 0) ? offset32 : page_start;
4503 /* Find the data_end addr */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004504 data_end = (page_end > offset32 + len32) ?
Michael Chanb6016b72005-05-26 13:03:09 -07004505 (offset32 + len32) : page_end;
4506
4507 /* Request access to the flash interface. */
4508 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4509 goto nvram_write_end;
4510
4511 /* Enable access to flash interface */
4512 bnx2_enable_nvram_access(bp);
4513
4514 cmd_flags = BNX2_NVM_COMMAND_FIRST;
Michael Chane30372c2007-07-16 18:26:23 -07004515 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004516 int j;
4517
4518 /* Read the whole page into the buffer
4519 * (non-buffer flash only) */
4520 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4521 if (j == (bp->flash_info->page_size - 4)) {
4522 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4523 }
4524 rc = bnx2_nvram_read_dword(bp,
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004525 page_start + j,
4526 &flash_buffer[j],
Michael Chanb6016b72005-05-26 13:03:09 -07004527 cmd_flags);
4528
4529 if (rc)
4530 goto nvram_write_end;
4531
4532 cmd_flags = 0;
4533 }
4534 }
4535
4536 /* Enable writes to flash interface (unlock write-protect) */
4537 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4538 goto nvram_write_end;
4539
Michael Chanb6016b72005-05-26 13:03:09 -07004540 /* Loop to write back the buffer data from page_start to
4541 * data_start */
4542 i = 0;
Michael Chane30372c2007-07-16 18:26:23 -07004543 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanc8738792007-03-30 14:53:06 -07004544 /* Erase the page */
4545 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4546 goto nvram_write_end;
4547
4548 /* Re-enable the write again for the actual write */
4549 bnx2_enable_nvram_write(bp);
4550
Michael Chanb6016b72005-05-26 13:03:09 -07004551 for (addr = page_start; addr < data_start;
4552 addr += 4, i += 4) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004553
Michael Chanb6016b72005-05-26 13:03:09 -07004554 rc = bnx2_nvram_write_dword(bp, addr,
4555 &flash_buffer[i], cmd_flags);
4556
4557 if (rc != 0)
4558 goto nvram_write_end;
4559
4560 cmd_flags = 0;
4561 }
4562 }
4563
4564 /* Loop to write the new data from data_start to data_end */
Michael Chanbae25762006-05-22 16:38:38 -07004565 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
Michael Chanb6016b72005-05-26 13:03:09 -07004566 if ((addr == page_end - 4) ||
Michael Chane30372c2007-07-16 18:26:23 -07004567 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
Michael Chanb6016b72005-05-26 13:03:09 -07004568 (addr == data_end - 4))) {
4569
4570 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4571 }
4572 rc = bnx2_nvram_write_dword(bp, addr, buf,
4573 cmd_flags);
4574
4575 if (rc != 0)
4576 goto nvram_write_end;
4577
4578 cmd_flags = 0;
4579 buf += 4;
4580 }
4581
4582 /* Loop to write back the buffer data from data_end
4583 * to page_end */
Michael Chane30372c2007-07-16 18:26:23 -07004584 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004585 for (addr = data_end; addr < page_end;
4586 addr += 4, i += 4) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004587
Michael Chanb6016b72005-05-26 13:03:09 -07004588 if (addr == page_end-4) {
4589 cmd_flags = BNX2_NVM_COMMAND_LAST;
4590 }
4591 rc = bnx2_nvram_write_dword(bp, addr,
4592 &flash_buffer[i], cmd_flags);
4593
4594 if (rc != 0)
4595 goto nvram_write_end;
4596
4597 cmd_flags = 0;
4598 }
4599 }
4600
4601 /* Disable writes to flash interface (lock write-protect) */
4602 bnx2_disable_nvram_write(bp);
4603
4604 /* Disable access to flash interface */
4605 bnx2_disable_nvram_access(bp);
4606 bnx2_release_nvram_lock(bp);
4607
4608 /* Increment written */
4609 written += data_end - data_start;
4610 }
4611
4612nvram_write_end:
Michael Chane6be7632007-01-08 19:56:13 -08004613 kfree(flash_buffer);
4614 kfree(align_buf);
Michael Chanb6016b72005-05-26 13:03:09 -07004615 return rc;
4616}
4617
Michael Chan0d8a6572007-07-07 22:49:43 -07004618static void
Michael Chan7c62e832008-07-14 22:39:03 -07004619bnx2_init_fw_cap(struct bnx2 *bp)
Michael Chan0d8a6572007-07-07 22:49:43 -07004620{
Michael Chan7c62e832008-07-14 22:39:03 -07004621 u32 val, sig = 0;
Michael Chan0d8a6572007-07-07 22:49:43 -07004622
Michael Chan583c28e2008-01-21 19:51:35 -08004623 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
Michael Chan7c62e832008-07-14 22:39:03 -07004624 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4625
4626 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4627 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
Michael Chan0d8a6572007-07-07 22:49:43 -07004628
Michael Chan2726d6e2008-01-29 21:35:05 -08004629 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
Michael Chan0d8a6572007-07-07 22:49:43 -07004630 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4631 return;
4632
Michael Chan7c62e832008-07-14 22:39:03 -07004633 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4634 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4635 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4636 }
4637
4638 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4639 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4640 u32 link;
4641
Michael Chan583c28e2008-01-21 19:51:35 -08004642 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
Michael Chan0d8a6572007-07-07 22:49:43 -07004643
Michael Chan7c62e832008-07-14 22:39:03 -07004644 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4645 if (link & BNX2_LINK_STATUS_SERDES_LINK)
Michael Chan0d8a6572007-07-07 22:49:43 -07004646 bp->phy_port = PORT_FIBRE;
4647 else
4648 bp->phy_port = PORT_TP;
Michael Chan489310a2007-10-10 16:16:31 -07004649
Michael Chan7c62e832008-07-14 22:39:03 -07004650 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4651 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
Michael Chan0d8a6572007-07-07 22:49:43 -07004652 }
Michael Chan7c62e832008-07-14 22:39:03 -07004653
4654 if (netif_running(bp->dev) && sig)
4655 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
Michael Chan0d8a6572007-07-07 22:49:43 -07004656}
4657
Michael Chanb4b36042007-12-20 19:59:30 -08004658static void
4659bnx2_setup_msix_tbl(struct bnx2 *bp)
4660{
4661 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4662
4663 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4664 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4665}
4666
Michael Chanb6016b72005-05-26 13:03:09 -07004667static int
4668bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4669{
4670 u32 val;
4671 int i, rc = 0;
Michael Chan489310a2007-10-10 16:16:31 -07004672 u8 old_port;
Michael Chanb6016b72005-05-26 13:03:09 -07004673
4674 /* Wait for the current PCI transaction to complete before
4675 * issuing a reset. */
4676 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4677 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4678 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4679 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4680 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4681 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4682 udelay(5);
4683
Michael Chanb090ae22006-01-23 16:07:10 -08004684 /* Wait for the firmware to tell us it is ok to issue a reset. */
Michael Chana2f13892008-07-14 22:38:23 -07004685 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
Michael Chanb090ae22006-01-23 16:07:10 -08004686
Michael Chanb6016b72005-05-26 13:03:09 -07004687 /* Deposit a driver reset signature so the firmware knows that
4688 * this is a soft reset. */
Michael Chan2726d6e2008-01-29 21:35:05 -08004689 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4690 BNX2_DRV_RESET_SIGNATURE_MAGIC);
Michael Chanb6016b72005-05-26 13:03:09 -07004691
Michael Chanb6016b72005-05-26 13:03:09 -07004692 /* Do a dummy read to force the chip to complete all current transaction
4693 * before we issue a reset. */
4694 val = REG_RD(bp, BNX2_MISC_ID);
4695
Michael Chan234754d2006-11-19 14:11:41 -08004696 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4697 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4698 REG_RD(bp, BNX2_MISC_COMMAND);
4699 udelay(5);
Michael Chanb6016b72005-05-26 13:03:09 -07004700
Michael Chan234754d2006-11-19 14:11:41 -08004701 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4702 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
Michael Chanb6016b72005-05-26 13:03:09 -07004703
Michael Chan234754d2006-11-19 14:11:41 -08004704 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004705
Michael Chan234754d2006-11-19 14:11:41 -08004706 } else {
4707 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4708 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4709 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4710
4711 /* Chip reset. */
4712 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4713
Michael Chan594a9df2007-08-28 15:39:42 -07004714 /* Reading back any register after chip reset will hang the
4715 * bus on 5706 A0 and A1. The msleep below provides plenty
4716 * of margin for write posting.
4717 */
Michael Chan234754d2006-11-19 14:11:41 -08004718 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
Arjan van de Ven8e545882007-08-28 14:34:43 -07004719 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4720 msleep(20);
Michael Chanb6016b72005-05-26 13:03:09 -07004721
Michael Chan234754d2006-11-19 14:11:41 -08004722 /* Reset takes approximate 30 usec */
4723 for (i = 0; i < 10; i++) {
4724 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4725 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4726 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4727 break;
4728 udelay(10);
4729 }
4730
4731 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4732 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4733 printk(KERN_ERR PFX "Chip reset did not complete\n");
4734 return -EBUSY;
4735 }
Michael Chanb6016b72005-05-26 13:03:09 -07004736 }
4737
4738 /* Make sure byte swapping is properly configured. */
4739 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4740 if (val != 0x01020304) {
4741 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4742 return -ENODEV;
4743 }
4744
Michael Chanb6016b72005-05-26 13:03:09 -07004745 /* Wait for the firmware to finish its initialization. */
Michael Chana2f13892008-07-14 22:38:23 -07004746 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
Michael Chanb090ae22006-01-23 16:07:10 -08004747 if (rc)
4748 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004749
Michael Chan0d8a6572007-07-07 22:49:43 -07004750 spin_lock_bh(&bp->phy_lock);
Michael Chan489310a2007-10-10 16:16:31 -07004751 old_port = bp->phy_port;
Michael Chan7c62e832008-07-14 22:39:03 -07004752 bnx2_init_fw_cap(bp);
Michael Chan583c28e2008-01-21 19:51:35 -08004753 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4754 old_port != bp->phy_port)
Michael Chan0d8a6572007-07-07 22:49:43 -07004755 bnx2_set_default_remote_link(bp);
4756 spin_unlock_bh(&bp->phy_lock);
4757
Michael Chanb6016b72005-05-26 13:03:09 -07004758 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4759 /* Adjust the voltage regular to two steps lower. The default
4760 * of this register is 0x0000000e. */
4761 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4762
4763 /* Remove bad rbuf memory from the free pool. */
4764 rc = bnx2_alloc_bad_rbuf(bp);
4765 }
4766
David S. Millerf86e82f2008-01-21 17:15:40 -08004767 if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chanb4b36042007-12-20 19:59:30 -08004768 bnx2_setup_msix_tbl(bp);
4769
Michael Chanb6016b72005-05-26 13:03:09 -07004770 return rc;
4771}
4772
4773static int
4774bnx2_init_chip(struct bnx2 *bp)
4775{
Michael Chand8026d92008-11-12 16:02:20 -08004776 u32 val, mtu;
Michael Chanb4b36042007-12-20 19:59:30 -08004777 int rc, i;
Michael Chanb6016b72005-05-26 13:03:09 -07004778
4779 /* Make sure the interrupt is not active. */
4780 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4781
4782 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4783 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4784#ifdef __BIG_ENDIAN
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004785 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
Michael Chanb6016b72005-05-26 13:03:09 -07004786#endif
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004787 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
Michael Chanb6016b72005-05-26 13:03:09 -07004788 DMA_READ_CHANS << 12 |
4789 DMA_WRITE_CHANS << 16;
4790
4791 val |= (0x2 << 20) | (1 << 11);
4792
David S. Millerf86e82f2008-01-21 17:15:40 -08004793 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
Michael Chanb6016b72005-05-26 13:03:09 -07004794 val |= (1 << 23);
4795
4796 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
David S. Millerf86e82f2008-01-21 17:15:40 -08004797 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
Michael Chanb6016b72005-05-26 13:03:09 -07004798 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4799
4800 REG_WR(bp, BNX2_DMA_CONFIG, val);
4801
4802 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4803 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4804 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4805 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4806 }
4807
David S. Millerf86e82f2008-01-21 17:15:40 -08004808 if (bp->flags & BNX2_FLAG_PCIX) {
Michael Chanb6016b72005-05-26 13:03:09 -07004809 u16 val16;
4810
4811 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4812 &val16);
4813 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4814 val16 & ~PCI_X_CMD_ERO);
4815 }
4816
4817 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4818 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4819 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4820 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4821
4822 /* Initialize context mapping and zero out the quick contexts. The
4823 * context block must have already been enabled. */
Michael Chan641bdcd2007-06-04 21:22:24 -07004824 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4825 rc = bnx2_init_5709_context(bp);
4826 if (rc)
4827 return rc;
4828 } else
Michael Chan59b47d82006-11-19 14:10:45 -08004829 bnx2_init_context(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07004830
Michael Chanfba9fe92006-06-12 22:21:25 -07004831 if ((rc = bnx2_init_cpus(bp)) != 0)
4832 return rc;
4833
Michael Chanb6016b72005-05-26 13:03:09 -07004834 bnx2_init_nvram(bp);
4835
Benjamin Li5fcaed02008-07-14 22:39:52 -07004836 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07004837
4838 val = REG_RD(bp, BNX2_MQ_CONFIG);
4839 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4840 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
Michael Chan4edd4732009-06-08 18:14:42 -07004841 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4842 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4843 if (CHIP_REV(bp) == CHIP_REV_Ax)
4844 val |= BNX2_MQ_CONFIG_HALT_DIS;
4845 }
Michael Chan68c9f752007-04-24 15:35:53 -07004846
Michael Chanb6016b72005-05-26 13:03:09 -07004847 REG_WR(bp, BNX2_MQ_CONFIG, val);
4848
4849 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4850 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4851 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4852
4853 val = (BCM_PAGE_BITS - 8) << 24;
4854 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4855
4856 /* Configure page size. */
4857 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4858 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4859 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4860 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4861
4862 val = bp->mac_addr[0] +
4863 (bp->mac_addr[1] << 8) +
4864 (bp->mac_addr[2] << 16) +
4865 bp->mac_addr[3] +
4866 (bp->mac_addr[4] << 8) +
4867 (bp->mac_addr[5] << 16);
4868 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4869
4870 /* Program the MTU. Also include 4 bytes for CRC32. */
Michael Chand8026d92008-11-12 16:02:20 -08004871 mtu = bp->dev->mtu;
4872 val = mtu + ETH_HLEN + ETH_FCS_LEN;
Michael Chanb6016b72005-05-26 13:03:09 -07004873 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4874 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4875 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4876
Michael Chand8026d92008-11-12 16:02:20 -08004877 if (mtu < 1500)
4878 mtu = 1500;
4879
4880 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4881 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4882 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4883
Michael Chan155d5562009-08-21 16:20:43 +00004884 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
Michael Chanb4b36042007-12-20 19:59:30 -08004885 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4886 bp->bnx2_napi[i].last_status_idx = 0;
4887
Michael Chanefba0182008-12-03 00:36:15 -08004888 bp->idle_chk_status_idx = 0xffff;
4889
Michael Chanb6016b72005-05-26 13:03:09 -07004890 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4891
4892 /* Set up how to generate a link change interrupt. */
4893 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4894
4895 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4896 (u64) bp->status_blk_mapping & 0xffffffff);
4897 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4898
4899 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4900 (u64) bp->stats_blk_mapping & 0xffffffff);
4901 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4902 (u64) bp->stats_blk_mapping >> 32);
4903
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004904 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
Michael Chanb6016b72005-05-26 13:03:09 -07004905 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4906
4907 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4908 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4909
4910 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4911 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4912
4913 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4914
4915 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4916
4917 REG_WR(bp, BNX2_HC_COM_TICKS,
4918 (bp->com_ticks_int << 16) | bp->com_ticks);
4919
4920 REG_WR(bp, BNX2_HC_CMD_TICKS,
4921 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4922
Michael Chan61d9e3f2009-08-21 16:20:46 +00004923 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
Michael Chan02537b062007-06-04 21:24:07 -07004924 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4925 else
Michael Chan7ea69202007-07-16 18:27:10 -07004926 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
Michael Chanb6016b72005-05-26 13:03:09 -07004927 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4928
4929 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
Michael Chan8e6a72c2007-05-03 13:24:48 -07004930 val = BNX2_HC_CONFIG_COLLECT_STATS;
Michael Chanb6016b72005-05-26 13:03:09 -07004931 else {
Michael Chan8e6a72c2007-05-03 13:24:48 -07004932 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4933 BNX2_HC_CONFIG_COLLECT_STATS;
Michael Chanb6016b72005-05-26 13:03:09 -07004934 }
4935
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004936 if (bp->irq_nvecs > 1) {
Michael Chanc76c0472007-12-20 20:01:19 -08004937 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4938 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4939
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004940 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4941 }
4942
4943 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
Michael Chancf7474a2009-08-21 16:20:48 +00004944 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004945
4946 REG_WR(bp, BNX2_HC_CONFIG, val);
4947
4948 for (i = 1; i < bp->irq_nvecs; i++) {
4949 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4950 BNX2_HC_SB_CONFIG_1;
4951
Michael Chan6f743ca2008-01-29 21:34:08 -08004952 REG_WR(bp, base,
Michael Chanc76c0472007-12-20 20:01:19 -08004953 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004954 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
Michael Chanc76c0472007-12-20 20:01:19 -08004955 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4956
Michael Chan6f743ca2008-01-29 21:34:08 -08004957 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
Michael Chanc76c0472007-12-20 20:01:19 -08004958 (bp->tx_quick_cons_trip_int << 16) |
4959 bp->tx_quick_cons_trip);
4960
Michael Chan6f743ca2008-01-29 21:34:08 -08004961 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
Michael Chanc76c0472007-12-20 20:01:19 -08004962 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4963
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004964 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4965 (bp->rx_quick_cons_trip_int << 16) |
4966 bp->rx_quick_cons_trip);
4967
4968 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4969 (bp->rx_ticks_int << 16) | bp->rx_ticks);
Michael Chanc76c0472007-12-20 20:01:19 -08004970 }
4971
Michael Chanb6016b72005-05-26 13:03:09 -07004972 /* Clear internal stats counters. */
4973 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4974
Michael Chanda3e4fb2007-05-03 13:24:23 -07004975 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
Michael Chanb6016b72005-05-26 13:03:09 -07004976
4977 /* Initialize the receive filter. */
4978 bnx2_set_rx_mode(bp->dev);
4979
Michael Chan0aa38df2007-06-04 21:23:06 -07004980 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4981 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4982 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4983 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4984 }
Michael Chanb090ae22006-01-23 16:07:10 -08004985 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
Michael Chana2f13892008-07-14 22:38:23 -07004986 1, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07004987
Michael Chandf149d72007-07-07 22:51:36 -07004988 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
Michael Chanb6016b72005-05-26 13:03:09 -07004989 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4990
4991 udelay(20);
4992
Michael Chanbf5295b2006-03-23 01:11:56 -08004993 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4994
Michael Chanb090ae22006-01-23 16:07:10 -08004995 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004996}
4997
Michael Chan59b47d82006-11-19 14:10:45 -08004998static void
Michael Chanc76c0472007-12-20 20:01:19 -08004999bnx2_clear_ring_states(struct bnx2 *bp)
5000{
5001 struct bnx2_napi *bnapi;
Michael Chan35e90102008-06-19 16:37:42 -07005002 struct bnx2_tx_ring_info *txr;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005003 struct bnx2_rx_ring_info *rxr;
Michael Chanc76c0472007-12-20 20:01:19 -08005004 int i;
5005
5006 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5007 bnapi = &bp->bnx2_napi[i];
Michael Chan35e90102008-06-19 16:37:42 -07005008 txr = &bnapi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005009 rxr = &bnapi->rx_ring;
Michael Chanc76c0472007-12-20 20:01:19 -08005010
Michael Chan35e90102008-06-19 16:37:42 -07005011 txr->tx_cons = 0;
5012 txr->hw_tx_cons = 0;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005013 rxr->rx_prod_bseq = 0;
5014 rxr->rx_prod = 0;
5015 rxr->rx_cons = 0;
5016 rxr->rx_pg_prod = 0;
5017 rxr->rx_pg_cons = 0;
Michael Chanc76c0472007-12-20 20:01:19 -08005018 }
5019}
5020
5021static void
Michael Chan35e90102008-06-19 16:37:42 -07005022bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
Michael Chan59b47d82006-11-19 14:10:45 -08005023{
5024 u32 val, offset0, offset1, offset2, offset3;
Michael Chan62a83132008-01-29 21:35:40 -08005025 u32 cid_addr = GET_CID_ADDR(cid);
Michael Chan59b47d82006-11-19 14:10:45 -08005026
5027 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5028 offset0 = BNX2_L2CTX_TYPE_XI;
5029 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5030 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5031 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5032 } else {
5033 offset0 = BNX2_L2CTX_TYPE;
5034 offset1 = BNX2_L2CTX_CMD_TYPE;
5035 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5036 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5037 }
5038 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
Michael Chan62a83132008-01-29 21:35:40 -08005039 bnx2_ctx_wr(bp, cid_addr, offset0, val);
Michael Chan59b47d82006-11-19 14:10:45 -08005040
5041 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
Michael Chan62a83132008-01-29 21:35:40 -08005042 bnx2_ctx_wr(bp, cid_addr, offset1, val);
Michael Chan59b47d82006-11-19 14:10:45 -08005043
Michael Chan35e90102008-06-19 16:37:42 -07005044 val = (u64) txr->tx_desc_mapping >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08005045 bnx2_ctx_wr(bp, cid_addr, offset2, val);
Michael Chan59b47d82006-11-19 14:10:45 -08005046
Michael Chan35e90102008-06-19 16:37:42 -07005047 val = (u64) txr->tx_desc_mapping & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08005048 bnx2_ctx_wr(bp, cid_addr, offset3, val);
Michael Chan59b47d82006-11-19 14:10:45 -08005049}
Michael Chanb6016b72005-05-26 13:03:09 -07005050
5051static void
Michael Chan35e90102008-06-19 16:37:42 -07005052bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
Michael Chanb6016b72005-05-26 13:03:09 -07005053{
5054 struct tx_bd *txbd;
Michael Chanc76c0472007-12-20 20:01:19 -08005055 u32 cid = TX_CID;
5056 struct bnx2_napi *bnapi;
Michael Chan35e90102008-06-19 16:37:42 -07005057 struct bnx2_tx_ring_info *txr;
Michael Chanc76c0472007-12-20 20:01:19 -08005058
Michael Chan35e90102008-06-19 16:37:42 -07005059 bnapi = &bp->bnx2_napi[ring_num];
5060 txr = &bnapi->tx_ring;
5061
5062 if (ring_num == 0)
5063 cid = TX_CID;
5064 else
5065 cid = TX_TSS_CID + ring_num - 1;
Michael Chanb6016b72005-05-26 13:03:09 -07005066
Michael Chan2f8af122006-08-15 01:39:10 -07005067 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5068
Michael Chan35e90102008-06-19 16:37:42 -07005069 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005070
Michael Chan35e90102008-06-19 16:37:42 -07005071 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5072 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
Michael Chanb6016b72005-05-26 13:03:09 -07005073
Michael Chan35e90102008-06-19 16:37:42 -07005074 txr->tx_prod = 0;
5075 txr->tx_prod_bseq = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005076
Michael Chan35e90102008-06-19 16:37:42 -07005077 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5078 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
Michael Chanb6016b72005-05-26 13:03:09 -07005079
Michael Chan35e90102008-06-19 16:37:42 -07005080 bnx2_init_tx_context(bp, cid, txr);
Michael Chanb6016b72005-05-26 13:03:09 -07005081}
5082
5083static void
Michael Chan5d5d0012007-12-12 11:17:43 -08005084bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5085 int num_rings)
Michael Chanb6016b72005-05-26 13:03:09 -07005086{
Michael Chanb6016b72005-05-26 13:03:09 -07005087 int i;
Michael Chan5d5d0012007-12-12 11:17:43 -08005088 struct rx_bd *rxbd;
Michael Chanb6016b72005-05-26 13:03:09 -07005089
Michael Chan5d5d0012007-12-12 11:17:43 -08005090 for (i = 0; i < num_rings; i++) {
Michael Chan13daffa2006-03-20 17:49:20 -08005091 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07005092
Michael Chan5d5d0012007-12-12 11:17:43 -08005093 rxbd = &rx_ring[i][0];
Michael Chan13daffa2006-03-20 17:49:20 -08005094 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
Michael Chan5d5d0012007-12-12 11:17:43 -08005095 rxbd->rx_bd_len = buf_size;
Michael Chan13daffa2006-03-20 17:49:20 -08005096 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5097 }
Michael Chan5d5d0012007-12-12 11:17:43 -08005098 if (i == (num_rings - 1))
Michael Chan13daffa2006-03-20 17:49:20 -08005099 j = 0;
5100 else
5101 j = i + 1;
Michael Chan5d5d0012007-12-12 11:17:43 -08005102 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5103 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
Michael Chan13daffa2006-03-20 17:49:20 -08005104 }
Michael Chan5d5d0012007-12-12 11:17:43 -08005105}
5106
5107static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07005108bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
Michael Chan5d5d0012007-12-12 11:17:43 -08005109{
5110 int i;
5111 u16 prod, ring_prod;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005112 u32 cid, rx_cid_addr, val;
5113 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5114 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chan5d5d0012007-12-12 11:17:43 -08005115
Michael Chanbb4f98a2008-06-19 16:38:19 -07005116 if (ring_num == 0)
5117 cid = RX_CID;
5118 else
5119 cid = RX_RSS_CID + ring_num - 1;
5120
5121 rx_cid_addr = GET_CID_ADDR(cid);
5122
5123 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
Michael Chan5d5d0012007-12-12 11:17:43 -08005124 bp->rx_buf_use_size, bp->rx_max_ring);
5125
Michael Chanbb4f98a2008-06-19 16:38:19 -07005126 bnx2_init_rx_context(bp, cid);
Michael Chan83e3fc82008-01-29 21:37:17 -08005127
5128 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5129 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5130 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5131 }
5132
Michael Chan62a83132008-01-29 21:35:40 -08005133 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
Michael Chan47bf4242007-12-12 11:19:12 -08005134 if (bp->rx_pg_ring_size) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07005135 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5136 rxr->rx_pg_desc_mapping,
Michael Chan47bf4242007-12-12 11:19:12 -08005137 PAGE_SIZE, bp->rx_max_pg_ring);
5138 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
Michael Chan62a83132008-01-29 21:35:40 -08005139 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5140 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005141 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
Michael Chan47bf4242007-12-12 11:19:12 -08005142
Michael Chanbb4f98a2008-06-19 16:38:19 -07005143 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08005144 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
Michael Chan47bf4242007-12-12 11:19:12 -08005145
Michael Chanbb4f98a2008-06-19 16:38:19 -07005146 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08005147 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
Michael Chan47bf4242007-12-12 11:19:12 -08005148
5149 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5150 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5151 }
Michael Chanb6016b72005-05-26 13:03:09 -07005152
Michael Chanbb4f98a2008-06-19 16:38:19 -07005153 val = (u64) rxr->rx_desc_mapping[0] >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08005154 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
Michael Chanb6016b72005-05-26 13:03:09 -07005155
Michael Chanbb4f98a2008-06-19 16:38:19 -07005156 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08005157 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
Michael Chanb6016b72005-05-26 13:03:09 -07005158
Michael Chanbb4f98a2008-06-19 16:38:19 -07005159 ring_prod = prod = rxr->rx_pg_prod;
Michael Chan47bf4242007-12-12 11:19:12 -08005160 for (i = 0; i < bp->rx_pg_ring_size; i++) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07005161 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
Michael Chan47bf4242007-12-12 11:19:12 -08005162 break;
5163 prod = NEXT_RX_BD(prod);
5164 ring_prod = RX_PG_RING_IDX(prod);
5165 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07005166 rxr->rx_pg_prod = prod;
Michael Chan47bf4242007-12-12 11:19:12 -08005167
Michael Chanbb4f98a2008-06-19 16:38:19 -07005168 ring_prod = prod = rxr->rx_prod;
Michael Chan236b6392006-03-20 17:49:02 -08005169 for (i = 0; i < bp->rx_ring_size; i++) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07005170 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
Michael Chanb6016b72005-05-26 13:03:09 -07005171 break;
Michael Chanb6016b72005-05-26 13:03:09 -07005172 prod = NEXT_RX_BD(prod);
5173 ring_prod = RX_RING_IDX(prod);
5174 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07005175 rxr->rx_prod = prod;
Michael Chanb6016b72005-05-26 13:03:09 -07005176
Michael Chanbb4f98a2008-06-19 16:38:19 -07005177 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5178 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5179 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
Michael Chanb6016b72005-05-26 13:03:09 -07005180
Michael Chanbb4f98a2008-06-19 16:38:19 -07005181 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5182 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5183
5184 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07005185}
5186
Michael Chan35e90102008-06-19 16:37:42 -07005187static void
5188bnx2_init_all_rings(struct bnx2 *bp)
5189{
5190 int i;
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005191 u32 val;
Michael Chan35e90102008-06-19 16:37:42 -07005192
5193 bnx2_clear_ring_states(bp);
5194
5195 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5196 for (i = 0; i < bp->num_tx_rings; i++)
5197 bnx2_init_tx_ring(bp, i);
5198
5199 if (bp->num_tx_rings > 1)
5200 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5201 (TX_TSS_CID << 7));
5202
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005203 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5204 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5205
Michael Chanbb4f98a2008-06-19 16:38:19 -07005206 for (i = 0; i < bp->num_rx_rings; i++)
5207 bnx2_init_rx_ring(bp, i);
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005208
5209 if (bp->num_rx_rings > 1) {
5210 u32 tbl_32;
5211 u8 *tbl = (u8 *) &tbl_32;
5212
5213 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5214 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5215
5216 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5217 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5218 if ((i % 4) == 3)
5219 bnx2_reg_wr_ind(bp,
5220 BNX2_RXP_SCRATCH_RSS_TBL + i,
5221 cpu_to_be32(tbl_32));
5222 }
5223
5224 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5225 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5226
5227 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5228
5229 }
Michael Chan35e90102008-06-19 16:37:42 -07005230}
5231
Michael Chan5d5d0012007-12-12 11:17:43 -08005232static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
Michael Chan13daffa2006-03-20 17:49:20 -08005233{
Michael Chan5d5d0012007-12-12 11:17:43 -08005234 u32 max, num_rings = 1;
Michael Chan13daffa2006-03-20 17:49:20 -08005235
Michael Chan5d5d0012007-12-12 11:17:43 -08005236 while (ring_size > MAX_RX_DESC_CNT) {
5237 ring_size -= MAX_RX_DESC_CNT;
Michael Chan13daffa2006-03-20 17:49:20 -08005238 num_rings++;
5239 }
5240 /* round to next power of 2 */
Michael Chan5d5d0012007-12-12 11:17:43 -08005241 max = max_size;
Michael Chan13daffa2006-03-20 17:49:20 -08005242 while ((max & num_rings) == 0)
5243 max >>= 1;
5244
5245 if (num_rings != max)
5246 max <<= 1;
5247
Michael Chan5d5d0012007-12-12 11:17:43 -08005248 return max;
5249}
5250
5251static void
5252bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5253{
Michael Chan84eaa182007-12-12 11:19:57 -08005254 u32 rx_size, rx_space, jumbo_size;
Michael Chan5d5d0012007-12-12 11:17:43 -08005255
5256 /* 8 for CRC and VLAN */
Benjamin Lid89cb6a2008-05-16 22:18:57 -07005257 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
Michael Chan5d5d0012007-12-12 11:17:43 -08005258
Michael Chan84eaa182007-12-12 11:19:57 -08005259 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5260 sizeof(struct skb_shared_info);
5261
Benjamin Li601d3d12008-05-16 22:19:35 -07005262 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
Michael Chan47bf4242007-12-12 11:19:12 -08005263 bp->rx_pg_ring_size = 0;
5264 bp->rx_max_pg_ring = 0;
5265 bp->rx_max_pg_ring_idx = 0;
David S. Millerf86e82f2008-01-21 17:15:40 -08005266 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
Michael Chan84eaa182007-12-12 11:19:57 -08005267 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5268
5269 jumbo_size = size * pages;
5270 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5271 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5272
5273 bp->rx_pg_ring_size = jumbo_size;
5274 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5275 MAX_RX_PG_RINGS);
5276 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
Benjamin Li601d3d12008-05-16 22:19:35 -07005277 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
Michael Chan84eaa182007-12-12 11:19:57 -08005278 bp->rx_copy_thresh = 0;
5279 }
Michael Chan5d5d0012007-12-12 11:17:43 -08005280
5281 bp->rx_buf_use_size = rx_size;
5282 /* hw alignment */
5283 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
Benjamin Lid89cb6a2008-05-16 22:18:57 -07005284 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
Michael Chan5d5d0012007-12-12 11:17:43 -08005285 bp->rx_ring_size = size;
5286 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
Michael Chan13daffa2006-03-20 17:49:20 -08005287 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5288}
5289
5290static void
Michael Chanb6016b72005-05-26 13:03:09 -07005291bnx2_free_tx_skbs(struct bnx2 *bp)
5292{
5293 int i;
5294
Michael Chan35e90102008-06-19 16:37:42 -07005295 for (i = 0; i < bp->num_tx_rings; i++) {
5296 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5297 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5298 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07005299
Michael Chan35e90102008-06-19 16:37:42 -07005300 if (txr->tx_buf_ring == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07005301 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005302
Michael Chan35e90102008-06-19 16:37:42 -07005303 for (j = 0; j < TX_DESC_CNT; ) {
Benjamin Li3d16af82008-10-09 12:26:41 -07005304 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
Michael Chan35e90102008-06-19 16:37:42 -07005305 struct sk_buff *skb = tx_buf->skb;
Alexander Duycke95524a2009-12-02 16:47:57 +00005306 int k, last;
Michael Chan35e90102008-06-19 16:37:42 -07005307
5308 if (skb == NULL) {
5309 j++;
5310 continue;
5311 }
5312
Alexander Duycke95524a2009-12-02 16:47:57 +00005313 pci_unmap_single(bp->pdev,
5314 pci_unmap_addr(tx_buf, mapping),
5315 skb_headlen(skb),
5316 PCI_DMA_TODEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07005317
Michael Chan35e90102008-06-19 16:37:42 -07005318 tx_buf->skb = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07005319
Alexander Duycke95524a2009-12-02 16:47:57 +00005320 last = tx_buf->nr_frags;
5321 j++;
5322 for (k = 0; k < last; k++, j++) {
5323 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5324 pci_unmap_page(bp->pdev,
5325 pci_unmap_addr(tx_buf, mapping),
5326 skb_shinfo(skb)->frags[k].size,
5327 PCI_DMA_TODEVICE);
5328 }
Michael Chan35e90102008-06-19 16:37:42 -07005329 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07005330 }
Michael Chanb6016b72005-05-26 13:03:09 -07005331 }
Michael Chanb6016b72005-05-26 13:03:09 -07005332}
5333
5334static void
5335bnx2_free_rx_skbs(struct bnx2 *bp)
5336{
5337 int i;
5338
Michael Chanbb4f98a2008-06-19 16:38:19 -07005339 for (i = 0; i < bp->num_rx_rings; i++) {
5340 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5341 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5342 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07005343
Michael Chanbb4f98a2008-06-19 16:38:19 -07005344 if (rxr->rx_buf_ring == NULL)
5345 return;
Michael Chanb6016b72005-05-26 13:03:09 -07005346
Michael Chanbb4f98a2008-06-19 16:38:19 -07005347 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5348 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5349 struct sk_buff *skb = rx_buf->skb;
Michael Chanb6016b72005-05-26 13:03:09 -07005350
Michael Chanbb4f98a2008-06-19 16:38:19 -07005351 if (skb == NULL)
5352 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005353
Michael Chanbb4f98a2008-06-19 16:38:19 -07005354 pci_unmap_single(bp->pdev,
5355 pci_unmap_addr(rx_buf, mapping),
5356 bp->rx_buf_use_size,
5357 PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07005358
Michael Chanbb4f98a2008-06-19 16:38:19 -07005359 rx_buf->skb = NULL;
5360
5361 dev_kfree_skb(skb);
5362 }
5363 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5364 bnx2_free_rx_page(bp, rxr, j);
Michael Chanb6016b72005-05-26 13:03:09 -07005365 }
5366}
5367
5368static void
5369bnx2_free_skbs(struct bnx2 *bp)
5370{
5371 bnx2_free_tx_skbs(bp);
5372 bnx2_free_rx_skbs(bp);
5373}
5374
5375static int
5376bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5377{
5378 int rc;
5379
5380 rc = bnx2_reset_chip(bp, reset_code);
5381 bnx2_free_skbs(bp);
5382 if (rc)
5383 return rc;
5384
Michael Chanfba9fe92006-06-12 22:21:25 -07005385 if ((rc = bnx2_init_chip(bp)) != 0)
5386 return rc;
5387
Michael Chan35e90102008-06-19 16:37:42 -07005388 bnx2_init_all_rings(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005389 return 0;
5390}
5391
5392static int
Michael Chan9a120bc2008-05-16 22:17:45 -07005393bnx2_init_nic(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07005394{
5395 int rc;
5396
5397 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5398 return rc;
5399
Michael Chan80be4432006-11-19 14:07:28 -08005400 spin_lock_bh(&bp->phy_lock);
Michael Chan9a120bc2008-05-16 22:17:45 -07005401 bnx2_init_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07005402 bnx2_set_link(bp);
Michael Chan543a8272008-05-02 16:56:44 -07005403 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5404 bnx2_remote_phy_event(bp);
Michael Chan0d8a6572007-07-07 22:49:43 -07005405 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07005406 return 0;
5407}
5408
5409static int
Michael Chan74bf4ba2008-10-09 12:21:08 -07005410bnx2_shutdown_chip(struct bnx2 *bp)
5411{
5412 u32 reset_code;
5413
5414 if (bp->flags & BNX2_FLAG_NO_WOL)
5415 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5416 else if (bp->wol)
5417 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5418 else
5419 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5420
5421 return bnx2_reset_chip(bp, reset_code);
5422}
5423
5424static int
Michael Chanb6016b72005-05-26 13:03:09 -07005425bnx2_test_registers(struct bnx2 *bp)
5426{
5427 int ret;
Michael Chan5bae30c2007-05-03 13:18:46 -07005428 int i, is_5709;
Arjan van de Venf71e1302006-03-03 21:33:57 -05005429 static const struct {
Michael Chanb6016b72005-05-26 13:03:09 -07005430 u16 offset;
5431 u16 flags;
Michael Chan5bae30c2007-05-03 13:18:46 -07005432#define BNX2_FL_NOT_5709 1
Michael Chanb6016b72005-05-26 13:03:09 -07005433 u32 rw_mask;
5434 u32 ro_mask;
5435 } reg_tbl[] = {
5436 { 0x006c, 0, 0x00000000, 0x0000003f },
5437 { 0x0090, 0, 0xffffffff, 0x00000000 },
5438 { 0x0094, 0, 0x00000000, 0x00000000 },
5439
Michael Chan5bae30c2007-05-03 13:18:46 -07005440 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5441 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5442 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5443 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5444 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5445 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5446 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5447 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5448 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
Michael Chanb6016b72005-05-26 13:03:09 -07005449
Michael Chan5bae30c2007-05-03 13:18:46 -07005450 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5451 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5452 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5453 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5454 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5455 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
Michael Chanb6016b72005-05-26 13:03:09 -07005456
Michael Chan5bae30c2007-05-03 13:18:46 -07005457 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5458 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5459 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005460
5461 { 0x1000, 0, 0x00000000, 0x00000001 },
Michael Chan15b169c2008-05-02 16:57:08 -07005462 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
Michael Chanb6016b72005-05-26 13:03:09 -07005463
5464 { 0x1408, 0, 0x01c00800, 0x00000000 },
5465 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5466 { 0x14a8, 0, 0x00000000, 0x000001ff },
Michael Chan5b0c76a2005-11-04 08:45:49 -08005467 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005468 { 0x14b0, 0, 0x00000002, 0x00000001 },
5469 { 0x14b8, 0, 0x00000000, 0x00000000 },
5470 { 0x14c0, 0, 0x00000000, 0x00000009 },
5471 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5472 { 0x14cc, 0, 0x00000000, 0x00000001 },
5473 { 0x14d0, 0, 0xffffffff, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005474
5475 { 0x1800, 0, 0x00000000, 0x00000001 },
5476 { 0x1804, 0, 0x00000000, 0x00000003 },
Michael Chanb6016b72005-05-26 13:03:09 -07005477
5478 { 0x2800, 0, 0x00000000, 0x00000001 },
5479 { 0x2804, 0, 0x00000000, 0x00003f01 },
5480 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5481 { 0x2810, 0, 0xffff0000, 0x00000000 },
5482 { 0x2814, 0, 0xffff0000, 0x00000000 },
5483 { 0x2818, 0, 0xffff0000, 0x00000000 },
5484 { 0x281c, 0, 0xffff0000, 0x00000000 },
5485 { 0x2834, 0, 0xffffffff, 0x00000000 },
5486 { 0x2840, 0, 0x00000000, 0xffffffff },
5487 { 0x2844, 0, 0x00000000, 0xffffffff },
5488 { 0x2848, 0, 0xffffffff, 0x00000000 },
5489 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5490
5491 { 0x2c00, 0, 0x00000000, 0x00000011 },
5492 { 0x2c04, 0, 0x00000000, 0x00030007 },
5493
Michael Chanb6016b72005-05-26 13:03:09 -07005494 { 0x3c00, 0, 0x00000000, 0x00000001 },
5495 { 0x3c04, 0, 0x00000000, 0x00070000 },
5496 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5497 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5498 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5499 { 0x3c14, 0, 0x00000000, 0xffffffff },
5500 { 0x3c18, 0, 0x00000000, 0xffffffff },
5501 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5502 { 0x3c20, 0, 0xffffff00, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005503
5504 { 0x5004, 0, 0x00000000, 0x0000007f },
5505 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005506
Michael Chanb6016b72005-05-26 13:03:09 -07005507 { 0x5c00, 0, 0x00000000, 0x00000001 },
5508 { 0x5c04, 0, 0x00000000, 0x0003000f },
5509 { 0x5c08, 0, 0x00000003, 0x00000000 },
5510 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5511 { 0x5c10, 0, 0x00000000, 0xffffffff },
5512 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5513 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5514 { 0x5c88, 0, 0x00000000, 0x00077373 },
5515 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5516
5517 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5518 { 0x680c, 0, 0xffffffff, 0x00000000 },
5519 { 0x6810, 0, 0xffffffff, 0x00000000 },
5520 { 0x6814, 0, 0xffffffff, 0x00000000 },
5521 { 0x6818, 0, 0xffffffff, 0x00000000 },
5522 { 0x681c, 0, 0xffffffff, 0x00000000 },
5523 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5524 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5525 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5526 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5527 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5528 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5529 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5530 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5531 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5532 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5533 { 0x684c, 0, 0xffffffff, 0x00000000 },
5534 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5535 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5536 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5537 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5538 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5539 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5540
5541 { 0xffff, 0, 0x00000000, 0x00000000 },
5542 };
5543
5544 ret = 0;
Michael Chan5bae30c2007-05-03 13:18:46 -07005545 is_5709 = 0;
5546 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5547 is_5709 = 1;
5548
Michael Chanb6016b72005-05-26 13:03:09 -07005549 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5550 u32 offset, rw_mask, ro_mask, save_val, val;
Michael Chan5bae30c2007-05-03 13:18:46 -07005551 u16 flags = reg_tbl[i].flags;
5552
5553 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5554 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005555
5556 offset = (u32) reg_tbl[i].offset;
5557 rw_mask = reg_tbl[i].rw_mask;
5558 ro_mask = reg_tbl[i].ro_mask;
5559
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005560 save_val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005561
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005562 writel(0, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005563
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005564 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005565 if ((val & rw_mask) != 0) {
5566 goto reg_test_err;
5567 }
5568
5569 if ((val & ro_mask) != (save_val & ro_mask)) {
5570 goto reg_test_err;
5571 }
5572
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005573 writel(0xffffffff, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005574
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005575 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005576 if ((val & rw_mask) != rw_mask) {
5577 goto reg_test_err;
5578 }
5579
5580 if ((val & ro_mask) != (save_val & ro_mask)) {
5581 goto reg_test_err;
5582 }
5583
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005584 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005585 continue;
5586
5587reg_test_err:
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005588 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005589 ret = -ENODEV;
5590 break;
5591 }
5592 return ret;
5593}
5594
5595static int
5596bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5597{
Arjan van de Venf71e1302006-03-03 21:33:57 -05005598 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
Michael Chanb6016b72005-05-26 13:03:09 -07005599 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5600 int i;
5601
5602 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5603 u32 offset;
5604
5605 for (offset = 0; offset < size; offset += 4) {
5606
Michael Chan2726d6e2008-01-29 21:35:05 -08005607 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
Michael Chanb6016b72005-05-26 13:03:09 -07005608
Michael Chan2726d6e2008-01-29 21:35:05 -08005609 if (bnx2_reg_rd_ind(bp, start + offset) !=
Michael Chanb6016b72005-05-26 13:03:09 -07005610 test_pattern[i]) {
5611 return -ENODEV;
5612 }
5613 }
5614 }
5615 return 0;
5616}
5617
5618static int
5619bnx2_test_memory(struct bnx2 *bp)
5620{
5621 int ret = 0;
5622 int i;
Michael Chan5bae30c2007-05-03 13:18:46 -07005623 static struct mem_entry {
Michael Chanb6016b72005-05-26 13:03:09 -07005624 u32 offset;
5625 u32 len;
Michael Chan5bae30c2007-05-03 13:18:46 -07005626 } mem_tbl_5706[] = {
Michael Chanb6016b72005-05-26 13:03:09 -07005627 { 0x60000, 0x4000 },
Michael Chan5b0c76a2005-11-04 08:45:49 -08005628 { 0xa0000, 0x3000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005629 { 0xe0000, 0x4000 },
5630 { 0x120000, 0x4000 },
5631 { 0x1a0000, 0x4000 },
5632 { 0x160000, 0x4000 },
5633 { 0xffffffff, 0 },
Michael Chan5bae30c2007-05-03 13:18:46 -07005634 },
5635 mem_tbl_5709[] = {
5636 { 0x60000, 0x4000 },
5637 { 0xa0000, 0x3000 },
5638 { 0xe0000, 0x4000 },
5639 { 0x120000, 0x4000 },
5640 { 0x1a0000, 0x4000 },
5641 { 0xffffffff, 0 },
Michael Chanb6016b72005-05-26 13:03:09 -07005642 };
Michael Chan5bae30c2007-05-03 13:18:46 -07005643 struct mem_entry *mem_tbl;
5644
5645 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5646 mem_tbl = mem_tbl_5709;
5647 else
5648 mem_tbl = mem_tbl_5706;
Michael Chanb6016b72005-05-26 13:03:09 -07005649
5650 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5651 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5652 mem_tbl[i].len)) != 0) {
5653 return ret;
5654 }
5655 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005656
Michael Chanb6016b72005-05-26 13:03:09 -07005657 return ret;
5658}
5659
Michael Chanbc5a0692006-01-23 16:13:22 -08005660#define BNX2_MAC_LOOPBACK 0
5661#define BNX2_PHY_LOOPBACK 1
5662
Michael Chanb6016b72005-05-26 13:03:09 -07005663static int
Michael Chanbc5a0692006-01-23 16:13:22 -08005664bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
Michael Chanb6016b72005-05-26 13:03:09 -07005665{
5666 unsigned int pkt_size, num_pkts, i;
5667 struct sk_buff *skb, *rx_skb;
5668 unsigned char *packet;
Michael Chanbc5a0692006-01-23 16:13:22 -08005669 u16 rx_start_idx, rx_idx;
Michael Chanb6016b72005-05-26 13:03:09 -07005670 dma_addr_t map;
5671 struct tx_bd *txbd;
5672 struct sw_bd *rx_buf;
5673 struct l2_fhdr *rx_hdr;
5674 int ret = -ENODEV;
Michael Chanc76c0472007-12-20 20:01:19 -08005675 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
Michael Chan35e90102008-06-19 16:37:42 -07005676 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005677 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanc76c0472007-12-20 20:01:19 -08005678
5679 tx_napi = bnapi;
Michael Chanb6016b72005-05-26 13:03:09 -07005680
Michael Chan35e90102008-06-19 16:37:42 -07005681 txr = &tx_napi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005682 rxr = &bnapi->rx_ring;
Michael Chanbc5a0692006-01-23 16:13:22 -08005683 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5684 bp->loopback = MAC_LOOPBACK;
5685 bnx2_set_mac_loopback(bp);
5686 }
5687 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
Michael Chan583c28e2008-01-21 19:51:35 -08005688 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan489310a2007-10-10 16:16:31 -07005689 return 0;
5690
Michael Chan80be4432006-11-19 14:07:28 -08005691 bp->loopback = PHY_LOOPBACK;
Michael Chanbc5a0692006-01-23 16:13:22 -08005692 bnx2_set_phy_loopback(bp);
5693 }
5694 else
5695 return -EINVAL;
Michael Chanb6016b72005-05-26 13:03:09 -07005696
Michael Chan84eaa182007-12-12 11:19:57 -08005697 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
Michael Chan932f3772006-08-15 01:39:36 -07005698 skb = netdev_alloc_skb(bp->dev, pkt_size);
John W. Linvilleb6cbc3b62005-11-10 12:58:00 -08005699 if (!skb)
5700 return -ENOMEM;
Michael Chanb6016b72005-05-26 13:03:09 -07005701 packet = skb_put(skb, pkt_size);
Michael Chan66342922006-12-14 15:57:04 -08005702 memcpy(packet, bp->dev->dev_addr, 6);
Michael Chanb6016b72005-05-26 13:03:09 -07005703 memset(packet + 6, 0x0, 8);
5704 for (i = 14; i < pkt_size; i++)
5705 packet[i] = (unsigned char) (i & 0xff);
5706
Alexander Duycke95524a2009-12-02 16:47:57 +00005707 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5708 PCI_DMA_TODEVICE);
5709 if (pci_dma_mapping_error(bp->pdev, map)) {
Benjamin Li3d16af82008-10-09 12:26:41 -07005710 dev_kfree_skb(skb);
5711 return -EIO;
5712 }
Michael Chanb6016b72005-05-26 13:03:09 -07005713
Michael Chanbf5295b2006-03-23 01:11:56 -08005714 REG_WR(bp, BNX2_HC_COMMAND,
5715 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5716
Michael Chanb6016b72005-05-26 13:03:09 -07005717 REG_RD(bp, BNX2_HC_COMMAND);
5718
5719 udelay(5);
Michael Chan35efa7c2007-12-20 19:56:37 -08005720 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07005721
Michael Chanb6016b72005-05-26 13:03:09 -07005722 num_pkts = 0;
5723
Michael Chan35e90102008-06-19 16:37:42 -07005724 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
Michael Chanb6016b72005-05-26 13:03:09 -07005725
5726 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5727 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5728 txbd->tx_bd_mss_nbytes = pkt_size;
5729 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5730
5731 num_pkts++;
Michael Chan35e90102008-06-19 16:37:42 -07005732 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5733 txr->tx_prod_bseq += pkt_size;
Michael Chanb6016b72005-05-26 13:03:09 -07005734
Michael Chan35e90102008-06-19 16:37:42 -07005735 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5736 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07005737
5738 udelay(100);
5739
Michael Chanbf5295b2006-03-23 01:11:56 -08005740 REG_WR(bp, BNX2_HC_COMMAND,
5741 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5742
Michael Chanb6016b72005-05-26 13:03:09 -07005743 REG_RD(bp, BNX2_HC_COMMAND);
5744
5745 udelay(5);
5746
Alexander Duycke95524a2009-12-02 16:47:57 +00005747 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
Michael Chan745720e2006-06-29 12:37:41 -07005748 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07005749
Michael Chan35e90102008-06-19 16:37:42 -07005750 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
Michael Chanb6016b72005-05-26 13:03:09 -07005751 goto loopback_test_done;
Michael Chanb6016b72005-05-26 13:03:09 -07005752
Michael Chan35efa7c2007-12-20 19:56:37 -08005753 rx_idx = bnx2_get_hw_rx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07005754 if (rx_idx != rx_start_idx + num_pkts) {
5755 goto loopback_test_done;
5756 }
5757
Michael Chanbb4f98a2008-06-19 16:38:19 -07005758 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
Michael Chanb6016b72005-05-26 13:03:09 -07005759 rx_skb = rx_buf->skb;
5760
5761 rx_hdr = (struct l2_fhdr *) rx_skb->data;
Benjamin Lid89cb6a2008-05-16 22:18:57 -07005762 skb_reserve(rx_skb, BNX2_RX_OFFSET);
Michael Chanb6016b72005-05-26 13:03:09 -07005763
5764 pci_dma_sync_single_for_cpu(bp->pdev,
5765 pci_unmap_addr(rx_buf, mapping),
5766 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5767
Michael Chanade2bfe2006-01-23 16:09:51 -08005768 if (rx_hdr->l2_fhdr_status &
Michael Chanb6016b72005-05-26 13:03:09 -07005769 (L2_FHDR_ERRORS_BAD_CRC |
5770 L2_FHDR_ERRORS_PHY_DECODE |
5771 L2_FHDR_ERRORS_ALIGNMENT |
5772 L2_FHDR_ERRORS_TOO_SHORT |
5773 L2_FHDR_ERRORS_GIANT_FRAME)) {
5774
5775 goto loopback_test_done;
5776 }
5777
5778 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5779 goto loopback_test_done;
5780 }
5781
5782 for (i = 14; i < pkt_size; i++) {
5783 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5784 goto loopback_test_done;
5785 }
5786 }
5787
5788 ret = 0;
5789
5790loopback_test_done:
5791 bp->loopback = 0;
5792 return ret;
5793}
5794
Michael Chanbc5a0692006-01-23 16:13:22 -08005795#define BNX2_MAC_LOOPBACK_FAILED 1
5796#define BNX2_PHY_LOOPBACK_FAILED 2
5797#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5798 BNX2_PHY_LOOPBACK_FAILED)
5799
5800static int
5801bnx2_test_loopback(struct bnx2 *bp)
5802{
5803 int rc = 0;
5804
5805 if (!netif_running(bp->dev))
5806 return BNX2_LOOPBACK_FAILED;
5807
5808 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5809 spin_lock_bh(&bp->phy_lock);
Michael Chan9a120bc2008-05-16 22:17:45 -07005810 bnx2_init_phy(bp, 1);
Michael Chanbc5a0692006-01-23 16:13:22 -08005811 spin_unlock_bh(&bp->phy_lock);
5812 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5813 rc |= BNX2_MAC_LOOPBACK_FAILED;
5814 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5815 rc |= BNX2_PHY_LOOPBACK_FAILED;
5816 return rc;
5817}
5818
Michael Chanb6016b72005-05-26 13:03:09 -07005819#define NVRAM_SIZE 0x200
5820#define CRC32_RESIDUAL 0xdebb20e3
5821
5822static int
5823bnx2_test_nvram(struct bnx2 *bp)
5824{
Al Virob491edd2007-12-22 19:44:51 +00005825 __be32 buf[NVRAM_SIZE / 4];
Michael Chanb6016b72005-05-26 13:03:09 -07005826 u8 *data = (u8 *) buf;
5827 int rc = 0;
5828 u32 magic, csum;
5829
5830 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5831 goto test_nvram_done;
5832
5833 magic = be32_to_cpu(buf[0]);
5834 if (magic != 0x669955aa) {
5835 rc = -ENODEV;
5836 goto test_nvram_done;
5837 }
5838
5839 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5840 goto test_nvram_done;
5841
5842 csum = ether_crc_le(0x100, data);
5843 if (csum != CRC32_RESIDUAL) {
5844 rc = -ENODEV;
5845 goto test_nvram_done;
5846 }
5847
5848 csum = ether_crc_le(0x100, data + 0x100);
5849 if (csum != CRC32_RESIDUAL) {
5850 rc = -ENODEV;
5851 }
5852
5853test_nvram_done:
5854 return rc;
5855}
5856
5857static int
5858bnx2_test_link(struct bnx2 *bp)
5859{
5860 u32 bmsr;
5861
Michael Chan9f52b562008-10-09 12:21:46 -07005862 if (!netif_running(bp->dev))
5863 return -ENODEV;
5864
Michael Chan583c28e2008-01-21 19:51:35 -08005865 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan489310a2007-10-10 16:16:31 -07005866 if (bp->link_up)
5867 return 0;
5868 return -ENODEV;
5869 }
Michael Chanc770a652005-08-25 15:38:39 -07005870 spin_lock_bh(&bp->phy_lock);
Michael Chan27a005b2007-05-03 13:23:41 -07005871 bnx2_enable_bmsr1(bp);
5872 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5873 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5874 bnx2_disable_bmsr1(bp);
Michael Chanc770a652005-08-25 15:38:39 -07005875 spin_unlock_bh(&bp->phy_lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005876
Michael Chanb6016b72005-05-26 13:03:09 -07005877 if (bmsr & BMSR_LSTATUS) {
5878 return 0;
5879 }
5880 return -ENODEV;
5881}
5882
5883static int
5884bnx2_test_intr(struct bnx2 *bp)
5885{
5886 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07005887 u16 status_idx;
5888
5889 if (!netif_running(bp->dev))
5890 return -ENODEV;
5891
5892 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5893
5894 /* This register is not touched during run-time. */
Michael Chanbf5295b2006-03-23 01:11:56 -08005895 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
Michael Chanb6016b72005-05-26 13:03:09 -07005896 REG_RD(bp, BNX2_HC_COMMAND);
5897
5898 for (i = 0; i < 10; i++) {
5899 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5900 status_idx) {
5901
5902 break;
5903 }
5904
5905 msleep_interruptible(10);
5906 }
5907 if (i < 10)
5908 return 0;
5909
5910 return -ENODEV;
5911}
5912
Michael Chan38ea3682008-02-23 19:48:57 -08005913/* Determining link for parallel detection. */
Michael Chanb2fadea2008-01-21 17:07:06 -08005914static int
5915bnx2_5706_serdes_has_link(struct bnx2 *bp)
5916{
5917 u32 mode_ctl, an_dbg, exp;
5918
Michael Chan38ea3682008-02-23 19:48:57 -08005919 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5920 return 0;
5921
Michael Chanb2fadea2008-01-21 17:07:06 -08005922 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5923 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5924
5925 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5926 return 0;
5927
5928 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5929 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5930 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5931
Michael Chanf3014c02008-01-29 21:33:03 -08005932 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
Michael Chanb2fadea2008-01-21 17:07:06 -08005933 return 0;
5934
5935 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5936 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5937 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5938
5939 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5940 return 0;
5941
5942 return 1;
5943}
5944
Michael Chanb6016b72005-05-26 13:03:09 -07005945static void
Michael Chan48b01e22006-11-19 14:08:00 -08005946bnx2_5706_serdes_timer(struct bnx2 *bp)
5947{
Michael Chanb2fadea2008-01-21 17:07:06 -08005948 int check_link = 1;
5949
Michael Chan48b01e22006-11-19 14:08:00 -08005950 spin_lock(&bp->phy_lock);
Michael Chanb2fadea2008-01-21 17:07:06 -08005951 if (bp->serdes_an_pending) {
Michael Chan48b01e22006-11-19 14:08:00 -08005952 bp->serdes_an_pending--;
Michael Chanb2fadea2008-01-21 17:07:06 -08005953 check_link = 0;
5954 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005955 u32 bmcr;
5956
Benjamin Liac392ab2008-09-18 16:40:49 -07005957 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chan48b01e22006-11-19 14:08:00 -08005958
Michael Chanca58c3a2007-05-03 13:22:52 -07005959 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005960
5961 if (bmcr & BMCR_ANENABLE) {
Michael Chanb2fadea2008-01-21 17:07:06 -08005962 if (bnx2_5706_serdes_has_link(bp)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005963 bmcr &= ~BMCR_ANENABLE;
5964 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
Michael Chanca58c3a2007-05-03 13:22:52 -07005965 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
Michael Chan583c28e2008-01-21 19:51:35 -08005966 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chan48b01e22006-11-19 14:08:00 -08005967 }
5968 }
5969 }
5970 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
Michael Chan583c28e2008-01-21 19:51:35 -08005971 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005972 u32 phy2;
5973
5974 bnx2_write_phy(bp, 0x17, 0x0f01);
5975 bnx2_read_phy(bp, 0x15, &phy2);
5976 if (phy2 & 0x20) {
5977 u32 bmcr;
5978
Michael Chanca58c3a2007-05-03 13:22:52 -07005979 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005980 bmcr |= BMCR_ANENABLE;
Michael Chanca58c3a2007-05-03 13:22:52 -07005981 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005982
Michael Chan583c28e2008-01-21 19:51:35 -08005983 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chan48b01e22006-11-19 14:08:00 -08005984 }
5985 } else
Benjamin Liac392ab2008-09-18 16:40:49 -07005986 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chan48b01e22006-11-19 14:08:00 -08005987
Michael Chana2724e22008-02-23 19:47:44 -08005988 if (check_link) {
Michael Chanb2fadea2008-01-21 17:07:06 -08005989 u32 val;
5990
5991 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5992 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5993 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5994
Michael Chana2724e22008-02-23 19:47:44 -08005995 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5996 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5997 bnx2_5706s_force_link_dn(bp, 1);
5998 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5999 } else
6000 bnx2_set_link(bp);
6001 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6002 bnx2_set_link(bp);
Michael Chanb2fadea2008-01-21 17:07:06 -08006003 }
Michael Chan48b01e22006-11-19 14:08:00 -08006004 spin_unlock(&bp->phy_lock);
6005}
6006
6007static void
Michael Chanf8dd0642006-11-19 14:08:29 -08006008bnx2_5708_serdes_timer(struct bnx2 *bp)
6009{
Michael Chan583c28e2008-01-21 19:51:35 -08006010 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07006011 return;
6012
Michael Chan583c28e2008-01-21 19:51:35 -08006013 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
Michael Chanf8dd0642006-11-19 14:08:29 -08006014 bp->serdes_an_pending = 0;
6015 return;
6016 }
6017
6018 spin_lock(&bp->phy_lock);
6019 if (bp->serdes_an_pending)
6020 bp->serdes_an_pending--;
6021 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6022 u32 bmcr;
6023
Michael Chanca58c3a2007-05-03 13:22:52 -07006024 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanf8dd0642006-11-19 14:08:29 -08006025 if (bmcr & BMCR_ANENABLE) {
Michael Chan605a9e22007-05-03 13:23:13 -07006026 bnx2_enable_forced_2g5(bp);
Michael Chan40105c02008-11-12 16:02:45 -08006027 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
Michael Chanf8dd0642006-11-19 14:08:29 -08006028 } else {
Michael Chan605a9e22007-05-03 13:23:13 -07006029 bnx2_disable_forced_2g5(bp);
Michael Chanf8dd0642006-11-19 14:08:29 -08006030 bp->serdes_an_pending = 2;
Benjamin Liac392ab2008-09-18 16:40:49 -07006031 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanf8dd0642006-11-19 14:08:29 -08006032 }
6033
6034 } else
Benjamin Liac392ab2008-09-18 16:40:49 -07006035 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanf8dd0642006-11-19 14:08:29 -08006036
6037 spin_unlock(&bp->phy_lock);
6038}
6039
6040static void
Michael Chanb6016b72005-05-26 13:03:09 -07006041bnx2_timer(unsigned long data)
6042{
6043 struct bnx2 *bp = (struct bnx2 *) data;
Michael Chanb6016b72005-05-26 13:03:09 -07006044
Michael Chancd339a02005-08-25 15:35:24 -07006045 if (!netif_running(bp->dev))
6046 return;
6047
Michael Chanb6016b72005-05-26 13:03:09 -07006048 if (atomic_read(&bp->intr_sem) != 0)
6049 goto bnx2_restart_timer;
6050
Michael Chanefba0182008-12-03 00:36:15 -08006051 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6052 BNX2_FLAG_USING_MSI)
6053 bnx2_chk_missed_msi(bp);
6054
Michael Chandf149d72007-07-07 22:51:36 -07006055 bnx2_send_heart_beat(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006056
Michael Chan2726d6e2008-01-29 21:35:05 -08006057 bp->stats_blk->stat_FwRxDrop =
6058 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
Michael Chancea94db2006-06-12 22:16:13 -07006059
Michael Chan02537b062007-06-04 21:24:07 -07006060 /* workaround occasional corrupted counters */
Michael Chan61d9e3f2009-08-21 16:20:46 +00006061 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
Michael Chan02537b062007-06-04 21:24:07 -07006062 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6063 BNX2_HC_COMMAND_STATS_NOW);
6064
Michael Chan583c28e2008-01-21 19:51:35 -08006065 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanf8dd0642006-11-19 14:08:29 -08006066 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6067 bnx2_5706_serdes_timer(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07006068 else
Michael Chanf8dd0642006-11-19 14:08:29 -08006069 bnx2_5708_serdes_timer(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006070 }
6071
6072bnx2_restart_timer:
Michael Chancd339a02005-08-25 15:35:24 -07006073 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07006074}
6075
Michael Chan8e6a72c2007-05-03 13:24:48 -07006076static int
6077bnx2_request_irq(struct bnx2 *bp)
6078{
Michael Chan6d866ff2007-12-20 19:56:09 -08006079 unsigned long flags;
Michael Chanb4b36042007-12-20 19:59:30 -08006080 struct bnx2_irq *irq;
6081 int rc = 0, i;
Michael Chan8e6a72c2007-05-03 13:24:48 -07006082
David S. Millerf86e82f2008-01-21 17:15:40 -08006083 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
Michael Chan6d866ff2007-12-20 19:56:09 -08006084 flags = 0;
6085 else
6086 flags = IRQF_SHARED;
Michael Chanb4b36042007-12-20 19:59:30 -08006087
6088 for (i = 0; i < bp->irq_nvecs; i++) {
6089 irq = &bp->irq_tbl[i];
Michael Chanc76c0472007-12-20 20:01:19 -08006090 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
Michael Chanf0ea2e62008-06-19 16:41:57 -07006091 &bp->bnx2_napi[i]);
Michael Chanb4b36042007-12-20 19:59:30 -08006092 if (rc)
6093 break;
6094 irq->requested = 1;
6095 }
Michael Chan8e6a72c2007-05-03 13:24:48 -07006096 return rc;
6097}
6098
6099static void
6100bnx2_free_irq(struct bnx2 *bp)
6101{
Michael Chanb4b36042007-12-20 19:59:30 -08006102 struct bnx2_irq *irq;
6103 int i;
Michael Chan8e6a72c2007-05-03 13:24:48 -07006104
Michael Chanb4b36042007-12-20 19:59:30 -08006105 for (i = 0; i < bp->irq_nvecs; i++) {
6106 irq = &bp->irq_tbl[i];
6107 if (irq->requested)
Michael Chanf0ea2e62008-06-19 16:41:57 -07006108 free_irq(irq->vector, &bp->bnx2_napi[i]);
Michael Chanb4b36042007-12-20 19:59:30 -08006109 irq->requested = 0;
Michael Chan6d866ff2007-12-20 19:56:09 -08006110 }
David S. Millerf86e82f2008-01-21 17:15:40 -08006111 if (bp->flags & BNX2_FLAG_USING_MSI)
Michael Chanb4b36042007-12-20 19:59:30 -08006112 pci_disable_msi(bp->pdev);
David S. Millerf86e82f2008-01-21 17:15:40 -08006113 else if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chanb4b36042007-12-20 19:59:30 -08006114 pci_disable_msix(bp->pdev);
6115
David S. Millerf86e82f2008-01-21 17:15:40 -08006116 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
Michael Chanb4b36042007-12-20 19:59:30 -08006117}
6118
6119static void
Michael Chan5e9ad9e2008-06-19 16:43:17 -07006120bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
Michael Chanb4b36042007-12-20 19:59:30 -08006121{
Michael Chan57851d82007-12-20 20:01:44 -08006122 int i, rc;
6123 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
Michael Chan4e1d0de2008-12-16 20:27:45 -08006124 struct net_device *dev = bp->dev;
6125 const int len = sizeof(bp->irq_tbl[0].name);
Michael Chan57851d82007-12-20 20:01:44 -08006126
Michael Chanb4b36042007-12-20 19:59:30 -08006127 bnx2_setup_msix_tbl(bp);
6128 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6129 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6130 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
Michael Chan57851d82007-12-20 20:01:44 -08006131
6132 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6133 msix_ent[i].entry = i;
6134 msix_ent[i].vector = 0;
6135 }
6136
6137 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6138 if (rc != 0)
6139 return;
6140
Michael Chan5e9ad9e2008-06-19 16:43:17 -07006141 bp->irq_nvecs = msix_vecs;
David S. Millerf86e82f2008-01-21 17:15:40 -08006142 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
Michael Chan69010312009-03-18 18:11:51 -07006143 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
Michael Chan57851d82007-12-20 20:01:44 -08006144 bp->irq_tbl[i].vector = msix_ent[i].vector;
Michael Chan69010312009-03-18 18:11:51 -07006145 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6146 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6147 }
Michael Chan6d866ff2007-12-20 19:56:09 -08006148}
6149
6150static void
6151bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6152{
Michael Chan5e9ad9e2008-06-19 16:43:17 -07006153 int cpus = num_online_cpus();
Benjamin Li706bf242008-07-18 17:55:11 -07006154 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
Michael Chan5e9ad9e2008-06-19 16:43:17 -07006155
Michael Chan6d866ff2007-12-20 19:56:09 -08006156 bp->irq_tbl[0].handler = bnx2_interrupt;
6157 strcpy(bp->irq_tbl[0].name, bp->dev->name);
Michael Chanb4b36042007-12-20 19:59:30 -08006158 bp->irq_nvecs = 1;
6159 bp->irq_tbl[0].vector = bp->pdev->irq;
Michael Chan6d866ff2007-12-20 19:56:09 -08006160
Michael Chan5e9ad9e2008-06-19 16:43:17 -07006161 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
6162 bnx2_enable_msix(bp, msix_vecs);
Michael Chanb4b36042007-12-20 19:59:30 -08006163
David S. Millerf86e82f2008-01-21 17:15:40 -08006164 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6165 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
Michael Chan6d866ff2007-12-20 19:56:09 -08006166 if (pci_enable_msi(bp->pdev) == 0) {
David S. Millerf86e82f2008-01-21 17:15:40 -08006167 bp->flags |= BNX2_FLAG_USING_MSI;
Michael Chan6d866ff2007-12-20 19:56:09 -08006168 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
David S. Millerf86e82f2008-01-21 17:15:40 -08006169 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
Michael Chan6d866ff2007-12-20 19:56:09 -08006170 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6171 } else
6172 bp->irq_tbl[0].handler = bnx2_msi;
Michael Chanb4b36042007-12-20 19:59:30 -08006173
6174 bp->irq_tbl[0].vector = bp->pdev->irq;
Michael Chan6d866ff2007-12-20 19:56:09 -08006175 }
6176 }
Benjamin Li706bf242008-07-18 17:55:11 -07006177
6178 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6179 bp->dev->real_num_tx_queues = bp->num_tx_rings;
6180
Michael Chan5e9ad9e2008-06-19 16:43:17 -07006181 bp->num_rx_rings = bp->irq_nvecs;
Michael Chan8e6a72c2007-05-03 13:24:48 -07006182}
6183
Michael Chanb6016b72005-05-26 13:03:09 -07006184/* Called with rtnl_lock */
6185static int
6186bnx2_open(struct net_device *dev)
6187{
Michael Chan972ec0d2006-01-23 16:12:43 -08006188 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006189 int rc;
6190
Michael Chan1b2f9222007-05-03 13:20:19 -07006191 netif_carrier_off(dev);
6192
Pavel Machek829ca9a2005-09-03 15:56:56 -07006193 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07006194 bnx2_disable_int(bp);
6195
Michael Chan6d866ff2007-12-20 19:56:09 -08006196 bnx2_setup_int_mode(bp, disable_msi);
Michael Chan35efa7c2007-12-20 19:56:37 -08006197 bnx2_napi_enable(bp);
Michael Chan35e90102008-06-19 16:37:42 -07006198 rc = bnx2_alloc_mem(bp);
Michael Chan2739a8b2008-06-19 16:44:10 -07006199 if (rc)
6200 goto open_err;
Michael Chan35e90102008-06-19 16:37:42 -07006201
Michael Chan8e6a72c2007-05-03 13:24:48 -07006202 rc = bnx2_request_irq(bp);
Michael Chan2739a8b2008-06-19 16:44:10 -07006203 if (rc)
6204 goto open_err;
Michael Chanb6016b72005-05-26 13:03:09 -07006205
Michael Chan9a120bc2008-05-16 22:17:45 -07006206 rc = bnx2_init_nic(bp, 1);
Michael Chan2739a8b2008-06-19 16:44:10 -07006207 if (rc)
6208 goto open_err;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006209
Michael Chancd339a02005-08-25 15:35:24 -07006210 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07006211
6212 atomic_set(&bp->intr_sem, 0);
6213
6214 bnx2_enable_int(bp);
6215
David S. Millerf86e82f2008-01-21 17:15:40 -08006216 if (bp->flags & BNX2_FLAG_USING_MSI) {
Michael Chanb6016b72005-05-26 13:03:09 -07006217 /* Test MSI to make sure it is working
6218 * If MSI test fails, go back to INTx mode
6219 */
6220 if (bnx2_test_intr(bp) != 0) {
6221 printk(KERN_WARNING PFX "%s: No interrupt was generated"
6222 " using MSI, switching to INTx mode. Please"
6223 " report this failure to the PCI maintainer"
6224 " and include system chipset information.\n",
6225 bp->dev->name);
6226
6227 bnx2_disable_int(bp);
Michael Chan8e6a72c2007-05-03 13:24:48 -07006228 bnx2_free_irq(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006229
Michael Chan6d866ff2007-12-20 19:56:09 -08006230 bnx2_setup_int_mode(bp, 1);
6231
Michael Chan9a120bc2008-05-16 22:17:45 -07006232 rc = bnx2_init_nic(bp, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07006233
Michael Chan8e6a72c2007-05-03 13:24:48 -07006234 if (!rc)
6235 rc = bnx2_request_irq(bp);
6236
Michael Chanb6016b72005-05-26 13:03:09 -07006237 if (rc) {
Michael Chanb6016b72005-05-26 13:03:09 -07006238 del_timer_sync(&bp->timer);
Michael Chan2739a8b2008-06-19 16:44:10 -07006239 goto open_err;
Michael Chanb6016b72005-05-26 13:03:09 -07006240 }
6241 bnx2_enable_int(bp);
6242 }
6243 }
David S. Millerf86e82f2008-01-21 17:15:40 -08006244 if (bp->flags & BNX2_FLAG_USING_MSI)
Michael Chanb6016b72005-05-26 13:03:09 -07006245 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
David S. Millerf86e82f2008-01-21 17:15:40 -08006246 else if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chan57851d82007-12-20 20:01:44 -08006247 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
Michael Chanb6016b72005-05-26 13:03:09 -07006248
Benjamin Li706bf242008-07-18 17:55:11 -07006249 netif_tx_start_all_queues(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006250
6251 return 0;
Michael Chan2739a8b2008-06-19 16:44:10 -07006252
6253open_err:
6254 bnx2_napi_disable(bp);
6255 bnx2_free_skbs(bp);
6256 bnx2_free_irq(bp);
6257 bnx2_free_mem(bp);
6258 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07006259}
6260
6261static void
David Howellsc4028952006-11-22 14:57:56 +00006262bnx2_reset_task(struct work_struct *work)
Michael Chanb6016b72005-05-26 13:03:09 -07006263{
David Howellsc4028952006-11-22 14:57:56 +00006264 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
Michael Chanb6016b72005-05-26 13:03:09 -07006265
Michael Chan51bf6bb2009-12-03 09:46:31 +00006266 rtnl_lock();
6267 if (!netif_running(bp->dev)) {
6268 rtnl_unlock();
Michael Chanafdc08b2005-08-25 15:34:29 -07006269 return;
Michael Chan51bf6bb2009-12-03 09:46:31 +00006270 }
Michael Chanafdc08b2005-08-25 15:34:29 -07006271
Michael Chanb6016b72005-05-26 13:03:09 -07006272 bnx2_netif_stop(bp);
6273
Michael Chan9a120bc2008-05-16 22:17:45 -07006274 bnx2_init_nic(bp, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07006275
6276 atomic_set(&bp->intr_sem, 1);
6277 bnx2_netif_start(bp);
Michael Chan51bf6bb2009-12-03 09:46:31 +00006278 rtnl_unlock();
Michael Chanb6016b72005-05-26 13:03:09 -07006279}
6280
6281static void
Michael Chan20175c52009-12-03 09:46:32 +00006282bnx2_dump_state(struct bnx2 *bp)
6283{
6284 struct net_device *dev = bp->dev;
6285
6286 printk(KERN_ERR PFX "%s DEBUG: intr_sem[%x]\n", dev->name,
6287 atomic_read(&bp->intr_sem));
6288 printk(KERN_ERR PFX "%s DEBUG: EMAC_TX_STATUS[%08x] "
6289 "RPM_MGMT_PKT_CTRL[%08x]\n", dev->name,
6290 REG_RD(bp, BNX2_EMAC_TX_STATUS),
6291 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6292 printk(KERN_ERR PFX "%s DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
6293 dev->name, bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P0),
6294 bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P1));
6295 printk(KERN_ERR PFX "%s DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6296 dev->name, REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6297 if (bp->flags & BNX2_FLAG_USING_MSIX)
6298 printk(KERN_ERR PFX "%s DEBUG: PBA[%08x]\n", dev->name,
6299 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6300}
6301
6302static void
Michael Chanb6016b72005-05-26 13:03:09 -07006303bnx2_tx_timeout(struct net_device *dev)
6304{
Michael Chan972ec0d2006-01-23 16:12:43 -08006305 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006306
Michael Chan20175c52009-12-03 09:46:32 +00006307 bnx2_dump_state(bp);
6308
Michael Chanb6016b72005-05-26 13:03:09 -07006309 /* This allows the netif to be shutdown gracefully before resetting */
6310 schedule_work(&bp->reset_task);
6311}
6312
6313#ifdef BCM_VLAN
6314/* Called with rtnl_lock */
6315static void
6316bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6317{
Michael Chan972ec0d2006-01-23 16:12:43 -08006318 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006319
Michael Chan37675462009-08-21 16:20:44 +00006320 if (netif_running(dev))
6321 bnx2_netif_stop(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006322
6323 bp->vlgrp = vlgrp;
Michael Chan37675462009-08-21 16:20:44 +00006324
6325 if (!netif_running(dev))
6326 return;
6327
Michael Chanb6016b72005-05-26 13:03:09 -07006328 bnx2_set_rx_mode(dev);
Michael Chan7c62e832008-07-14 22:39:03 -07006329 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6330 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07006331
6332 bnx2_netif_start(bp);
6333}
Michael Chanb6016b72005-05-26 13:03:09 -07006334#endif
6335
Herbert Xu932ff272006-06-09 12:20:56 -07006336/* Called with netif_tx_lock.
Michael Chan2f8af122006-08-15 01:39:10 -07006337 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6338 * netif_wake_queue().
Michael Chanb6016b72005-05-26 13:03:09 -07006339 */
Stephen Hemminger613573252009-08-31 19:50:58 +00006340static netdev_tx_t
Michael Chanb6016b72005-05-26 13:03:09 -07006341bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6342{
Michael Chan972ec0d2006-01-23 16:12:43 -08006343 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006344 dma_addr_t mapping;
6345 struct tx_bd *txbd;
Benjamin Li3d16af82008-10-09 12:26:41 -07006346 struct sw_tx_bd *tx_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07006347 u32 len, vlan_tag_flags, last_frag, mss;
6348 u16 prod, ring_prod;
6349 int i;
Benjamin Li706bf242008-07-18 17:55:11 -07006350 struct bnx2_napi *bnapi;
6351 struct bnx2_tx_ring_info *txr;
6352 struct netdev_queue *txq;
6353
6354 /* Determine which tx ring we will be placed on */
6355 i = skb_get_queue_mapping(skb);
6356 bnapi = &bp->bnx2_napi[i];
6357 txr = &bnapi->tx_ring;
6358 txq = netdev_get_tx_queue(dev, i);
Michael Chanb6016b72005-05-26 13:03:09 -07006359
Michael Chan35e90102008-06-19 16:37:42 -07006360 if (unlikely(bnx2_tx_avail(bp, txr) <
Michael Chana550c992007-12-20 19:56:59 -08006361 (skb_shinfo(skb)->nr_frags + 1))) {
Benjamin Li706bf242008-07-18 17:55:11 -07006362 netif_tx_stop_queue(txq);
Michael Chanb6016b72005-05-26 13:03:09 -07006363 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
6364 dev->name);
6365
6366 return NETDEV_TX_BUSY;
6367 }
6368 len = skb_headlen(skb);
Michael Chan35e90102008-06-19 16:37:42 -07006369 prod = txr->tx_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07006370 ring_prod = TX_RING_IDX(prod);
6371
6372 vlan_tag_flags = 0;
Patrick McHardy84fa7932006-08-29 16:44:56 -07006373 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Michael Chanb6016b72005-05-26 13:03:09 -07006374 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6375 }
6376
Michael Chan729b85c2008-08-14 15:29:39 -07006377#ifdef BCM_VLAN
Al Viro79ea13c2008-01-24 02:06:46 -08006378 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
Michael Chanb6016b72005-05-26 13:03:09 -07006379 vlan_tag_flags |=
6380 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6381 }
Michael Chan729b85c2008-08-14 15:29:39 -07006382#endif
Michael Chanfde82052007-05-03 17:23:35 -07006383 if ((mss = skb_shinfo(skb)->gso_size)) {
Michael Chana1efb4b2008-10-09 12:24:39 -07006384 u32 tcp_opt_len;
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006385 struct iphdr *iph;
Michael Chanb6016b72005-05-26 13:03:09 -07006386
Michael Chanb6016b72005-05-26 13:03:09 -07006387 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6388
Michael Chan4666f872007-05-03 13:22:28 -07006389 tcp_opt_len = tcp_optlen(skb);
Arnaldo Carvalho de Meloab6a5bb2007-03-18 17:43:48 -07006390
Michael Chan4666f872007-05-03 13:22:28 -07006391 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6392 u32 tcp_off = skb_transport_offset(skb) -
6393 sizeof(struct ipv6hdr) - ETH_HLEN;
Michael Chanb6016b72005-05-26 13:03:09 -07006394
Michael Chan4666f872007-05-03 13:22:28 -07006395 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6396 TX_BD_FLAGS_SW_FLAGS;
6397 if (likely(tcp_off == 0))
6398 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6399 else {
6400 tcp_off >>= 3;
6401 vlan_tag_flags |= ((tcp_off & 0x3) <<
6402 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6403 ((tcp_off & 0x10) <<
6404 TX_BD_FLAGS_TCP6_OFF4_SHL);
6405 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6406 }
6407 } else {
Michael Chan4666f872007-05-03 13:22:28 -07006408 iph = ip_hdr(skb);
Michael Chan4666f872007-05-03 13:22:28 -07006409 if (tcp_opt_len || (iph->ihl > 5)) {
6410 vlan_tag_flags |= ((iph->ihl - 5) +
6411 (tcp_opt_len >> 2)) << 8;
6412 }
Michael Chanb6016b72005-05-26 13:03:09 -07006413 }
Michael Chan4666f872007-05-03 13:22:28 -07006414 } else
Michael Chanb6016b72005-05-26 13:03:09 -07006415 mss = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07006416
Alexander Duycke95524a2009-12-02 16:47:57 +00006417 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6418 if (pci_dma_mapping_error(bp->pdev, mapping)) {
Benjamin Li3d16af82008-10-09 12:26:41 -07006419 dev_kfree_skb(skb);
6420 return NETDEV_TX_OK;
6421 }
6422
Michael Chan35e90102008-06-19 16:37:42 -07006423 tx_buf = &txr->tx_buf_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006424 tx_buf->skb = skb;
Alexander Duycke95524a2009-12-02 16:47:57 +00006425 pci_unmap_addr_set(tx_buf, mapping, mapping);
Michael Chanb6016b72005-05-26 13:03:09 -07006426
Michael Chan35e90102008-06-19 16:37:42 -07006427 txbd = &txr->tx_desc_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006428
6429 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6430 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6431 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6432 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6433
6434 last_frag = skb_shinfo(skb)->nr_frags;
Eric Dumazetd62fda02009-05-12 20:48:02 +00006435 tx_buf->nr_frags = last_frag;
6436 tx_buf->is_gso = skb_is_gso(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07006437
6438 for (i = 0; i < last_frag; i++) {
6439 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6440
6441 prod = NEXT_TX_BD(prod);
6442 ring_prod = TX_RING_IDX(prod);
Michael Chan35e90102008-06-19 16:37:42 -07006443 txbd = &txr->tx_desc_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006444
6445 len = frag->size;
Alexander Duycke95524a2009-12-02 16:47:57 +00006446 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6447 len, PCI_DMA_TODEVICE);
6448 if (pci_dma_mapping_error(bp->pdev, mapping))
6449 goto dma_error;
6450 pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6451 mapping);
Michael Chanb6016b72005-05-26 13:03:09 -07006452
6453 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6454 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6455 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6456 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6457
6458 }
6459 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6460
6461 prod = NEXT_TX_BD(prod);
Michael Chan35e90102008-06-19 16:37:42 -07006462 txr->tx_prod_bseq += skb->len;
Michael Chanb6016b72005-05-26 13:03:09 -07006463
Michael Chan35e90102008-06-19 16:37:42 -07006464 REG_WR16(bp, txr->tx_bidx_addr, prod);
6465 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07006466
6467 mmiowb();
6468
Michael Chan35e90102008-06-19 16:37:42 -07006469 txr->tx_prod = prod;
Michael Chanb6016b72005-05-26 13:03:09 -07006470
Michael Chan35e90102008-06-19 16:37:42 -07006471 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
Benjamin Li706bf242008-07-18 17:55:11 -07006472 netif_tx_stop_queue(txq);
Michael Chan35e90102008-06-19 16:37:42 -07006473 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
Benjamin Li706bf242008-07-18 17:55:11 -07006474 netif_tx_wake_queue(txq);
Michael Chanb6016b72005-05-26 13:03:09 -07006475 }
6476
6477 return NETDEV_TX_OK;
Alexander Duycke95524a2009-12-02 16:47:57 +00006478dma_error:
6479 /* save value of frag that failed */
6480 last_frag = i;
6481
6482 /* start back at beginning and unmap skb */
6483 prod = txr->tx_prod;
6484 ring_prod = TX_RING_IDX(prod);
6485 tx_buf = &txr->tx_buf_ring[ring_prod];
6486 tx_buf->skb = NULL;
6487 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
6488 skb_headlen(skb), PCI_DMA_TODEVICE);
6489
6490 /* unmap remaining mapped pages */
6491 for (i = 0; i < last_frag; i++) {
6492 prod = NEXT_TX_BD(prod);
6493 ring_prod = TX_RING_IDX(prod);
6494 tx_buf = &txr->tx_buf_ring[ring_prod];
6495 pci_unmap_page(bp->pdev, pci_unmap_addr(tx_buf, mapping),
6496 skb_shinfo(skb)->frags[i].size,
6497 PCI_DMA_TODEVICE);
6498 }
6499
6500 dev_kfree_skb(skb);
6501 return NETDEV_TX_OK;
Michael Chanb6016b72005-05-26 13:03:09 -07006502}
6503
6504/* Called with rtnl_lock */
6505static int
6506bnx2_close(struct net_device *dev)
6507{
Michael Chan972ec0d2006-01-23 16:12:43 -08006508 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006509
David S. Miller4bb073c2008-06-12 02:22:02 -07006510 cancel_work_sync(&bp->reset_task);
Michael Chanafdc08b2005-08-25 15:34:29 -07006511
Stephen Hemmingerbea33482007-10-03 16:41:36 -07006512 bnx2_disable_int_sync(bp);
Michael Chan35efa7c2007-12-20 19:56:37 -08006513 bnx2_napi_disable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006514 del_timer_sync(&bp->timer);
Michael Chan74bf4ba2008-10-09 12:21:08 -07006515 bnx2_shutdown_chip(bp);
Michael Chan8e6a72c2007-05-03 13:24:48 -07006516 bnx2_free_irq(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006517 bnx2_free_skbs(bp);
6518 bnx2_free_mem(bp);
6519 bp->link_up = 0;
6520 netif_carrier_off(bp->dev);
Pavel Machek829ca9a2005-09-03 15:56:56 -07006521 bnx2_set_power_state(bp, PCI_D3hot);
Michael Chanb6016b72005-05-26 13:03:09 -07006522 return 0;
6523}
6524
6525#define GET_NET_STATS64(ctr) \
6526 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6527 (unsigned long) (ctr##_lo)
6528
6529#define GET_NET_STATS32(ctr) \
6530 (ctr##_lo)
6531
6532#if (BITS_PER_LONG == 64)
6533#define GET_NET_STATS GET_NET_STATS64
6534#else
6535#define GET_NET_STATS GET_NET_STATS32
6536#endif
6537
6538static struct net_device_stats *
6539bnx2_get_stats(struct net_device *dev)
6540{
Michael Chan972ec0d2006-01-23 16:12:43 -08006541 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006542 struct statistics_block *stats_blk = bp->stats_blk;
Ilpo Järvinend8e80342008-11-28 15:52:43 -08006543 struct net_device_stats *net_stats = &dev->stats;
Michael Chanb6016b72005-05-26 13:03:09 -07006544
6545 if (bp->stats_blk == NULL) {
6546 return net_stats;
6547 }
6548 net_stats->rx_packets =
6549 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6550 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6551 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6552
6553 net_stats->tx_packets =
6554 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6555 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6556 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6557
6558 net_stats->rx_bytes =
6559 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6560
6561 net_stats->tx_bytes =
6562 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6563
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006564 net_stats->multicast =
Michael Chanb6016b72005-05-26 13:03:09 -07006565 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6566
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006567 net_stats->collisions =
Michael Chanb6016b72005-05-26 13:03:09 -07006568 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6569
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006570 net_stats->rx_length_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07006571 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6572 stats_blk->stat_EtherStatsOverrsizePkts);
6573
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006574 net_stats->rx_over_errors =
Michael Chan790dab22009-08-21 16:20:47 +00006575 (unsigned long) (stats_blk->stat_IfInFTQDiscards +
6576 stats_blk->stat_IfInMBUFDiscards);
Michael Chanb6016b72005-05-26 13:03:09 -07006577
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006578 net_stats->rx_frame_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07006579 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6580
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006581 net_stats->rx_crc_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07006582 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6583
6584 net_stats->rx_errors = net_stats->rx_length_errors +
6585 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6586 net_stats->rx_crc_errors;
6587
6588 net_stats->tx_aborted_errors =
6589 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6590 stats_blk->stat_Dot3StatsLateCollisions);
6591
Michael Chan5b0c76a2005-11-04 08:45:49 -08006592 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6593 (CHIP_ID(bp) == CHIP_ID_5708_A0))
Michael Chanb6016b72005-05-26 13:03:09 -07006594 net_stats->tx_carrier_errors = 0;
6595 else {
6596 net_stats->tx_carrier_errors =
6597 (unsigned long)
6598 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6599 }
6600
6601 net_stats->tx_errors =
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006602 (unsigned long)
Michael Chanb6016b72005-05-26 13:03:09 -07006603 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6604 +
6605 net_stats->tx_aborted_errors +
6606 net_stats->tx_carrier_errors;
6607
Michael Chancea94db2006-06-12 22:16:13 -07006608 net_stats->rx_missed_errors =
Michael Chan790dab22009-08-21 16:20:47 +00006609 (unsigned long) (stats_blk->stat_IfInFTQDiscards +
6610 stats_blk->stat_IfInMBUFDiscards + stats_blk->stat_FwRxDrop);
Michael Chancea94db2006-06-12 22:16:13 -07006611
Michael Chanb6016b72005-05-26 13:03:09 -07006612 return net_stats;
6613}
6614
6615/* All ethtool functions called with rtnl_lock */
6616
6617static int
6618bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6619{
Michael Chan972ec0d2006-01-23 16:12:43 -08006620 struct bnx2 *bp = netdev_priv(dev);
Michael Chan7b6b8342007-07-07 22:50:15 -07006621 int support_serdes = 0, support_copper = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07006622
6623 cmd->supported = SUPPORTED_Autoneg;
Michael Chan583c28e2008-01-21 19:51:35 -08006624 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan7b6b8342007-07-07 22:50:15 -07006625 support_serdes = 1;
6626 support_copper = 1;
6627 } else if (bp->phy_port == PORT_FIBRE)
6628 support_serdes = 1;
6629 else
6630 support_copper = 1;
6631
6632 if (support_serdes) {
Michael Chanb6016b72005-05-26 13:03:09 -07006633 cmd->supported |= SUPPORTED_1000baseT_Full |
6634 SUPPORTED_FIBRE;
Michael Chan583c28e2008-01-21 19:51:35 -08006635 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
Michael Chan605a9e22007-05-03 13:23:13 -07006636 cmd->supported |= SUPPORTED_2500baseX_Full;
Michael Chanb6016b72005-05-26 13:03:09 -07006637
Michael Chanb6016b72005-05-26 13:03:09 -07006638 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006639 if (support_copper) {
Michael Chanb6016b72005-05-26 13:03:09 -07006640 cmd->supported |= SUPPORTED_10baseT_Half |
6641 SUPPORTED_10baseT_Full |
6642 SUPPORTED_100baseT_Half |
6643 SUPPORTED_100baseT_Full |
6644 SUPPORTED_1000baseT_Full |
6645 SUPPORTED_TP;
6646
Michael Chanb6016b72005-05-26 13:03:09 -07006647 }
6648
Michael Chan7b6b8342007-07-07 22:50:15 -07006649 spin_lock_bh(&bp->phy_lock);
6650 cmd->port = bp->phy_port;
Michael Chanb6016b72005-05-26 13:03:09 -07006651 cmd->advertising = bp->advertising;
6652
6653 if (bp->autoneg & AUTONEG_SPEED) {
6654 cmd->autoneg = AUTONEG_ENABLE;
6655 }
6656 else {
6657 cmd->autoneg = AUTONEG_DISABLE;
6658 }
6659
6660 if (netif_carrier_ok(dev)) {
6661 cmd->speed = bp->line_speed;
6662 cmd->duplex = bp->duplex;
6663 }
6664 else {
6665 cmd->speed = -1;
6666 cmd->duplex = -1;
6667 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006668 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006669
6670 cmd->transceiver = XCVR_INTERNAL;
6671 cmd->phy_address = bp->phy_addr;
6672
6673 return 0;
6674}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006675
Michael Chanb6016b72005-05-26 13:03:09 -07006676static int
6677bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6678{
Michael Chan972ec0d2006-01-23 16:12:43 -08006679 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006680 u8 autoneg = bp->autoneg;
6681 u8 req_duplex = bp->req_duplex;
6682 u16 req_line_speed = bp->req_line_speed;
6683 u32 advertising = bp->advertising;
Michael Chan7b6b8342007-07-07 22:50:15 -07006684 int err = -EINVAL;
6685
6686 spin_lock_bh(&bp->phy_lock);
6687
6688 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6689 goto err_out_unlock;
6690
Michael Chan583c28e2008-01-21 19:51:35 -08006691 if (cmd->port != bp->phy_port &&
6692 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
Michael Chan7b6b8342007-07-07 22:50:15 -07006693 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006694
Michael Chand6b14482008-07-14 22:37:21 -07006695 /* If device is down, we can store the settings only if the user
6696 * is setting the currently active port.
6697 */
6698 if (!netif_running(dev) && cmd->port != bp->phy_port)
6699 goto err_out_unlock;
6700
Michael Chanb6016b72005-05-26 13:03:09 -07006701 if (cmd->autoneg == AUTONEG_ENABLE) {
6702 autoneg |= AUTONEG_SPEED;
6703
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006704 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
Michael Chanb6016b72005-05-26 13:03:09 -07006705
6706 /* allow advertising 1 speed */
6707 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6708 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6709 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6710 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6711
Michael Chan7b6b8342007-07-07 22:50:15 -07006712 if (cmd->port == PORT_FIBRE)
6713 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006714
6715 advertising = cmd->advertising;
6716
Michael Chan27a005b2007-05-03 13:23:41 -07006717 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
Michael Chan583c28e2008-01-21 19:51:35 -08006718 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
Michael Chan7b6b8342007-07-07 22:50:15 -07006719 (cmd->port == PORT_TP))
6720 goto err_out_unlock;
6721 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
Michael Chanb6016b72005-05-26 13:03:09 -07006722 advertising = cmd->advertising;
Michael Chan7b6b8342007-07-07 22:50:15 -07006723 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6724 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006725 else {
Michael Chan7b6b8342007-07-07 22:50:15 -07006726 if (cmd->port == PORT_FIBRE)
Michael Chanb6016b72005-05-26 13:03:09 -07006727 advertising = ETHTOOL_ALL_FIBRE_SPEED;
Michael Chan7b6b8342007-07-07 22:50:15 -07006728 else
Michael Chanb6016b72005-05-26 13:03:09 -07006729 advertising = ETHTOOL_ALL_COPPER_SPEED;
Michael Chanb6016b72005-05-26 13:03:09 -07006730 }
6731 advertising |= ADVERTISED_Autoneg;
6732 }
6733 else {
Michael Chan7b6b8342007-07-07 22:50:15 -07006734 if (cmd->port == PORT_FIBRE) {
Michael Chan80be4432006-11-19 14:07:28 -08006735 if ((cmd->speed != SPEED_1000 &&
6736 cmd->speed != SPEED_2500) ||
6737 (cmd->duplex != DUPLEX_FULL))
Michael Chan7b6b8342007-07-07 22:50:15 -07006738 goto err_out_unlock;
Michael Chan80be4432006-11-19 14:07:28 -08006739
6740 if (cmd->speed == SPEED_2500 &&
Michael Chan583c28e2008-01-21 19:51:35 -08006741 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan7b6b8342007-07-07 22:50:15 -07006742 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006743 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006744 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6745 goto err_out_unlock;
6746
Michael Chanb6016b72005-05-26 13:03:09 -07006747 autoneg &= ~AUTONEG_SPEED;
6748 req_line_speed = cmd->speed;
6749 req_duplex = cmd->duplex;
6750 advertising = 0;
6751 }
6752
6753 bp->autoneg = autoneg;
6754 bp->advertising = advertising;
6755 bp->req_line_speed = req_line_speed;
6756 bp->req_duplex = req_duplex;
6757
Michael Chand6b14482008-07-14 22:37:21 -07006758 err = 0;
6759 /* If device is down, the new settings will be picked up when it is
6760 * brought up.
6761 */
6762 if (netif_running(dev))
6763 err = bnx2_setup_phy(bp, cmd->port);
Michael Chanb6016b72005-05-26 13:03:09 -07006764
Michael Chan7b6b8342007-07-07 22:50:15 -07006765err_out_unlock:
Michael Chanc770a652005-08-25 15:38:39 -07006766 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006767
Michael Chan7b6b8342007-07-07 22:50:15 -07006768 return err;
Michael Chanb6016b72005-05-26 13:03:09 -07006769}
6770
6771static void
6772bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6773{
Michael Chan972ec0d2006-01-23 16:12:43 -08006774 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006775
6776 strcpy(info->driver, DRV_MODULE_NAME);
6777 strcpy(info->version, DRV_MODULE_VERSION);
6778 strcpy(info->bus_info, pci_name(bp->pdev));
Michael Chan58fc2ea2007-07-07 22:52:02 -07006779 strcpy(info->fw_version, bp->fw_version);
Michael Chanb6016b72005-05-26 13:03:09 -07006780}
6781
Michael Chan244ac4f2006-03-20 17:48:46 -08006782#define BNX2_REGDUMP_LEN (32 * 1024)
6783
6784static int
6785bnx2_get_regs_len(struct net_device *dev)
6786{
6787 return BNX2_REGDUMP_LEN;
6788}
6789
6790static void
6791bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6792{
6793 u32 *p = _p, i, offset;
6794 u8 *orig_p = _p;
6795 struct bnx2 *bp = netdev_priv(dev);
6796 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6797 0x0800, 0x0880, 0x0c00, 0x0c10,
6798 0x0c30, 0x0d08, 0x1000, 0x101c,
6799 0x1040, 0x1048, 0x1080, 0x10a4,
6800 0x1400, 0x1490, 0x1498, 0x14f0,
6801 0x1500, 0x155c, 0x1580, 0x15dc,
6802 0x1600, 0x1658, 0x1680, 0x16d8,
6803 0x1800, 0x1820, 0x1840, 0x1854,
6804 0x1880, 0x1894, 0x1900, 0x1984,
6805 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6806 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6807 0x2000, 0x2030, 0x23c0, 0x2400,
6808 0x2800, 0x2820, 0x2830, 0x2850,
6809 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6810 0x3c00, 0x3c94, 0x4000, 0x4010,
6811 0x4080, 0x4090, 0x43c0, 0x4458,
6812 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6813 0x4fc0, 0x5010, 0x53c0, 0x5444,
6814 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6815 0x5fc0, 0x6000, 0x6400, 0x6428,
6816 0x6800, 0x6848, 0x684c, 0x6860,
6817 0x6888, 0x6910, 0x8000 };
6818
6819 regs->version = 0;
6820
6821 memset(p, 0, BNX2_REGDUMP_LEN);
6822
6823 if (!netif_running(bp->dev))
6824 return;
6825
6826 i = 0;
6827 offset = reg_boundaries[0];
6828 p += offset;
6829 while (offset < BNX2_REGDUMP_LEN) {
6830 *p++ = REG_RD(bp, offset);
6831 offset += 4;
6832 if (offset == reg_boundaries[i + 1]) {
6833 offset = reg_boundaries[i + 2];
6834 p = (u32 *) (orig_p + offset);
6835 i += 2;
6836 }
6837 }
6838}
6839
Michael Chanb6016b72005-05-26 13:03:09 -07006840static void
6841bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6842{
Michael Chan972ec0d2006-01-23 16:12:43 -08006843 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006844
David S. Millerf86e82f2008-01-21 17:15:40 -08006845 if (bp->flags & BNX2_FLAG_NO_WOL) {
Michael Chanb6016b72005-05-26 13:03:09 -07006846 wol->supported = 0;
6847 wol->wolopts = 0;
6848 }
6849 else {
6850 wol->supported = WAKE_MAGIC;
6851 if (bp->wol)
6852 wol->wolopts = WAKE_MAGIC;
6853 else
6854 wol->wolopts = 0;
6855 }
6856 memset(&wol->sopass, 0, sizeof(wol->sopass));
6857}
6858
6859static int
6860bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6861{
Michael Chan972ec0d2006-01-23 16:12:43 -08006862 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006863
6864 if (wol->wolopts & ~WAKE_MAGIC)
6865 return -EINVAL;
6866
6867 if (wol->wolopts & WAKE_MAGIC) {
David S. Millerf86e82f2008-01-21 17:15:40 -08006868 if (bp->flags & BNX2_FLAG_NO_WOL)
Michael Chanb6016b72005-05-26 13:03:09 -07006869 return -EINVAL;
6870
6871 bp->wol = 1;
6872 }
6873 else {
6874 bp->wol = 0;
6875 }
6876 return 0;
6877}
6878
6879static int
6880bnx2_nway_reset(struct net_device *dev)
6881{
Michael Chan972ec0d2006-01-23 16:12:43 -08006882 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006883 u32 bmcr;
6884
Michael Chan9f52b562008-10-09 12:21:46 -07006885 if (!netif_running(dev))
6886 return -EAGAIN;
6887
Michael Chanb6016b72005-05-26 13:03:09 -07006888 if (!(bp->autoneg & AUTONEG_SPEED)) {
6889 return -EINVAL;
6890 }
6891
Michael Chanc770a652005-08-25 15:38:39 -07006892 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006893
Michael Chan583c28e2008-01-21 19:51:35 -08006894 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan7b6b8342007-07-07 22:50:15 -07006895 int rc;
6896
6897 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6898 spin_unlock_bh(&bp->phy_lock);
6899 return rc;
6900 }
6901
Michael Chanb6016b72005-05-26 13:03:09 -07006902 /* Force a link down visible on the other side */
Michael Chan583c28e2008-01-21 19:51:35 -08006903 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanca58c3a2007-05-03 13:22:52 -07006904 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chanc770a652005-08-25 15:38:39 -07006905 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006906
6907 msleep(20);
6908
Michael Chanc770a652005-08-25 15:38:39 -07006909 spin_lock_bh(&bp->phy_lock);
Michael Chanf8dd0642006-11-19 14:08:29 -08006910
Michael Chan40105c02008-11-12 16:02:45 -08006911 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
Michael Chanf8dd0642006-11-19 14:08:29 -08006912 bp->serdes_an_pending = 1;
6913 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07006914 }
6915
Michael Chanca58c3a2007-05-03 13:22:52 -07006916 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07006917 bmcr &= ~BMCR_LOOPBACK;
Michael Chanca58c3a2007-05-03 13:22:52 -07006918 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
Michael Chanb6016b72005-05-26 13:03:09 -07006919
Michael Chanc770a652005-08-25 15:38:39 -07006920 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006921
6922 return 0;
6923}
6924
Ooiwa Naohiro7959ea22009-06-24 00:19:06 -07006925static u32
6926bnx2_get_link(struct net_device *dev)
6927{
6928 struct bnx2 *bp = netdev_priv(dev);
6929
6930 return bp->link_up;
6931}
6932
Michael Chanb6016b72005-05-26 13:03:09 -07006933static int
6934bnx2_get_eeprom_len(struct net_device *dev)
6935{
Michael Chan972ec0d2006-01-23 16:12:43 -08006936 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006937
Michael Chan1122db72006-01-23 16:11:42 -08006938 if (bp->flash_info == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07006939 return 0;
6940
Michael Chan1122db72006-01-23 16:11:42 -08006941 return (int) bp->flash_size;
Michael Chanb6016b72005-05-26 13:03:09 -07006942}
6943
6944static int
6945bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6946 u8 *eebuf)
6947{
Michael Chan972ec0d2006-01-23 16:12:43 -08006948 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006949 int rc;
6950
Michael Chan9f52b562008-10-09 12:21:46 -07006951 if (!netif_running(dev))
6952 return -EAGAIN;
6953
John W. Linville1064e942005-11-10 12:58:24 -08006954 /* parameters already validated in ethtool_get_eeprom */
Michael Chanb6016b72005-05-26 13:03:09 -07006955
6956 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6957
6958 return rc;
6959}
6960
6961static int
6962bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6963 u8 *eebuf)
6964{
Michael Chan972ec0d2006-01-23 16:12:43 -08006965 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006966 int rc;
6967
Michael Chan9f52b562008-10-09 12:21:46 -07006968 if (!netif_running(dev))
6969 return -EAGAIN;
6970
John W. Linville1064e942005-11-10 12:58:24 -08006971 /* parameters already validated in ethtool_set_eeprom */
Michael Chanb6016b72005-05-26 13:03:09 -07006972
6973 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6974
6975 return rc;
6976}
6977
6978static int
6979bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6980{
Michael Chan972ec0d2006-01-23 16:12:43 -08006981 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006982
6983 memset(coal, 0, sizeof(struct ethtool_coalesce));
6984
6985 coal->rx_coalesce_usecs = bp->rx_ticks;
6986 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6987 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6988 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6989
6990 coal->tx_coalesce_usecs = bp->tx_ticks;
6991 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6992 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6993 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6994
6995 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6996
6997 return 0;
6998}
6999
7000static int
7001bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7002{
Michael Chan972ec0d2006-01-23 16:12:43 -08007003 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007004
7005 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7006 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7007
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007008 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
Michael Chanb6016b72005-05-26 13:03:09 -07007009 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7010
7011 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7012 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7013
7014 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7015 if (bp->rx_quick_cons_trip_int > 0xff)
7016 bp->rx_quick_cons_trip_int = 0xff;
7017
7018 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7019 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7020
7021 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7022 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7023
7024 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7025 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7026
7027 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7028 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7029 0xff;
7030
7031 bp->stats_ticks = coal->stats_block_coalesce_usecs;
Michael Chan61d9e3f2009-08-21 16:20:46 +00007032 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
Michael Chan02537b062007-06-04 21:24:07 -07007033 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7034 bp->stats_ticks = USEC_PER_SEC;
7035 }
Michael Chan7ea69202007-07-16 18:27:10 -07007036 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7037 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7038 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
Michael Chanb6016b72005-05-26 13:03:09 -07007039
7040 if (netif_running(bp->dev)) {
7041 bnx2_netif_stop(bp);
Michael Chan9a120bc2008-05-16 22:17:45 -07007042 bnx2_init_nic(bp, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07007043 bnx2_netif_start(bp);
7044 }
7045
7046 return 0;
7047}
7048
7049static void
7050bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7051{
Michael Chan972ec0d2006-01-23 16:12:43 -08007052 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007053
Michael Chan13daffa2006-03-20 17:49:20 -08007054 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
Michael Chanb6016b72005-05-26 13:03:09 -07007055 ering->rx_mini_max_pending = 0;
Michael Chan47bf4242007-12-12 11:19:12 -08007056 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
Michael Chanb6016b72005-05-26 13:03:09 -07007057
7058 ering->rx_pending = bp->rx_ring_size;
7059 ering->rx_mini_pending = 0;
Michael Chan47bf4242007-12-12 11:19:12 -08007060 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
Michael Chanb6016b72005-05-26 13:03:09 -07007061
7062 ering->tx_max_pending = MAX_TX_DESC_CNT;
7063 ering->tx_pending = bp->tx_ring_size;
7064}
7065
7066static int
Michael Chan5d5d0012007-12-12 11:17:43 -08007067bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
Michael Chanb6016b72005-05-26 13:03:09 -07007068{
Michael Chan13daffa2006-03-20 17:49:20 -08007069 if (netif_running(bp->dev)) {
7070 bnx2_netif_stop(bp);
7071 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7072 bnx2_free_skbs(bp);
7073 bnx2_free_mem(bp);
7074 }
7075
Michael Chan5d5d0012007-12-12 11:17:43 -08007076 bnx2_set_rx_ring_size(bp, rx);
7077 bp->tx_ring_size = tx;
Michael Chanb6016b72005-05-26 13:03:09 -07007078
7079 if (netif_running(bp->dev)) {
Michael Chan13daffa2006-03-20 17:49:20 -08007080 int rc;
7081
7082 rc = bnx2_alloc_mem(bp);
Michael Chan6fefb65e2009-08-21 16:20:45 +00007083 if (!rc)
7084 rc = bnx2_init_nic(bp, 0);
7085
7086 if (rc) {
7087 bnx2_napi_enable(bp);
7088 dev_close(bp->dev);
Michael Chan13daffa2006-03-20 17:49:20 -08007089 return rc;
Michael Chan6fefb65e2009-08-21 16:20:45 +00007090 }
Michael Chanb6016b72005-05-26 13:03:09 -07007091 bnx2_netif_start(bp);
7092 }
Michael Chanb6016b72005-05-26 13:03:09 -07007093 return 0;
7094}
7095
Michael Chan5d5d0012007-12-12 11:17:43 -08007096static int
7097bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7098{
7099 struct bnx2 *bp = netdev_priv(dev);
7100 int rc;
7101
7102 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7103 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7104 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7105
7106 return -EINVAL;
7107 }
7108 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7109 return rc;
7110}
7111
Michael Chanb6016b72005-05-26 13:03:09 -07007112static void
7113bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7114{
Michael Chan972ec0d2006-01-23 16:12:43 -08007115 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007116
7117 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7118 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7119 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7120}
7121
7122static int
7123bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7124{
Michael Chan972ec0d2006-01-23 16:12:43 -08007125 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007126
7127 bp->req_flow_ctrl = 0;
7128 if (epause->rx_pause)
7129 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7130 if (epause->tx_pause)
7131 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7132
7133 if (epause->autoneg) {
7134 bp->autoneg |= AUTONEG_FLOW_CTRL;
7135 }
7136 else {
7137 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7138 }
7139
Michael Chan9f52b562008-10-09 12:21:46 -07007140 if (netif_running(dev)) {
7141 spin_lock_bh(&bp->phy_lock);
7142 bnx2_setup_phy(bp, bp->phy_port);
7143 spin_unlock_bh(&bp->phy_lock);
7144 }
Michael Chanb6016b72005-05-26 13:03:09 -07007145
7146 return 0;
7147}
7148
7149static u32
7150bnx2_get_rx_csum(struct net_device *dev)
7151{
Michael Chan972ec0d2006-01-23 16:12:43 -08007152 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007153
7154 return bp->rx_csum;
7155}
7156
7157static int
7158bnx2_set_rx_csum(struct net_device *dev, u32 data)
7159{
Michael Chan972ec0d2006-01-23 16:12:43 -08007160 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007161
7162 bp->rx_csum = data;
7163 return 0;
7164}
7165
Michael Chanb11d6212006-06-29 12:31:21 -07007166static int
7167bnx2_set_tso(struct net_device *dev, u32 data)
7168{
Michael Chan4666f872007-05-03 13:22:28 -07007169 struct bnx2 *bp = netdev_priv(dev);
7170
7171 if (data) {
Michael Chanb11d6212006-06-29 12:31:21 -07007172 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
Michael Chan4666f872007-05-03 13:22:28 -07007173 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7174 dev->features |= NETIF_F_TSO6;
7175 } else
7176 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7177 NETIF_F_TSO_ECN);
Michael Chanb11d6212006-06-29 12:31:21 -07007178 return 0;
7179}
7180
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007181static struct {
Michael Chanb6016b72005-05-26 13:03:09 -07007182 char string[ETH_GSTRING_LEN];
Michael Chan790dab22009-08-21 16:20:47 +00007183} bnx2_stats_str_arr[] = {
Michael Chanb6016b72005-05-26 13:03:09 -07007184 { "rx_bytes" },
7185 { "rx_error_bytes" },
7186 { "tx_bytes" },
7187 { "tx_error_bytes" },
7188 { "rx_ucast_packets" },
7189 { "rx_mcast_packets" },
7190 { "rx_bcast_packets" },
7191 { "tx_ucast_packets" },
7192 { "tx_mcast_packets" },
7193 { "tx_bcast_packets" },
7194 { "tx_mac_errors" },
7195 { "tx_carrier_errors" },
7196 { "rx_crc_errors" },
7197 { "rx_align_errors" },
7198 { "tx_single_collisions" },
7199 { "tx_multi_collisions" },
7200 { "tx_deferred" },
7201 { "tx_excess_collisions" },
7202 { "tx_late_collisions" },
7203 { "tx_total_collisions" },
7204 { "rx_fragments" },
7205 { "rx_jabbers" },
7206 { "rx_undersize_packets" },
7207 { "rx_oversize_packets" },
7208 { "rx_64_byte_packets" },
7209 { "rx_65_to_127_byte_packets" },
7210 { "rx_128_to_255_byte_packets" },
7211 { "rx_256_to_511_byte_packets" },
7212 { "rx_512_to_1023_byte_packets" },
7213 { "rx_1024_to_1522_byte_packets" },
7214 { "rx_1523_to_9022_byte_packets" },
7215 { "tx_64_byte_packets" },
7216 { "tx_65_to_127_byte_packets" },
7217 { "tx_128_to_255_byte_packets" },
7218 { "tx_256_to_511_byte_packets" },
7219 { "tx_512_to_1023_byte_packets" },
7220 { "tx_1024_to_1522_byte_packets" },
7221 { "tx_1523_to_9022_byte_packets" },
7222 { "rx_xon_frames" },
7223 { "rx_xoff_frames" },
7224 { "tx_xon_frames" },
7225 { "tx_xoff_frames" },
7226 { "rx_mac_ctrl_frames" },
7227 { "rx_filtered_packets" },
Michael Chan790dab22009-08-21 16:20:47 +00007228 { "rx_ftq_discards" },
Michael Chanb6016b72005-05-26 13:03:09 -07007229 { "rx_discards" },
Michael Chancea94db2006-06-12 22:16:13 -07007230 { "rx_fw_discards" },
Michael Chanb6016b72005-05-26 13:03:09 -07007231};
7232
Michael Chan790dab22009-08-21 16:20:47 +00007233#define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7234 sizeof(bnx2_stats_str_arr[0]))
7235
Michael Chanb6016b72005-05-26 13:03:09 -07007236#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7237
Arjan van de Venf71e1302006-03-03 21:33:57 -05007238static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -07007239 STATS_OFFSET32(stat_IfHCInOctets_hi),
7240 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7241 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7242 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7243 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7244 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7245 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7246 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7247 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7248 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7249 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007250 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7251 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7252 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7253 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7254 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7255 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7256 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7257 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7258 STATS_OFFSET32(stat_EtherStatsCollisions),
7259 STATS_OFFSET32(stat_EtherStatsFragments),
7260 STATS_OFFSET32(stat_EtherStatsJabbers),
7261 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7262 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7263 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7264 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7265 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7266 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7267 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7268 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7269 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7270 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7271 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7272 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7273 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7274 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7275 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7276 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7277 STATS_OFFSET32(stat_XonPauseFramesReceived),
7278 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7279 STATS_OFFSET32(stat_OutXonSent),
7280 STATS_OFFSET32(stat_OutXoffSent),
7281 STATS_OFFSET32(stat_MacControlFramesReceived),
7282 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
Michael Chan790dab22009-08-21 16:20:47 +00007283 STATS_OFFSET32(stat_IfInFTQDiscards),
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007284 STATS_OFFSET32(stat_IfInMBUFDiscards),
Michael Chancea94db2006-06-12 22:16:13 -07007285 STATS_OFFSET32(stat_FwRxDrop),
Michael Chanb6016b72005-05-26 13:03:09 -07007286};
7287
7288/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7289 * skipped because of errata.
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007290 */
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007291static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -07007292 8,0,8,8,8,8,8,8,8,8,
7293 4,0,4,4,4,4,4,4,4,4,
7294 4,4,4,4,4,4,4,4,4,4,
7295 4,4,4,4,4,4,4,4,4,4,
Michael Chan790dab22009-08-21 16:20:47 +00007296 4,4,4,4,4,4,4,
Michael Chanb6016b72005-05-26 13:03:09 -07007297};
7298
Michael Chan5b0c76a2005-11-04 08:45:49 -08007299static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7300 8,0,8,8,8,8,8,8,8,8,
7301 4,4,4,4,4,4,4,4,4,4,
7302 4,4,4,4,4,4,4,4,4,4,
7303 4,4,4,4,4,4,4,4,4,4,
Michael Chan790dab22009-08-21 16:20:47 +00007304 4,4,4,4,4,4,4,
Michael Chan5b0c76a2005-11-04 08:45:49 -08007305};
7306
Michael Chanb6016b72005-05-26 13:03:09 -07007307#define BNX2_NUM_TESTS 6
7308
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007309static struct {
Michael Chanb6016b72005-05-26 13:03:09 -07007310 char string[ETH_GSTRING_LEN];
7311} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7312 { "register_test (offline)" },
7313 { "memory_test (offline)" },
7314 { "loopback_test (offline)" },
7315 { "nvram_test (online)" },
7316 { "interrupt_test (online)" },
7317 { "link_test (online)" },
7318};
7319
7320static int
Jeff Garzikb9f2c042007-10-03 18:07:32 -07007321bnx2_get_sset_count(struct net_device *dev, int sset)
Michael Chanb6016b72005-05-26 13:03:09 -07007322{
Jeff Garzikb9f2c042007-10-03 18:07:32 -07007323 switch (sset) {
7324 case ETH_SS_TEST:
7325 return BNX2_NUM_TESTS;
7326 case ETH_SS_STATS:
7327 return BNX2_NUM_STATS;
7328 default:
7329 return -EOPNOTSUPP;
7330 }
Michael Chanb6016b72005-05-26 13:03:09 -07007331}
7332
7333static void
7334bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7335{
Michael Chan972ec0d2006-01-23 16:12:43 -08007336 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007337
Michael Chan9f52b562008-10-09 12:21:46 -07007338 bnx2_set_power_state(bp, PCI_D0);
7339
Michael Chanb6016b72005-05-26 13:03:09 -07007340 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7341 if (etest->flags & ETH_TEST_FL_OFFLINE) {
Michael Chan80be4432006-11-19 14:07:28 -08007342 int i;
7343
Michael Chanb6016b72005-05-26 13:03:09 -07007344 bnx2_netif_stop(bp);
7345 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7346 bnx2_free_skbs(bp);
7347
7348 if (bnx2_test_registers(bp) != 0) {
7349 buf[0] = 1;
7350 etest->flags |= ETH_TEST_FL_FAILED;
7351 }
7352 if (bnx2_test_memory(bp) != 0) {
7353 buf[1] = 1;
7354 etest->flags |= ETH_TEST_FL_FAILED;
7355 }
Michael Chanbc5a0692006-01-23 16:13:22 -08007356 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
Michael Chanb6016b72005-05-26 13:03:09 -07007357 etest->flags |= ETH_TEST_FL_FAILED;
Michael Chanb6016b72005-05-26 13:03:09 -07007358
Michael Chan9f52b562008-10-09 12:21:46 -07007359 if (!netif_running(bp->dev))
7360 bnx2_shutdown_chip(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007361 else {
Michael Chan9a120bc2008-05-16 22:17:45 -07007362 bnx2_init_nic(bp, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07007363 bnx2_netif_start(bp);
7364 }
7365
7366 /* wait for link up */
Michael Chan80be4432006-11-19 14:07:28 -08007367 for (i = 0; i < 7; i++) {
7368 if (bp->link_up)
7369 break;
7370 msleep_interruptible(1000);
7371 }
Michael Chanb6016b72005-05-26 13:03:09 -07007372 }
7373
7374 if (bnx2_test_nvram(bp) != 0) {
7375 buf[3] = 1;
7376 etest->flags |= ETH_TEST_FL_FAILED;
7377 }
7378 if (bnx2_test_intr(bp) != 0) {
7379 buf[4] = 1;
7380 etest->flags |= ETH_TEST_FL_FAILED;
7381 }
7382
7383 if (bnx2_test_link(bp) != 0) {
7384 buf[5] = 1;
7385 etest->flags |= ETH_TEST_FL_FAILED;
7386
7387 }
Michael Chan9f52b562008-10-09 12:21:46 -07007388 if (!netif_running(bp->dev))
7389 bnx2_set_power_state(bp, PCI_D3hot);
Michael Chanb6016b72005-05-26 13:03:09 -07007390}
7391
7392static void
7393bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7394{
7395 switch (stringset) {
7396 case ETH_SS_STATS:
7397 memcpy(buf, bnx2_stats_str_arr,
7398 sizeof(bnx2_stats_str_arr));
7399 break;
7400 case ETH_SS_TEST:
7401 memcpy(buf, bnx2_tests_str_arr,
7402 sizeof(bnx2_tests_str_arr));
7403 break;
7404 }
7405}
7406
Michael Chanb6016b72005-05-26 13:03:09 -07007407static void
7408bnx2_get_ethtool_stats(struct net_device *dev,
7409 struct ethtool_stats *stats, u64 *buf)
7410{
Michael Chan972ec0d2006-01-23 16:12:43 -08007411 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007412 int i;
7413 u32 *hw_stats = (u32 *) bp->stats_blk;
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007414 u8 *stats_len_arr = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07007415
7416 if (hw_stats == NULL) {
7417 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7418 return;
7419 }
7420
Michael Chan5b0c76a2005-11-04 08:45:49 -08007421 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7422 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7423 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7424 (CHIP_ID(bp) == CHIP_ID_5708_A0))
Michael Chanb6016b72005-05-26 13:03:09 -07007425 stats_len_arr = bnx2_5706_stats_len_arr;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007426 else
7427 stats_len_arr = bnx2_5708_stats_len_arr;
Michael Chanb6016b72005-05-26 13:03:09 -07007428
7429 for (i = 0; i < BNX2_NUM_STATS; i++) {
7430 if (stats_len_arr[i] == 0) {
7431 /* skip this counter */
7432 buf[i] = 0;
7433 continue;
7434 }
7435 if (stats_len_arr[i] == 4) {
7436 /* 4-byte counter */
7437 buf[i] = (u64)
7438 *(hw_stats + bnx2_stats_offset_arr[i]);
7439 continue;
7440 }
7441 /* 8-byte counter */
7442 buf[i] = (((u64) *(hw_stats +
7443 bnx2_stats_offset_arr[i])) << 32) +
7444 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7445 }
7446}
7447
7448static int
7449bnx2_phys_id(struct net_device *dev, u32 data)
7450{
Michael Chan972ec0d2006-01-23 16:12:43 -08007451 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007452 int i;
7453 u32 save;
7454
Michael Chan9f52b562008-10-09 12:21:46 -07007455 bnx2_set_power_state(bp, PCI_D0);
7456
Michael Chanb6016b72005-05-26 13:03:09 -07007457 if (data == 0)
7458 data = 2;
7459
7460 save = REG_RD(bp, BNX2_MISC_CFG);
7461 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7462
7463 for (i = 0; i < (data * 2); i++) {
7464 if ((i % 2) == 0) {
7465 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7466 }
7467 else {
7468 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7469 BNX2_EMAC_LED_1000MB_OVERRIDE |
7470 BNX2_EMAC_LED_100MB_OVERRIDE |
7471 BNX2_EMAC_LED_10MB_OVERRIDE |
7472 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7473 BNX2_EMAC_LED_TRAFFIC);
7474 }
7475 msleep_interruptible(500);
7476 if (signal_pending(current))
7477 break;
7478 }
7479 REG_WR(bp, BNX2_EMAC_LED, 0);
7480 REG_WR(bp, BNX2_MISC_CFG, save);
Michael Chan9f52b562008-10-09 12:21:46 -07007481
7482 if (!netif_running(dev))
7483 bnx2_set_power_state(bp, PCI_D3hot);
7484
Michael Chanb6016b72005-05-26 13:03:09 -07007485 return 0;
7486}
7487
Michael Chan4666f872007-05-03 13:22:28 -07007488static int
7489bnx2_set_tx_csum(struct net_device *dev, u32 data)
7490{
7491 struct bnx2 *bp = netdev_priv(dev);
7492
7493 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chan6460d942007-07-14 19:07:52 -07007494 return (ethtool_op_set_tx_ipv6_csum(dev, data));
Michael Chan4666f872007-05-03 13:22:28 -07007495 else
7496 return (ethtool_op_set_tx_csum(dev, data));
7497}
7498
Jeff Garzik7282d492006-09-13 14:30:00 -04007499static const struct ethtool_ops bnx2_ethtool_ops = {
Michael Chanb6016b72005-05-26 13:03:09 -07007500 .get_settings = bnx2_get_settings,
7501 .set_settings = bnx2_set_settings,
7502 .get_drvinfo = bnx2_get_drvinfo,
Michael Chan244ac4f2006-03-20 17:48:46 -08007503 .get_regs_len = bnx2_get_regs_len,
7504 .get_regs = bnx2_get_regs,
Michael Chanb6016b72005-05-26 13:03:09 -07007505 .get_wol = bnx2_get_wol,
7506 .set_wol = bnx2_set_wol,
7507 .nway_reset = bnx2_nway_reset,
Ooiwa Naohiro7959ea22009-06-24 00:19:06 -07007508 .get_link = bnx2_get_link,
Michael Chanb6016b72005-05-26 13:03:09 -07007509 .get_eeprom_len = bnx2_get_eeprom_len,
7510 .get_eeprom = bnx2_get_eeprom,
7511 .set_eeprom = bnx2_set_eeprom,
7512 .get_coalesce = bnx2_get_coalesce,
7513 .set_coalesce = bnx2_set_coalesce,
7514 .get_ringparam = bnx2_get_ringparam,
7515 .set_ringparam = bnx2_set_ringparam,
7516 .get_pauseparam = bnx2_get_pauseparam,
7517 .set_pauseparam = bnx2_set_pauseparam,
7518 .get_rx_csum = bnx2_get_rx_csum,
7519 .set_rx_csum = bnx2_set_rx_csum,
Michael Chan4666f872007-05-03 13:22:28 -07007520 .set_tx_csum = bnx2_set_tx_csum,
Michael Chanb6016b72005-05-26 13:03:09 -07007521 .set_sg = ethtool_op_set_sg,
Michael Chanb11d6212006-06-29 12:31:21 -07007522 .set_tso = bnx2_set_tso,
Michael Chanb6016b72005-05-26 13:03:09 -07007523 .self_test = bnx2_self_test,
7524 .get_strings = bnx2_get_strings,
7525 .phys_id = bnx2_phys_id,
Michael Chanb6016b72005-05-26 13:03:09 -07007526 .get_ethtool_stats = bnx2_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07007527 .get_sset_count = bnx2_get_sset_count,
Michael Chanb6016b72005-05-26 13:03:09 -07007528};
7529
7530/* Called with rtnl_lock */
7531static int
7532bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7533{
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007534 struct mii_ioctl_data *data = if_mii(ifr);
Michael Chan972ec0d2006-01-23 16:12:43 -08007535 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007536 int err;
7537
7538 switch(cmd) {
7539 case SIOCGMIIPHY:
7540 data->phy_id = bp->phy_addr;
7541
7542 /* fallthru */
7543 case SIOCGMIIREG: {
7544 u32 mii_regval;
7545
Michael Chan583c28e2008-01-21 19:51:35 -08007546 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan7b6b8342007-07-07 22:50:15 -07007547 return -EOPNOTSUPP;
7548
Michael Chandad3e452007-05-03 13:18:03 -07007549 if (!netif_running(dev))
7550 return -EAGAIN;
7551
Michael Chanc770a652005-08-25 15:38:39 -07007552 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007553 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
Michael Chanc770a652005-08-25 15:38:39 -07007554 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007555
7556 data->val_out = mii_regval;
7557
7558 return err;
7559 }
7560
7561 case SIOCSMIIREG:
Michael Chan583c28e2008-01-21 19:51:35 -08007562 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan7b6b8342007-07-07 22:50:15 -07007563 return -EOPNOTSUPP;
7564
Michael Chandad3e452007-05-03 13:18:03 -07007565 if (!netif_running(dev))
7566 return -EAGAIN;
7567
Michael Chanc770a652005-08-25 15:38:39 -07007568 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007569 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
Michael Chanc770a652005-08-25 15:38:39 -07007570 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007571
7572 return err;
7573
7574 default:
7575 /* do nothing */
7576 break;
7577 }
7578 return -EOPNOTSUPP;
7579}
7580
7581/* Called with rtnl_lock */
7582static int
7583bnx2_change_mac_addr(struct net_device *dev, void *p)
7584{
7585 struct sockaddr *addr = p;
Michael Chan972ec0d2006-01-23 16:12:43 -08007586 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007587
Michael Chan73eef4c2005-08-25 15:39:15 -07007588 if (!is_valid_ether_addr(addr->sa_data))
7589 return -EINVAL;
7590
Michael Chanb6016b72005-05-26 13:03:09 -07007591 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7592 if (netif_running(dev))
Benjamin Li5fcaed02008-07-14 22:39:52 -07007593 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07007594
7595 return 0;
7596}
7597
7598/* Called with rtnl_lock */
7599static int
7600bnx2_change_mtu(struct net_device *dev, int new_mtu)
7601{
Michael Chan972ec0d2006-01-23 16:12:43 -08007602 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007603
7604 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7605 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7606 return -EINVAL;
7607
7608 dev->mtu = new_mtu;
Michael Chan5d5d0012007-12-12 11:17:43 -08007609 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
Michael Chanb6016b72005-05-26 13:03:09 -07007610}
7611
7612#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7613static void
7614poll_bnx2(struct net_device *dev)
7615{
Michael Chan972ec0d2006-01-23 16:12:43 -08007616 struct bnx2 *bp = netdev_priv(dev);
Neil Hormanb2af2c12008-11-12 16:23:44 -08007617 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07007618
Neil Hormanb2af2c12008-11-12 16:23:44 -08007619 for (i = 0; i < bp->irq_nvecs; i++) {
7620 disable_irq(bp->irq_tbl[i].vector);
7621 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7622 enable_irq(bp->irq_tbl[i].vector);
7623 }
Michael Chanb6016b72005-05-26 13:03:09 -07007624}
7625#endif
7626
Michael Chan253c8b72007-01-08 19:56:01 -08007627static void __devinit
7628bnx2_get_5709_media(struct bnx2 *bp)
7629{
7630 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7631 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7632 u32 strap;
7633
7634 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7635 return;
7636 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
Michael Chan583c28e2008-01-21 19:51:35 -08007637 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007638 return;
7639 }
7640
7641 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7642 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7643 else
7644 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7645
7646 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7647 switch (strap) {
7648 case 0x4:
7649 case 0x5:
7650 case 0x6:
Michael Chan583c28e2008-01-21 19:51:35 -08007651 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007652 return;
7653 }
7654 } else {
7655 switch (strap) {
7656 case 0x1:
7657 case 0x2:
7658 case 0x4:
Michael Chan583c28e2008-01-21 19:51:35 -08007659 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007660 return;
7661 }
7662 }
7663}
7664
Michael Chan883e5152007-05-03 13:25:11 -07007665static void __devinit
7666bnx2_get_pci_speed(struct bnx2 *bp)
7667{
7668 u32 reg;
7669
7670 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7671 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7672 u32 clkreg;
7673
David S. Millerf86e82f2008-01-21 17:15:40 -08007674 bp->flags |= BNX2_FLAG_PCIX;
Michael Chan883e5152007-05-03 13:25:11 -07007675
7676 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7677
7678 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7679 switch (clkreg) {
7680 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7681 bp->bus_speed_mhz = 133;
7682 break;
7683
7684 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7685 bp->bus_speed_mhz = 100;
7686 break;
7687
7688 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7689 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7690 bp->bus_speed_mhz = 66;
7691 break;
7692
7693 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7694 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7695 bp->bus_speed_mhz = 50;
7696 break;
7697
7698 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7699 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7700 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7701 bp->bus_speed_mhz = 33;
7702 break;
7703 }
7704 }
7705 else {
7706 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7707 bp->bus_speed_mhz = 66;
7708 else
7709 bp->bus_speed_mhz = 33;
7710 }
7711
7712 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
David S. Millerf86e82f2008-01-21 17:15:40 -08007713 bp->flags |= BNX2_FLAG_PCI_32BIT;
Michael Chan883e5152007-05-03 13:25:11 -07007714
7715}
7716
Michael Chanb6016b72005-05-26 13:03:09 -07007717static int __devinit
7718bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7719{
7720 struct bnx2 *bp;
7721 unsigned long mem_len;
Michael Chan58fc2ea2007-07-07 22:52:02 -07007722 int rc, i, j;
Michael Chanb6016b72005-05-26 13:03:09 -07007723 u32 reg;
Michael Chan40453c82007-05-03 13:19:18 -07007724 u64 dma_mask, persist_dma_mask;
Michael Chanb6016b72005-05-26 13:03:09 -07007725
Michael Chanb6016b72005-05-26 13:03:09 -07007726 SET_NETDEV_DEV(dev, &pdev->dev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007727 bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007728
7729 bp->flags = 0;
7730 bp->phy_flags = 0;
7731
7732 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7733 rc = pci_enable_device(pdev);
7734 if (rc) {
Joe Perches898eb712007-10-18 03:06:30 -07007735 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007736 goto err_out;
7737 }
7738
7739 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007740 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007741 "Cannot find PCI device base address, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007742 rc = -ENODEV;
7743 goto err_out_disable;
7744 }
7745
7746 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7747 if (rc) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007748 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007749 goto err_out_disable;
7750 }
7751
7752 pci_set_master(pdev);
Wendy Xiong6ff2da42008-05-16 22:18:21 -07007753 pci_save_state(pdev);
Michael Chanb6016b72005-05-26 13:03:09 -07007754
7755 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7756 if (bp->pm_cap == 0) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007757 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007758 "Cannot find power management capability, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007759 rc = -EIO;
7760 goto err_out_release;
7761 }
7762
Michael Chanb6016b72005-05-26 13:03:09 -07007763 bp->dev = dev;
7764 bp->pdev = pdev;
7765
7766 spin_lock_init(&bp->phy_lock);
Michael Chan1b8227c2007-05-03 13:24:05 -07007767 spin_lock_init(&bp->indirect_lock);
Michael Chanc5a88952009-08-14 15:49:45 +00007768#ifdef BCM_CNIC
7769 mutex_init(&bp->cnic_lock);
7770#endif
David Howellsc4028952006-11-22 14:57:56 +00007771 INIT_WORK(&bp->reset_task, bnx2_reset_task);
Michael Chanb6016b72005-05-26 13:03:09 -07007772
7773 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
Michael Chan4edd4732009-06-08 18:14:42 -07007774 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
Michael Chanb6016b72005-05-26 13:03:09 -07007775 dev->mem_end = dev->mem_start + mem_len;
7776 dev->irq = pdev->irq;
7777
7778 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7779
7780 if (!bp->regview) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007781 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007782 rc = -ENOMEM;
7783 goto err_out_release;
7784 }
7785
7786 /* Configure byte swap and enable write to the reg_window registers.
7787 * Rely on CPU to do target byte swapping on big endian systems
7788 * The chip's target access swapping will not swap all accesses
7789 */
7790 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7791 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7792 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7793
Pavel Machek829ca9a2005-09-03 15:56:56 -07007794 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07007795
7796 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7797
Michael Chan883e5152007-05-03 13:25:11 -07007798 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7799 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7800 dev_err(&pdev->dev,
7801 "Cannot find PCIE capability, aborting.\n");
7802 rc = -EIO;
7803 goto err_out_unmap;
7804 }
David S. Millerf86e82f2008-01-21 17:15:40 -08007805 bp->flags |= BNX2_FLAG_PCIE;
Michael Chan2dd201d2008-01-21 17:06:09 -08007806 if (CHIP_REV(bp) == CHIP_REV_Ax)
David S. Millerf86e82f2008-01-21 17:15:40 -08007807 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
Michael Chan883e5152007-05-03 13:25:11 -07007808 } else {
Michael Chan59b47d82006-11-19 14:10:45 -08007809 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7810 if (bp->pcix_cap == 0) {
7811 dev_err(&pdev->dev,
7812 "Cannot find PCIX capability, aborting.\n");
7813 rc = -EIO;
7814 goto err_out_unmap;
7815 }
Michael Chan61d9e3f2009-08-21 16:20:46 +00007816 bp->flags |= BNX2_FLAG_BROKEN_STATS;
Michael Chan59b47d82006-11-19 14:10:45 -08007817 }
7818
Michael Chanb4b36042007-12-20 19:59:30 -08007819 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7820 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
David S. Millerf86e82f2008-01-21 17:15:40 -08007821 bp->flags |= BNX2_FLAG_MSIX_CAP;
Michael Chanb4b36042007-12-20 19:59:30 -08007822 }
7823
Michael Chan8e6a72c2007-05-03 13:24:48 -07007824 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7825 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
David S. Millerf86e82f2008-01-21 17:15:40 -08007826 bp->flags |= BNX2_FLAG_MSI_CAP;
Michael Chan8e6a72c2007-05-03 13:24:48 -07007827 }
7828
Michael Chan40453c82007-05-03 13:19:18 -07007829 /* 5708 cannot support DMA addresses > 40-bit. */
7830 if (CHIP_NUM(bp) == CHIP_NUM_5708)
Yang Hongyang50cf1562009-04-06 19:01:14 -07007831 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
Michael Chan40453c82007-05-03 13:19:18 -07007832 else
Yang Hongyang6a355282009-04-06 19:01:13 -07007833 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
Michael Chan40453c82007-05-03 13:19:18 -07007834
7835 /* Configure DMA attributes. */
7836 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7837 dev->features |= NETIF_F_HIGHDMA;
7838 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7839 if (rc) {
7840 dev_err(&pdev->dev,
7841 "pci_set_consistent_dma_mask failed, aborting.\n");
7842 goto err_out_unmap;
7843 }
Yang Hongyang284901a2009-04-06 19:01:15 -07007844 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
Michael Chan40453c82007-05-03 13:19:18 -07007845 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7846 goto err_out_unmap;
7847 }
7848
David S. Millerf86e82f2008-01-21 17:15:40 -08007849 if (!(bp->flags & BNX2_FLAG_PCIE))
Michael Chan883e5152007-05-03 13:25:11 -07007850 bnx2_get_pci_speed(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007851
7852 /* 5706A0 may falsely detect SERR and PERR. */
7853 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7854 reg = REG_RD(bp, PCI_COMMAND);
7855 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7856 REG_WR(bp, PCI_COMMAND, reg);
7857 }
7858 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
David S. Millerf86e82f2008-01-21 17:15:40 -08007859 !(bp->flags & BNX2_FLAG_PCIX)) {
Michael Chanb6016b72005-05-26 13:03:09 -07007860
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007861 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007862 "5706 A1 can only be used in a PCIX bus, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007863 goto err_out_unmap;
7864 }
7865
7866 bnx2_init_nvram(bp);
7867
Michael Chan2726d6e2008-01-29 21:35:05 -08007868 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
Michael Chane3648b32005-11-04 08:51:21 -08007869
7870 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
Michael Chan24cb2302007-01-25 15:49:56 -08007871 BNX2_SHM_HDR_SIGNATURE_SIG) {
7872 u32 off = PCI_FUNC(pdev->devfn) << 2;
7873
Michael Chan2726d6e2008-01-29 21:35:05 -08007874 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
Michael Chan24cb2302007-01-25 15:49:56 -08007875 } else
Michael Chane3648b32005-11-04 08:51:21 -08007876 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7877
Michael Chanb6016b72005-05-26 13:03:09 -07007878 /* Get the permanent MAC address. First we need to make sure the
7879 * firmware is actually running.
7880 */
Michael Chan2726d6e2008-01-29 21:35:05 -08007881 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
Michael Chanb6016b72005-05-26 13:03:09 -07007882
7883 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7884 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007885 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007886 rc = -ENODEV;
7887 goto err_out_unmap;
7888 }
7889
Michael Chan2726d6e2008-01-29 21:35:05 -08007890 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007891 for (i = 0, j = 0; i < 3; i++) {
7892 u8 num, k, skip0;
7893
7894 num = (u8) (reg >> (24 - (i * 8)));
7895 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7896 if (num >= k || !skip0 || k == 1) {
7897 bp->fw_version[j++] = (num / k) + '0';
7898 skip0 = 0;
7899 }
7900 }
7901 if (i != 2)
7902 bp->fw_version[j++] = '.';
7903 }
Michael Chan2726d6e2008-01-29 21:35:05 -08007904 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
Michael Chan846f5c62007-10-10 16:16:51 -07007905 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7906 bp->wol = 1;
7907
7908 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007909 bp->flags |= BNX2_FLAG_ASF_ENABLE;
Michael Chanc2d3db82007-07-16 18:26:43 -07007910
7911 for (i = 0; i < 30; i++) {
Michael Chan2726d6e2008-01-29 21:35:05 -08007912 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
Michael Chanc2d3db82007-07-16 18:26:43 -07007913 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7914 break;
7915 msleep(10);
7916 }
7917 }
Michael Chan2726d6e2008-01-29 21:35:05 -08007918 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007919 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7920 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7921 reg != BNX2_CONDITION_MFW_RUN_NONE) {
Michael Chan2726d6e2008-01-29 21:35:05 -08007922 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007923
7924 bp->fw_version[j++] = ' ';
7925 for (i = 0; i < 3; i++) {
Michael Chan2726d6e2008-01-29 21:35:05 -08007926 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007927 reg = swab32(reg);
7928 memcpy(&bp->fw_version[j], &reg, 4);
7929 j += 4;
7930 }
7931 }
Michael Chanb6016b72005-05-26 13:03:09 -07007932
Michael Chan2726d6e2008-01-29 21:35:05 -08007933 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
Michael Chanb6016b72005-05-26 13:03:09 -07007934 bp->mac_addr[0] = (u8) (reg >> 8);
7935 bp->mac_addr[1] = (u8) reg;
7936
Michael Chan2726d6e2008-01-29 21:35:05 -08007937 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
Michael Chanb6016b72005-05-26 13:03:09 -07007938 bp->mac_addr[2] = (u8) (reg >> 24);
7939 bp->mac_addr[3] = (u8) (reg >> 16);
7940 bp->mac_addr[4] = (u8) (reg >> 8);
7941 bp->mac_addr[5] = (u8) reg;
7942
7943 bp->tx_ring_size = MAX_TX_DESC_CNT;
Michael Chan932f3772006-08-15 01:39:36 -07007944 bnx2_set_rx_ring_size(bp, 255);
Michael Chanb6016b72005-05-26 13:03:09 -07007945
7946 bp->rx_csum = 1;
7947
Michael Chancf7474a2009-08-21 16:20:48 +00007948 bp->tx_quick_cons_trip_int = 2;
Michael Chanb6016b72005-05-26 13:03:09 -07007949 bp->tx_quick_cons_trip = 20;
Michael Chancf7474a2009-08-21 16:20:48 +00007950 bp->tx_ticks_int = 18;
Michael Chanb6016b72005-05-26 13:03:09 -07007951 bp->tx_ticks = 80;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007952
Michael Chancf7474a2009-08-21 16:20:48 +00007953 bp->rx_quick_cons_trip_int = 2;
7954 bp->rx_quick_cons_trip = 12;
Michael Chanb6016b72005-05-26 13:03:09 -07007955 bp->rx_ticks_int = 18;
7956 bp->rx_ticks = 18;
7957
Michael Chan7ea69202007-07-16 18:27:10 -07007958 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
Michael Chanb6016b72005-05-26 13:03:09 -07007959
Benjamin Liac392ab2008-09-18 16:40:49 -07007960 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanb6016b72005-05-26 13:03:09 -07007961
Michael Chan5b0c76a2005-11-04 08:45:49 -08007962 bp->phy_addr = 1;
7963
Michael Chanb6016b72005-05-26 13:03:09 -07007964 /* Disable WOL support if we are running on a SERDES chip. */
Michael Chan253c8b72007-01-08 19:56:01 -08007965 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7966 bnx2_get_5709_media(bp);
7967 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
Michael Chan583c28e2008-01-21 19:51:35 -08007968 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chanbac0dff2006-11-19 14:15:05 -08007969
Michael Chan0d8a6572007-07-07 22:49:43 -07007970 bp->phy_port = PORT_TP;
Michael Chan583c28e2008-01-21 19:51:35 -08007971 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan0d8a6572007-07-07 22:49:43 -07007972 bp->phy_port = PORT_FIBRE;
Michael Chan2726d6e2008-01-29 21:35:05 -08007973 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
Michael Chan846f5c62007-10-10 16:16:51 -07007974 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007975 bp->flags |= BNX2_FLAG_NO_WOL;
Michael Chan846f5c62007-10-10 16:16:51 -07007976 bp->wol = 0;
7977 }
Michael Chan38ea3682008-02-23 19:48:57 -08007978 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7979 /* Don't do parallel detect on this board because of
7980 * some board problems. The link will not go down
7981 * if we do parallel detect.
7982 */
7983 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7984 pdev->subsystem_device == 0x310c)
7985 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7986 } else {
Michael Chan5b0c76a2005-11-04 08:45:49 -08007987 bp->phy_addr = 2;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007988 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
Michael Chan583c28e2008-01-21 19:51:35 -08007989 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007990 }
Michael Chan261dd5c2007-01-08 19:55:46 -08007991 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7992 CHIP_NUM(bp) == CHIP_NUM_5708)
Michael Chan583c28e2008-01-21 19:51:35 -08007993 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
Michael Chanfb0c18b2007-12-10 17:18:23 -08007994 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7995 (CHIP_REV(bp) == CHIP_REV_Ax ||
7996 CHIP_REV(bp) == CHIP_REV_Bx))
Michael Chan583c28e2008-01-21 19:51:35 -08007997 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
Michael Chanb6016b72005-05-26 13:03:09 -07007998
Michael Chan7c62e832008-07-14 22:39:03 -07007999 bnx2_init_fw_cap(bp);
8000
Michael Chan16088272006-06-12 22:16:43 -07008001 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8002 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
Michael Chan5ec6d7b2008-11-12 16:01:41 -08008003 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8004 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
David S. Millerf86e82f2008-01-21 17:15:40 -08008005 bp->flags |= BNX2_FLAG_NO_WOL;
Michael Chan846f5c62007-10-10 16:16:51 -07008006 bp->wol = 0;
8007 }
Michael Chandda1e392006-01-23 16:08:14 -08008008
Michael Chanb6016b72005-05-26 13:03:09 -07008009 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8010 bp->tx_quick_cons_trip_int =
8011 bp->tx_quick_cons_trip;
8012 bp->tx_ticks_int = bp->tx_ticks;
8013 bp->rx_quick_cons_trip_int =
8014 bp->rx_quick_cons_trip;
8015 bp->rx_ticks_int = bp->rx_ticks;
8016 bp->comp_prod_trip_int = bp->comp_prod_trip;
8017 bp->com_ticks_int = bp->com_ticks;
8018 bp->cmd_ticks_int = bp->cmd_ticks;
8019 }
8020
Michael Chanf9317a42006-09-29 17:06:23 -07008021 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8022 *
8023 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8024 * with byte enables disabled on the unused 32-bit word. This is legal
8025 * but causes problems on the AMD 8132 which will eventually stop
8026 * responding after a while.
8027 *
8028 * AMD believes this incompatibility is unique to the 5706, and
Michael Ellerman88187df2007-01-25 19:34:07 +11008029 * prefers to locally disable MSI rather than globally disabling it.
Michael Chanf9317a42006-09-29 17:06:23 -07008030 */
8031 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8032 struct pci_dev *amd_8132 = NULL;
8033
8034 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8035 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8036 amd_8132))) {
Michael Chanf9317a42006-09-29 17:06:23 -07008037
Auke Kok44c10132007-06-08 15:46:36 -07008038 if (amd_8132->revision >= 0x10 &&
8039 amd_8132->revision <= 0x13) {
Michael Chanf9317a42006-09-29 17:06:23 -07008040 disable_msi = 1;
8041 pci_dev_put(amd_8132);
8042 break;
8043 }
8044 }
8045 }
8046
Michael Chandeaf3912007-07-07 22:48:00 -07008047 bnx2_set_default_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07008048 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8049
Michael Chancd339a02005-08-25 15:35:24 -07008050 init_timer(&bp->timer);
Benjamin Liac392ab2008-09-18 16:40:49 -07008051 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
Michael Chancd339a02005-08-25 15:35:24 -07008052 bp->timer.data = (unsigned long) bp;
8053 bp->timer.function = bnx2_timer;
8054
Michael Chanb6016b72005-05-26 13:03:09 -07008055 return 0;
8056
8057err_out_unmap:
8058 if (bp->regview) {
8059 iounmap(bp->regview);
Michael Chan73eef4c2005-08-25 15:39:15 -07008060 bp->regview = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07008061 }
8062
8063err_out_release:
8064 pci_release_regions(pdev);
8065
8066err_out_disable:
8067 pci_disable_device(pdev);
8068 pci_set_drvdata(pdev, NULL);
8069
8070err_out:
8071 return rc;
8072}
8073
Michael Chan883e5152007-05-03 13:25:11 -07008074static char * __devinit
8075bnx2_bus_string(struct bnx2 *bp, char *str)
8076{
8077 char *s = str;
8078
David S. Millerf86e82f2008-01-21 17:15:40 -08008079 if (bp->flags & BNX2_FLAG_PCIE) {
Michael Chan883e5152007-05-03 13:25:11 -07008080 s += sprintf(s, "PCI Express");
8081 } else {
8082 s += sprintf(s, "PCI");
David S. Millerf86e82f2008-01-21 17:15:40 -08008083 if (bp->flags & BNX2_FLAG_PCIX)
Michael Chan883e5152007-05-03 13:25:11 -07008084 s += sprintf(s, "-X");
David S. Millerf86e82f2008-01-21 17:15:40 -08008085 if (bp->flags & BNX2_FLAG_PCI_32BIT)
Michael Chan883e5152007-05-03 13:25:11 -07008086 s += sprintf(s, " 32-bit");
8087 else
8088 s += sprintf(s, " 64-bit");
8089 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8090 }
8091 return str;
8092}
8093
Michael Chan2ba582b2007-12-21 15:04:49 -08008094static void __devinit
Michael Chan35efa7c2007-12-20 19:56:37 -08008095bnx2_init_napi(struct bnx2 *bp)
8096{
Michael Chanb4b36042007-12-20 19:59:30 -08008097 int i;
Michael Chan35efa7c2007-12-20 19:56:37 -08008098
Michael Chanb4b36042007-12-20 19:59:30 -08008099 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
Michael Chan35e90102008-06-19 16:37:42 -07008100 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8101 int (*poll)(struct napi_struct *, int);
8102
8103 if (i == 0)
8104 poll = bnx2_poll;
8105 else
Michael Chanf0ea2e62008-06-19 16:41:57 -07008106 poll = bnx2_poll_msix;
Michael Chan35e90102008-06-19 16:37:42 -07008107
8108 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
Michael Chanb4b36042007-12-20 19:59:30 -08008109 bnapi->bp = bp;
8110 }
Michael Chan35efa7c2007-12-20 19:56:37 -08008111}
8112
Stephen Hemminger0421eae2008-11-21 17:31:27 -08008113static const struct net_device_ops bnx2_netdev_ops = {
8114 .ndo_open = bnx2_open,
8115 .ndo_start_xmit = bnx2_start_xmit,
8116 .ndo_stop = bnx2_close,
8117 .ndo_get_stats = bnx2_get_stats,
8118 .ndo_set_rx_mode = bnx2_set_rx_mode,
8119 .ndo_do_ioctl = bnx2_ioctl,
8120 .ndo_validate_addr = eth_validate_addr,
8121 .ndo_set_mac_address = bnx2_change_mac_addr,
8122 .ndo_change_mtu = bnx2_change_mtu,
8123 .ndo_tx_timeout = bnx2_tx_timeout,
8124#ifdef BCM_VLAN
8125 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
8126#endif
8127#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
8128 .ndo_poll_controller = poll_bnx2,
8129#endif
8130};
8131
Eric Dumazet72dccb02009-07-23 02:01:38 +00008132static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8133{
8134#ifdef BCM_VLAN
8135 dev->vlan_features |= flags;
8136#endif
8137}
8138
Michael Chan35efa7c2007-12-20 19:56:37 -08008139static int __devinit
Michael Chanb6016b72005-05-26 13:03:09 -07008140bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8141{
8142 static int version_printed = 0;
8143 struct net_device *dev = NULL;
8144 struct bnx2 *bp;
Joe Perches0795af52007-10-03 17:59:30 -07008145 int rc;
Michael Chan883e5152007-05-03 13:25:11 -07008146 char str[40];
Michael Chanb6016b72005-05-26 13:03:09 -07008147
8148 if (version_printed++ == 0)
8149 printk(KERN_INFO "%s", version);
8150
8151 /* dev zeroed in init_etherdev */
Benjamin Li706bf242008-07-18 17:55:11 -07008152 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
Michael Chanb6016b72005-05-26 13:03:09 -07008153
8154 if (!dev)
8155 return -ENOMEM;
8156
8157 rc = bnx2_init_board(pdev, dev);
8158 if (rc < 0) {
8159 free_netdev(dev);
8160 return rc;
8161 }
8162
Stephen Hemminger0421eae2008-11-21 17:31:27 -08008163 dev->netdev_ops = &bnx2_netdev_ops;
Michael Chanb6016b72005-05-26 13:03:09 -07008164 dev->watchdog_timeo = TX_TIMEOUT;
Michael Chanb6016b72005-05-26 13:03:09 -07008165 dev->ethtool_ops = &bnx2_ethtool_ops;
Michael Chanb6016b72005-05-26 13:03:09 -07008166
Michael Chan972ec0d2006-01-23 16:12:43 -08008167 bp = netdev_priv(dev);
Michael Chan35efa7c2007-12-20 19:56:37 -08008168 bnx2_init_napi(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07008169
Michael Chan1b2f9222007-05-03 13:20:19 -07008170 pci_set_drvdata(pdev, dev);
8171
Michael Chan57579f72009-04-04 16:51:14 -07008172 rc = bnx2_request_firmware(bp);
8173 if (rc)
8174 goto error;
8175
Michael Chan1b2f9222007-05-03 13:20:19 -07008176 memcpy(dev->dev_addr, bp->mac_addr, 6);
8177 memcpy(dev->perm_addr, bp->mac_addr, 6);
Michael Chan1b2f9222007-05-03 13:20:19 -07008178
Stephen Hemmingerd212f872007-06-27 00:47:37 -07008179 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Eric Dumazet72dccb02009-07-23 02:01:38 +00008180 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8181 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
Stephen Hemmingerd212f872007-06-27 00:47:37 -07008182 dev->features |= NETIF_F_IPV6_CSUM;
Eric Dumazet72dccb02009-07-23 02:01:38 +00008183 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8184 }
Michael Chan1b2f9222007-05-03 13:20:19 -07008185#ifdef BCM_VLAN
8186 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8187#endif
8188 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
Eric Dumazet72dccb02009-07-23 02:01:38 +00008189 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8190 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
Michael Chan4666f872007-05-03 13:22:28 -07008191 dev->features |= NETIF_F_TSO6;
Eric Dumazet72dccb02009-07-23 02:01:38 +00008192 vlan_features_add(dev, NETIF_F_TSO6);
8193 }
Michael Chanb6016b72005-05-26 13:03:09 -07008194 if ((rc = register_netdev(dev))) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04008195 dev_err(&pdev->dev, "Cannot register net device\n");
Michael Chan57579f72009-04-04 16:51:14 -07008196 goto error;
Michael Chanb6016b72005-05-26 13:03:09 -07008197 }
8198
Michael Chan883e5152007-05-03 13:25:11 -07008199 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
Johannes Berge1749612008-10-27 15:59:26 -07008200 "IRQ %d, node addr %pM\n",
Michael Chanb6016b72005-05-26 13:03:09 -07008201 dev->name,
Benjamin Lifbbf68b2008-09-18 16:40:03 -07008202 board_info[ent->driver_data].name,
Michael Chanb6016b72005-05-26 13:03:09 -07008203 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8204 ((CHIP_ID(bp) & 0x0ff0) >> 4),
Michael Chan883e5152007-05-03 13:25:11 -07008205 bnx2_bus_string(bp, str),
Michael Chanb6016b72005-05-26 13:03:09 -07008206 dev->base_addr,
Johannes Berge1749612008-10-27 15:59:26 -07008207 bp->pdev->irq, dev->dev_addr);
Michael Chanb6016b72005-05-26 13:03:09 -07008208
Michael Chanb6016b72005-05-26 13:03:09 -07008209 return 0;
Michael Chan57579f72009-04-04 16:51:14 -07008210
8211error:
8212 if (bp->mips_firmware)
8213 release_firmware(bp->mips_firmware);
8214 if (bp->rv2p_firmware)
8215 release_firmware(bp->rv2p_firmware);
8216
8217 if (bp->regview)
8218 iounmap(bp->regview);
8219 pci_release_regions(pdev);
8220 pci_disable_device(pdev);
8221 pci_set_drvdata(pdev, NULL);
8222 free_netdev(dev);
8223 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07008224}
8225
8226static void __devexit
8227bnx2_remove_one(struct pci_dev *pdev)
8228{
8229 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08008230 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07008231
Michael Chanafdc08b2005-08-25 15:34:29 -07008232 flush_scheduled_work();
8233
Michael Chanb6016b72005-05-26 13:03:09 -07008234 unregister_netdev(dev);
8235
Michael Chan57579f72009-04-04 16:51:14 -07008236 if (bp->mips_firmware)
8237 release_firmware(bp->mips_firmware);
8238 if (bp->rv2p_firmware)
8239 release_firmware(bp->rv2p_firmware);
8240
Michael Chanb6016b72005-05-26 13:03:09 -07008241 if (bp->regview)
8242 iounmap(bp->regview);
8243
8244 free_netdev(dev);
8245 pci_release_regions(pdev);
8246 pci_disable_device(pdev);
8247 pci_set_drvdata(pdev, NULL);
8248}
8249
8250static int
Pavel Machek829ca9a2005-09-03 15:56:56 -07008251bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
Michael Chanb6016b72005-05-26 13:03:09 -07008252{
8253 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08008254 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07008255
Michael Chan6caebb02007-08-03 20:57:25 -07008256 /* PCI register 4 needs to be saved whether netif_running() or not.
8257 * MSI address and data need to be saved if using MSI and
8258 * netif_running().
8259 */
8260 pci_save_state(pdev);
Michael Chanb6016b72005-05-26 13:03:09 -07008261 if (!netif_running(dev))
8262 return 0;
8263
Michael Chan1d60290f2006-03-20 17:50:08 -08008264 flush_scheduled_work();
Michael Chanb6016b72005-05-26 13:03:09 -07008265 bnx2_netif_stop(bp);
8266 netif_device_detach(dev);
8267 del_timer_sync(&bp->timer);
Michael Chan74bf4ba2008-10-09 12:21:08 -07008268 bnx2_shutdown_chip(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07008269 bnx2_free_skbs(bp);
Pavel Machek829ca9a2005-09-03 15:56:56 -07008270 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
Michael Chanb6016b72005-05-26 13:03:09 -07008271 return 0;
8272}
8273
8274static int
8275bnx2_resume(struct pci_dev *pdev)
8276{
8277 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08008278 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07008279
Michael Chan6caebb02007-08-03 20:57:25 -07008280 pci_restore_state(pdev);
Michael Chanb6016b72005-05-26 13:03:09 -07008281 if (!netif_running(dev))
8282 return 0;
8283
Pavel Machek829ca9a2005-09-03 15:56:56 -07008284 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07008285 netif_device_attach(dev);
Michael Chan9a120bc2008-05-16 22:17:45 -07008286 bnx2_init_nic(bp, 1);
Michael Chanb6016b72005-05-26 13:03:09 -07008287 bnx2_netif_start(bp);
8288 return 0;
8289}
8290
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008291/**
8292 * bnx2_io_error_detected - called when PCI error is detected
8293 * @pdev: Pointer to PCI device
8294 * @state: The current pci connection state
8295 *
8296 * This function is called after a PCI bus error affecting
8297 * this device has been detected.
8298 */
8299static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8300 pci_channel_state_t state)
8301{
8302 struct net_device *dev = pci_get_drvdata(pdev);
8303 struct bnx2 *bp = netdev_priv(dev);
8304
8305 rtnl_lock();
8306 netif_device_detach(dev);
8307
Dean Nelson2ec3de22009-07-31 09:13:18 +00008308 if (state == pci_channel_io_perm_failure) {
8309 rtnl_unlock();
8310 return PCI_ERS_RESULT_DISCONNECT;
8311 }
8312
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008313 if (netif_running(dev)) {
8314 bnx2_netif_stop(bp);
8315 del_timer_sync(&bp->timer);
8316 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8317 }
8318
8319 pci_disable_device(pdev);
8320 rtnl_unlock();
8321
8322 /* Request a slot slot reset. */
8323 return PCI_ERS_RESULT_NEED_RESET;
8324}
8325
8326/**
8327 * bnx2_io_slot_reset - called after the pci bus has been reset.
8328 * @pdev: Pointer to PCI device
8329 *
8330 * Restart the card from scratch, as if from a cold-boot.
8331 */
8332static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8333{
8334 struct net_device *dev = pci_get_drvdata(pdev);
8335 struct bnx2 *bp = netdev_priv(dev);
8336
8337 rtnl_lock();
8338 if (pci_enable_device(pdev)) {
8339 dev_err(&pdev->dev,
8340 "Cannot re-enable PCI device after reset.\n");
8341 rtnl_unlock();
8342 return PCI_ERS_RESULT_DISCONNECT;
8343 }
8344 pci_set_master(pdev);
8345 pci_restore_state(pdev);
Breno Leitao529fab62009-11-26 07:31:49 +00008346 pci_save_state(pdev);
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008347
8348 if (netif_running(dev)) {
8349 bnx2_set_power_state(bp, PCI_D0);
8350 bnx2_init_nic(bp, 1);
8351 }
8352
8353 rtnl_unlock();
8354 return PCI_ERS_RESULT_RECOVERED;
8355}
8356
8357/**
8358 * bnx2_io_resume - called when traffic can start flowing again.
8359 * @pdev: Pointer to PCI device
8360 *
8361 * This callback is called when the error recovery driver tells us that
8362 * its OK to resume normal operation.
8363 */
8364static void bnx2_io_resume(struct pci_dev *pdev)
8365{
8366 struct net_device *dev = pci_get_drvdata(pdev);
8367 struct bnx2 *bp = netdev_priv(dev);
8368
8369 rtnl_lock();
8370 if (netif_running(dev))
8371 bnx2_netif_start(bp);
8372
8373 netif_device_attach(dev);
8374 rtnl_unlock();
8375}
8376
8377static struct pci_error_handlers bnx2_err_handler = {
8378 .error_detected = bnx2_io_error_detected,
8379 .slot_reset = bnx2_io_slot_reset,
8380 .resume = bnx2_io_resume,
8381};
8382
Michael Chanb6016b72005-05-26 13:03:09 -07008383static struct pci_driver bnx2_pci_driver = {
Peter Hagervall14ab9b82005-08-10 14:18:16 -07008384 .name = DRV_MODULE_NAME,
8385 .id_table = bnx2_pci_tbl,
8386 .probe = bnx2_init_one,
8387 .remove = __devexit_p(bnx2_remove_one),
8388 .suspend = bnx2_suspend,
8389 .resume = bnx2_resume,
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008390 .err_handler = &bnx2_err_handler,
Michael Chanb6016b72005-05-26 13:03:09 -07008391};
8392
8393static int __init bnx2_init(void)
8394{
Jeff Garzik29917622006-08-19 17:48:59 -04008395 return pci_register_driver(&bnx2_pci_driver);
Michael Chanb6016b72005-05-26 13:03:09 -07008396}
8397
8398static void __exit bnx2_cleanup(void)
8399{
8400 pci_unregister_driver(&bnx2_pci_driver);
8401}
8402
8403module_init(bnx2_init);
8404module_exit(bnx2_cleanup);
8405
8406
8407