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Mika Westerberg011f23a2010-05-06 04:47:04 +00001/*
2 * Driver for Cirrus Logic EP93xx SPI controller.
3 *
Mika Westerberg626a96d2011-05-29 13:10:06 +03004 * Copyright (C) 2010-2011 Mika Westerberg
Mika Westerberg011f23a2010-05-06 04:47:04 +00005 *
6 * Explicit FIFO handling code was inspired by amba-pl022 driver.
7 *
8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
9 *
10 * For more information about the SPI controller see documentation on Cirrus
11 * Logic web site:
12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/io.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/delay.h>
23#include <linux/device.h>
Mika Westerberg626a96d2011-05-29 13:10:06 +030024#include <linux/dmaengine.h>
Mika Westerberg011f23a2010-05-06 04:47:04 +000025#include <linux/bitops.h>
26#include <linux/interrupt.h>
Mika Westerberg5bdb76132011-10-15 21:40:09 +030027#include <linux/module.h>
Mika Westerberg011f23a2010-05-06 04:47:04 +000028#include <linux/platform_device.h>
Mika Westerberg011f23a2010-05-06 04:47:04 +000029#include <linux/sched.h>
Mika Westerberg626a96d2011-05-29 13:10:06 +030030#include <linux/scatterlist.h>
Mika Westerberg011f23a2010-05-06 04:47:04 +000031#include <linux/spi/spi.h>
32
Arnd Bergmanna3b29242012-08-24 15:12:11 +020033#include <linux/platform_data/dma-ep93xx.h>
34#include <linux/platform_data/spi-ep93xx.h>
Mika Westerberg011f23a2010-05-06 04:47:04 +000035
36#define SSPCR0 0x0000
37#define SSPCR0_MODE_SHIFT 6
38#define SSPCR0_SCR_SHIFT 8
39
40#define SSPCR1 0x0004
41#define SSPCR1_RIE BIT(0)
42#define SSPCR1_TIE BIT(1)
43#define SSPCR1_RORIE BIT(2)
44#define SSPCR1_LBM BIT(3)
45#define SSPCR1_SSE BIT(4)
46#define SSPCR1_MS BIT(5)
47#define SSPCR1_SOD BIT(6)
48
49#define SSPDR 0x0008
50
51#define SSPSR 0x000c
52#define SSPSR_TFE BIT(0)
53#define SSPSR_TNF BIT(1)
54#define SSPSR_RNE BIT(2)
55#define SSPSR_RFF BIT(3)
56#define SSPSR_BSY BIT(4)
57#define SSPCPSR 0x0010
58
59#define SSPIIR 0x0014
60#define SSPIIR_RIS BIT(0)
61#define SSPIIR_TIS BIT(1)
62#define SSPIIR_RORIS BIT(2)
63#define SSPICR SSPIIR
64
65/* timeout in milliseconds */
66#define SPI_TIMEOUT 5
67/* maximum depth of RX/TX FIFO */
68#define SPI_FIFO_SIZE 8
69
70/**
71 * struct ep93xx_spi - EP93xx SPI controller structure
Mika Westerberg011f23a2010-05-06 04:47:04 +000072 * @pdev: pointer to platform device
73 * @clk: clock for the controller
74 * @regs_base: pointer to ioremap()'d registers
Mika Westerberg626a96d2011-05-29 13:10:06 +030075 * @sspdr_phys: physical address of the SSPDR register
Mika Westerberg011f23a2010-05-06 04:47:04 +000076 * @wait: wait here until given transfer is completed
Mika Westerberg011f23a2010-05-06 04:47:04 +000077 * @current_msg: message that is currently processed (or %NULL if none)
78 * @tx: current byte in transfer to transmit
79 * @rx: current byte in transfer to receive
80 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
81 * frame decreases this level and sending one frame increases it.
Mika Westerberg626a96d2011-05-29 13:10:06 +030082 * @dma_rx: RX DMA channel
83 * @dma_tx: TX DMA channel
84 * @dma_rx_data: RX parameters passed to the DMA engine
85 * @dma_tx_data: TX parameters passed to the DMA engine
86 * @rx_sgt: sg table for RX transfers
87 * @tx_sgt: sg table for TX transfers
88 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
89 * the client
Mika Westerberg011f23a2010-05-06 04:47:04 +000090 */
91struct ep93xx_spi {
Mika Westerberg011f23a2010-05-06 04:47:04 +000092 const struct platform_device *pdev;
93 struct clk *clk;
94 void __iomem *regs_base;
Mika Westerberg626a96d2011-05-29 13:10:06 +030095 unsigned long sspdr_phys;
Mika Westerberg011f23a2010-05-06 04:47:04 +000096 struct completion wait;
Mika Westerberg011f23a2010-05-06 04:47:04 +000097 struct spi_message *current_msg;
98 size_t tx;
99 size_t rx;
100 size_t fifo_level;
Mika Westerberg626a96d2011-05-29 13:10:06 +0300101 struct dma_chan *dma_rx;
102 struct dma_chan *dma_tx;
103 struct ep93xx_dma_data dma_rx_data;
104 struct ep93xx_dma_data dma_tx_data;
105 struct sg_table rx_sgt;
106 struct sg_table tx_sgt;
107 void *zeropage;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000108};
109
110/**
111 * struct ep93xx_spi_chip - SPI device hardware settings
112 * @spi: back pointer to the SPI device
Mika Westerberg011f23a2010-05-06 04:47:04 +0000113 * @ops: private chip operations
Mika Westerberg011f23a2010-05-06 04:47:04 +0000114 */
115struct ep93xx_spi_chip {
116 const struct spi_device *spi;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000117 struct ep93xx_spi_chip_ops *ops;
118};
119
120/* converts bits per word to CR0.DSS value */
121#define bits_per_word_to_dss(bpw) ((bpw) - 1)
122
H Hartley Sweeten8d7586b2013-07-02 10:06:26 -0700123static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi,
124 u16 reg, u8 value)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000125{
H Hartley Sweeten8d7586b2013-07-02 10:06:26 -0700126 writeb(value, espi->regs_base + reg);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000127}
128
H Hartley Sweeten8d7586b2013-07-02 10:06:26 -0700129static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000130{
H Hartley Sweeten8d7586b2013-07-02 10:06:26 -0700131 return readb(spi->regs_base + reg);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000132}
133
H Hartley Sweeten8d7586b2013-07-02 10:06:26 -0700134static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi,
135 u16 reg, u16 value)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000136{
H Hartley Sweeten8d7586b2013-07-02 10:06:26 -0700137 writew(value, espi->regs_base + reg);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000138}
139
H Hartley Sweeten8d7586b2013-07-02 10:06:26 -0700140static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000141{
H Hartley Sweeten8d7586b2013-07-02 10:06:26 -0700142 return readw(spi->regs_base + reg);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000143}
144
145static int ep93xx_spi_enable(const struct ep93xx_spi *espi)
146{
147 u8 regval;
148 int err;
149
150 err = clk_enable(espi->clk);
151 if (err)
152 return err;
153
154 regval = ep93xx_spi_read_u8(espi, SSPCR1);
155 regval |= SSPCR1_SSE;
156 ep93xx_spi_write_u8(espi, SSPCR1, regval);
157
158 return 0;
159}
160
161static void ep93xx_spi_disable(const struct ep93xx_spi *espi)
162{
163 u8 regval;
164
165 regval = ep93xx_spi_read_u8(espi, SSPCR1);
166 regval &= ~SSPCR1_SSE;
167 ep93xx_spi_write_u8(espi, SSPCR1, regval);
168
169 clk_disable(espi->clk);
170}
171
172static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
173{
174 u8 regval;
175
176 regval = ep93xx_spi_read_u8(espi, SSPCR1);
177 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
178 ep93xx_spi_write_u8(espi, SSPCR1, regval);
179}
180
181static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
182{
183 u8 regval;
184
185 regval = ep93xx_spi_read_u8(espi, SSPCR1);
186 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
187 ep93xx_spi_write_u8(espi, SSPCR1, regval);
188}
189
190/**
191 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
192 * @espi: ep93xx SPI controller struct
Mika Westerberg011f23a2010-05-06 04:47:04 +0000193 * @rate: desired SPI output clock rate
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700194 * @div_cpsr: pointer to return the cpsr (pre-scaler) divider
195 * @div_scr: pointer to return the scr divider
Mika Westerberg011f23a2010-05-06 04:47:04 +0000196 */
197static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
Axel Lin56fc0b42014-02-08 23:52:26 +0800198 u32 rate, u8 *div_cpsr, u8 *div_scr)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000199{
Axel Lin56fc0b42014-02-08 23:52:26 +0800200 struct spi_master *master = platform_get_drvdata(espi->pdev);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000201 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
202 int cpsr, scr;
203
204 /*
205 * Make sure that max value is between values supported by the
206 * controller. Note that minimum value is already checked in
H Hartley Sweeten84ddb3c2013-07-08 09:12:37 -0700207 * ep93xx_spi_transfer_one_message().
Mika Westerberg011f23a2010-05-06 04:47:04 +0000208 */
Axel Lin56fc0b42014-02-08 23:52:26 +0800209 rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000210
211 /*
212 * Calculate divisors so that we can get speed according the
213 * following formula:
214 * rate = spi_clock_rate / (cpsr * (1 + scr))
215 *
216 * cpsr must be even number and starts from 2, scr can be any number
217 * between 0 and 255.
218 */
219 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
220 for (scr = 0; scr <= 255; scr++) {
221 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700222 *div_scr = (u8)scr;
223 *div_cpsr = (u8)cpsr;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000224 return 0;
225 }
226 }
227 }
228
229 return -EINVAL;
230}
231
232static void ep93xx_spi_cs_control(struct spi_device *spi, bool control)
233{
234 struct ep93xx_spi_chip *chip = spi_get_ctldata(spi);
235 int value = (spi->mode & SPI_CS_HIGH) ? control : !control;
236
237 if (chip->ops && chip->ops->cs_control)
238 chip->ops->cs_control(spi, value);
239}
240
241/**
242 * ep93xx_spi_setup() - setup an SPI device
243 * @spi: SPI device to setup
244 *
245 * This function sets up SPI device mode, speed etc. Can be called multiple
246 * times for a single device. Returns %0 in case of success, negative error in
247 * case of failure. When this function returns success, the device is
248 * deselected.
249 */
250static int ep93xx_spi_setup(struct spi_device *spi)
251{
252 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
253 struct ep93xx_spi_chip *chip;
254
Mika Westerberg011f23a2010-05-06 04:47:04 +0000255 chip = spi_get_ctldata(spi);
256 if (!chip) {
257 dev_dbg(&espi->pdev->dev, "initial setup for %s\n",
258 spi->modalias);
259
260 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
261 if (!chip)
262 return -ENOMEM;
263
264 chip->spi = spi;
265 chip->ops = spi->controller_data;
266
267 if (chip->ops && chip->ops->setup) {
268 int ret = chip->ops->setup(spi);
Jingoo Han175a3ed2014-09-02 11:50:13 +0900269
Mika Westerberg011f23a2010-05-06 04:47:04 +0000270 if (ret) {
271 kfree(chip);
272 return ret;
273 }
274 }
275
276 spi_set_ctldata(spi, chip);
277 }
278
Mika Westerberg011f23a2010-05-06 04:47:04 +0000279 ep93xx_spi_cs_control(spi, false);
280 return 0;
281}
282
283/**
Mika Westerberg011f23a2010-05-06 04:47:04 +0000284 * ep93xx_spi_cleanup() - cleans up master controller specific state
285 * @spi: SPI device to cleanup
286 *
287 * This function releases master controller specific state for given @spi
288 * device.
289 */
290static void ep93xx_spi_cleanup(struct spi_device *spi)
291{
292 struct ep93xx_spi_chip *chip;
293
294 chip = spi_get_ctldata(spi);
295 if (chip) {
296 if (chip->ops && chip->ops->cleanup)
297 chip->ops->cleanup(spi);
298 spi_set_ctldata(spi, NULL);
299 kfree(chip);
300 }
301}
302
303/**
304 * ep93xx_spi_chip_setup() - configures hardware according to given @chip
305 * @espi: ep93xx SPI controller struct
306 * @chip: chip specific settings
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700307 * @speed_hz: transfer speed
H Hartley Sweetend9b65df2013-07-02 10:09:29 -0700308 * @bits_per_word: transfer bits_per_word
Mika Westerberg011f23a2010-05-06 04:47:04 +0000309 */
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700310static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
311 const struct ep93xx_spi_chip *chip,
312 u32 speed_hz, u8 bits_per_word)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000313{
H Hartley Sweetend9b65df2013-07-02 10:09:29 -0700314 u8 dss = bits_per_word_to_dss(bits_per_word);
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700315 u8 div_cpsr = 0;
316 u8 div_scr = 0;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000317 u16 cr0;
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700318 int err;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000319
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700320 err = ep93xx_spi_calc_divisors(espi, speed_hz, &div_cpsr, &div_scr);
321 if (err)
322 return err;
323
324 cr0 = div_scr << SSPCR0_SCR_SHIFT;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000325 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT;
H Hartley Sweetend9b65df2013-07-02 10:09:29 -0700326 cr0 |= dss;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000327
328 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700329 chip->spi->mode, div_cpsr, div_scr, dss);
Jarkko Nikulaa1829d22013-10-11 13:53:59 +0300330 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x\n", cr0);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000331
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700332 ep93xx_spi_write_u8(espi, SSPCPSR, div_cpsr);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000333 ep93xx_spi_write_u16(espi, SSPCR0, cr0);
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700334
335 return 0;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000336}
337
Mika Westerberg011f23a2010-05-06 04:47:04 +0000338static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
339{
H Hartley Sweeten701c3582013-07-02 10:07:01 -0700340 if (t->bits_per_word > 8) {
Mika Westerberg011f23a2010-05-06 04:47:04 +0000341 u16 tx_val = 0;
342
343 if (t->tx_buf)
344 tx_val = ((u16 *)t->tx_buf)[espi->tx];
345 ep93xx_spi_write_u16(espi, SSPDR, tx_val);
346 espi->tx += sizeof(tx_val);
347 } else {
348 u8 tx_val = 0;
349
350 if (t->tx_buf)
351 tx_val = ((u8 *)t->tx_buf)[espi->tx];
352 ep93xx_spi_write_u8(espi, SSPDR, tx_val);
353 espi->tx += sizeof(tx_val);
354 }
355}
356
357static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
358{
H Hartley Sweeten701c3582013-07-02 10:07:01 -0700359 if (t->bits_per_word > 8) {
Mika Westerberg011f23a2010-05-06 04:47:04 +0000360 u16 rx_val;
361
362 rx_val = ep93xx_spi_read_u16(espi, SSPDR);
363 if (t->rx_buf)
364 ((u16 *)t->rx_buf)[espi->rx] = rx_val;
365 espi->rx += sizeof(rx_val);
366 } else {
367 u8 rx_val;
368
369 rx_val = ep93xx_spi_read_u8(espi, SSPDR);
370 if (t->rx_buf)
371 ((u8 *)t->rx_buf)[espi->rx] = rx_val;
372 espi->rx += sizeof(rx_val);
373 }
374}
375
376/**
377 * ep93xx_spi_read_write() - perform next RX/TX transfer
378 * @espi: ep93xx SPI controller struct
379 *
380 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
381 * called several times, the whole transfer will be completed. Returns
382 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
383 *
384 * When this function is finished, RX FIFO should be empty and TX FIFO should be
385 * full.
386 */
387static int ep93xx_spi_read_write(struct ep93xx_spi *espi)
388{
389 struct spi_message *msg = espi->current_msg;
390 struct spi_transfer *t = msg->state;
391
392 /* read as long as RX FIFO has frames in it */
393 while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) {
394 ep93xx_do_read(espi, t);
395 espi->fifo_level--;
396 }
397
398 /* write as long as TX FIFO has room */
399 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) {
400 ep93xx_do_write(espi, t);
401 espi->fifo_level++;
402 }
403
Mika Westerberg626a96d2011-05-29 13:10:06 +0300404 if (espi->rx == t->len)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000405 return 0;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000406
407 return -EINPROGRESS;
408}
409
Mika Westerberg626a96d2011-05-29 13:10:06 +0300410static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
411{
412 /*
413 * Now everything is set up for the current transfer. We prime the TX
414 * FIFO, enable interrupts, and wait for the transfer to complete.
415 */
416 if (ep93xx_spi_read_write(espi)) {
417 ep93xx_spi_enable_interrupts(espi);
418 wait_for_completion(&espi->wait);
419 }
420}
421
422/**
423 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
424 * @espi: ep93xx SPI controller struct
425 * @dir: DMA transfer direction
426 *
427 * Function configures the DMA, maps the buffer and prepares the DMA
428 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
429 * in case of failure.
430 */
431static struct dma_async_tx_descriptor *
H Hartley Sweetend4b9b572012-04-17 18:46:36 -0700432ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
Mika Westerberg626a96d2011-05-29 13:10:06 +0300433{
434 struct spi_transfer *t = espi->current_msg->state;
435 struct dma_async_tx_descriptor *txd;
436 enum dma_slave_buswidth buswidth;
437 struct dma_slave_config conf;
438 struct scatterlist *sg;
439 struct sg_table *sgt;
440 struct dma_chan *chan;
441 const void *buf, *pbuf;
442 size_t len = t->len;
443 int i, ret, nents;
444
H Hartley Sweeten701c3582013-07-02 10:07:01 -0700445 if (t->bits_per_word > 8)
Mika Westerberg626a96d2011-05-29 13:10:06 +0300446 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
447 else
448 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
449
450 memset(&conf, 0, sizeof(conf));
451 conf.direction = dir;
452
H Hartley Sweetend4b9b572012-04-17 18:46:36 -0700453 if (dir == DMA_DEV_TO_MEM) {
Mika Westerberg626a96d2011-05-29 13:10:06 +0300454 chan = espi->dma_rx;
455 buf = t->rx_buf;
456 sgt = &espi->rx_sgt;
457
458 conf.src_addr = espi->sspdr_phys;
459 conf.src_addr_width = buswidth;
460 } else {
461 chan = espi->dma_tx;
462 buf = t->tx_buf;
463 sgt = &espi->tx_sgt;
464
465 conf.dst_addr = espi->sspdr_phys;
466 conf.dst_addr_width = buswidth;
467 }
468
469 ret = dmaengine_slave_config(chan, &conf);
470 if (ret)
471 return ERR_PTR(ret);
472
473 /*
474 * We need to split the transfer into PAGE_SIZE'd chunks. This is
475 * because we are using @espi->zeropage to provide a zero RX buffer
476 * for the TX transfers and we have only allocated one page for that.
477 *
478 * For performance reasons we allocate a new sg_table only when
479 * needed. Otherwise we will re-use the current one. Eventually the
480 * last sg_table is released in ep93xx_spi_release_dma().
481 */
482
483 nents = DIV_ROUND_UP(len, PAGE_SIZE);
484 if (nents != sgt->nents) {
485 sg_free_table(sgt);
486
487 ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
488 if (ret)
489 return ERR_PTR(ret);
490 }
491
492 pbuf = buf;
493 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
494 size_t bytes = min_t(size_t, len, PAGE_SIZE);
495
496 if (buf) {
497 sg_set_page(sg, virt_to_page(pbuf), bytes,
498 offset_in_page(pbuf));
499 } else {
500 sg_set_page(sg, virt_to_page(espi->zeropage),
501 bytes, 0);
502 }
503
504 pbuf += bytes;
505 len -= bytes;
506 }
507
508 if (WARN_ON(len)) {
Jarkko Nikulaa1829d22013-10-11 13:53:59 +0300509 dev_warn(&espi->pdev->dev, "len = %zu expected 0!\n", len);
Mika Westerberg626a96d2011-05-29 13:10:06 +0300510 return ERR_PTR(-EINVAL);
511 }
512
513 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
514 if (!nents)
515 return ERR_PTR(-ENOMEM);
516
H Hartley Sweetend4b9b572012-04-17 18:46:36 -0700517 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK);
Mika Westerberg626a96d2011-05-29 13:10:06 +0300518 if (!txd) {
519 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
520 return ERR_PTR(-ENOMEM);
521 }
522 return txd;
523}
524
525/**
526 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
527 * @espi: ep93xx SPI controller struct
528 * @dir: DMA transfer direction
529 *
530 * Function finishes with the DMA transfer. After this, the DMA buffer is
531 * unmapped.
532 */
533static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi,
H Hartley Sweetend4b9b572012-04-17 18:46:36 -0700534 enum dma_transfer_direction dir)
Mika Westerberg626a96d2011-05-29 13:10:06 +0300535{
536 struct dma_chan *chan;
537 struct sg_table *sgt;
538
H Hartley Sweetend4b9b572012-04-17 18:46:36 -0700539 if (dir == DMA_DEV_TO_MEM) {
Mika Westerberg626a96d2011-05-29 13:10:06 +0300540 chan = espi->dma_rx;
541 sgt = &espi->rx_sgt;
542 } else {
543 chan = espi->dma_tx;
544 sgt = &espi->tx_sgt;
545 }
546
547 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
548}
549
550static void ep93xx_spi_dma_callback(void *callback_param)
551{
552 complete(callback_param);
553}
554
555static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi)
556{
557 struct spi_message *msg = espi->current_msg;
558 struct dma_async_tx_descriptor *rxd, *txd;
559
H Hartley Sweetend4b9b572012-04-17 18:46:36 -0700560 rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM);
Mika Westerberg626a96d2011-05-29 13:10:06 +0300561 if (IS_ERR(rxd)) {
562 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
563 msg->status = PTR_ERR(rxd);
564 return;
565 }
566
H Hartley Sweetend4b9b572012-04-17 18:46:36 -0700567 txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV);
Mika Westerberg626a96d2011-05-29 13:10:06 +0300568 if (IS_ERR(txd)) {
H Hartley Sweetend4b9b572012-04-17 18:46:36 -0700569 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
Mika Westerberg626a96d2011-05-29 13:10:06 +0300570 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd));
571 msg->status = PTR_ERR(txd);
572 return;
573 }
574
575 /* We are ready when RX is done */
576 rxd->callback = ep93xx_spi_dma_callback;
577 rxd->callback_param = &espi->wait;
578
579 /* Now submit both descriptors and wait while they finish */
580 dmaengine_submit(rxd);
581 dmaengine_submit(txd);
582
583 dma_async_issue_pending(espi->dma_rx);
584 dma_async_issue_pending(espi->dma_tx);
585
586 wait_for_completion(&espi->wait);
587
H Hartley Sweetend4b9b572012-04-17 18:46:36 -0700588 ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV);
589 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
Mika Westerberg626a96d2011-05-29 13:10:06 +0300590}
591
Mika Westerberg011f23a2010-05-06 04:47:04 +0000592/**
593 * ep93xx_spi_process_transfer() - processes one SPI transfer
594 * @espi: ep93xx SPI controller struct
595 * @msg: current message
596 * @t: transfer to process
597 *
598 * This function processes one SPI transfer given in @t. Function waits until
599 * transfer is complete (may sleep) and updates @msg->status based on whether
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300600 * transfer was successfully processed or not.
Mika Westerberg011f23a2010-05-06 04:47:04 +0000601 */
602static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
603 struct spi_message *msg,
604 struct spi_transfer *t)
605{
606 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi);
H Hartley Sweeten4870c212013-06-28 11:43:34 -0700607 int err;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000608
609 msg->state = t;
610
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700611 err = ep93xx_spi_chip_setup(espi, chip, t->speed_hz, t->bits_per_word);
H Hartley Sweeten4870c212013-06-28 11:43:34 -0700612 if (err) {
H Hartley Sweetenf7ef1da2013-07-02 10:10:29 -0700613 dev_err(&espi->pdev->dev,
614 "failed to setup chip for transfer\n");
H Hartley Sweeten4870c212013-06-28 11:43:34 -0700615 msg->status = err;
616 return;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000617 }
618
619 espi->rx = 0;
620 espi->tx = 0;
621
622 /*
Mika Westerberg626a96d2011-05-29 13:10:06 +0300623 * There is no point of setting up DMA for the transfers which will
624 * fit into the FIFO and can be transferred with a single interrupt.
625 * So in these cases we will be using PIO and don't bother for DMA.
Mika Westerberg011f23a2010-05-06 04:47:04 +0000626 */
Mika Westerberg626a96d2011-05-29 13:10:06 +0300627 if (espi->dma_rx && t->len > SPI_FIFO_SIZE)
628 ep93xx_spi_dma_transfer(espi);
629 else
630 ep93xx_spi_pio_transfer(espi);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000631
632 /*
633 * In case of error during transmit, we bail out from processing
634 * the message.
635 */
636 if (msg->status)
637 return;
638
Mika Westerberg626a96d2011-05-29 13:10:06 +0300639 msg->actual_length += t->len;
640
Mika Westerberg011f23a2010-05-06 04:47:04 +0000641 /*
642 * After this transfer is finished, perform any possible
643 * post-transfer actions requested by the protocol driver.
644 */
645 if (t->delay_usecs) {
646 set_current_state(TASK_UNINTERRUPTIBLE);
647 schedule_timeout(usecs_to_jiffies(t->delay_usecs));
648 }
649 if (t->cs_change) {
650 if (!list_is_last(&t->transfer_list, &msg->transfers)) {
651 /*
652 * In case protocol driver is asking us to drop the
653 * chipselect briefly, we let the scheduler to handle
654 * any "delay" here.
655 */
656 ep93xx_spi_cs_control(msg->spi, false);
657 cond_resched();
658 ep93xx_spi_cs_control(msg->spi, true);
659 }
660 }
Mika Westerberg011f23a2010-05-06 04:47:04 +0000661}
662
663/*
664 * ep93xx_spi_process_message() - process one SPI message
665 * @espi: ep93xx SPI controller struct
666 * @msg: message to process
667 *
668 * This function processes a single SPI message. We go through all transfers in
669 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
670 * asserted during the whole message (unless per transfer cs_change is set).
671 *
672 * @msg->status contains %0 in case of success or negative error code in case of
673 * failure.
674 */
675static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
676 struct spi_message *msg)
677{
678 unsigned long timeout;
679 struct spi_transfer *t;
680 int err;
681
682 /*
683 * Enable the SPI controller and its clock.
684 */
685 err = ep93xx_spi_enable(espi);
686 if (err) {
687 dev_err(&espi->pdev->dev, "failed to enable SPI controller\n");
688 msg->status = err;
689 return;
690 }
691
692 /*
693 * Just to be sure: flush any data from RX FIFO.
694 */
695 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
696 while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) {
697 if (time_after(jiffies, timeout)) {
698 dev_warn(&espi->pdev->dev,
699 "timeout while flushing RX FIFO\n");
700 msg->status = -ETIMEDOUT;
701 return;
702 }
703 ep93xx_spi_read_u16(espi, SSPDR);
704 }
705
706 /*
707 * We explicitly handle FIFO level. This way we don't have to check TX
708 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
709 */
710 espi->fifo_level = 0;
711
712 /*
H Hartley Sweeten4870c212013-06-28 11:43:34 -0700713 * Assert the chipselect.
Mika Westerberg011f23a2010-05-06 04:47:04 +0000714 */
Mika Westerberg011f23a2010-05-06 04:47:04 +0000715 ep93xx_spi_cs_control(msg->spi, true);
716
717 list_for_each_entry(t, &msg->transfers, transfer_list) {
718 ep93xx_spi_process_transfer(espi, msg, t);
719 if (msg->status)
720 break;
721 }
722
723 /*
724 * Now the whole message is transferred (or failed for some reason). We
725 * deselect the device and disable the SPI controller.
726 */
727 ep93xx_spi_cs_control(msg->spi, false);
728 ep93xx_spi_disable(espi);
729}
730
H Hartley Sweeten84ddb3c2013-07-08 09:12:37 -0700731static int ep93xx_spi_transfer_one_message(struct spi_master *master,
732 struct spi_message *msg)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000733{
H Hartley Sweeten84ddb3c2013-07-08 09:12:37 -0700734 struct ep93xx_spi *espi = spi_master_get_devdata(master);
H Hartley Sweeten84ddb3c2013-07-08 09:12:37 -0700735
736 msg->state = NULL;
737 msg->status = 0;
738 msg->actual_length = 0;
739
Mika Westerberg011f23a2010-05-06 04:47:04 +0000740 espi->current_msg = msg;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000741 ep93xx_spi_process_message(espi, msg);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000742 espi->current_msg = NULL;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000743
H Hartley Sweeten84ddb3c2013-07-08 09:12:37 -0700744 spi_finalize_current_message(master);
745
746 return 0;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000747}
748
749static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
750{
751 struct ep93xx_spi *espi = dev_id;
752 u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR);
753
754 /*
755 * If we got ROR (receive overrun) interrupt we know that something is
756 * wrong. Just abort the message.
757 */
758 if (unlikely(irq_status & SSPIIR_RORIS)) {
759 /* clear the overrun interrupt */
760 ep93xx_spi_write_u8(espi, SSPICR, 0);
761 dev_warn(&espi->pdev->dev,
762 "receive overrun, aborting the message\n");
763 espi->current_msg->status = -EIO;
764 } else {
765 /*
766 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
767 * simply execute next data transfer.
768 */
769 if (ep93xx_spi_read_write(espi)) {
770 /*
771 * In normal case, there still is some processing left
772 * for current transfer. Let's wait for the next
773 * interrupt then.
774 */
775 return IRQ_HANDLED;
776 }
777 }
778
779 /*
780 * Current transfer is finished, either with error or with success. In
781 * any case we disable interrupts and notify the worker to handle
782 * any post-processing of the message.
783 */
784 ep93xx_spi_disable_interrupts(espi);
785 complete(&espi->wait);
786 return IRQ_HANDLED;
787}
788
Mika Westerberg626a96d2011-05-29 13:10:06 +0300789static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
790{
791 if (ep93xx_dma_chan_is_m2p(chan))
792 return false;
793
794 chan->private = filter_param;
795 return true;
796}
797
798static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
799{
800 dma_cap_mask_t mask;
801 int ret;
802
803 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
804 if (!espi->zeropage)
805 return -ENOMEM;
806
807 dma_cap_zero(mask);
808 dma_cap_set(DMA_SLAVE, mask);
809
810 espi->dma_rx_data.port = EP93XX_DMA_SSP;
Vinod Koula485df42011-10-14 10:47:38 +0530811 espi->dma_rx_data.direction = DMA_DEV_TO_MEM;
Mika Westerberg626a96d2011-05-29 13:10:06 +0300812 espi->dma_rx_data.name = "ep93xx-spi-rx";
813
814 espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
815 &espi->dma_rx_data);
816 if (!espi->dma_rx) {
817 ret = -ENODEV;
818 goto fail_free_page;
819 }
820
821 espi->dma_tx_data.port = EP93XX_DMA_SSP;
Vinod Koula485df42011-10-14 10:47:38 +0530822 espi->dma_tx_data.direction = DMA_MEM_TO_DEV;
Mika Westerberg626a96d2011-05-29 13:10:06 +0300823 espi->dma_tx_data.name = "ep93xx-spi-tx";
824
825 espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
826 &espi->dma_tx_data);
827 if (!espi->dma_tx) {
828 ret = -ENODEV;
829 goto fail_release_rx;
830 }
831
832 return 0;
833
834fail_release_rx:
835 dma_release_channel(espi->dma_rx);
836 espi->dma_rx = NULL;
837fail_free_page:
838 free_page((unsigned long)espi->zeropage);
839
840 return ret;
841}
842
843static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
844{
845 if (espi->dma_rx) {
846 dma_release_channel(espi->dma_rx);
847 sg_free_table(&espi->rx_sgt);
848 }
849 if (espi->dma_tx) {
850 dma_release_channel(espi->dma_tx);
851 sg_free_table(&espi->tx_sgt);
852 }
853
854 if (espi->zeropage)
855 free_page((unsigned long)espi->zeropage);
856}
857
Grant Likelyfd4a3192012-12-07 16:57:14 +0000858static int ep93xx_spi_probe(struct platform_device *pdev)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000859{
860 struct spi_master *master;
861 struct ep93xx_spi_info *info;
862 struct ep93xx_spi *espi;
863 struct resource *res;
Hannu Heikkinen6d6467e2012-05-09 17:26:26 +0300864 int irq;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000865 int error;
866
Jingoo Han8074cf02013-07-30 16:58:59 +0900867 info = dev_get_platdata(&pdev->dev);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000868
H Hartley Sweeten48a77762013-07-02 10:07:53 -0700869 irq = platform_get_irq(pdev, 0);
870 if (irq < 0) {
871 dev_err(&pdev->dev, "failed to get irq resources\n");
872 return -EBUSY;
873 }
874
875 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
876 if (!res) {
877 dev_err(&pdev->dev, "unable to get iomem resource\n");
878 return -ENODEV;
879 }
880
Mika Westerberg011f23a2010-05-06 04:47:04 +0000881 master = spi_alloc_master(&pdev->dev, sizeof(*espi));
H Hartley Sweetenb2d185e2013-07-02 10:08:59 -0700882 if (!master)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000883 return -ENOMEM;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000884
885 master->setup = ep93xx_spi_setup;
H Hartley Sweeten84ddb3c2013-07-08 09:12:37 -0700886 master->transfer_one_message = ep93xx_spi_transfer_one_message;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000887 master->cleanup = ep93xx_spi_cleanup;
888 master->bus_num = pdev->id;
889 master->num_chipselect = info->num_chipselect;
890 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
Stephen Warren24778be2013-05-21 20:36:35 -0600891 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000892
893 platform_set_drvdata(pdev, master);
894
895 espi = spi_master_get_devdata(master);
896
H Hartley Sweetene6eb8d92013-07-02 10:08:21 -0700897 espi->clk = devm_clk_get(&pdev->dev, NULL);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000898 if (IS_ERR(espi->clk)) {
899 dev_err(&pdev->dev, "unable to get spi clock\n");
900 error = PTR_ERR(espi->clk);
901 goto fail_release_master;
902 }
903
Mika Westerberg011f23a2010-05-06 04:47:04 +0000904 init_completion(&espi->wait);
905
906 /*
907 * Calculate maximum and minimum supported clock rates
908 * for the controller.
909 */
Axel Lin56fc0b42014-02-08 23:52:26 +0800910 master->max_speed_hz = clk_get_rate(espi->clk) / 2;
911 master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000912 espi->pdev = pdev;
913
Mika Westerberg626a96d2011-05-29 13:10:06 +0300914 espi->sspdr_phys = res->start + SSPDR;
Hannu Heikkinen6d6467e2012-05-09 17:26:26 +0300915
Thierry Redingb0ee5602013-01-21 11:09:18 +0100916 espi->regs_base = devm_ioremap_resource(&pdev->dev, res);
917 if (IS_ERR(espi->regs_base)) {
918 error = PTR_ERR(espi->regs_base);
H Hartley Sweetene6eb8d92013-07-02 10:08:21 -0700919 goto fail_release_master;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000920 }
921
Hannu Heikkinen6d6467e2012-05-09 17:26:26 +0300922 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
923 0, "ep93xx-spi", espi);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000924 if (error) {
925 dev_err(&pdev->dev, "failed to request irq\n");
H Hartley Sweetene6eb8d92013-07-02 10:08:21 -0700926 goto fail_release_master;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000927 }
928
Mika Westerberg626a96d2011-05-29 13:10:06 +0300929 if (info->use_dma && ep93xx_spi_setup_dma(espi))
930 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
931
Mika Westerberg011f23a2010-05-06 04:47:04 +0000932 /* make sure that the hardware is disabled */
933 ep93xx_spi_write_u8(espi, SSPCR1, 0);
934
Jingoo Han434eaf32013-09-24 13:30:41 +0900935 error = devm_spi_register_master(&pdev->dev, master);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000936 if (error) {
937 dev_err(&pdev->dev, "failed to register SPI master\n");
H Hartley Sweeten84ddb3c2013-07-08 09:12:37 -0700938 goto fail_free_dma;
Mika Westerberg011f23a2010-05-06 04:47:04 +0000939 }
940
941 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
Hannu Heikkinen6d6467e2012-05-09 17:26:26 +0300942 (unsigned long)res->start, irq);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000943
944 return 0;
945
Mika Westerberg626a96d2011-05-29 13:10:06 +0300946fail_free_dma:
947 ep93xx_spi_release_dma(espi);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000948fail_release_master:
949 spi_master_put(master);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000950
951 return error;
952}
953
Grant Likelyfd4a3192012-12-07 16:57:14 +0000954static int ep93xx_spi_remove(struct platform_device *pdev)
Mika Westerberg011f23a2010-05-06 04:47:04 +0000955{
956 struct spi_master *master = platform_get_drvdata(pdev);
957 struct ep93xx_spi *espi = spi_master_get_devdata(master);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000958
Mika Westerberg626a96d2011-05-29 13:10:06 +0300959 ep93xx_spi_release_dma(espi);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000960
Mika Westerberg011f23a2010-05-06 04:47:04 +0000961 return 0;
962}
963
964static struct platform_driver ep93xx_spi_driver = {
965 .driver = {
966 .name = "ep93xx-spi",
Mika Westerberg011f23a2010-05-06 04:47:04 +0000967 },
Grant Likely940ab882011-10-05 11:29:49 -0600968 .probe = ep93xx_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000969 .remove = ep93xx_spi_remove,
Mika Westerberg011f23a2010-05-06 04:47:04 +0000970};
Grant Likely940ab882011-10-05 11:29:49 -0600971module_platform_driver(ep93xx_spi_driver);
Mika Westerberg011f23a2010-05-06 04:47:04 +0000972
973MODULE_DESCRIPTION("EP93xx SPI Controller driver");
974MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
975MODULE_LICENSE("GPL");
976MODULE_ALIAS("platform:ep93xx-spi");