blob: 6b65a102b49ded103b8169131a41089e7db2332a [file] [log] [blame]
Ralf Baechlef65aad42012-10-17 00:39:09 +02001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Wind River Systems,
7 * written by Ralf Baechle <ralf@linux-mips.org>
Daniel Walker1bc021e2013-09-20 15:46:41 -07008 *
9 * Copyright (c) 2013 by Cisco Systems, Inc.
10 * All rights reserved.
Ralf Baechlef65aad42012-10-17 00:39:09 +020011 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/io.h>
16#include <linux/edac.h>
Daniel Walker1bc021e2013-09-20 15:46:41 -070017#include <linux/ctype.h>
Ralf Baechlef65aad42012-10-17 00:39:09 +020018
David Daneye1ced092012-11-15 13:58:59 -080019#include <asm/octeon/octeon.h>
20#include <asm/octeon/cvmx-lmcx-defs.h>
Ralf Baechlef65aad42012-10-17 00:39:09 +020021
22#include "edac_core.h"
23#include "edac_module.h"
Ralf Baechlef65aad42012-10-17 00:39:09 +020024
David Daneye1ced092012-11-15 13:58:59 -080025#define OCTEON_MAX_MC 4
Ralf Baechlef65aad42012-10-17 00:39:09 +020026
Daniel Walker1bc021e2013-09-20 15:46:41 -070027#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
28
29struct octeon_lmc_pvt {
30 unsigned long inject;
31 unsigned long error_type;
32 unsigned long dimm;
33 unsigned long rank;
34 unsigned long bank;
35 unsigned long row;
36 unsigned long col;
37};
38
David Daneye1ced092012-11-15 13:58:59 -080039static void octeon_lmc_edac_poll(struct mem_ctl_info *mci)
Ralf Baechlef65aad42012-10-17 00:39:09 +020040{
David Daneye1ced092012-11-15 13:58:59 -080041 union cvmx_lmcx_mem_cfg0 cfg0;
42 bool do_clear = false;
Ralf Baechlef65aad42012-10-17 00:39:09 +020043 char msg[64];
44
David Daneye1ced092012-11-15 13:58:59 -080045 cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx));
46 if (cfg0.s.sec_err || cfg0.s.ded_err) {
47 union cvmx_lmcx_fadr fadr;
48 fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
49 snprintf(msg, sizeof(msg),
50 "DIMM %d rank %d bank %d row %d col %d",
51 fadr.cn30xx.fdimm, fadr.cn30xx.fbunk,
52 fadr.cn30xx.fbank, fadr.cn30xx.frow, fadr.cn30xx.fcol);
Ralf Baechlef65aad42012-10-17 00:39:09 +020053 }
54
David Daneye1ced092012-11-15 13:58:59 -080055 if (cfg0.s.sec_err) {
56 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
57 -1, -1, -1, msg, "");
58 cfg0.s.sec_err = -1; /* Done, re-arm */
59 do_clear = true;
Ralf Baechlef65aad42012-10-17 00:39:09 +020060 }
61
David Daneye1ced092012-11-15 13:58:59 -080062 if (cfg0.s.ded_err) {
63 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
64 -1, -1, -1, msg, "");
65 cfg0.s.ded_err = -1; /* Done, re-arm */
66 do_clear = true;
67 }
68 if (do_clear)
69 cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64);
Ralf Baechlef65aad42012-10-17 00:39:09 +020070}
71
David Daneye1ced092012-11-15 13:58:59 -080072static void octeon_lmc_edac_poll_o2(struct mem_ctl_info *mci)
73{
Daniel Walker1bc021e2013-09-20 15:46:41 -070074 struct octeon_lmc_pvt *pvt = mci->pvt_info;
David Daneye1ced092012-11-15 13:58:59 -080075 union cvmx_lmcx_int int_reg;
76 bool do_clear = false;
77 char msg[64];
78
Daniel Walker1bc021e2013-09-20 15:46:41 -070079 if (!pvt->inject)
80 int_reg.u64 = cvmx_read_csr(CVMX_LMCX_INT(mci->mc_idx));
81 else {
James Hogan10ddc772017-11-13 16:12:06 +000082 int_reg.u64 = 0;
Daniel Walker1bc021e2013-09-20 15:46:41 -070083 if (pvt->error_type == 1)
84 int_reg.s.sec_err = 1;
85 if (pvt->error_type == 2)
86 int_reg.s.ded_err = 1;
87 }
88
David Daneye1ced092012-11-15 13:58:59 -080089 if (int_reg.s.sec_err || int_reg.s.ded_err) {
90 union cvmx_lmcx_fadr fadr;
Daniel Walker1bc021e2013-09-20 15:46:41 -070091 if (likely(!pvt->inject))
92 fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
93 else {
94 fadr.cn61xx.fdimm = pvt->dimm;
95 fadr.cn61xx.fbunk = pvt->rank;
96 fadr.cn61xx.fbank = pvt->bank;
97 fadr.cn61xx.frow = pvt->row;
98 fadr.cn61xx.fcol = pvt->col;
99 }
David Daneye1ced092012-11-15 13:58:59 -0800100 snprintf(msg, sizeof(msg),
101 "DIMM %d rank %d bank %d row %d col %d",
102 fadr.cn61xx.fdimm, fadr.cn61xx.fbunk,
103 fadr.cn61xx.fbank, fadr.cn61xx.frow, fadr.cn61xx.fcol);
104 }
105
106 if (int_reg.s.sec_err) {
107 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
108 -1, -1, -1, msg, "");
109 int_reg.s.sec_err = -1; /* Done, re-arm */
110 do_clear = true;
111 }
112
113 if (int_reg.s.ded_err) {
114 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
115 -1, -1, -1, msg, "");
116 int_reg.s.ded_err = -1; /* Done, re-arm */
117 do_clear = true;
118 }
Daniel Walker1bc021e2013-09-20 15:46:41 -0700119
120 if (do_clear) {
121 if (likely(!pvt->inject))
122 cvmx_write_csr(CVMX_LMCX_INT(mci->mc_idx), int_reg.u64);
123 else
124 pvt->inject = 0;
125 }
126}
127
128/************************ MC SYSFS parts ***********************************/
129
130/* Only a couple naming differences per template, so very similar */
131#define TEMPLATE_SHOW(reg) \
132static ssize_t octeon_mc_inject_##reg##_show(struct device *dev, \
133 struct device_attribute *attr, \
134 char *data) \
135{ \
136 struct mem_ctl_info *mci = to_mci(dev); \
137 struct octeon_lmc_pvt *pvt = mci->pvt_info; \
138 return sprintf(data, "%016llu\n", (u64)pvt->reg); \
139}
140
141#define TEMPLATE_STORE(reg) \
142static ssize_t octeon_mc_inject_##reg##_store(struct device *dev, \
143 struct device_attribute *attr, \
144 const char *data, size_t count) \
145{ \
146 struct mem_ctl_info *mci = to_mci(dev); \
147 struct octeon_lmc_pvt *pvt = mci->pvt_info; \
148 if (isdigit(*data)) { \
149 if (!kstrtoul(data, 0, &pvt->reg)) \
150 return count; \
151 } \
152 return 0; \
153}
154
155TEMPLATE_SHOW(inject);
156TEMPLATE_STORE(inject);
157TEMPLATE_SHOW(dimm);
158TEMPLATE_STORE(dimm);
159TEMPLATE_SHOW(bank);
160TEMPLATE_STORE(bank);
161TEMPLATE_SHOW(rank);
162TEMPLATE_STORE(rank);
163TEMPLATE_SHOW(row);
164TEMPLATE_STORE(row);
165TEMPLATE_SHOW(col);
166TEMPLATE_STORE(col);
167
168static ssize_t octeon_mc_inject_error_type_store(struct device *dev,
169 struct device_attribute *attr,
170 const char *data,
171 size_t count)
172{
173 struct mem_ctl_info *mci = to_mci(dev);
174 struct octeon_lmc_pvt *pvt = mci->pvt_info;
175
176 if (!strncmp(data, "single", 6))
177 pvt->error_type = 1;
178 else if (!strncmp(data, "double", 6))
179 pvt->error_type = 2;
180
181 return count;
182}
183
184static ssize_t octeon_mc_inject_error_type_show(struct device *dev,
185 struct device_attribute *attr,
186 char *data)
187{
188 struct mem_ctl_info *mci = to_mci(dev);
189 struct octeon_lmc_pvt *pvt = mci->pvt_info;
190 if (pvt->error_type == 1)
191 return sprintf(data, "single");
192 else if (pvt->error_type == 2)
193 return sprintf(data, "double");
194
195 return 0;
196}
197
198static DEVICE_ATTR(inject, S_IRUGO | S_IWUSR,
199 octeon_mc_inject_inject_show, octeon_mc_inject_inject_store);
200static DEVICE_ATTR(error_type, S_IRUGO | S_IWUSR,
201 octeon_mc_inject_error_type_show, octeon_mc_inject_error_type_store);
202static DEVICE_ATTR(dimm, S_IRUGO | S_IWUSR,
203 octeon_mc_inject_dimm_show, octeon_mc_inject_dimm_store);
204static DEVICE_ATTR(rank, S_IRUGO | S_IWUSR,
205 octeon_mc_inject_rank_show, octeon_mc_inject_rank_store);
206static DEVICE_ATTR(bank, S_IRUGO | S_IWUSR,
207 octeon_mc_inject_bank_show, octeon_mc_inject_bank_store);
208static DEVICE_ATTR(row, S_IRUGO | S_IWUSR,
209 octeon_mc_inject_row_show, octeon_mc_inject_row_store);
210static DEVICE_ATTR(col, S_IRUGO | S_IWUSR,
211 octeon_mc_inject_col_show, octeon_mc_inject_col_store);
212
Takashi Iwai1bf06a02015-02-04 11:48:57 +0100213static struct attribute *octeon_dev_attrs[] = {
214 &dev_attr_inject.attr,
215 &dev_attr_error_type.attr,
216 &dev_attr_dimm.attr,
217 &dev_attr_rank.attr,
218 &dev_attr_bank.attr,
219 &dev_attr_row.attr,
220 &dev_attr_col.attr,
221 NULL
222};
Daniel Walker1bc021e2013-09-20 15:46:41 -0700223
Takashi Iwai1bf06a02015-02-04 11:48:57 +0100224ATTRIBUTE_GROUPS(octeon_dev);
David Daneye1ced092012-11-15 13:58:59 -0800225
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800226static int octeon_lmc_edac_probe(struct platform_device *pdev)
Ralf Baechlef65aad42012-10-17 00:39:09 +0200227{
228 struct mem_ctl_info *mci;
David Daneye1ced092012-11-15 13:58:59 -0800229 struct edac_mc_layer layers[1];
230 int mc = pdev->id;
Ralf Baechlef65aad42012-10-17 00:39:09 +0200231
Daniel Walker5331de02013-09-20 15:46:40 -0700232 opstate_init();
233
David Daneye1ced092012-11-15 13:58:59 -0800234 layers[0].type = EDAC_MC_LAYER_CHANNEL;
235 layers[0].size = 1;
236 layers[0].is_virt_csrow = false;
Ralf Baechlef65aad42012-10-17 00:39:09 +0200237
Aaro Koskinen75a15a72015-07-01 13:38:52 +0300238 if (OCTEON_IS_OCTEON1PLUS()) {
David Daneye1ced092012-11-15 13:58:59 -0800239 union cvmx_lmcx_mem_cfg0 cfg0;
Ralf Baechlef65aad42012-10-17 00:39:09 +0200240
David Daneye1ced092012-11-15 13:58:59 -0800241 cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0));
242 if (!cfg0.s.ecc_ena) {
243 dev_info(&pdev->dev, "Disabled (ECC not enabled)\n");
244 return 0;
245 }
Ralf Baechlef65aad42012-10-17 00:39:09 +0200246
Daniel Walker1bc021e2013-09-20 15:46:41 -0700247 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
David Daneye1ced092012-11-15 13:58:59 -0800248 if (!mci)
249 return -ENXIO;
250
251 mci->pdev = &pdev->dev;
252 mci->dev_name = dev_name(&pdev->dev);
253
254 mci->mod_name = "octeon-lmc";
255 mci->ctl_name = "octeon-lmc-err";
256 mci->edac_check = octeon_lmc_edac_poll;
257
Takashi Iwai1bf06a02015-02-04 11:48:57 +0100258 if (edac_mc_add_mc_with_groups(mci, octeon_dev_groups)) {
David Daneye1ced092012-11-15 13:58:59 -0800259 dev_err(&pdev->dev, "edac_mc_add_mc() failed\n");
260 edac_mc_free(mci);
261 return -ENXIO;
262 }
263
264 cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
265 cfg0.s.intr_ded_ena = 0; /* We poll */
266 cfg0.s.intr_sec_ena = 0;
267 cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), cfg0.u64);
268 } else {
269 /* OCTEON II */
270 union cvmx_lmcx_int_en en;
271 union cvmx_lmcx_config config;
272
273 config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(0));
274 if (!config.s.ecc_ena) {
275 dev_info(&pdev->dev, "Disabled (ECC not enabled)\n");
276 return 0;
277 }
278
Daniel Walker1bc021e2013-09-20 15:46:41 -0700279 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
David Daneye1ced092012-11-15 13:58:59 -0800280 if (!mci)
281 return -ENXIO;
282
283 mci->pdev = &pdev->dev;
284 mci->dev_name = dev_name(&pdev->dev);
285
286 mci->mod_name = "octeon-lmc";
287 mci->ctl_name = "co_lmc_err";
288 mci->edac_check = octeon_lmc_edac_poll_o2;
289
Takashi Iwai1bf06a02015-02-04 11:48:57 +0100290 if (edac_mc_add_mc_with_groups(mci, octeon_dev_groups)) {
David Daneye1ced092012-11-15 13:58:59 -0800291 dev_err(&pdev->dev, "edac_mc_add_mc() failed\n");
292 edac_mc_free(mci);
293 return -ENXIO;
294 }
295
296 en.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
297 en.s.intr_ded_ena = 0; /* We poll */
298 en.s.intr_sec_ena = 0;
299 cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), en.u64);
Ralf Baechlef65aad42012-10-17 00:39:09 +0200300 }
David Daneye1ced092012-11-15 13:58:59 -0800301 platform_set_drvdata(pdev, mci);
Ralf Baechlef65aad42012-10-17 00:39:09 +0200302
303 return 0;
Ralf Baechlef65aad42012-10-17 00:39:09 +0200304}
305
David Daneye1ced092012-11-15 13:58:59 -0800306static int octeon_lmc_edac_remove(struct platform_device *pdev)
Ralf Baechlef65aad42012-10-17 00:39:09 +0200307{
308 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
309
Ralf Baechlef65aad42012-10-17 00:39:09 +0200310 edac_mc_del_mc(&pdev->dev);
311 edac_mc_free(mci);
Ralf Baechlef65aad42012-10-17 00:39:09 +0200312 return 0;
313}
314
David Daneye1ced092012-11-15 13:58:59 -0800315static struct platform_driver octeon_lmc_edac_driver = {
316 .probe = octeon_lmc_edac_probe,
317 .remove = octeon_lmc_edac_remove,
Ralf Baechlef65aad42012-10-17 00:39:09 +0200318 .driver = {
David Daneye1ced092012-11-15 13:58:59 -0800319 .name = "octeon_lmc_edac",
Ralf Baechlef65aad42012-10-17 00:39:09 +0200320 }
321};
David Daneye1ced092012-11-15 13:58:59 -0800322module_platform_driver(octeon_lmc_edac_driver);
Ralf Baechlef65aad42012-10-17 00:39:09 +0200323
324MODULE_LICENSE("GPL");
325MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");