blob: 8bf4fce0813a8ee53a38b3e1d0baa82ddffa9e31 [file] [log] [blame]
Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005 Fen Systems Ltd.
4 * Copyright 2006 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef EFX_SPI_H
12#define EFX_SPI_H
13
14#include "net_driver.h"
15
16/**************************************************************************
17 *
18 * Basic SPI command set and bit definitions
19 *
20 *************************************************************************/
21
Ben Hutchings4a5b5042008-09-01 12:47:16 +010022#define SPI_WRSR 0x01 /* Write status register */
23#define SPI_WRITE 0x02 /* Write data to memory array */
24#define SPI_READ 0x03 /* Read data from memory array */
25#define SPI_WRDI 0x04 /* Reset write enable latch */
26#define SPI_RDSR 0x05 /* Read status register */
27#define SPI_WREN 0x06 /* Set write enable latch */
Ben Hutchingsf4150722008-11-04 20:34:28 +000028#define SPI_SST_EWSR 0x50 /* SST: Enable write to status register */
Ben Hutchings4a5b5042008-09-01 12:47:16 +010029
30#define SPI_STATUS_WPEN 0x80 /* Write-protect pin enabled */
31#define SPI_STATUS_BP2 0x10 /* Block protection bit 2 */
32#define SPI_STATUS_BP1 0x08 /* Block protection bit 1 */
33#define SPI_STATUS_BP0 0x04 /* Block protection bit 0 */
34#define SPI_STATUS_WEN 0x02 /* State of the write enable latch */
35#define SPI_STATUS_NRDY 0x01 /* Device busy flag */
36
37/**
38 * struct efx_spi_device - an Efx SPI (Serial Peripheral Interface) device
Ben Hutchings4a5b5042008-09-01 12:47:16 +010039 * @device_id: Controller's id for the device
40 * @size: Size (in bytes)
41 * @addr_len: Number of address bytes in read/write commands
42 * @munge_address: Flag whether addresses should be munged.
43 * Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
44 * use bit 3 of the command byte as address bit A8, rather
45 * than having a two-byte address. If this flag is set, then
46 * commands should be munged in this way.
Ben Hutchingsf4150722008-11-04 20:34:28 +000047 * @erase_command: Erase command (or 0 if sector erase not needed).
48 * @erase_size: Erase sector size (in bytes)
49 * Erase commands affect sectors with this size and alignment.
50 * This must be a power of two.
Ben Hutchings4a5b5042008-09-01 12:47:16 +010051 * @block_size: Write block size (in bytes).
52 * Write commands are limited to blocks with this size and alignment.
Ben Hutchings8ceee662008-04-27 12:55:59 +010053 */
Ben Hutchings4a5b5042008-09-01 12:47:16 +010054struct efx_spi_device {
Ben Hutchings4a5b5042008-09-01 12:47:16 +010055 int device_id;
56 unsigned int size;
57 unsigned int addr_len;
58 unsigned int munge_address:1;
Ben Hutchingsf4150722008-11-04 20:34:28 +000059 u8 erase_command;
60 unsigned int erase_size;
Ben Hutchings4a5b5042008-09-01 12:47:16 +010061 unsigned int block_size;
62};
Ben Hutchings8ceee662008-04-27 12:55:59 +010063
Ben Hutchings76884832009-11-29 15:10:44 +000064int falcon_spi_cmd(struct efx_nic *efx,
65 const struct efx_spi_device *spi, unsigned int command,
Ben Hutchings23d30f02008-12-12 21:56:11 -080066 int address, const void* in, void *out, size_t len);
Ben Hutchings76884832009-11-29 15:10:44 +000067int falcon_spi_wait_write(struct efx_nic *efx,
68 const struct efx_spi_device *spi);
69int falcon_spi_read(struct efx_nic *efx,
70 const struct efx_spi_device *spi, loff_t start,
Ben Hutchings4a5b5042008-09-01 12:47:16 +010071 size_t len, size_t *retlen, u8 *buffer);
Ben Hutchings76884832009-11-29 15:10:44 +000072int falcon_spi_write(struct efx_nic *efx,
73 const struct efx_spi_device *spi, loff_t start,
Ben Hutchings4a5b5042008-09-01 12:47:16 +010074 size_t len, size_t *retlen, const u8 *buffer);
Ben Hutchings8ceee662008-04-27 12:55:59 +010075
Ben Hutchings0a95f562008-11-04 20:33:11 +000076/*
77 * SFC4000 flash is partitioned into:
78 * 0-0x400 chip and board config (see falcon_hwdefs.h)
79 * 0x400-0x8000 unused (or may contain VPD if EEPROM not present)
80 * 0x8000-end boot code (mapped to PCI expansion ROM)
81 * SFC4000 small EEPROM (size < 0x400) is used for VPD only.
82 * SFC4000 large EEPROM (size >= 0x400) is partitioned into:
83 * 0-0x400 chip and board config
84 * configurable VPD
85 * 0x800-0x1800 boot config
86 * Aside from the chip and board config, all of these are optional and may
87 * be absent or truncated depending on the devices used.
88 */
89#define FALCON_NVCONFIG_END 0x400U
Ben Hutchingsf4150722008-11-04 20:34:28 +000090#define FALCON_FLASH_BOOTCODE_START 0x8000U
Ben Hutchings0a95f562008-11-04 20:33:11 +000091#define EFX_EEPROM_BOOTCONFIG_START 0x800U
92#define EFX_EEPROM_BOOTCONFIG_END 0x1800U
93
Ben Hutchings8ceee662008-04-27 12:55:59 +010094#endif /* EFX_SPI_H */