blob: 65eab9b63a7936c500df65b4e76fcc2abfb100a3 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Version 2.13
3 *
4 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
5 * IDE driver for Linux.
6 *
7 * Copyright (c) 2000-2002 Vojtech Pavlik
8 *
9 * Based on the work of:
10 * Andre Hedrick
11 */
12
13/*
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published by
16 * the Free Software Foundation.
17 */
18
19#include <linux/config.h>
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/ioport.h>
23#include <linux/blkdev.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/ide.h>
27#include <asm/io.h>
28
29#include "ide-timing.h"
30
31#define DISPLAY_AMD_TIMINGS
32
33#define AMD_IDE_ENABLE (0x00 + amd_config->base)
34#define AMD_IDE_CONFIG (0x01 + amd_config->base)
35#define AMD_CABLE_DETECT (0x02 + amd_config->base)
36#define AMD_DRIVE_TIMING (0x08 + amd_config->base)
37#define AMD_8BIT_TIMING (0x0e + amd_config->base)
38#define AMD_ADDRESS_SETUP (0x0c + amd_config->base)
39#define AMD_UDMA_TIMING (0x10 + amd_config->base)
40
41#define AMD_UDMA 0x07
42#define AMD_UDMA_33 0x01
43#define AMD_UDMA_66 0x02
44#define AMD_UDMA_100 0x03
45#define AMD_UDMA_133 0x04
46#define AMD_CHECK_SWDMA 0x08
47#define AMD_BAD_SWDMA 0x10
48#define AMD_BAD_FIFO 0x20
49#define AMD_CHECK_SERENADE 0x40
50
51/*
52 * AMD SouthBridge chips.
53 */
54
55static struct amd_ide_chip {
56 unsigned short id;
57 unsigned long base;
58 unsigned char flags;
59} amd_ide_chips[] = {
60 { PCI_DEVICE_ID_AMD_COBRA_7401, 0x40, AMD_UDMA_33 | AMD_BAD_SWDMA },
61 { PCI_DEVICE_ID_AMD_VIPER_7409, 0x40, AMD_UDMA_66 | AMD_CHECK_SWDMA },
62 { PCI_DEVICE_ID_AMD_VIPER_7411, 0x40, AMD_UDMA_100 | AMD_BAD_FIFO },
63 { PCI_DEVICE_ID_AMD_OPUS_7441, 0x40, AMD_UDMA_100 },
64 { PCI_DEVICE_ID_AMD_8111_IDE, 0x40, AMD_UDMA_133 | AMD_CHECK_SERENADE },
65 { PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x50, AMD_UDMA_100 },
66 { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x50, AMD_UDMA_133 },
67 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, 0x50, AMD_UDMA_133 },
68 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, 0x50, AMD_UDMA_133 },
69 { PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, 0x50, AMD_UDMA_133 },
70 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, 0x50, AMD_UDMA_133 },
71 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, 0x50, AMD_UDMA_133 },
72 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, 0x50, AMD_UDMA_133 },
73 { PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, AMD_UDMA_133 },
74 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, AMD_UDMA_133 },
Andy Curridaf00f982005-05-23 08:55:45 -070075 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, 0x50, AMD_UDMA_133 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 { 0 }
77};
78
79static struct amd_ide_chip *amd_config;
80static ide_pci_device_t *amd_chipset;
81static unsigned int amd_80w;
82static unsigned int amd_clock;
83
84static char *amd_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
85static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
86
87/*
88 * AMD /proc entry.
89 */
90
91#ifdef CONFIG_PROC_FS
92
93#include <linux/stat.h>
94#include <linux/proc_fs.h>
95
96static u8 amd74xx_proc;
97
98static unsigned char amd_udma2cyc[] = { 4, 6, 8, 10, 3, 2, 1, 15 };
99static unsigned long amd_base;
100static struct pci_dev *bmide_dev;
101extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
102
103#define amd_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
104#define amd_print_drive(name, format, arg...)\
105 p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
106
107static int amd74xx_get_info(char *buffer, char **addr, off_t offset, int count)
108{
109 int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
110 uen[4], udma[4], active8b[4], recover8b[4];
111 struct pci_dev *dev = bmide_dev;
112 unsigned int v, u, i;
113 unsigned short c, w;
114 unsigned char t;
115 int len;
116 char *p = buffer;
117
118 amd_print("----------AMD BusMastering IDE Configuration----------------");
119
120 amd_print("Driver Version: 2.13");
121 amd_print("South Bridge: %s", pci_name(bmide_dev));
122
123 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
124 amd_print("Revision: IDE %#x", t);
125 amd_print("Highest DMA rate: %s", amd_dma[amd_config->flags & AMD_UDMA]);
126
127 amd_print("BM-DMA base: %#lx", amd_base);
128 amd_print("PCI clock: %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10);
129
130 amd_print("-----------------------Primary IDE-------Secondary IDE------");
131
132 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
133 amd_print("Prefetch Buffer: %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
134 amd_print("Post Write Buffer: %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
135
136 pci_read_config_byte(dev, AMD_IDE_ENABLE, &t);
137 amd_print("Enabled: %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
138
139 c = inb(amd_base + 0x02) | (inb(amd_base + 0x0a) << 8);
140 amd_print("Simplex only: %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
141
142 amd_print("Cable Type: %10s%20s", (amd_80w & 1) ? "80w" : "40w", (amd_80w & 2) ? "80w" : "40w");
143
144 if (!amd_clock)
145 return p - buffer;
146
147 amd_print("-------------------drive0----drive1----drive2----drive3-----");
148
149 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
150 pci_read_config_dword(dev, AMD_DRIVE_TIMING, &v);
151 pci_read_config_word(dev, AMD_8BIT_TIMING, &w);
152 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
153
154 for (i = 0; i < 4; i++) {
155 setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
156 recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
157 active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
158 active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
159 recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
160
161 udma[i] = amd_udma2cyc[((u >> ((3 - i) << 3)) & 0x7)];
162 uen[i] = ((u >> ((3 - i) << 3)) & 0x40) ? 1 : 0;
163 den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
164
165 if (den[i] && uen[i] && udma[i] == 1) {
166 speed[i] = amd_clock * 3;
167 cycle[i] = 666666 / amd_clock;
168 continue;
169 }
170
171 if (den[i] && uen[i] && udma[i] == 15) {
172 speed[i] = amd_clock * 4;
173 cycle[i] = 500000 / amd_clock;
174 continue;
175 }
176
177 speed[i] = 4 * amd_clock / ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2);
178 cycle[i] = 1000000 * ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2) / amd_clock / 2;
179 }
180
181 amd_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
182
183 amd_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / amd_clock);
184 amd_print_drive("Cmd Active: ", "%8dns", 1000000 * active8b[i] / amd_clock);
185 amd_print_drive("Cmd Recovery: ", "%8dns", 1000000 * recover8b[i] / amd_clock);
186 amd_print_drive("Data Active: ", "%8dns", 1000000 * active[i] / amd_clock);
187 amd_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / amd_clock);
188 amd_print_drive("Cycle Time: ", "%8dns", cycle[i]);
189 amd_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);
190
191 /* hoping p - buffer is less than 4K... */
192 len = (p - buffer) - offset;
193 *addr = buffer + offset;
194
195 return len > count ? count : len;
196}
197
198#endif
199
200/*
201 * amd_set_speed() writes timing values to the chipset registers
202 */
203
204static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
205{
206 unsigned char t;
207
208 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
209 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
210 pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t);
211
212 pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)),
213 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
214
215 pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn),
216 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
217
218 switch (amd_config->flags & AMD_UDMA) {
219 case AMD_UDMA_33: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
220 case AMD_UDMA_66: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
221 case AMD_UDMA_100: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
222 case AMD_UDMA_133: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
223 default: return;
224 }
225
226 pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t);
227}
228
229/*
230 * amd_set_drive() computes timing values configures the drive and
231 * the chipset to a desired transfer mode. It also can be called
232 * by upper layers.
233 */
234
235static int amd_set_drive(ide_drive_t *drive, u8 speed)
236{
237 ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
238 struct ide_timing t, p;
239 int T, UT;
240
241 if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
242 if (ide_config_drive_speed(drive, speed))
243 printk(KERN_WARNING "ide%d: Drive %d didn't accept speed setting. Oh, well.\n",
244 drive->dn >> 1, drive->dn & 1);
245
246 T = 1000000000 / amd_clock;
247 UT = T / min_t(int, max_t(int, amd_config->flags & AMD_UDMA, 1), 2);
248
249 ide_timing_compute(drive, speed, &t, T, UT);
250
251 if (peer->present) {
252 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
253 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
254 }
255
256 if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
257 if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
258
259 amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
260
261 if (!drive->init_speed)
262 drive->init_speed = speed;
263 drive->current_speed = speed;
264
265 return 0;
266}
267
268/*
269 * amd74xx_tune_drive() is a callback from upper layers for
270 * PIO-only tuning.
271 */
272
273static void amd74xx_tune_drive(ide_drive_t *drive, u8 pio)
274{
275 if (pio == 255) {
276 amd_set_drive(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
277 return;
278 }
279
280 amd_set_drive(drive, XFER_PIO_0 + min_t(byte, pio, 5));
281}
282
283/*
284 * amd74xx_dmaproc() is a callback from upper layers that can do
285 * a lot, but we use it for DMA/PIO tuning only, delegating everything
286 * else to the default ide_dmaproc().
287 */
288
289static int amd74xx_ide_dma_check(ide_drive_t *drive)
290{
291 int w80 = HWIF(drive)->udma_four;
292
293 u8 speed = ide_find_best_mode(drive,
294 XFER_PIO | XFER_EPIO | XFER_MWDMA | XFER_UDMA |
295 ((amd_config->flags & AMD_BAD_SWDMA) ? 0 : XFER_SWDMA) |
296 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_66 ? XFER_UDMA_66 : 0) |
297 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_100 ? XFER_UDMA_100 : 0) |
298 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_133 ? XFER_UDMA_133 : 0));
299
300 amd_set_drive(drive, speed);
301
302 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
303 return HWIF(drive)->ide_dma_on(drive);
304 return HWIF(drive)->ide_dma_off_quietly(drive);
305}
306
307/*
308 * The initialization callback. Here we determine the IDE chip type
309 * and initialize its drive independent registers.
310 */
311
Herbert Xue895f922005-07-03 16:15:41 +0200312static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const char *name)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313{
314 unsigned char t;
315 unsigned int u;
316 int i;
317
318/*
319 * Check for bad SWDMA.
320 */
321
322 if (amd_config->flags & AMD_CHECK_SWDMA) {
323 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
324 if (t <= 7)
325 amd_config->flags |= AMD_BAD_SWDMA;
326 }
327
328/*
329 * Check 80-wire cable presence.
330 */
331
332 switch (amd_config->flags & AMD_UDMA) {
333
334 case AMD_UDMA_133:
335 case AMD_UDMA_100:
336 pci_read_config_byte(dev, AMD_CABLE_DETECT, &t);
337 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
338 amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
339 for (i = 24; i >= 0; i -= 8)
340 if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
341 printk(KERN_WARNING "%s: BIOS didn't set cable bits correctly. Enabling workaround.\n",
342 amd_chipset->name);
343 amd_80w |= (1 << (1 - (i >> 4)));
344 }
345 break;
346
347 case AMD_UDMA_66:
348 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
349 for (i = 24; i >= 0; i -= 8)
350 if ((u >> i) & 4)
351 amd_80w |= (1 << (1 - (i >> 4)));
352 break;
353 }
354
355/*
356 * Take care of prefetch & postwrite.
357 */
358
359 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
360 pci_write_config_byte(dev, AMD_IDE_CONFIG,
361 (amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t | 0xf0));
362
363/*
364 * Take care of incorrectly wired Serenade mainboards.
365 */
366
367 if ((amd_config->flags & AMD_CHECK_SERENADE) &&
368 dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
369 dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
370 amd_config->flags = AMD_UDMA_100;
371
372/*
373 * Determine the system bus clock.
374 */
375
376 amd_clock = system_bus_clock() * 1000;
377
378 switch (amd_clock) {
379 case 33000: amd_clock = 33333; break;
380 case 37000: amd_clock = 37500; break;
381 case 41000: amd_clock = 41666; break;
382 }
383
384 if (amd_clock < 20000 || amd_clock > 50000) {
385 printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
386 amd_chipset->name, amd_clock);
387 printk(KERN_WARNING "%s: Use ide0=ata66 if you want to assume 80-wire cable\n",
388 amd_chipset->name);
389 amd_clock = 33333;
390 }
391
392/*
393 * Print the boot message.
394 */
395
396 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
397 printk(KERN_INFO "%s: %s (rev %02x) %s controller\n",
398 amd_chipset->name, pci_name(dev), t, amd_dma[amd_config->flags & AMD_UDMA]);
399
400/*
401 * Register /proc/ide/amd74xx entry
402 */
403
404#if defined(DISPLAY_AMD_TIMINGS) && defined(CONFIG_PROC_FS)
405 if (!amd74xx_proc) {
406 amd_base = pci_resource_start(dev, 4);
407 bmide_dev = dev;
408 ide_pci_create_host_proc("amd74xx", amd74xx_get_info);
409 amd74xx_proc = 1;
410 }
411#endif /* DISPLAY_AMD_TIMINGS && CONFIG_PROC_FS */
412
413 return dev->irq;
414}
415
Herbert Xue895f922005-07-03 16:15:41 +0200416static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417{
418 int i;
419
420 if (hwif->irq == 0) /* 0 is bogus but will do for now */
421 hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);
422
423 hwif->autodma = 0;
424
425 hwif->tuneproc = &amd74xx_tune_drive;
426 hwif->speedproc = &amd_set_drive;
427
428 for (i = 0; i < 2; i++) {
429 hwif->drives[i].io_32bit = 1;
430 hwif->drives[i].unmask = 1;
431 hwif->drives[i].autotune = 1;
432 hwif->drives[i].dn = hwif->channel * 2 + i;
433 }
434
435 if (!hwif->dma_base)
436 return;
437
438 hwif->atapi_dma = 1;
439 hwif->ultra_mask = 0x7f;
440 hwif->mwdma_mask = 0x07;
441 hwif->swdma_mask = 0x07;
442
443 if (!hwif->udma_four)
444 hwif->udma_four = (amd_80w >> hwif->channel) & 1;
445 hwif->ide_dma_check = &amd74xx_ide_dma_check;
446 if (!noautodma)
447 hwif->autodma = 1;
448 hwif->drives[0].autodma = hwif->autodma;
449 hwif->drives[1].autodma = hwif->autodma;
450}
451
452#define DECLARE_AMD_DEV(name_str) \
453 { \
454 .name = name_str, \
455 .init_chipset = init_chipset_amd74xx, \
456 .init_hwif = init_hwif_amd74xx, \
457 .channels = 2, \
458 .autodma = AUTODMA, \
459 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
460 .bootable = ON_BOARD, \
461 }
462
463#define DECLARE_NV_DEV(name_str) \
464 { \
465 .name = name_str, \
466 .init_chipset = init_chipset_amd74xx, \
467 .init_hwif = init_hwif_amd74xx, \
468 .channels = 2, \
469 .autodma = AUTODMA, \
470 .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
471 .bootable = ON_BOARD, \
472 }
473
474static ide_pci_device_t amd74xx_chipsets[] __devinitdata = {
475 /* 0 */ DECLARE_AMD_DEV("AMD7401"),
476 /* 1 */ DECLARE_AMD_DEV("AMD7409"),
477 /* 2 */ DECLARE_AMD_DEV("AMD7411"),
478 /* 3 */ DECLARE_AMD_DEV("AMD7441"),
479 /* 4 */ DECLARE_AMD_DEV("AMD8111"),
480
481 /* 5 */ DECLARE_NV_DEV("NFORCE"),
482 /* 6 */ DECLARE_NV_DEV("NFORCE2"),
483 /* 7 */ DECLARE_NV_DEV("NFORCE2-U400R"),
484 /* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA"),
485 /* 9 */ DECLARE_NV_DEV("NFORCE3-150"),
486 /* 10 */ DECLARE_NV_DEV("NFORCE3-250"),
487 /* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA"),
488 /* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2"),
489 /* 13 */ DECLARE_NV_DEV("NFORCE-CK804"),
490 /* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"),
Andy Curridaf00f982005-05-23 08:55:45 -0700491 /* 15 */ DECLARE_NV_DEV("NFORCE-MCP51"),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492};
493
494static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
495{
496 amd_chipset = amd74xx_chipsets + id->driver_data;
497 amd_config = amd_ide_chips + id->driver_data;
498 if (dev->device != amd_config->id) {
499 printk(KERN_ERR "%s: assertion 0x%02x == 0x%02x failed !\n",
500 pci_name(dev), dev->device, amd_config->id);
501 return -ENODEV;
502 }
503 return ide_setup_pci_device(dev, amd_chipset);
504}
505
506static struct pci_device_id amd74xx_pci_tbl[] = {
507 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
508 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
509 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
510 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
511 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
512 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
513 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
514 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
515#ifdef CONFIG_BLK_DEV_IDE_SATA
516 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
517#endif
518 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
519 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10 },
520#ifdef CONFIG_BLK_DEV_IDE_SATA
521 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11 },
522 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12 },
523#endif
524 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13 },
525 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14 },
Andy Curridaf00f982005-05-23 08:55:45 -0700526 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527 { 0, },
528};
529MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
530
531static struct pci_driver driver = {
532 .name = "AMD_IDE",
533 .id_table = amd74xx_pci_tbl,
534 .probe = amd74xx_probe,
535};
536
537static int amd74xx_ide_init(void)
538{
539 return ide_pci_register_driver(&driver);
540}
541
542module_init(amd74xx_ide_init);
543
544MODULE_AUTHOR("Vojtech Pavlik");
545MODULE_DESCRIPTION("AMD PCI IDE driver");
546MODULE_LICENSE("GPL");