Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | comment "Processor Type" |
| 2 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | # Select CPU types depending on the architecture selected. This selects |
| 4 | # which CPUs we support in the kernel image, and the compiler instruction |
| 5 | # optimiser behaviour. |
| 6 | |
| 7 | # ARM610 |
| 8 | config CPU_ARM610 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 9 | bool "Support ARM610 processor" if ARCH_RPC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | select CPU_32v3 |
| 11 | select CPU_CACHE_V3 |
| 12 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 13 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 14 | select CPU_COPY_V3 if MMU |
| 15 | select CPU_TLB_V3 if MMU |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 16 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | help |
| 18 | The ARM610 is the successor to the ARM3 processor |
| 19 | and was produced by VLSI Technology Inc. |
| 20 | |
| 21 | Say Y if you want support for the ARM610 processor. |
| 22 | Otherwise, say N. |
| 23 | |
Hyok S. Choi | 07e0da7 | 2006-09-26 17:37:36 +0900 | [diff] [blame] | 24 | # ARM7TDMI |
| 25 | config CPU_ARM7TDMI |
| 26 | bool "Support ARM7TDMI processor" |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 27 | depends on !MMU |
Hyok S. Choi | 07e0da7 | 2006-09-26 17:37:36 +0900 | [diff] [blame] | 28 | select CPU_32v4T |
| 29 | select CPU_ABRT_LV4T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 30 | select CPU_PABRT_LEGACY |
Hyok S. Choi | 07e0da7 | 2006-09-26 17:37:36 +0900 | [diff] [blame] | 31 | select CPU_CACHE_V4 |
| 32 | help |
| 33 | A 32-bit RISC microprocessor based on the ARM7 processor core |
| 34 | which has no memory control unit and cache. |
| 35 | |
| 36 | Say Y if you want support for the ARM7TDMI processor. |
| 37 | Otherwise, say N. |
| 38 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | # ARM710 |
| 40 | config CPU_ARM710 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 41 | bool "Support ARM710 processor" if ARCH_RPC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | select CPU_32v3 |
| 43 | select CPU_CACHE_V3 |
| 44 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 45 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 46 | select CPU_COPY_V3 if MMU |
| 47 | select CPU_TLB_V3 if MMU |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 48 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | help |
| 50 | A 32-bit RISC microprocessor based on the ARM7 processor core |
| 51 | designed by Advanced RISC Machines Ltd. The ARM710 is the |
| 52 | successor to the ARM610 processor. It was released in |
| 53 | July 1994 by VLSI Technology Inc. |
| 54 | |
| 55 | Say Y if you want support for the ARM710 processor. |
| 56 | Otherwise, say N. |
| 57 | |
| 58 | # ARM720T |
| 59 | config CPU_ARM720T |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 60 | bool "Support ARM720T processor" if ARCH_INTEGRATOR |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 61 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | select CPU_ABRT_LV4T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 63 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | select CPU_CACHE_V4 |
| 65 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 66 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 67 | select CPU_COPY_V4WT if MMU |
| 68 | select CPU_TLB_V4WT if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | help |
| 70 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and |
| 71 | MMU built around an ARM7TDMI core. |
| 72 | |
| 73 | Say Y if you want support for the ARM720T processor. |
| 74 | Otherwise, say N. |
| 75 | |
Hyok S. Choi | b731c31 | 2006-09-26 17:37:50 +0900 | [diff] [blame] | 76 | # ARM740T |
| 77 | config CPU_ARM740T |
| 78 | bool "Support ARM740T processor" if ARCH_INTEGRATOR |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 79 | depends on !MMU |
Hyok S. Choi | b731c31 | 2006-09-26 17:37:50 +0900 | [diff] [blame] | 80 | select CPU_32v4T |
| 81 | select CPU_ABRT_LV4T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 82 | select CPU_PABRT_LEGACY |
Hyok S. Choi | b731c31 | 2006-09-26 17:37:50 +0900 | [diff] [blame] | 83 | select CPU_CACHE_V3 # although the core is v4t |
| 84 | select CPU_CP15_MPU |
| 85 | help |
| 86 | A 32-bit RISC processor with 8KB cache or 4KB variants, |
| 87 | write buffer and MPU(Protection Unit) built around |
| 88 | an ARM7TDMI core. |
| 89 | |
| 90 | Say Y if you want support for the ARM740T processor. |
| 91 | Otherwise, say N. |
| 92 | |
Hyok S. Choi | 43f5f01 | 2006-09-26 17:38:05 +0900 | [diff] [blame] | 93 | # ARM9TDMI |
| 94 | config CPU_ARM9TDMI |
| 95 | bool "Support ARM9TDMI processor" |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 96 | depends on !MMU |
Hyok S. Choi | 43f5f01 | 2006-09-26 17:38:05 +0900 | [diff] [blame] | 97 | select CPU_32v4T |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 98 | select CPU_ABRT_NOMMU |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 99 | select CPU_PABRT_LEGACY |
Hyok S. Choi | 43f5f01 | 2006-09-26 17:38:05 +0900 | [diff] [blame] | 100 | select CPU_CACHE_V4 |
| 101 | help |
| 102 | A 32-bit RISC microprocessor based on the ARM9 processor core |
| 103 | which has no memory control unit and cache. |
| 104 | |
| 105 | Say Y if you want support for the ARM9TDMI processor. |
| 106 | Otherwise, say N. |
| 107 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | # ARM920T |
| 109 | config CPU_ARM920T |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 110 | bool "Support ARM920T processor" if ARCH_INTEGRATOR |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 111 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | select CPU_ABRT_EV4T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 113 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | select CPU_CACHE_V4WT |
| 115 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 116 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 117 | select CPU_COPY_V4WB if MMU |
| 118 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 119 | help |
| 120 | The ARM920T is licensed to be produced by numerous vendors, |
Hartley Sweeten | c768e676 | 2009-10-21 02:27:01 +0100 | [diff] [blame] | 121 | and is used in the Cirrus EP93xx and the Samsung S3C2410. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 122 | |
| 123 | Say Y if you want support for the ARM920T processor. |
| 124 | Otherwise, say N. |
| 125 | |
| 126 | # ARM922T |
| 127 | config CPU_ARM922T |
| 128 | bool "Support ARM922T processor" if ARCH_INTEGRATOR |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 129 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | select CPU_ABRT_EV4T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 131 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | select CPU_CACHE_V4WT |
| 133 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 134 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 135 | select CPU_COPY_V4WB if MMU |
| 136 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | help |
| 138 | The ARM922T is a version of the ARM920T, but with smaller |
| 139 | instruction and data caches. It is used in Altera's |
Andrew Victor | c53c9cf | 2007-05-11 21:01:28 +0100 | [diff] [blame] | 140 | Excalibur XA device family and Micrel's KS8695 Centaur. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | |
| 142 | Say Y if you want support for the ARM922T processor. |
| 143 | Otherwise, say N. |
| 144 | |
| 145 | # ARM925T |
| 146 | config CPU_ARM925T |
Tony Lindgren | b288f75 | 2005-07-10 19:58:08 +0100 | [diff] [blame] | 147 | bool "Support ARM925T processor" if ARCH_OMAP1 |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 148 | select CPU_32v4T |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | select CPU_ABRT_EV4T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 150 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | select CPU_CACHE_V4WT |
| 152 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 153 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 154 | select CPU_COPY_V4WB if MMU |
| 155 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | help |
| 157 | The ARM925T is a mix between the ARM920T and ARM926T, but with |
| 158 | different instruction and data caches. It is used in TI's OMAP |
| 159 | device family. |
| 160 | |
| 161 | Say Y if you want support for the ARM925T processor. |
| 162 | Otherwise, say N. |
| 163 | |
| 164 | # ARM926T |
| 165 | config CPU_ARM926T |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 166 | bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | select CPU_32v5 |
| 168 | select CPU_ABRT_EV5TJ |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 169 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 171 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 172 | select CPU_COPY_V4WB if MMU |
| 173 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | help |
| 175 | This is a variant of the ARM920. It has slightly different |
| 176 | instruction sequences for cache and TLB operations. Curiously, |
| 177 | there is no documentation on it at the ARM corporate website. |
| 178 | |
| 179 | Say Y if you want support for the ARM926T processor. |
| 180 | Otherwise, say N. |
| 181 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 182 | # FA526 |
| 183 | config CPU_FA526 |
| 184 | bool |
| 185 | select CPU_32v4 |
| 186 | select CPU_ABRT_EV4 |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 187 | select CPU_PABRT_LEGACY |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 188 | select CPU_CACHE_VIVT |
| 189 | select CPU_CP15_MMU |
| 190 | select CPU_CACHE_FA |
| 191 | select CPU_COPY_FA if MMU |
| 192 | select CPU_TLB_FA if MMU |
| 193 | help |
| 194 | The FA526 is a version of the ARMv4 compatible processor with |
| 195 | Branch Target Buffer, Unified TLB and cache line size 16. |
| 196 | |
| 197 | Say Y if you want support for the FA526 processor. |
| 198 | Otherwise, say N. |
| 199 | |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 200 | # ARM940T |
| 201 | config CPU_ARM940T |
| 202 | bool "Support ARM940T processor" if ARCH_INTEGRATOR |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 203 | depends on !MMU |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 204 | select CPU_32v4T |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 205 | select CPU_ABRT_NOMMU |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 206 | select CPU_PABRT_LEGACY |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 207 | select CPU_CACHE_VIVT |
| 208 | select CPU_CP15_MPU |
| 209 | help |
| 210 | ARM940T is a member of the ARM9TDMI family of general- |
Matt LaPlante | 3cb2fcc | 2006-11-30 05:22:59 +0100 | [diff] [blame] | 211 | purpose microprocessors with MPU and separate 4KB |
Hyok S. Choi | d60674e | 2006-09-26 17:38:18 +0900 | [diff] [blame] | 212 | instruction and 4KB data cases, each with a 4-word line |
| 213 | length. |
| 214 | |
| 215 | Say Y if you want support for the ARM940T processor. |
| 216 | Otherwise, say N. |
| 217 | |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 218 | # ARM946E-S |
| 219 | config CPU_ARM946E |
| 220 | bool "Support ARM946E-S processor" if ARCH_INTEGRATOR |
Russell King | 6b237a3 | 2006-09-27 17:44:39 +0100 | [diff] [blame] | 221 | depends on !MMU |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 222 | select CPU_32v5 |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 223 | select CPU_ABRT_NOMMU |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 224 | select CPU_PABRT_LEGACY |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 225 | select CPU_CACHE_VIVT |
| 226 | select CPU_CP15_MPU |
| 227 | help |
| 228 | ARM946E-S is a member of the ARM9E-S family of high- |
| 229 | performance, 32-bit system-on-chip processor solutions. |
| 230 | The TCM and ARMv5TE 32-bit instruction set is supported. |
| 231 | |
| 232 | Say Y if you want support for the ARM946E-S processor. |
| 233 | Otherwise, say N. |
| 234 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | # ARM1020 - needs validating |
| 236 | config CPU_ARM1020 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 237 | bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | select CPU_32v5 |
| 239 | select CPU_ABRT_EV4T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 240 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | select CPU_CACHE_V4WT |
| 242 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 243 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 244 | select CPU_COPY_V4WB if MMU |
| 245 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 246 | help |
| 247 | The ARM1020 is the 32K cached version of the ARM10 processor, |
| 248 | with an addition of a floating-point unit. |
| 249 | |
| 250 | Say Y if you want support for the ARM1020 processor. |
| 251 | Otherwise, say N. |
| 252 | |
| 253 | # ARM1020E - needs validating |
| 254 | config CPU_ARM1020E |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 255 | bool "Support ARM1020E processor" if ARCH_INTEGRATOR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | select CPU_32v5 |
| 257 | select CPU_ABRT_EV4T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 258 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 259 | select CPU_CACHE_V4WT |
| 260 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 261 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 262 | select CPU_COPY_V4WB if MMU |
| 263 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | depends on n |
| 265 | |
| 266 | # ARM1022E |
| 267 | config CPU_ARM1022 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 268 | bool "Support ARM1022E processor" if ARCH_INTEGRATOR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 269 | select CPU_32v5 |
| 270 | select CPU_ABRT_EV4T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 271 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 273 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 274 | select CPU_COPY_V4WB if MMU # can probably do better |
| 275 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | help |
| 277 | The ARM1022E is an implementation of the ARMv5TE architecture |
| 278 | based upon the ARM10 integer core with a 16KiB L1 Harvard cache, |
| 279 | embedded trace macrocell, and a floating-point unit. |
| 280 | |
| 281 | Say Y if you want support for the ARM1022E processor. |
| 282 | Otherwise, say N. |
| 283 | |
| 284 | # ARM1026EJ-S |
| 285 | config CPU_ARM1026 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 286 | bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | select CPU_32v5 |
| 288 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 289 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 290 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 291 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 292 | select CPU_COPY_V4WB if MMU # can probably do better |
| 293 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | help |
| 295 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture |
| 296 | based upon the ARM10 integer core. |
| 297 | |
| 298 | Say Y if you want support for the ARM1026EJ-S processor. |
| 299 | Otherwise, say N. |
| 300 | |
| 301 | # SA110 |
| 302 | config CPU_SA110 |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 303 | bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 304 | select CPU_32v3 if ARCH_RPC |
| 305 | select CPU_32v4 if !ARCH_RPC |
| 306 | select CPU_ABRT_EV4 |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 307 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 308 | select CPU_CACHE_V4WB |
| 309 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 310 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 311 | select CPU_COPY_V4WB if MMU |
| 312 | select CPU_TLB_V4WB if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 313 | help |
| 314 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and |
| 315 | is available at five speeds ranging from 100 MHz to 233 MHz. |
| 316 | More information is available at |
| 317 | <http://developer.intel.com/design/strong/sa110.htm>. |
| 318 | |
| 319 | Say Y if you want support for the SA-110 processor. |
| 320 | Otherwise, say N. |
| 321 | |
| 322 | # SA1100 |
| 323 | config CPU_SA1100 |
| 324 | bool |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 325 | select CPU_32v4 |
| 326 | select CPU_ABRT_EV4 |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 327 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | select CPU_CACHE_V4WB |
| 329 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 330 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 331 | select CPU_TLB_V4WB if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | |
| 333 | # XScale |
| 334 | config CPU_XSCALE |
| 335 | bool |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 336 | select CPU_32v5 |
| 337 | select CPU_ABRT_EV5T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 338 | select CPU_PABRT_LEGACY |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 339 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 340 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 341 | select CPU_TLB_V4WBI if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 342 | |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 343 | # XScale Core Version 3 |
| 344 | config CPU_XSC3 |
| 345 | bool |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 346 | select CPU_32v5 |
| 347 | select CPU_ABRT_EV5T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 348 | select CPU_PABRT_LEGACY |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 349 | select CPU_CACHE_VIVT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 350 | select CPU_CP15_MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 351 | select CPU_TLB_V4WBI if MMU |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 352 | select IO_36 |
| 353 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 354 | # Marvell PJ1 (Mohawk) |
| 355 | config CPU_MOHAWK |
| 356 | bool |
| 357 | select CPU_32v5 |
| 358 | select CPU_ABRT_EV5T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 359 | select CPU_PABRT_LEGACY |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 360 | select CPU_CACHE_VIVT |
| 361 | select CPU_CP15_MMU |
| 362 | select CPU_TLB_V4WBI if MMU |
| 363 | select CPU_COPY_V4WB if MMU |
| 364 | |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 365 | # Feroceon |
| 366 | config CPU_FEROCEON |
| 367 | bool |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 368 | select CPU_32v5 |
| 369 | select CPU_ABRT_EV5T |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 370 | select CPU_PABRT_LEGACY |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 371 | select CPU_CACHE_VIVT |
| 372 | select CPU_CP15_MMU |
Lennert Buytenhek | 0ed1507 | 2008-04-24 01:31:45 -0400 | [diff] [blame] | 373 | select CPU_COPY_FEROCEON if MMU |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 374 | select CPU_TLB_FEROCEON if MMU |
Assaf Hoffman | e50d640 | 2007-10-23 15:14:41 -0400 | [diff] [blame] | 375 | |
Tzachi Perelstein | d910a0a | 2007-11-06 10:35:40 +0200 | [diff] [blame] | 376 | config CPU_FEROCEON_OLD_ID |
| 377 | bool "Accept early Feroceon cores with an ARM926 ID" |
| 378 | depends on CPU_FEROCEON && !CPU_ARM926T |
| 379 | default y |
| 380 | help |
| 381 | This enables the usage of some old Feroceon cores |
| 382 | for which the CPU ID is equal to the ARM926 ID. |
| 383 | Relevant for Feroceon-1850 and early Feroceon-2850. |
| 384 | |
Haojian Zhuang | a455335 | 2010-11-24 11:54:19 +0800 | [diff] [blame] | 385 | # Marvell PJ4 |
| 386 | config CPU_PJ4 |
| 387 | bool |
| 388 | select CPU_V7 |
| 389 | select ARM_THUMBEE |
| 390 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 391 | # ARMv6 |
| 392 | config CPU_V6 |
Russell King | c786282 | 2011-01-17 18:20:05 +0000 | [diff] [blame] | 393 | bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | select CPU_32v6 |
| 395 | select CPU_ABRT_EV6 |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 396 | select CPU_PABRT_V6 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 397 | select CPU_CACHE_V6 |
| 398 | select CPU_CACHE_VIPT |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 399 | select CPU_CP15_MMU |
Catalin Marinas | 7b4c965 | 2007-07-20 11:42:57 +0100 | [diff] [blame] | 400 | select CPU_HAS_ASID if MMU |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 401 | select CPU_COPY_V6 if MMU |
| 402 | select CPU_TLB_V6 if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 403 | |
Russell King | 4a5f79e | 2005-11-03 15:48:21 +0000 | [diff] [blame] | 404 | # ARMv6k |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 405 | config CPU_V6K |
Russell King | c786282 | 2011-01-17 18:20:05 +0000 | [diff] [blame] | 406 | bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 407 | select CPU_32v6 |
Russell King | 60799c6 | 2011-01-15 16:25:04 +0000 | [diff] [blame] | 408 | select CPU_32v6K |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 409 | select CPU_ABRT_EV6 |
| 410 | select CPU_PABRT_V6 |
| 411 | select CPU_CACHE_V6 |
| 412 | select CPU_CACHE_VIPT |
| 413 | select CPU_CP15_MMU |
| 414 | select CPU_HAS_ASID if MMU |
| 415 | select CPU_COPY_V6 if MMU |
| 416 | select CPU_TLB_V6 if MMU |
Russell King | 4a5f79e | 2005-11-03 15:48:21 +0000 | [diff] [blame] | 417 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 418 | # ARMv7 |
| 419 | config CPU_V7 |
Colin Tuckley | 1b504bb | 2009-05-30 13:56:12 +0100 | [diff] [blame] | 420 | bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
Russell King | 15490ef | 2011-02-09 16:33:46 +0000 | [diff] [blame] | 421 | select CPU_32v6K |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 422 | select CPU_32v7 |
| 423 | select CPU_ABRT_EV7 |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 424 | select CPU_PABRT_V7 |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 425 | select CPU_CACHE_V7 |
| 426 | select CPU_CACHE_VIPT |
| 427 | select CPU_CP15_MMU |
Catalin Marinas | 2eb8c82 | 2007-07-20 11:43:02 +0100 | [diff] [blame] | 428 | select CPU_HAS_ASID if MMU |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 429 | select CPU_COPY_V6 if MMU |
Catalin Marinas | 2ccdd1e | 2007-05-18 11:25:31 +0100 | [diff] [blame] | 430 | select CPU_TLB_V7 if MMU |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 431 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 432 | # Figure out what processor architecture version we should be using. |
| 433 | # This defines the compiler instruction set which depends on the machine type. |
| 434 | config CPU_32v3 |
| 435 | bool |
Russell King | 60b6cf6 | 2006-06-19 17:36:43 +0100 | [diff] [blame] | 436 | select TLS_REG_EMUL if SMP || !MMU |
Russell King | 48fa14f | 2006-03-16 14:52:33 +0000 | [diff] [blame] | 437 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
Russell King | 8762df4 | 2011-01-17 15:53:56 +0000 | [diff] [blame] | 438 | select CPU_USE_DOMAINS if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 439 | |
| 440 | config CPU_32v4 |
| 441 | bool |
Russell King | 60b6cf6 | 2006-06-19 17:36:43 +0100 | [diff] [blame] | 442 | select TLS_REG_EMUL if SMP || !MMU |
Russell King | 48fa14f | 2006-03-16 14:52:33 +0000 | [diff] [blame] | 443 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
Russell King | 8762df4 | 2011-01-17 15:53:56 +0000 | [diff] [blame] | 444 | select CPU_USE_DOMAINS if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 445 | |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 446 | config CPU_32v4T |
| 447 | bool |
| 448 | select TLS_REG_EMUL if SMP || !MMU |
| 449 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
Russell King | 8762df4 | 2011-01-17 15:53:56 +0000 | [diff] [blame] | 450 | select CPU_USE_DOMAINS if MMU |
Lennert Buytenhek | 260e98e | 2006-08-28 12:51:20 +0100 | [diff] [blame] | 451 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 452 | config CPU_32v5 |
| 453 | bool |
Russell King | 60b6cf6 | 2006-06-19 17:36:43 +0100 | [diff] [blame] | 454 | select TLS_REG_EMUL if SMP || !MMU |
Russell King | 48fa14f | 2006-03-16 14:52:33 +0000 | [diff] [blame] | 455 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
Russell King | 8762df4 | 2011-01-17 15:53:56 +0000 | [diff] [blame] | 456 | select CPU_USE_DOMAINS if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | |
| 458 | config CPU_32v6 |
| 459 | bool |
Catalin Marinas | 367afaf | 2007-07-20 11:42:51 +0100 | [diff] [blame] | 460 | select TLS_REG_EMUL if !CPU_32v6K && !MMU |
Russell King | 8762df4 | 2011-01-17 15:53:56 +0000 | [diff] [blame] | 461 | select CPU_USE_DOMAINS if CPU_V6 && MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 463 | config CPU_32v6K |
Russell King | 60799c6 | 2011-01-15 16:25:04 +0000 | [diff] [blame] | 464 | bool |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 465 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 466 | config CPU_32v7 |
| 467 | bool |
| 468 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 469 | # The abort model |
Hyok S. Choi | 0f45d7f | 2006-09-28 21:46:16 +0900 | [diff] [blame] | 470 | config CPU_ABRT_NOMMU |
| 471 | bool |
| 472 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 473 | config CPU_ABRT_EV4 |
| 474 | bool |
| 475 | |
| 476 | config CPU_ABRT_EV4T |
| 477 | bool |
| 478 | |
| 479 | config CPU_ABRT_LV4T |
| 480 | bool |
| 481 | |
| 482 | config CPU_ABRT_EV5T |
| 483 | bool |
| 484 | |
| 485 | config CPU_ABRT_EV5TJ |
| 486 | bool |
| 487 | |
| 488 | config CPU_ABRT_EV6 |
| 489 | bool |
| 490 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 491 | config CPU_ABRT_EV7 |
| 492 | bool |
| 493 | |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 494 | config CPU_PABRT_LEGACY |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 495 | bool |
| 496 | |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 497 | config CPU_PABRT_V6 |
| 498 | bool |
| 499 | |
| 500 | config CPU_PABRT_V7 |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 501 | bool |
| 502 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | # The cache model |
| 504 | config CPU_CACHE_V3 |
| 505 | bool |
| 506 | |
| 507 | config CPU_CACHE_V4 |
| 508 | bool |
| 509 | |
| 510 | config CPU_CACHE_V4WT |
| 511 | bool |
| 512 | |
| 513 | config CPU_CACHE_V4WB |
| 514 | bool |
| 515 | |
| 516 | config CPU_CACHE_V6 |
| 517 | bool |
| 518 | |
Catalin Marinas | 23688e9 | 2007-05-08 22:45:26 +0100 | [diff] [blame] | 519 | config CPU_CACHE_V7 |
| 520 | bool |
| 521 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 522 | config CPU_CACHE_VIVT |
| 523 | bool |
| 524 | |
| 525 | config CPU_CACHE_VIPT |
| 526 | bool |
| 527 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 528 | config CPU_CACHE_FA |
| 529 | bool |
| 530 | |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 531 | if MMU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 532 | # The copy-page model |
| 533 | config CPU_COPY_V3 |
| 534 | bool |
| 535 | |
| 536 | config CPU_COPY_V4WT |
| 537 | bool |
| 538 | |
| 539 | config CPU_COPY_V4WB |
| 540 | bool |
| 541 | |
Lennert Buytenhek | 0ed1507 | 2008-04-24 01:31:45 -0400 | [diff] [blame] | 542 | config CPU_COPY_FEROCEON |
| 543 | bool |
| 544 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 545 | config CPU_COPY_FA |
| 546 | bool |
| 547 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 548 | config CPU_COPY_V6 |
| 549 | bool |
| 550 | |
| 551 | # This selects the TLB model |
| 552 | config CPU_TLB_V3 |
| 553 | bool |
| 554 | help |
| 555 | ARM Architecture Version 3 TLB. |
| 556 | |
| 557 | config CPU_TLB_V4WT |
| 558 | bool |
| 559 | help |
| 560 | ARM Architecture Version 4 TLB with writethrough cache. |
| 561 | |
| 562 | config CPU_TLB_V4WB |
| 563 | bool |
| 564 | help |
| 565 | ARM Architecture Version 4 TLB with writeback cache. |
| 566 | |
| 567 | config CPU_TLB_V4WBI |
| 568 | bool |
| 569 | help |
| 570 | ARM Architecture Version 4 TLB with writeback cache and invalidate |
| 571 | instruction cache entry. |
| 572 | |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 573 | config CPU_TLB_FEROCEON |
| 574 | bool |
| 575 | help |
| 576 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). |
| 577 | |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 578 | config CPU_TLB_FA |
| 579 | bool |
| 580 | help |
| 581 | Faraday ARM FA526 architecture, unified TLB with writeback cache |
| 582 | and invalidate instruction cache entry. Branch target buffer is |
| 583 | also supported. |
| 584 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 585 | config CPU_TLB_V6 |
| 586 | bool |
| 587 | |
Catalin Marinas | 2ccdd1e | 2007-05-18 11:25:31 +0100 | [diff] [blame] | 588 | config CPU_TLB_V7 |
| 589 | bool |
| 590 | |
Dave Estes | e220ba6 | 2009-08-11 17:58:49 -0400 | [diff] [blame] | 591 | config VERIFY_PERMISSION_FAULT |
| 592 | bool |
Hyok S. Choi | f9c21a6 | 2006-06-21 22:26:29 +0100 | [diff] [blame] | 593 | endif |
| 594 | |
Russell King | 516793c | 2007-05-17 10:19:23 +0100 | [diff] [blame] | 595 | config CPU_HAS_ASID |
| 596 | bool |
| 597 | help |
| 598 | This indicates whether the CPU has the ASID register; used to |
| 599 | tag TLB and possibly cache entries. |
| 600 | |
Hyok S. Choi | fefdaa0 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 601 | config CPU_CP15 |
| 602 | bool |
| 603 | help |
| 604 | Processor has the CP15 register. |
| 605 | |
| 606 | config CPU_CP15_MMU |
| 607 | bool |
| 608 | select CPU_CP15 |
| 609 | help |
| 610 | Processor has the CP15 register, which has MMU related registers. |
| 611 | |
| 612 | config CPU_CP15_MPU |
| 613 | bool |
| 614 | select CPU_CP15 |
| 615 | help |
| 616 | Processor has the CP15 register, which has MPU related registers. |
| 617 | |
Catalin Marinas | 247055a | 2010-09-13 16:03:21 +0100 | [diff] [blame] | 618 | config CPU_USE_DOMAINS |
| 619 | bool |
Catalin Marinas | 247055a | 2010-09-13 16:03:21 +0100 | [diff] [blame] | 620 | help |
| 621 | This option enables or disables the use of domain switching |
| 622 | via the set_fs() function. |
| 623 | |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 624 | # |
| 625 | # CPU supports 36-bit I/O |
| 626 | # |
| 627 | config IO_36 |
| 628 | bool |
| 629 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 630 | comment "Processor Features" |
| 631 | |
| 632 | config ARM_THUMB |
| 633 | bool "Support Thumb user binaries" |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 634 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 635 | default y |
| 636 | help |
| 637 | Say Y if you want to include kernel support for running user space |
| 638 | Thumb binaries. |
| 639 | |
| 640 | The Thumb instruction set is a compressed form of the standard ARM |
| 641 | instruction set resulting in smaller binaries at the expense of |
| 642 | slightly less efficient code. |
| 643 | |
| 644 | If you don't know what this all is, saying Y is a safe choice. |
| 645 | |
Catalin Marinas | d7f864b | 2008-04-18 22:43:06 +0100 | [diff] [blame] | 646 | config ARM_THUMBEE |
| 647 | bool "Enable ThumbEE CPU extension" |
| 648 | depends on CPU_V7 |
| 649 | help |
| 650 | Say Y here if you have a CPU with the ThumbEE extension and code to |
| 651 | make use of it. Say N for code that can run on CPUs without ThumbEE. |
| 652 | |
Leif Lindholm | 64d2dc3 | 2010-09-16 18:00:47 +0100 | [diff] [blame] | 653 | config SWP_EMULATE |
| 654 | bool "Emulate SWP/SWPB instructions" |
Russell King | bd1274d | 2011-03-16 23:35:26 +0000 | [diff] [blame] | 655 | depends on !CPU_USE_DOMAINS && CPU_V7 |
Leif Lindholm | 64d2dc3 | 2010-09-16 18:00:47 +0100 | [diff] [blame] | 656 | select HAVE_PROC_CPU if PROC_FS |
| 657 | default y if SMP |
| 658 | help |
| 659 | ARMv6 architecture deprecates use of the SWP/SWPB instructions. |
| 660 | ARMv7 multiprocessing extensions introduce the ability to disable |
| 661 | these instructions, triggering an undefined instruction exception |
| 662 | when executed. Say Y here to enable software emulation of these |
| 663 | instructions for userspace (not kernel) using LDREX/STREX. |
| 664 | Also creates /proc/cpu/swp_emulation for statistics. |
| 665 | |
| 666 | In some older versions of glibc [<=2.8] SWP is used during futex |
| 667 | trylock() operations with the assumption that the code will not |
| 668 | be preempted. This invalid assumption may be more likely to fail |
| 669 | with SWP emulation enabled, leading to deadlock of the user |
| 670 | application. |
| 671 | |
| 672 | NOTE: when accessing uncached shared regions, LDREX/STREX rely |
| 673 | on an external transaction monitoring block called a global |
| 674 | monitor to maintain update atomicity. If your system does not |
| 675 | implement a global monitor, this option can cause programs that |
| 676 | perform SWP operations to uncached memory to deadlock. |
| 677 | |
| 678 | If unsure, say Y. |
| 679 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 680 | config CPU_BIG_ENDIAN |
| 681 | bool "Build big-endian kernel" |
| 682 | depends on ARCH_SUPPORTS_BIG_ENDIAN |
| 683 | help |
| 684 | Say Y if you plan on running a kernel in big-endian mode. |
| 685 | Note that your board must be properly built and your board |
| 686 | port must properly enable any big-endian related features |
| 687 | of your chipset/board/processor. |
| 688 | |
Catalin Marinas | 2658485 | 2009-05-30 14:00:18 +0100 | [diff] [blame] | 689 | config CPU_ENDIAN_BE8 |
| 690 | bool |
| 691 | depends on CPU_BIG_ENDIAN |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 692 | default CPU_V6 || CPU_V6K || CPU_V7 |
Catalin Marinas | 2658485 | 2009-05-30 14:00:18 +0100 | [diff] [blame] | 693 | help |
| 694 | Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. |
| 695 | |
| 696 | config CPU_ENDIAN_BE32 |
| 697 | bool |
| 698 | depends on CPU_BIG_ENDIAN |
| 699 | default !CPU_ENDIAN_BE8 |
| 700 | help |
| 701 | Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. |
| 702 | |
Hyok S. Choi | 6afd6fa | 2006-09-28 21:46:34 +0900 | [diff] [blame] | 703 | config CPU_HIGH_VECTOR |
Robert P. J. Day | 6340aa6 | 2007-02-17 19:05:24 +0100 | [diff] [blame] | 704 | depends on !MMU && CPU_CP15 && !CPU_ARM740T |
Hyok S. Choi | 6afd6fa | 2006-09-28 21:46:34 +0900 | [diff] [blame] | 705 | bool "Select the High exception vector" |
Hyok S. Choi | 6afd6fa | 2006-09-28 21:46:34 +0900 | [diff] [blame] | 706 | help |
| 707 | Say Y here to select high exception vector(0xFFFF0000~). |
| 708 | The exception vector can be vary depending on the platform |
| 709 | design in nommu mode. If your platform needs to select |
| 710 | high exception vector, say Y. |
| 711 | Otherwise or if you are unsure, say N, and the low exception |
| 712 | vector (0x00000000~) will be used. |
| 713 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 714 | config CPU_ICACHE_DISABLE |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 715 | bool "Disable I-Cache (I-bit)" |
| 716 | depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 717 | help |
| 718 | Say Y here to disable the processor instruction cache. Unless |
| 719 | you have a reason not to or are unsure, say N. |
| 720 | |
| 721 | config CPU_DCACHE_DISABLE |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 722 | bool "Disable D-Cache (C-bit)" |
| 723 | depends on CPU_CP15 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 724 | help |
| 725 | Say Y here to disable the processor data cache. Unless |
| 726 | you have a reason not to or are unsure, say N. |
| 727 | |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 728 | config CPU_DCACHE_SIZE |
| 729 | hex |
| 730 | depends on CPU_ARM740T || CPU_ARM946E |
| 731 | default 0x00001000 if CPU_ARM740T |
| 732 | default 0x00002000 # default size for ARM946E-S |
| 733 | help |
| 734 | Some cores are synthesizable to have various sized cache. For |
| 735 | ARM946E-S case, it can vary from 0KB to 1MB. |
| 736 | To support such cache operations, it is efficient to know the size |
| 737 | before compile time. |
| 738 | If your SoC is configured to have a different size, define the value |
| 739 | here with proper conditions. |
| 740 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 741 | config CPU_DCACHE_WRITETHROUGH |
| 742 | bool "Force write through D-cache" |
Paulius Zaleckas | 28853ac | 2009-03-25 13:10:01 +0200 | [diff] [blame] | 743 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 744 | default y if CPU_ARM925T |
| 745 | help |
| 746 | Say Y here to use the data cache in writethrough mode. Unless you |
| 747 | specifically require this or are unsure, say N. |
| 748 | |
| 749 | config CPU_CACHE_ROUND_ROBIN |
| 750 | bool "Round robin I and D cache replacement algorithm" |
Hyok S. Choi | f37f46e | 2006-09-26 17:38:32 +0900 | [diff] [blame] | 751 | depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 752 | help |
| 753 | Say Y here to use the predictable round-robin cache replacement |
| 754 | policy. Unless you specifically require this or are unsure, say N. |
| 755 | |
| 756 | config CPU_BPREDICT_DISABLE |
| 757 | bool "Disable branch prediction" |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 758 | depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 759 | help |
| 760 | Say Y here to disable branch prediction. If unsure, say N. |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 761 | |
Nicolas Pitre | 4b0e07a | 2005-05-05 23:24:45 +0100 | [diff] [blame] | 762 | config TLS_REG_EMUL |
| 763 | bool |
Nicolas Pitre | 4b0e07a | 2005-05-05 23:24:45 +0100 | [diff] [blame] | 764 | help |
Nicolas Pitre | 70489c8 | 2005-05-12 19:27:12 +0100 | [diff] [blame] | 765 | An SMP system using a pre-ARMv6 processor (there are apparently |
| 766 | a few prototypes like that in existence) and therefore access to |
| 767 | that required register must be emulated. |
Nicolas Pitre | 4b0e07a | 2005-05-05 23:24:45 +0100 | [diff] [blame] | 768 | |
Nicolas Pitre | dcef1f6 | 2005-06-08 19:00:47 +0100 | [diff] [blame] | 769 | config NEEDS_SYSCALL_FOR_CMPXCHG |
| 770 | bool |
Nicolas Pitre | dcef1f6 | 2005-06-08 19:00:47 +0100 | [diff] [blame] | 771 | help |
| 772 | SMP on a pre-ARMv6 processor? Well OK then. |
| 773 | Forget about fast user space cmpxchg support. |
| 774 | It is just not possible. |
| 775 | |
Catalin Marinas | ad642d9 | 2010-06-21 15:10:07 +0100 | [diff] [blame] | 776 | config DMA_CACHE_RWFO |
| 777 | bool "Enable read/write for ownership DMA cache maintenance" |
Russell King | 3bc28c8 | 2011-01-18 13:30:33 +0000 | [diff] [blame] | 778 | depends on CPU_V6K && SMP |
Catalin Marinas | ad642d9 | 2010-06-21 15:10:07 +0100 | [diff] [blame] | 779 | default y |
| 780 | help |
| 781 | The Snoop Control Unit on ARM11MPCore does not detect the |
| 782 | cache maintenance operations and the dma_{map,unmap}_area() |
| 783 | functions may leave stale cache entries on other CPUs. By |
| 784 | enabling this option, Read or Write For Ownership in the ARMv6 |
| 785 | DMA cache maintenance functions is performed. These LDR/STR |
| 786 | instructions change the cache line state to shared or modified |
| 787 | so that the cache operation has the desired effect. |
| 788 | |
| 789 | Note that the workaround is only valid on processors that do |
| 790 | not perform speculative loads into the D-cache. For such |
| 791 | processors, if cache maintenance operations are not broadcast |
| 792 | in hardware, other workarounds are needed (e.g. cache |
| 793 | maintenance broadcasting in software via FIQ). |
| 794 | |
Catalin Marinas | 953233d | 2007-02-05 14:48:08 +0100 | [diff] [blame] | 795 | config OUTER_CACHE |
| 796 | bool |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 797 | |
Catalin Marinas | 319f551 | 2010-03-24 16:47:53 +0100 | [diff] [blame] | 798 | config OUTER_CACHE_SYNC |
| 799 | bool |
| 800 | help |
| 801 | The outer cache has a outer_cache_fns.sync function pointer |
| 802 | that can be used to drain the write buffer of the outer cache. |
| 803 | |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 804 | config CACHE_FEROCEON_L2 |
| 805 | bool "Enable the Feroceon L2 cache controller" |
Stanislav Samsonov | 794d15b | 2008-06-22 22:45:10 +0200 | [diff] [blame] | 806 | depends on ARCH_KIRKWOOD || ARCH_MV78XX0 |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 807 | default y |
Catalin Marinas | 382266a | 2007-02-05 14:48:19 +0100 | [diff] [blame] | 808 | select OUTER_CACHE |
Lennert Buytenhek | 99c6dc1 | 2008-06-22 22:45:04 +0200 | [diff] [blame] | 809 | help |
| 810 | This option enables the Feroceon L2 cache controller. |
| 811 | |
Ronen Shitrit | 4360bb4 | 2008-09-23 15:28:10 +0300 | [diff] [blame] | 812 | config CACHE_FEROCEON_L2_WRITETHROUGH |
| 813 | bool "Force Feroceon L2 cache write through" |
| 814 | depends on CACHE_FEROCEON_L2 |
Ronen Shitrit | 4360bb4 | 2008-09-23 15:28:10 +0300 | [diff] [blame] | 815 | help |
| 816 | Say Y here to use the Feroceon L2 cache in writethrough mode. |
| 817 | Unless you specifically require this, say N for writeback mode. |
| 818 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 819 | config CACHE_L2X0 |
Catalin Marinas | ba92795 | 2008-04-18 22:43:17 +0100 | [diff] [blame] | 820 | bool "Enable the L2x0 outer cache controller" |
Sascha Hauer | cb88214 | 2009-02-08 02:00:50 +0100 | [diff] [blame] | 821 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ |
Richard Zhao | c23eb89 | 2011-03-03 16:40:03 +0800 | [diff] [blame] | 822 | REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \ |
Kukjin Kim | 10606aa | 2011-02-14 15:05:27 +0900 | [diff] [blame] | 823 | ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \ |
Arnd Bergmann | 3a6cb8c | 2011-07-17 21:43:26 +0200 | [diff] [blame] | 824 | ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \ |
Rob Herring | 220e6cf | 2011-06-07 10:02:55 -0500 | [diff] [blame^] | 825 | ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK |
Catalin Marinas | ba92795 | 2008-04-18 22:43:17 +0100 | [diff] [blame] | 826 | default y |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 827 | select OUTER_CACHE |
Catalin Marinas | 23107c5 | 2010-03-24 16:48:53 +0100 | [diff] [blame] | 828 | select OUTER_CACHE_SYNC |
Catalin Marinas | ba92795 | 2008-04-18 22:43:17 +0100 | [diff] [blame] | 829 | help |
| 830 | This option enables the L2x0 PrimeCell. |
Eric Miao | 905a09d | 2008-06-06 16:34:03 +0800 | [diff] [blame] | 831 | |
Catalin Marinas | 9a6655e | 2010-08-31 13:05:22 +0100 | [diff] [blame] | 832 | config CACHE_PL310 |
| 833 | bool |
| 834 | depends on CACHE_L2X0 |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 835 | default y if CPU_V7 && !(CPU_V6 || CPU_V6K) |
Catalin Marinas | 9a6655e | 2010-08-31 13:05:22 +0100 | [diff] [blame] | 836 | help |
| 837 | This option enables optimisations for the PL310 cache |
| 838 | controller. |
| 839 | |
Lennert Buytenhek | 573a652 | 2009-11-24 19:33:52 +0200 | [diff] [blame] | 840 | config CACHE_TAUROS2 |
| 841 | bool "Enable the Tauros2 L2 cache controller" |
Haojian Zhuang | 3f408fa | 2010-11-24 11:54:21 +0800 | [diff] [blame] | 842 | depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) |
Lennert Buytenhek | 573a652 | 2009-11-24 19:33:52 +0200 | [diff] [blame] | 843 | default y |
| 844 | select OUTER_CACHE |
| 845 | help |
| 846 | This option enables the Tauros2 L2 cache controller (as |
| 847 | found on PJ1/PJ4). |
| 848 | |
Eric Miao | 905a09d | 2008-06-06 16:34:03 +0800 | [diff] [blame] | 849 | config CACHE_XSC3L2 |
| 850 | bool "Enable the L2 cache on XScale3" |
| 851 | depends on CPU_XSC3 |
| 852 | default y |
| 853 | select OUTER_CACHE |
| 854 | help |
| 855 | This option enables the L2 cache on XScale3. |
Kirill A. Shutemov | 910a17e | 2009-09-15 10:23:53 +0100 | [diff] [blame] | 856 | |
Russell King | 5637a12 | 2011-02-14 15:55:45 +0000 | [diff] [blame] | 857 | config ARM_L1_CACHE_SHIFT_6 |
| 858 | bool |
| 859 | help |
| 860 | Setting ARM L1 cache line size to 64 Bytes. |
| 861 | |
Kirill A. Shutemov | 910a17e | 2009-09-15 10:23:53 +0100 | [diff] [blame] | 862 | config ARM_L1_CACHE_SHIFT |
| 863 | int |
Kukjin Kim | d6d502f | 2010-02-22 00:02:59 +0100 | [diff] [blame] | 864 | default 6 if ARM_L1_CACHE_SHIFT_6 |
Kirill A. Shutemov | 910a17e | 2009-09-15 10:23:53 +0100 | [diff] [blame] | 865 | default 5 |
Russell King | 47ab0de | 2010-05-15 11:02:43 +0100 | [diff] [blame] | 866 | |
| 867 | config ARM_DMA_MEM_BUFFERABLE |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 868 | bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 |
Catalin Marinas | 42c4daf | 2010-07-01 13:22:48 +0100 | [diff] [blame] | 869 | depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ |
| 870 | MACH_REALVIEW_PB11MP) |
Russell King | e399b1a | 2011-01-17 15:08:32 +0000 | [diff] [blame] | 871 | default y if CPU_V6 || CPU_V6K || CPU_V7 |
Russell King | 47ab0de | 2010-05-15 11:02:43 +0100 | [diff] [blame] | 872 | help |
| 873 | Historically, the kernel has used strongly ordered mappings to |
| 874 | provide DMA coherent memory. With the advent of ARMv7, mapping |
| 875 | memory with differing types results in unpredictable behaviour, |
| 876 | so on these CPUs, this option is forced on. |
| 877 | |
| 878 | Multiple mappings with differing attributes is also unpredictable |
| 879 | on ARMv6 CPUs, but since they do not have aggressive speculative |
| 880 | prefetch, no harm appears to occur. |
| 881 | |
| 882 | However, drivers may be missing the necessary barriers for ARMv6, |
| 883 | and therefore turning this on may result in unpredictable driver |
| 884 | behaviour. Therefore, we offer this as an option. |
| 885 | |
| 886 | You are recommended say 'Y' here and debug any affected drivers. |
Russell King | ac1d426 | 2010-05-17 17:24:04 +0100 | [diff] [blame] | 887 | |
Catalin Marinas | e7c5650 | 2010-03-24 16:49:54 +0100 | [diff] [blame] | 888 | config ARCH_HAS_BARRIERS |
| 889 | bool |
| 890 | help |
| 891 | This option allows the use of custom mandatory barriers |
| 892 | included via the mach/barriers.h file. |