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Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -08001/*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
21
22#include <asm/io.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010023#include <mach/board.h>
24#include <mach/gpio.h>
25#include <mach/cpu.h>
David Brownellbb2d1c32007-02-20 13:58:19 -080026
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080027#include "atmel_spi.h"
28
29/*
30 * The core SPI transfer engine just talks to a register bank to set up
31 * DMA transfers; transfer queue progress is driven by IRQs. The clock
32 * framework provides the base clock, subdivided for each spi_device.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080033 */
34struct atmel_spi {
35 spinlock_t lock;
36
37 void __iomem *regs;
38 int irq;
39 struct clk *clk;
40 struct platform_device *pdev;
David Brownelldefbd3b2007-07-17 04:04:08 -070041 struct spi_device *stay;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080042
43 u8 stopping;
44 struct list_head queue;
45 struct spi_transfer *current_transfer;
Silvester Erdeg154443c2008-02-06 01:38:12 -080046 unsigned long current_remaining_bytes;
47 struct spi_transfer *next_transfer;
48 unsigned long next_remaining_bytes;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080049
50 void *buffer;
51 dma_addr_t buffer_dma;
52};
53
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -080054/* Controller-specific per-slave state */
55struct atmel_spi_device {
56 unsigned int npcs_pin;
57 u32 csr;
58};
59
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080060#define BUFFER_SIZE PAGE_SIZE
61#define INVALID_DMA_ADDRESS 0xffffffff
62
63/*
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -080064 * Version 2 of the SPI controller has
65 * - CR.LASTXFER
66 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
67 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
68 * - SPI_CSRx.CSAAT
69 * - SPI_CSRx.SBCR allows faster clocking
70 *
71 * We can determine the controller version by reading the VERSION
72 * register, but I haven't checked that it exists on all chips, and
73 * this is cheaper anyway.
74 */
75static bool atmel_spi_is_v2(void)
76{
77 return !cpu_is_at91rm9200();
78}
79
80/*
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080081 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
82 * they assume that spi slave device state will not change on deselect, so
David Brownelldefbd3b2007-07-17 04:04:08 -070083 * that automagic deselection is OK. ("NPCSx rises if no data is to be
84 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
85 * controllers have CSAAT and friends.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -080086 *
David Brownelldefbd3b2007-07-17 04:04:08 -070087 * Since the CSAAT functionality is a bit weird on newer controllers as
88 * well, we use GPIO to control nCSx pins on all controllers, updating
89 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
90 * support active-high chipselects despite the controller's belief that
91 * only active-low devices/systems exists.
92 *
93 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
94 * right when driven with GPIO. ("Mode Fault does not allow more than one
95 * Master on Chip Select 0.") No workaround exists for that ... so for
96 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
97 * and (c) will trigger that first erratum in some cases.
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -080098 *
99 * TODO: Test if the atmel_spi_is_v2() branch below works on
100 * AT91RM9200 if we use some other register than CSR0. However, don't
101 * do this unconditionally since AP7000 has an errata where the BITS
102 * field in CSR0 overrides all other CSRs.
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800103 */
104
David Brownelldefbd3b2007-07-17 04:04:08 -0700105static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800106{
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800107 struct atmel_spi_device *asd = spi->controller_state;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800108 unsigned active = spi->mode & SPI_CS_HIGH;
David Brownelldefbd3b2007-07-17 04:04:08 -0700109 u32 mr;
Atsushi Nemotof6febcc2008-02-23 15:23:39 -0800110
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800111 if (atmel_spi_is_v2()) {
112 /*
113 * Always use CSR0. This ensures that the clock
114 * switches to the correct idle polarity before we
115 * toggle the CS.
116 */
117 spi_writel(as, CSR0, asd->csr);
118 spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
119 | SPI_BIT(MSTR));
120 mr = spi_readl(as, MR);
121 gpio_set_value(asd->npcs_pin, active);
122 } else {
123 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
124 int i;
125 u32 csr;
126
127 /* Make sure clock polarity is correct */
128 for (i = 0; i < spi->master->num_chipselect; i++) {
129 csr = spi_readl(as, CSR0 + 4 * i);
130 if ((csr ^ cpol) & SPI_BIT(CPOL))
131 spi_writel(as, CSR0 + 4 * i,
132 csr ^ SPI_BIT(CPOL));
133 }
134
135 mr = spi_readl(as, MR);
136 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
137 if (spi->chip_select != 0)
138 gpio_set_value(asd->npcs_pin, active);
139 spi_writel(as, MR, mr);
Atsushi Nemotof6febcc2008-02-23 15:23:39 -0800140 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800141
David Brownelldefbd3b2007-07-17 04:04:08 -0700142 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800143 asd->npcs_pin, active ? " (high)" : "",
David Brownelldefbd3b2007-07-17 04:04:08 -0700144 mr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800145}
146
David Brownelldefbd3b2007-07-17 04:04:08 -0700147static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800148{
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800149 struct atmel_spi_device *asd = spi->controller_state;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800150 unsigned active = spi->mode & SPI_CS_HIGH;
David Brownelldefbd3b2007-07-17 04:04:08 -0700151 u32 mr;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800152
David Brownelldefbd3b2007-07-17 04:04:08 -0700153 /* only deactivate *this* device; sometimes transfers to
154 * another device may be active when this routine is called.
155 */
156 mr = spi_readl(as, MR);
157 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
158 mr = SPI_BFINS(PCS, 0xf, mr);
159 spi_writel(as, MR, mr);
160 }
161
162 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800163 asd->npcs_pin, active ? " (low)" : "",
David Brownelldefbd3b2007-07-17 04:04:08 -0700164 mr);
165
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800166 if (atmel_spi_is_v2() || spi->chip_select != 0)
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800167 gpio_set_value(asd->npcs_pin, !active);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800168}
169
Silvester Erdeg154443c2008-02-06 01:38:12 -0800170static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
171 struct spi_transfer *xfer)
172{
173 return msg->transfers.prev == &xfer->transfer_list;
174}
175
176static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
177{
178 return xfer->delay_usecs == 0 && !xfer->cs_change;
179}
180
181static void atmel_spi_next_xfer_data(struct spi_master *master,
182 struct spi_transfer *xfer,
183 dma_addr_t *tx_dma,
184 dma_addr_t *rx_dma,
185 u32 *plen)
186{
187 struct atmel_spi *as = spi_master_get_devdata(master);
188 u32 len = *plen;
189
190 /* use scratch buffer only when rx or tx data is unspecified */
191 if (xfer->rx_buf)
192 *rx_dma = xfer->rx_dma + xfer->len - len;
193 else {
194 *rx_dma = as->buffer_dma;
195 if (len > BUFFER_SIZE)
196 len = BUFFER_SIZE;
197 }
198 if (xfer->tx_buf)
199 *tx_dma = xfer->tx_dma + xfer->len - len;
200 else {
201 *tx_dma = as->buffer_dma;
202 if (len > BUFFER_SIZE)
203 len = BUFFER_SIZE;
204 memset(as->buffer, 0, len);
205 dma_sync_single_for_device(&as->pdev->dev,
206 as->buffer_dma, len, DMA_TO_DEVICE);
207 }
208
209 *plen = len;
210}
211
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800212/*
213 * Submit next transfer for DMA.
214 * lock is held, spi irq is blocked
215 */
216static void atmel_spi_next_xfer(struct spi_master *master,
217 struct spi_message *msg)
218{
219 struct atmel_spi *as = spi_master_get_devdata(master);
220 struct spi_transfer *xfer;
Gerard Kamdc329442008-08-04 13:41:12 -0700221 u32 len, remaining;
222 u32 ieval;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800223 dma_addr_t tx_dma, rx_dma;
224
Silvester Erdeg154443c2008-02-06 01:38:12 -0800225 if (!as->current_transfer)
226 xfer = list_entry(msg->transfers.next,
227 struct spi_transfer, transfer_list);
228 else if (!as->next_transfer)
229 xfer = list_entry(as->current_transfer->transfer_list.next,
230 struct spi_transfer, transfer_list);
231 else
232 xfer = NULL;
233
234 if (xfer) {
Gerard Kamdc329442008-08-04 13:41:12 -0700235 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
236
Silvester Erdeg154443c2008-02-06 01:38:12 -0800237 len = xfer->len;
238 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
239 remaining = xfer->len - len;
240
241 spi_writel(as, RPR, rx_dma);
242 spi_writel(as, TPR, tx_dma);
243
244 if (msg->spi->bits_per_word > 8)
245 len >>= 1;
246 spi_writel(as, RCR, len);
247 spi_writel(as, TCR, len);
Haavard Skinnemoen8bacb212008-02-06 01:38:13 -0800248
249 dev_dbg(&msg->spi->dev,
250 " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
251 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
252 xfer->rx_buf, xfer->rx_dma);
Silvester Erdeg154443c2008-02-06 01:38:12 -0800253 } else {
254 xfer = as->next_transfer;
255 remaining = as->next_remaining_bytes;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800256 }
257
Silvester Erdeg154443c2008-02-06 01:38:12 -0800258 as->current_transfer = xfer;
259 as->current_remaining_bytes = remaining;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800260
Silvester Erdeg154443c2008-02-06 01:38:12 -0800261 if (remaining > 0)
262 len = remaining;
Haavard Skinnemoen8bacb212008-02-06 01:38:13 -0800263 else if (!atmel_spi_xfer_is_last(msg, xfer)
264 && atmel_spi_xfer_can_be_chained(xfer)) {
Silvester Erdeg154443c2008-02-06 01:38:12 -0800265 xfer = list_entry(xfer->transfer_list.next,
266 struct spi_transfer, transfer_list);
267 len = xfer->len;
268 } else
269 xfer = NULL;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800270
Silvester Erdeg154443c2008-02-06 01:38:12 -0800271 as->next_transfer = xfer;
272
273 if (xfer) {
Gerard Kamdc329442008-08-04 13:41:12 -0700274 u32 total;
275
Silvester Erdeg154443c2008-02-06 01:38:12 -0800276 total = len;
277 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
278 as->next_remaining_bytes = total - len;
279
280 spi_writel(as, RNPR, rx_dma);
281 spi_writel(as, TNPR, tx_dma);
282
283 if (msg->spi->bits_per_word > 8)
284 len >>= 1;
285 spi_writel(as, RNCR, len);
286 spi_writel(as, TNCR, len);
Haavard Skinnemoen8bacb212008-02-06 01:38:13 -0800287
288 dev_dbg(&msg->spi->dev,
289 " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
290 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
291 xfer->rx_buf, xfer->rx_dma);
Gerard Kamdc329442008-08-04 13:41:12 -0700292 ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
Silvester Erdeg154443c2008-02-06 01:38:12 -0800293 } else {
294 spi_writel(as, RNCR, 0);
295 spi_writel(as, TNCR, 0);
Gerard Kamdc329442008-08-04 13:41:12 -0700296 ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800297 }
298
Silvester Erdeg154443c2008-02-06 01:38:12 -0800299 /* REVISIT: We're waiting for ENDRX before we start the next
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800300 * transfer because we need to handle some difficult timing
301 * issues otherwise. If we wait for ENDTX in one transfer and
302 * then starts waiting for ENDRX in the next, it's difficult
303 * to tell the difference between the ENDRX interrupt we're
304 * actually waiting for and the ENDRX interrupt of the
305 * previous transfer.
306 *
307 * It should be doable, though. Just not now...
308 */
Gerard Kamdc329442008-08-04 13:41:12 -0700309 spi_writel(as, IER, ieval);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800310 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
311}
312
313static void atmel_spi_next_message(struct spi_master *master)
314{
315 struct atmel_spi *as = spi_master_get_devdata(master);
316 struct spi_message *msg;
David Brownelldefbd3b2007-07-17 04:04:08 -0700317 struct spi_device *spi;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800318
319 BUG_ON(as->current_transfer);
320
321 msg = list_entry(as->queue.next, struct spi_message, queue);
David Brownelldefbd3b2007-07-17 04:04:08 -0700322 spi = msg->spi;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800323
Tony Jones49dce682007-10-16 01:27:48 -0700324 dev_dbg(master->dev.parent, "start message %p for %s\n",
Kay Sievers6c7377a2009-03-24 16:38:21 -0700325 msg, dev_name(&spi->dev));
David Brownelldefbd3b2007-07-17 04:04:08 -0700326
327 /* select chip if it's not still active */
328 if (as->stay) {
329 if (as->stay != spi) {
330 cs_deactivate(as, as->stay);
331 cs_activate(as, spi);
332 }
333 as->stay = NULL;
334 } else
335 cs_activate(as, spi);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800336
337 atmel_spi_next_xfer(master, msg);
338}
339
David Brownell8da08592007-07-17 04:04:07 -0700340/*
341 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
342 * - The buffer is either valid for CPU access, else NULL
343 * - If the buffer is valid, so is its DMA addresss
344 *
345 * This driver manages the dma addresss unless message->is_dma_mapped.
346 */
347static int
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800348atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
349{
David Brownell8da08592007-07-17 04:04:07 -0700350 struct device *dev = &as->pdev->dev;
351
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800352 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
David Brownell8da08592007-07-17 04:04:07 -0700353 if (xfer->tx_buf) {
354 xfer->tx_dma = dma_map_single(dev,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800355 (void *) xfer->tx_buf, xfer->len,
356 DMA_TO_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700357 if (dma_mapping_error(dev, xfer->tx_dma))
David Brownell8da08592007-07-17 04:04:07 -0700358 return -ENOMEM;
359 }
360 if (xfer->rx_buf) {
361 xfer->rx_dma = dma_map_single(dev,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800362 xfer->rx_buf, xfer->len,
363 DMA_FROM_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700364 if (dma_mapping_error(dev, xfer->rx_dma)) {
David Brownell8da08592007-07-17 04:04:07 -0700365 if (xfer->tx_buf)
366 dma_unmap_single(dev,
367 xfer->tx_dma, xfer->len,
368 DMA_TO_DEVICE);
369 return -ENOMEM;
370 }
371 }
372 return 0;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800373}
374
375static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
376 struct spi_transfer *xfer)
377{
378 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
Tony Jones49dce682007-10-16 01:27:48 -0700379 dma_unmap_single(master->dev.parent, xfer->tx_dma,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800380 xfer->len, DMA_TO_DEVICE);
381 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
Tony Jones49dce682007-10-16 01:27:48 -0700382 dma_unmap_single(master->dev.parent, xfer->rx_dma,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800383 xfer->len, DMA_FROM_DEVICE);
384}
385
386static void
387atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
David Brownelldefbd3b2007-07-17 04:04:08 -0700388 struct spi_message *msg, int status, int stay)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800389{
David Brownelldefbd3b2007-07-17 04:04:08 -0700390 if (!stay || status < 0)
391 cs_deactivate(as, msg->spi);
392 else
393 as->stay = msg->spi;
394
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800395 list_del(&msg->queue);
396 msg->status = status;
397
Tony Jones49dce682007-10-16 01:27:48 -0700398 dev_dbg(master->dev.parent,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800399 "xfer complete: %u bytes transferred\n",
400 msg->actual_length);
401
402 spin_unlock(&as->lock);
403 msg->complete(msg->context);
404 spin_lock(&as->lock);
405
406 as->current_transfer = NULL;
Silvester Erdeg154443c2008-02-06 01:38:12 -0800407 as->next_transfer = NULL;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800408
409 /* continue if needed */
410 if (list_empty(&as->queue) || as->stopping)
411 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
412 else
413 atmel_spi_next_message(master);
414}
415
416static irqreturn_t
417atmel_spi_interrupt(int irq, void *dev_id)
418{
419 struct spi_master *master = dev_id;
420 struct atmel_spi *as = spi_master_get_devdata(master);
421 struct spi_message *msg;
422 struct spi_transfer *xfer;
423 u32 status, pending, imr;
424 int ret = IRQ_NONE;
425
426 spin_lock(&as->lock);
427
428 xfer = as->current_transfer;
429 msg = list_entry(as->queue.next, struct spi_message, queue);
430
431 imr = spi_readl(as, IMR);
432 status = spi_readl(as, SR);
433 pending = status & imr;
434
435 if (pending & SPI_BIT(OVRES)) {
436 int timeout;
437
438 ret = IRQ_HANDLED;
439
Gerard Kamdc329442008-08-04 13:41:12 -0700440 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800441 | SPI_BIT(OVRES)));
442
443 /*
444 * When we get an overrun, we disregard the current
445 * transfer. Data will not be copied back from any
446 * bounce buffer and msg->actual_len will not be
447 * updated with the last xfer.
448 *
449 * We will also not process any remaning transfers in
450 * the message.
451 *
452 * First, stop the transfer and unmap the DMA buffers.
453 */
454 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
455 if (!msg->is_dma_mapped)
456 atmel_spi_dma_unmap_xfer(master, xfer);
457
458 /* REVISIT: udelay in irq is unfriendly */
459 if (xfer->delay_usecs)
460 udelay(xfer->delay_usecs);
461
Gerard Kamdc329442008-08-04 13:41:12 -0700462 dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800463 spi_readl(as, TCR), spi_readl(as, RCR));
464
465 /*
466 * Clean up DMA registers and make sure the data
467 * registers are empty.
468 */
469 spi_writel(as, RNCR, 0);
470 spi_writel(as, TNCR, 0);
471 spi_writel(as, RCR, 0);
472 spi_writel(as, TCR, 0);
473 for (timeout = 1000; timeout; timeout--)
474 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
475 break;
476 if (!timeout)
Tony Jones49dce682007-10-16 01:27:48 -0700477 dev_warn(master->dev.parent,
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800478 "timeout waiting for TXEMPTY");
479 while (spi_readl(as, SR) & SPI_BIT(RDRF))
480 spi_readl(as, RDR);
481
482 /* Clear any overrun happening while cleaning up */
483 spi_readl(as, SR);
484
David Brownelldefbd3b2007-07-17 04:04:08 -0700485 atmel_spi_msg_done(master, as, msg, -EIO, 0);
Gerard Kamdc329442008-08-04 13:41:12 -0700486 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800487 ret = IRQ_HANDLED;
488
489 spi_writel(as, IDR, pending);
490
Silvester Erdeg154443c2008-02-06 01:38:12 -0800491 if (as->current_remaining_bytes == 0) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800492 msg->actual_length += xfer->len;
493
494 if (!msg->is_dma_mapped)
495 atmel_spi_dma_unmap_xfer(master, xfer);
496
497 /* REVISIT: udelay in irq is unfriendly */
498 if (xfer->delay_usecs)
499 udelay(xfer->delay_usecs);
500
Silvester Erdeg154443c2008-02-06 01:38:12 -0800501 if (atmel_spi_xfer_is_last(msg, xfer)) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800502 /* report completed message */
David Brownelldefbd3b2007-07-17 04:04:08 -0700503 atmel_spi_msg_done(master, as, msg, 0,
504 xfer->cs_change);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800505 } else {
506 if (xfer->cs_change) {
David Brownelldefbd3b2007-07-17 04:04:08 -0700507 cs_deactivate(as, msg->spi);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800508 udelay(1);
David Brownelldefbd3b2007-07-17 04:04:08 -0700509 cs_activate(as, msg->spi);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800510 }
511
512 /*
513 * Not done yet. Submit the next transfer.
514 *
515 * FIXME handle protocol options for xfer
516 */
517 atmel_spi_next_xfer(master, msg);
518 }
519 } else {
520 /*
521 * Keep going, we still have data to send in
522 * the current transfer.
523 */
524 atmel_spi_next_xfer(master, msg);
525 }
526 }
527
528 spin_unlock(&as->lock);
529
530 return ret;
531}
532
David Brownelldccd5732007-07-17 04:04:02 -0700533/* the spi->mode bits understood by this driver: */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800534#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
535
536static int atmel_spi_setup(struct spi_device *spi)
537{
538 struct atmel_spi *as;
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800539 struct atmel_spi_device *asd;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800540 u32 scbr, csr;
541 unsigned int bits = spi->bits_per_word;
Haavard Skinnemoen592e7bf2008-04-30 00:52:17 -0700542 unsigned long bus_hz;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800543 unsigned int npcs_pin;
544 int ret;
545
546 as = spi_master_get_devdata(spi->master);
547
548 if (as->stopping)
549 return -ESHUTDOWN;
550
551 if (spi->chip_select > spi->master->num_chipselect) {
552 dev_dbg(&spi->dev,
553 "setup: invalid chipselect %u (%u defined)\n",
554 spi->chip_select, spi->master->num_chipselect);
555 return -EINVAL;
556 }
557
558 if (bits == 0)
559 bits = 8;
560 if (bits < 8 || bits > 16) {
561 dev_dbg(&spi->dev,
562 "setup: invalid bits_per_word %u (8 to 16)\n",
563 bits);
564 return -EINVAL;
565 }
566
567 if (spi->mode & ~MODEBITS) {
568 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
569 spi->mode & ~MODEBITS);
570 return -EINVAL;
571 }
572
David Brownelldefbd3b2007-07-17 04:04:08 -0700573 /* see notes above re chipselect */
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800574 if (!atmel_spi_is_v2()
David Brownelldefbd3b2007-07-17 04:04:08 -0700575 && spi->chip_select == 0
576 && (spi->mode & SPI_CS_HIGH)) {
577 dev_dbg(&spi->dev, "setup: can't be active-high\n");
578 return -EINVAL;
579 }
580
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800581 /* v1 chips start out at half the peripheral bus speed. */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800582 bus_hz = clk_get_rate(as->clk);
Haavard Skinnemoen5bfa26c2009-01-06 14:41:42 -0800583 if (!atmel_spi_is_v2())
Haavard Skinnemoen592e7bf2008-04-30 00:52:17 -0700584 bus_hz /= 2;
585
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800586 if (spi->max_speed_hz) {
Haavard Skinnemoen592e7bf2008-04-30 00:52:17 -0700587 /*
588 * Calculate the lowest divider that satisfies the
589 * constraint, assuming div32/fdiv/mbz == 0.
590 */
591 scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
592
593 /*
594 * If the resulting divider doesn't fit into the
595 * register bitfield, we can't satisfy the constraint.
596 */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800597 if (scbr >= (1 << SPI_SCBR_SIZE)) {
David Brownell8da08592007-07-17 04:04:07 -0700598 dev_dbg(&spi->dev,
599 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
600 spi->max_speed_hz, scbr, bus_hz/255);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800601 return -EINVAL;
602 }
603 } else
Haavard Skinnemoen592e7bf2008-04-30 00:52:17 -0700604 /* speed zero means "as slow as possible" */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800605 scbr = 0xff;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800606
607 csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
608 if (spi->mode & SPI_CPOL)
609 csr |= SPI_BIT(CPOL);
610 if (!(spi->mode & SPI_CPHA))
611 csr |= SPI_BIT(NCPHA);
612
Haavard Skinnemoen1eed29d2008-02-06 01:38:11 -0800613 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
614 *
615 * DLYBCT would add delays between words, slowing down transfers.
616 * It could potentially be useful to cope with DMA bottlenecks, but
617 * in those cases it's probably best to just use a lower bitrate.
618 */
619 csr |= SPI_BF(DLYBS, 0);
620 csr |= SPI_BF(DLYBCT, 0);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800621
622 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
623 npcs_pin = (unsigned int)spi->controller_data;
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800624 asd = spi->controller_state;
625 if (!asd) {
626 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
627 if (!asd)
628 return -ENOMEM;
629
Kay Sievers6c7377a2009-03-24 16:38:21 -0700630 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800631 if (ret) {
632 kfree(asd);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800633 return ret;
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800634 }
635
636 asd->npcs_pin = npcs_pin;
637 spi->controller_state = asd;
David Brownell28735a72007-03-16 13:38:14 -0800638 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
David Brownelldefbd3b2007-07-17 04:04:08 -0700639 } else {
640 unsigned long flags;
641
642 spin_lock_irqsave(&as->lock, flags);
643 if (as->stay == spi)
644 as->stay = NULL;
645 cs_deactivate(as, spi);
646 spin_unlock_irqrestore(&as->lock, flags);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800647 }
648
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800649 asd->csr = csr;
650
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800651 dev_dbg(&spi->dev,
652 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
Haavard Skinnemoen592e7bf2008-04-30 00:52:17 -0700653 bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800654
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800655 if (!atmel_spi_is_v2())
656 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800657
658 return 0;
659}
660
661static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
662{
663 struct atmel_spi *as;
664 struct spi_transfer *xfer;
665 unsigned long flags;
Tony Jones49dce682007-10-16 01:27:48 -0700666 struct device *controller = spi->master->dev.parent;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800667
668 as = spi_master_get_devdata(spi->master);
669
670 dev_dbg(controller, "new message %p submitted for %s\n",
Kay Sievers6c7377a2009-03-24 16:38:21 -0700671 msg, dev_name(&spi->dev));
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800672
Stanislaw Gruszka5b96f172009-01-15 13:50:44 -0800673 if (unlikely(list_empty(&msg->transfers)))
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800674 return -EINVAL;
675
676 if (as->stopping)
677 return -ESHUTDOWN;
678
679 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
Atsushi Nemoto06719812008-04-28 02:14:19 -0700680 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800681 dev_dbg(&spi->dev, "missing rx or tx buf\n");
682 return -EINVAL;
683 }
684
685 /* FIXME implement these protocol options!! */
686 if (xfer->bits_per_word || xfer->speed_hz) {
687 dev_dbg(&spi->dev, "no protocol options yet\n");
688 return -ENOPROTOOPT;
689 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800690
David Brownell8da08592007-07-17 04:04:07 -0700691 /*
692 * DMA map early, for performance (empties dcache ASAP) and
693 * better fault reporting. This is a DMA-only driver.
694 *
695 * NOTE that if dma_unmap_single() ever starts to do work on
696 * platforms supported by this driver, we would need to clean
697 * up mappings for previously-mapped transfers.
698 */
699 if (!msg->is_dma_mapped) {
700 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
701 return -ENOMEM;
702 }
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800703 }
704
David Brownelldefbd3b2007-07-17 04:04:08 -0700705#ifdef VERBOSE
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800706 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
707 dev_dbg(controller,
708 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
709 xfer, xfer->len,
710 xfer->tx_buf, xfer->tx_dma,
711 xfer->rx_buf, xfer->rx_dma);
712 }
David Brownelldefbd3b2007-07-17 04:04:08 -0700713#endif
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800714
715 msg->status = -EINPROGRESS;
716 msg->actual_length = 0;
717
718 spin_lock_irqsave(&as->lock, flags);
719 list_add_tail(&msg->queue, &as->queue);
720 if (!as->current_transfer)
721 atmel_spi_next_message(spi->master);
722 spin_unlock_irqrestore(&as->lock, flags);
723
724 return 0;
725}
726
David Brownellbb2d1c32007-02-20 13:58:19 -0800727static void atmel_spi_cleanup(struct spi_device *spi)
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800728{
David Brownelldefbd3b2007-07-17 04:04:08 -0700729 struct atmel_spi *as = spi_master_get_devdata(spi->master);
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800730 struct atmel_spi_device *asd = spi->controller_state;
David Brownelldefbd3b2007-07-17 04:04:08 -0700731 unsigned gpio = (unsigned) spi->controller_data;
732 unsigned long flags;
733
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800734 if (!asd)
David Brownelldefbd3b2007-07-17 04:04:08 -0700735 return;
736
737 spin_lock_irqsave(&as->lock, flags);
738 if (as->stay == spi) {
739 as->stay = NULL;
740 cs_deactivate(as, spi);
741 }
742 spin_unlock_irqrestore(&as->lock, flags);
743
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800744 spi->controller_state = NULL;
David Brownelldefbd3b2007-07-17 04:04:08 -0700745 gpio_free(gpio);
Haavard Skinnemoen5ee36c92009-01-06 14:41:43 -0800746 kfree(asd);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800747}
748
749/*-------------------------------------------------------------------------*/
750
751static int __init atmel_spi_probe(struct platform_device *pdev)
752{
753 struct resource *regs;
754 int irq;
755 struct clk *clk;
756 int ret;
757 struct spi_master *master;
758 struct atmel_spi *as;
759
760 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
761 if (!regs)
762 return -ENXIO;
763
764 irq = platform_get_irq(pdev, 0);
765 if (irq < 0)
766 return irq;
767
768 clk = clk_get(&pdev->dev, "spi_clk");
769 if (IS_ERR(clk))
770 return PTR_ERR(clk);
771
772 /* setup spi core then atmel-specific driver state */
773 ret = -ENOMEM;
774 master = spi_alloc_master(&pdev->dev, sizeof *as);
775 if (!master)
776 goto out_free;
777
778 master->bus_num = pdev->id;
779 master->num_chipselect = 4;
780 master->setup = atmel_spi_setup;
781 master->transfer = atmel_spi_transfer;
782 master->cleanup = atmel_spi_cleanup;
783 platform_set_drvdata(pdev, master);
784
785 as = spi_master_get_devdata(master);
786
David Brownell8da08592007-07-17 04:04:07 -0700787 /*
788 * Scratch buffer is used for throwaway rx and tx data.
789 * It's coherent to minimize dcache pollution.
790 */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800791 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
792 &as->buffer_dma, GFP_KERNEL);
793 if (!as->buffer)
794 goto out_free;
795
796 spin_lock_init(&as->lock);
797 INIT_LIST_HEAD(&as->queue);
798 as->pdev = pdev;
799 as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
800 if (!as->regs)
801 goto out_free_buffer;
802 as->irq = irq;
803 as->clk = clk;
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800804
805 ret = request_irq(irq, atmel_spi_interrupt, 0,
Kay Sievers6c7377a2009-03-24 16:38:21 -0700806 dev_name(&pdev->dev), master);
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800807 if (ret)
808 goto out_unmap_regs;
809
810 /* Initialize the hardware */
811 clk_enable(clk);
812 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -0800813 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800814 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
815 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
816 spi_writel(as, CR, SPI_BIT(SPIEN));
817
818 /* go! */
819 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
820 (unsigned long)regs->start, irq);
821
822 ret = spi_register_master(master);
823 if (ret)
824 goto out_reset_hw;
825
826 return 0;
827
828out_reset_hw:
829 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -0800830 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800831 clk_disable(clk);
832 free_irq(irq, master);
833out_unmap_regs:
834 iounmap(as->regs);
835out_free_buffer:
836 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
837 as->buffer_dma);
838out_free:
839 clk_put(clk);
840 spi_master_put(master);
841 return ret;
842}
843
844static int __exit atmel_spi_remove(struct platform_device *pdev)
845{
846 struct spi_master *master = platform_get_drvdata(pdev);
847 struct atmel_spi *as = spi_master_get_devdata(master);
848 struct spi_message *msg;
849
850 /* reset the hardware and block queue progress */
851 spin_lock_irq(&as->lock);
852 as->stopping = 1;
853 spi_writel(as, CR, SPI_BIT(SWRST));
Jean-Christophe Lallemand50d7d5b2008-11-12 13:27:00 -0800854 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
Haavard Skinnemoen754ce4f2007-02-14 00:33:09 -0800855 spi_readl(as, SR);
856 spin_unlock_irq(&as->lock);
857
858 /* Terminate remaining queued transfers */
859 list_for_each_entry(msg, &as->queue, queue) {
860 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
861 * but we shouldn't depend on that...
862 */
863 msg->status = -ESHUTDOWN;
864 msg->complete(msg->context);
865 }
866
867 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
868 as->buffer_dma);
869
870 clk_disable(as->clk);
871 clk_put(as->clk);
872 free_irq(as->irq, master);
873 iounmap(as->regs);
874
875 spi_unregister_master(master);
876
877 return 0;
878}
879
880#ifdef CONFIG_PM
881
882static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
883{
884 struct spi_master *master = platform_get_drvdata(pdev);
885 struct atmel_spi *as = spi_master_get_devdata(master);
886
887 clk_disable(as->clk);
888 return 0;
889}
890
891static int atmel_spi_resume(struct platform_device *pdev)
892{
893 struct spi_master *master = platform_get_drvdata(pdev);
894 struct atmel_spi *as = spi_master_get_devdata(master);
895
896 clk_enable(as->clk);
897 return 0;
898}
899
900#else
901#define atmel_spi_suspend NULL
902#define atmel_spi_resume NULL
903#endif
904
905
906static struct platform_driver atmel_spi_driver = {
907 .driver = {
908 .name = "atmel_spi",
909 .owner = THIS_MODULE,
910 },
911 .suspend = atmel_spi_suspend,
912 .resume = atmel_spi_resume,
913 .remove = __exit_p(atmel_spi_remove),
914};
915
916static int __init atmel_spi_init(void)
917{
918 return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
919}
920module_init(atmel_spi_init);
921
922static void __exit atmel_spi_exit(void)
923{
924 platform_driver_unregister(&atmel_spi_driver);
925}
926module_exit(atmel_spi_exit);
927
928MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
929MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
930MODULE_LICENSE("GPL");
Kay Sievers7e38c3c2008-04-10 21:29:20 -0700931MODULE_ALIAS("platform:atmel_spi");