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Marc Zyngiercc2d3212014-11-24 14:35:11 +00001/*
2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/bitmap.h>
19#include <linux/cpu.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/log2.h>
23#include <linux/mm.h>
24#include <linux/msi.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/of_irq.h>
28#include <linux/of_pci.h>
29#include <linux/of_platform.h>
30#include <linux/percpu.h>
31#include <linux/slab.h>
32
Joel Porquet41a83e02015-07-07 17:11:46 -040033#include <linux/irqchip.h>
Marc Zyngiercc2d3212014-11-24 14:35:11 +000034#include <linux/irqchip/arm-gic-v3.h>
35
36#include <asm/cacheflush.h>
37#include <asm/cputype.h>
38#include <asm/exception.h>
39
Marc Zyngiercc2d3212014-11-24 14:35:11 +000040#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1 << 0)
41
Marc Zyngierc48ed512014-11-24 14:35:12 +000042#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
43
Marc Zyngiercc2d3212014-11-24 14:35:11 +000044/*
45 * Collection structure - just an ID, and a redistributor address to
46 * ping. We use one per CPU as a bag of interrupts assigned to this
47 * CPU.
48 */
49struct its_collection {
50 u64 target_address;
51 u16 col_id;
52};
53
54/*
55 * The ITS structure - contains most of the infrastructure, with the
Marc Zyngier841514a2015-07-28 14:46:20 +010056 * top-level MSI domain, the command queue, the collections, and the
57 * list of devices writing to it.
Marc Zyngiercc2d3212014-11-24 14:35:11 +000058 */
59struct its_node {
60 raw_spinlock_t lock;
61 struct list_head entry;
Marc Zyngiercc2d3212014-11-24 14:35:11 +000062 void __iomem *base;
63 unsigned long phys_base;
64 struct its_cmd_block *cmd_base;
65 struct its_cmd_block *cmd_write;
66 void *tables[GITS_BASER_NR_REGS];
67 struct its_collection *collections;
68 struct list_head its_device_list;
69 u64 flags;
70 u32 ite_size;
71};
72
73#define ITS_ITT_ALIGN SZ_256
74
Marc Zyngier591e5be2015-07-17 10:46:42 +010075struct event_lpi_map {
76 unsigned long *lpi_map;
77 u16 *col_map;
78 irq_hw_number_t lpi_base;
79 int nr_lpis;
80};
81
Marc Zyngiercc2d3212014-11-24 14:35:11 +000082/*
83 * The ITS view of a device - belongs to an ITS, a collection, owns an
84 * interrupt translation table, and a list of interrupts.
85 */
86struct its_device {
87 struct list_head entry;
88 struct its_node *its;
Marc Zyngier591e5be2015-07-17 10:46:42 +010089 struct event_lpi_map event_map;
Marc Zyngiercc2d3212014-11-24 14:35:11 +000090 void *itt;
Marc Zyngiercc2d3212014-11-24 14:35:11 +000091 u32 nr_ites;
92 u32 device_id;
93};
94
Marc Zyngier1ac19ca2014-11-24 14:35:14 +000095static LIST_HEAD(its_nodes);
96static DEFINE_SPINLOCK(its_lock);
97static struct device_node *gic_root_node;
98static struct rdists *gic_rdists;
99
100#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
101#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
102
Marc Zyngier591e5be2015-07-17 10:46:42 +0100103static struct its_collection *dev_event_to_col(struct its_device *its_dev,
104 u32 event)
105{
106 struct its_node *its = its_dev->its;
107
108 return its->collections + its_dev->event_map.col_map[event];
109}
110
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000111/*
112 * ITS command descriptors - parameters to be encoded in a command
113 * block.
114 */
115struct its_cmd_desc {
116 union {
117 struct {
118 struct its_device *dev;
119 u32 event_id;
120 } its_inv_cmd;
121
122 struct {
123 struct its_device *dev;
124 u32 event_id;
125 } its_int_cmd;
126
127 struct {
128 struct its_device *dev;
129 int valid;
130 } its_mapd_cmd;
131
132 struct {
133 struct its_collection *col;
134 int valid;
135 } its_mapc_cmd;
136
137 struct {
138 struct its_device *dev;
139 u32 phys_id;
140 u32 event_id;
141 } its_mapvi_cmd;
142
143 struct {
144 struct its_device *dev;
145 struct its_collection *col;
Marc Zyngier591e5be2015-07-17 10:46:42 +0100146 u32 event_id;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000147 } its_movi_cmd;
148
149 struct {
150 struct its_device *dev;
151 u32 event_id;
152 } its_discard_cmd;
153
154 struct {
155 struct its_collection *col;
156 } its_invall_cmd;
157 };
158};
159
160/*
161 * The ITS command block, which is what the ITS actually parses.
162 */
163struct its_cmd_block {
164 u64 raw_cmd[4];
165};
166
167#define ITS_CMD_QUEUE_SZ SZ_64K
168#define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
169
170typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
171 struct its_cmd_desc *);
172
173static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
174{
175 cmd->raw_cmd[0] &= ~0xffUL;
176 cmd->raw_cmd[0] |= cmd_nr;
177}
178
179static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
180{
Andre Przywara7e195ba2015-03-27 14:15:03 +0000181 cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000182 cmd->raw_cmd[0] |= ((u64)devid) << 32;
183}
184
185static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
186{
187 cmd->raw_cmd[1] &= ~0xffffffffUL;
188 cmd->raw_cmd[1] |= id;
189}
190
191static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
192{
193 cmd->raw_cmd[1] &= 0xffffffffUL;
194 cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
195}
196
197static void its_encode_size(struct its_cmd_block *cmd, u8 size)
198{
199 cmd->raw_cmd[1] &= ~0x1fUL;
200 cmd->raw_cmd[1] |= size & 0x1f;
201}
202
203static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
204{
205 cmd->raw_cmd[2] &= ~0xffffffffffffUL;
206 cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
207}
208
209static void its_encode_valid(struct its_cmd_block *cmd, int valid)
210{
211 cmd->raw_cmd[2] &= ~(1UL << 63);
212 cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
213}
214
215static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
216{
217 cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
218 cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
219}
220
221static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
222{
223 cmd->raw_cmd[2] &= ~0xffffUL;
224 cmd->raw_cmd[2] |= col;
225}
226
227static inline void its_fixup_cmd(struct its_cmd_block *cmd)
228{
229 /* Let's fixup BE commands */
230 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
231 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
232 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
233 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
234}
235
236static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd,
237 struct its_cmd_desc *desc)
238{
239 unsigned long itt_addr;
Marc Zyngierc8481262014-12-12 10:51:24 +0000240 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000241
242 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
243 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
244
245 its_encode_cmd(cmd, GITS_CMD_MAPD);
246 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
247 its_encode_size(cmd, size - 1);
248 its_encode_itt(cmd, itt_addr);
249 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
250
251 its_fixup_cmd(cmd);
252
Marc Zyngier591e5be2015-07-17 10:46:42 +0100253 return NULL;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000254}
255
256static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
257 struct its_cmd_desc *desc)
258{
259 its_encode_cmd(cmd, GITS_CMD_MAPC);
260 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
261 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
262 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
263
264 its_fixup_cmd(cmd);
265
266 return desc->its_mapc_cmd.col;
267}
268
269static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
270 struct its_cmd_desc *desc)
271{
Marc Zyngier591e5be2015-07-17 10:46:42 +0100272 struct its_collection *col;
273
274 col = dev_event_to_col(desc->its_mapvi_cmd.dev,
275 desc->its_mapvi_cmd.event_id);
276
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000277 its_encode_cmd(cmd, GITS_CMD_MAPVI);
278 its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
279 its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
280 its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
Marc Zyngier591e5be2015-07-17 10:46:42 +0100281 its_encode_collection(cmd, col->col_id);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000282
283 its_fixup_cmd(cmd);
284
Marc Zyngier591e5be2015-07-17 10:46:42 +0100285 return col;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000286}
287
288static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd,
289 struct its_cmd_desc *desc)
290{
Marc Zyngier591e5be2015-07-17 10:46:42 +0100291 struct its_collection *col;
292
293 col = dev_event_to_col(desc->its_movi_cmd.dev,
294 desc->its_movi_cmd.event_id);
295
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000296 its_encode_cmd(cmd, GITS_CMD_MOVI);
297 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
Marc Zyngier591e5be2015-07-17 10:46:42 +0100298 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000299 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
300
301 its_fixup_cmd(cmd);
302
Marc Zyngier591e5be2015-07-17 10:46:42 +0100303 return col;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000304}
305
306static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd,
307 struct its_cmd_desc *desc)
308{
Marc Zyngier591e5be2015-07-17 10:46:42 +0100309 struct its_collection *col;
310
311 col = dev_event_to_col(desc->its_discard_cmd.dev,
312 desc->its_discard_cmd.event_id);
313
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000314 its_encode_cmd(cmd, GITS_CMD_DISCARD);
315 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
316 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
317
318 its_fixup_cmd(cmd);
319
Marc Zyngier591e5be2015-07-17 10:46:42 +0100320 return col;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000321}
322
323static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd,
324 struct its_cmd_desc *desc)
325{
Marc Zyngier591e5be2015-07-17 10:46:42 +0100326 struct its_collection *col;
327
328 col = dev_event_to_col(desc->its_inv_cmd.dev,
329 desc->its_inv_cmd.event_id);
330
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000331 its_encode_cmd(cmd, GITS_CMD_INV);
332 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
333 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
334
335 its_fixup_cmd(cmd);
336
Marc Zyngier591e5be2015-07-17 10:46:42 +0100337 return col;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000338}
339
340static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
341 struct its_cmd_desc *desc)
342{
343 its_encode_cmd(cmd, GITS_CMD_INVALL);
344 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
345
346 its_fixup_cmd(cmd);
347
348 return NULL;
349}
350
351static u64 its_cmd_ptr_to_offset(struct its_node *its,
352 struct its_cmd_block *ptr)
353{
354 return (ptr - its->cmd_base) * sizeof(*ptr);
355}
356
357static int its_queue_full(struct its_node *its)
358{
359 int widx;
360 int ridx;
361
362 widx = its->cmd_write - its->cmd_base;
363 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
364
365 /* This is incredibly unlikely to happen, unless the ITS locks up. */
366 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
367 return 1;
368
369 return 0;
370}
371
372static struct its_cmd_block *its_allocate_entry(struct its_node *its)
373{
374 struct its_cmd_block *cmd;
375 u32 count = 1000000; /* 1s! */
376
377 while (its_queue_full(its)) {
378 count--;
379 if (!count) {
380 pr_err_ratelimited("ITS queue not draining\n");
381 return NULL;
382 }
383 cpu_relax();
384 udelay(1);
385 }
386
387 cmd = its->cmd_write++;
388
389 /* Handle queue wrapping */
390 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
391 its->cmd_write = its->cmd_base;
392
393 return cmd;
394}
395
396static struct its_cmd_block *its_post_commands(struct its_node *its)
397{
398 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
399
400 writel_relaxed(wr, its->base + GITS_CWRITER);
401
402 return its->cmd_write;
403}
404
405static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
406{
407 /*
408 * Make sure the commands written to memory are observable by
409 * the ITS.
410 */
411 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
412 __flush_dcache_area(cmd, sizeof(*cmd));
413 else
414 dsb(ishst);
415}
416
417static void its_wait_for_range_completion(struct its_node *its,
418 struct its_cmd_block *from,
419 struct its_cmd_block *to)
420{
421 u64 rd_idx, from_idx, to_idx;
422 u32 count = 1000000; /* 1s! */
423
424 from_idx = its_cmd_ptr_to_offset(its, from);
425 to_idx = its_cmd_ptr_to_offset(its, to);
426
427 while (1) {
428 rd_idx = readl_relaxed(its->base + GITS_CREADR);
429 if (rd_idx >= to_idx || rd_idx < from_idx)
430 break;
431
432 count--;
433 if (!count) {
434 pr_err_ratelimited("ITS queue timeout\n");
435 return;
436 }
437 cpu_relax();
438 udelay(1);
439 }
440}
441
442static void its_send_single_command(struct its_node *its,
443 its_cmd_builder_t builder,
444 struct its_cmd_desc *desc)
445{
446 struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
447 struct its_collection *sync_col;
Marc Zyngier3e39e8f52015-03-06 16:37:43 +0000448 unsigned long flags;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000449
Marc Zyngier3e39e8f52015-03-06 16:37:43 +0000450 raw_spin_lock_irqsave(&its->lock, flags);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000451
452 cmd = its_allocate_entry(its);
453 if (!cmd) { /* We're soooooo screewed... */
454 pr_err_ratelimited("ITS can't allocate, dropping command\n");
Marc Zyngier3e39e8f52015-03-06 16:37:43 +0000455 raw_spin_unlock_irqrestore(&its->lock, flags);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000456 return;
457 }
458 sync_col = builder(cmd, desc);
459 its_flush_cmd(its, cmd);
460
461 if (sync_col) {
462 sync_cmd = its_allocate_entry(its);
463 if (!sync_cmd) {
464 pr_err_ratelimited("ITS can't SYNC, skipping\n");
465 goto post;
466 }
467 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
468 its_encode_target(sync_cmd, sync_col->target_address);
469 its_fixup_cmd(sync_cmd);
470 its_flush_cmd(its, sync_cmd);
471 }
472
473post:
474 next_cmd = its_post_commands(its);
Marc Zyngier3e39e8f52015-03-06 16:37:43 +0000475 raw_spin_unlock_irqrestore(&its->lock, flags);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000476
477 its_wait_for_range_completion(its, cmd, next_cmd);
478}
479
480static void its_send_inv(struct its_device *dev, u32 event_id)
481{
482 struct its_cmd_desc desc;
483
484 desc.its_inv_cmd.dev = dev;
485 desc.its_inv_cmd.event_id = event_id;
486
487 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
488}
489
490static void its_send_mapd(struct its_device *dev, int valid)
491{
492 struct its_cmd_desc desc;
493
494 desc.its_mapd_cmd.dev = dev;
495 desc.its_mapd_cmd.valid = !!valid;
496
497 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
498}
499
500static void its_send_mapc(struct its_node *its, struct its_collection *col,
501 int valid)
502{
503 struct its_cmd_desc desc;
504
505 desc.its_mapc_cmd.col = col;
506 desc.its_mapc_cmd.valid = !!valid;
507
508 its_send_single_command(its, its_build_mapc_cmd, &desc);
509}
510
511static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id)
512{
513 struct its_cmd_desc desc;
514
515 desc.its_mapvi_cmd.dev = dev;
516 desc.its_mapvi_cmd.phys_id = irq_id;
517 desc.its_mapvi_cmd.event_id = id;
518
519 its_send_single_command(dev->its, its_build_mapvi_cmd, &desc);
520}
521
522static void its_send_movi(struct its_device *dev,
523 struct its_collection *col, u32 id)
524{
525 struct its_cmd_desc desc;
526
527 desc.its_movi_cmd.dev = dev;
528 desc.its_movi_cmd.col = col;
Marc Zyngier591e5be2015-07-17 10:46:42 +0100529 desc.its_movi_cmd.event_id = id;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000530
531 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
532}
533
534static void its_send_discard(struct its_device *dev, u32 id)
535{
536 struct its_cmd_desc desc;
537
538 desc.its_discard_cmd.dev = dev;
539 desc.its_discard_cmd.event_id = id;
540
541 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
542}
543
544static void its_send_invall(struct its_node *its, struct its_collection *col)
545{
546 struct its_cmd_desc desc;
547
548 desc.its_invall_cmd.col = col;
549
550 its_send_single_command(its, its_build_invall_cmd, &desc);
551}
Marc Zyngierc48ed512014-11-24 14:35:12 +0000552
553/*
554 * irqchip functions - assumes MSI, mostly.
555 */
556
557static inline u32 its_get_event_id(struct irq_data *d)
558{
559 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
Marc Zyngier591e5be2015-07-17 10:46:42 +0100560 return d->hwirq - its_dev->event_map.lpi_base;
Marc Zyngierc48ed512014-11-24 14:35:12 +0000561}
562
563static void lpi_set_config(struct irq_data *d, bool enable)
564{
565 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
566 irq_hw_number_t hwirq = d->hwirq;
567 u32 id = its_get_event_id(d);
568 u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192;
569
570 if (enable)
571 *cfg |= LPI_PROP_ENABLED;
572 else
573 *cfg &= ~LPI_PROP_ENABLED;
574
575 /*
576 * Make the above write visible to the redistributors.
577 * And yes, we're flushing exactly: One. Single. Byte.
578 * Humpf...
579 */
580 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
581 __flush_dcache_area(cfg, sizeof(*cfg));
582 else
583 dsb(ishst);
584 its_send_inv(its_dev, id);
585}
586
587static void its_mask_irq(struct irq_data *d)
588{
589 lpi_set_config(d, false);
590}
591
592static void its_unmask_irq(struct irq_data *d)
593{
594 lpi_set_config(d, true);
595}
596
597static void its_eoi_irq(struct irq_data *d)
598{
599 gic_write_eoir(d->hwirq);
600}
601
602static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
603 bool force)
604{
605 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
606 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
607 struct its_collection *target_col;
608 u32 id = its_get_event_id(d);
609
610 if (cpu >= nr_cpu_ids)
611 return -EINVAL;
612
613 target_col = &its_dev->its->collections[cpu];
614 its_send_movi(its_dev, target_col, id);
Marc Zyngier591e5be2015-07-17 10:46:42 +0100615 its_dev->event_map.col_map[id] = cpu;
Marc Zyngierc48ed512014-11-24 14:35:12 +0000616
617 return IRQ_SET_MASK_OK_DONE;
618}
619
Marc Zyngierb48ac832014-11-24 14:35:16 +0000620static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
621{
622 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
623 struct its_node *its;
624 u64 addr;
625
626 its = its_dev->its;
627 addr = its->phys_base + GITS_TRANSLATER;
628
629 msg->address_lo = addr & ((1UL << 32) - 1);
630 msg->address_hi = addr >> 32;
631 msg->data = its_get_event_id(d);
632}
633
Marc Zyngierc48ed512014-11-24 14:35:12 +0000634static struct irq_chip its_irq_chip = {
635 .name = "ITS",
636 .irq_mask = its_mask_irq,
637 .irq_unmask = its_unmask_irq,
638 .irq_eoi = its_eoi_irq,
639 .irq_set_affinity = its_set_affinity,
Marc Zyngierb48ac832014-11-24 14:35:16 +0000640 .irq_compose_msi_msg = its_irq_compose_msi_msg,
641};
642
Marc Zyngierbf9529f2014-11-24 14:35:13 +0000643/*
644 * How we allocate LPIs:
645 *
646 * The GIC has id_bits bits for interrupt identifiers. From there, we
647 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
648 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
649 * bits to the right.
650 *
651 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
652 */
653#define IRQS_PER_CHUNK_SHIFT 5
654#define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT)
655
656static unsigned long *lpi_bitmap;
657static u32 lpi_chunks;
658static DEFINE_SPINLOCK(lpi_lock);
659
660static int its_lpi_to_chunk(int lpi)
661{
662 return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
663}
664
665static int its_chunk_to_lpi(int chunk)
666{
667 return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
668}
669
670static int its_lpi_init(u32 id_bits)
671{
672 lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
673
674 lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
675 GFP_KERNEL);
676 if (!lpi_bitmap) {
677 lpi_chunks = 0;
678 return -ENOMEM;
679 }
680
681 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
682 return 0;
683}
684
685static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
686{
687 unsigned long *bitmap = NULL;
688 int chunk_id;
689 int nr_chunks;
690 int i;
691
692 nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
693
694 spin_lock(&lpi_lock);
695
696 do {
697 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
698 0, nr_chunks, 0);
699 if (chunk_id < lpi_chunks)
700 break;
701
702 nr_chunks--;
703 } while (nr_chunks > 0);
704
705 if (!nr_chunks)
706 goto out;
707
708 bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
709 GFP_ATOMIC);
710 if (!bitmap)
711 goto out;
712
713 for (i = 0; i < nr_chunks; i++)
714 set_bit(chunk_id + i, lpi_bitmap);
715
716 *base = its_chunk_to_lpi(chunk_id);
717 *nr_ids = nr_chunks * IRQS_PER_CHUNK;
718
719out:
720 spin_unlock(&lpi_lock);
721
722 return bitmap;
723}
724
Marc Zyngier591e5be2015-07-17 10:46:42 +0100725static void its_lpi_free(struct event_lpi_map *map)
Marc Zyngierbf9529f2014-11-24 14:35:13 +0000726{
Marc Zyngier591e5be2015-07-17 10:46:42 +0100727 int base = map->lpi_base;
728 int nr_ids = map->nr_lpis;
Marc Zyngierbf9529f2014-11-24 14:35:13 +0000729 int lpi;
730
731 spin_lock(&lpi_lock);
732
733 for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
734 int chunk = its_lpi_to_chunk(lpi);
735 BUG_ON(chunk > lpi_chunks);
736 if (test_bit(chunk, lpi_bitmap)) {
737 clear_bit(chunk, lpi_bitmap);
738 } else {
739 pr_err("Bad LPI chunk %d\n", chunk);
740 }
741 }
742
743 spin_unlock(&lpi_lock);
744
Marc Zyngier591e5be2015-07-17 10:46:42 +0100745 kfree(map->lpi_map);
746 kfree(map->col_map);
Marc Zyngierbf9529f2014-11-24 14:35:13 +0000747}
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000748
749/*
750 * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
751 * deal with (one configuration byte per interrupt). PENDBASE has to
752 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
753 */
754#define LPI_PROPBASE_SZ SZ_64K
755#define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K)
756
757/*
758 * This is how many bits of ID we need, including the useless ones.
759 */
760#define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K)
761
762#define LPI_PROP_DEFAULT_PRIO 0xa0
763
764static int __init its_alloc_lpi_tables(void)
765{
766 phys_addr_t paddr;
767
768 gic_rdists->prop_page = alloc_pages(GFP_NOWAIT,
769 get_order(LPI_PROPBASE_SZ));
770 if (!gic_rdists->prop_page) {
771 pr_err("Failed to allocate PROPBASE\n");
772 return -ENOMEM;
773 }
774
775 paddr = page_to_phys(gic_rdists->prop_page);
776 pr_info("GIC: using LPI property table @%pa\n", &paddr);
777
778 /* Priority 0xa0, Group-1, disabled */
779 memset(page_address(gic_rdists->prop_page),
780 LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
781 LPI_PROPBASE_SZ);
782
783 /* Make sure the GIC will observe the written configuration */
784 __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
785
786 return 0;
787}
788
789static const char *its_base_type_string[] = {
790 [GITS_BASER_TYPE_DEVICE] = "Devices",
791 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
792 [GITS_BASER_TYPE_CPU] = "Physical CPUs",
793 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
794 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
795 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
796 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
797};
798
799static void its_free_tables(struct its_node *its)
800{
801 int i;
802
803 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
804 if (its->tables[i]) {
805 free_page((unsigned long)its->tables[i]);
806 its->tables[i] = NULL;
807 }
808 }
809}
810
Marc Zyngier841514a2015-07-28 14:46:20 +0100811static int its_alloc_tables(const char *node_name, struct its_node *its)
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000812{
813 int err;
814 int i;
Yun Wu790b57a2015-03-06 16:37:47 +0000815 int psz = SZ_64K;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000816 u64 shr = GITS_BASER_InnerShareable;
Marc Zyngier241a3862015-03-27 14:15:05 +0000817 u64 cache = GITS_BASER_WaWb;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000818
819 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
820 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
821 u64 type = GITS_BASER_TYPE(val);
822 u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
Yun Wu790b57a2015-03-06 16:37:47 +0000823 int order = get_order(psz);
Marc Zyngierf54b97e2015-03-06 16:37:41 +0000824 int alloc_size;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000825 u64 tmp;
826 void *base;
827
828 if (type == GITS_BASER_TYPE_NONE)
829 continue;
830
Marc Zyngierf54b97e2015-03-06 16:37:41 +0000831 /*
832 * Allocate as many entries as required to fit the
833 * range of device IDs that the ITS can grok... The ID
834 * space being incredibly sparse, this results in a
835 * massive waste of memory.
836 *
837 * For other tables, only allocate a single page.
838 */
839 if (type == GITS_BASER_TYPE_DEVICE) {
840 u64 typer = readq_relaxed(its->base + GITS_TYPER);
841 u32 ids = GITS_TYPER_DEVBITS(typer);
842
Minghuan Lian3ad2a5f2015-05-20 10:13:15 -0500843 /*
844 * 'order' was initialized earlier to the default page
845 * granule of the the ITS. We can't have an allocation
846 * smaller than that. If the requested allocation
847 * is smaller, round up to the default page granule.
848 */
849 order = max(get_order((1UL << ids) * entry_size),
850 order);
Yun Wu1d277042015-03-06 16:37:48 +0000851 if (order >= MAX_ORDER) {
852 order = MAX_ORDER - 1;
853 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
Marc Zyngier841514a2015-07-28 14:46:20 +0100854 node_name, order);
Yun Wu1d277042015-03-06 16:37:48 +0000855 }
Marc Zyngierf54b97e2015-03-06 16:37:41 +0000856 }
857
858 alloc_size = (1 << order) * PAGE_SIZE;
859 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000860 if (!base) {
861 err = -ENOMEM;
862 goto out_free;
863 }
864
865 its->tables[i] = base;
866
867retry_baser:
868 val = (virt_to_phys(base) |
869 (type << GITS_BASER_TYPE_SHIFT) |
870 ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
Marc Zyngier241a3862015-03-27 14:15:05 +0000871 cache |
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000872 shr |
873 GITS_BASER_VALID);
874
875 switch (psz) {
876 case SZ_4K:
877 val |= GITS_BASER_PAGE_SIZE_4K;
878 break;
879 case SZ_16K:
880 val |= GITS_BASER_PAGE_SIZE_16K;
881 break;
882 case SZ_64K:
883 val |= GITS_BASER_PAGE_SIZE_64K;
884 break;
885 }
886
Marc Zyngierf54b97e2015-03-06 16:37:41 +0000887 val |= (alloc_size / psz) - 1;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000888
889 writeq_relaxed(val, its->base + GITS_BASER + i * 8);
890 tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
891
892 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
893 /*
894 * Shareability didn't stick. Just use
895 * whatever the read reported, which is likely
896 * to be the only thing this redistributor
Marc Zyngier241a3862015-03-27 14:15:05 +0000897 * supports. If that's zero, make it
898 * non-cacheable as well.
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000899 */
900 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
Marc Zyngier5a9a8912015-09-13 12:14:32 +0100901 if (!shr) {
Marc Zyngier241a3862015-03-27 14:15:05 +0000902 cache = GITS_BASER_nC;
Marc Zyngier5a9a8912015-09-13 12:14:32 +0100903 __flush_dcache_area(base, alloc_size);
904 }
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000905 goto retry_baser;
906 }
907
908 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
909 /*
910 * Page size didn't stick. Let's try a smaller
911 * size and retry. If we reach 4K, then
912 * something is horribly wrong...
913 */
914 switch (psz) {
915 case SZ_16K:
916 psz = SZ_4K;
917 goto retry_baser;
918 case SZ_64K:
919 psz = SZ_16K;
920 goto retry_baser;
921 }
922 }
923
924 if (val != tmp) {
925 pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
Marc Zyngier841514a2015-07-28 14:46:20 +0100926 node_name, i,
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000927 (unsigned long) val, (unsigned long) tmp);
928 err = -ENXIO;
929 goto out_free;
930 }
931
932 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
Marc Zyngierf54b97e2015-03-06 16:37:41 +0000933 (int)(alloc_size / entry_size),
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000934 its_base_type_string[type],
935 (unsigned long)virt_to_phys(base),
936 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
937 }
938
939 return 0;
940
941out_free:
942 its_free_tables(its);
943
944 return err;
945}
946
947static int its_alloc_collections(struct its_node *its)
948{
949 its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
950 GFP_KERNEL);
951 if (!its->collections)
952 return -ENOMEM;
953
954 return 0;
955}
956
957static void its_cpu_init_lpis(void)
958{
959 void __iomem *rbase = gic_data_rdist_rd_base();
960 struct page *pend_page;
961 u64 val, tmp;
962
963 /* If we didn't allocate the pending table yet, do it now */
964 pend_page = gic_data_rdist()->pend_page;
965 if (!pend_page) {
966 phys_addr_t paddr;
967 /*
968 * The pending pages have to be at least 64kB aligned,
969 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
970 */
971 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO,
972 get_order(max(LPI_PENDBASE_SZ, SZ_64K)));
973 if (!pend_page) {
974 pr_err("Failed to allocate PENDBASE for CPU%d\n",
975 smp_processor_id());
976 return;
977 }
978
979 /* Make sure the GIC will observe the zero-ed page */
980 __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
981
982 paddr = page_to_phys(pend_page);
983 pr_info("CPU%d: using LPI pending table @%pa\n",
984 smp_processor_id(), &paddr);
985 gic_data_rdist()->pend_page = pend_page;
986 }
987
988 /* Disable LPIs */
989 val = readl_relaxed(rbase + GICR_CTLR);
990 val &= ~GICR_CTLR_ENABLE_LPIS;
991 writel_relaxed(val, rbase + GICR_CTLR);
992
993 /*
994 * Make sure any change to the table is observable by the GIC.
995 */
996 dsb(sy);
997
998 /* set PROPBASE */
999 val = (page_to_phys(gic_rdists->prop_page) |
1000 GICR_PROPBASER_InnerShareable |
1001 GICR_PROPBASER_WaWb |
1002 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1003
1004 writeq_relaxed(val, rbase + GICR_PROPBASER);
1005 tmp = readq_relaxed(rbase + GICR_PROPBASER);
1006
1007 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
Marc Zyngier241a3862015-03-27 14:15:05 +00001008 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1009 /*
1010 * The HW reports non-shareable, we must
1011 * remove the cacheability attributes as
1012 * well.
1013 */
1014 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1015 GICR_PROPBASER_CACHEABILITY_MASK);
1016 val |= GICR_PROPBASER_nC;
1017 writeq_relaxed(val, rbase + GICR_PROPBASER);
1018 }
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00001019 pr_info_once("GIC: using cache flushing for LPI property table\n");
1020 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1021 }
1022
1023 /* set PENDBASE */
1024 val = (page_to_phys(pend_page) |
Marc Zyngier4ad3e362015-03-27 14:15:04 +00001025 GICR_PENDBASER_InnerShareable |
1026 GICR_PENDBASER_WaWb);
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00001027
1028 writeq_relaxed(val, rbase + GICR_PENDBASER);
Marc Zyngier241a3862015-03-27 14:15:05 +00001029 tmp = readq_relaxed(rbase + GICR_PENDBASER);
1030
1031 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1032 /*
1033 * The HW reports non-shareable, we must remove the
1034 * cacheability attributes as well.
1035 */
1036 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1037 GICR_PENDBASER_CACHEABILITY_MASK);
1038 val |= GICR_PENDBASER_nC;
1039 writeq_relaxed(val, rbase + GICR_PENDBASER);
1040 }
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00001041
1042 /* Enable LPIs */
1043 val = readl_relaxed(rbase + GICR_CTLR);
1044 val |= GICR_CTLR_ENABLE_LPIS;
1045 writel_relaxed(val, rbase + GICR_CTLR);
1046
1047 /* Make sure the GIC has seen the above */
1048 dsb(sy);
1049}
1050
1051static void its_cpu_init_collection(void)
1052{
1053 struct its_node *its;
1054 int cpu;
1055
1056 spin_lock(&its_lock);
1057 cpu = smp_processor_id();
1058
1059 list_for_each_entry(its, &its_nodes, entry) {
1060 u64 target;
1061
1062 /*
1063 * We now have to bind each collection to its target
1064 * redistributor.
1065 */
1066 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1067 /*
1068 * This ITS wants the physical address of the
1069 * redistributor.
1070 */
1071 target = gic_data_rdist()->phys_base;
1072 } else {
1073 /*
1074 * This ITS wants a linear CPU number.
1075 */
1076 target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
Marc Zyngier263fcd32015-03-27 14:15:02 +00001077 target = GICR_TYPER_CPU_NUMBER(target) << 16;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00001078 }
1079
1080 /* Perform collection mapping */
1081 its->collections[cpu].target_address = target;
1082 its->collections[cpu].col_id = cpu;
1083
1084 its_send_mapc(its, &its->collections[cpu], 1);
1085 its_send_invall(its, &its->collections[cpu]);
1086 }
1087
1088 spin_unlock(&its_lock);
1089}
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001090
1091static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1092{
1093 struct its_device *its_dev = NULL, *tmp;
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00001094 unsigned long flags;
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001095
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00001096 raw_spin_lock_irqsave(&its->lock, flags);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001097
1098 list_for_each_entry(tmp, &its->its_device_list, entry) {
1099 if (tmp->device_id == dev_id) {
1100 its_dev = tmp;
1101 break;
1102 }
1103 }
1104
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00001105 raw_spin_unlock_irqrestore(&its->lock, flags);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001106
1107 return its_dev;
1108}
1109
1110static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1111 int nvecs)
1112{
1113 struct its_device *dev;
1114 unsigned long *lpi_map;
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00001115 unsigned long flags;
Marc Zyngier591e5be2015-07-17 10:46:42 +01001116 u16 *col_map = NULL;
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001117 void *itt;
1118 int lpi_base;
1119 int nr_lpis;
Marc Zyngierc8481262014-12-12 10:51:24 +00001120 int nr_ites;
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001121 int sz;
1122
1123 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
Marc Zyngierc8481262014-12-12 10:51:24 +00001124 /*
1125 * At least one bit of EventID is being used, hence a minimum
1126 * of two entries. No, the architecture doesn't let you
1127 * express an ITT with a single entry.
1128 */
Will Deacon96555c42014-12-17 14:11:09 +00001129 nr_ites = max(2UL, roundup_pow_of_two(nvecs));
Marc Zyngierc8481262014-12-12 10:51:24 +00001130 sz = nr_ites * its->ite_size;
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001131 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
Yun Wu6c834122015-03-06 16:37:46 +00001132 itt = kzalloc(sz, GFP_KERNEL);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001133 lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
Marc Zyngier591e5be2015-07-17 10:46:42 +01001134 if (lpi_map)
1135 col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001136
Marc Zyngier591e5be2015-07-17 10:46:42 +01001137 if (!dev || !itt || !lpi_map || !col_map) {
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001138 kfree(dev);
1139 kfree(itt);
1140 kfree(lpi_map);
Marc Zyngier591e5be2015-07-17 10:46:42 +01001141 kfree(col_map);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001142 return NULL;
1143 }
1144
Marc Zyngier5a9a8912015-09-13 12:14:32 +01001145 __flush_dcache_area(itt, sz);
1146
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001147 dev->its = its;
1148 dev->itt = itt;
Marc Zyngierc8481262014-12-12 10:51:24 +00001149 dev->nr_ites = nr_ites;
Marc Zyngier591e5be2015-07-17 10:46:42 +01001150 dev->event_map.lpi_map = lpi_map;
1151 dev->event_map.col_map = col_map;
1152 dev->event_map.lpi_base = lpi_base;
1153 dev->event_map.nr_lpis = nr_lpis;
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001154 dev->device_id = dev_id;
1155 INIT_LIST_HEAD(&dev->entry);
1156
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00001157 raw_spin_lock_irqsave(&its->lock, flags);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001158 list_add(&dev->entry, &its->its_device_list);
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00001159 raw_spin_unlock_irqrestore(&its->lock, flags);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001160
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001161 /* Map device to its ITT */
1162 its_send_mapd(dev, 1);
1163
1164 return dev;
1165}
1166
1167static void its_free_device(struct its_device *its_dev)
1168{
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00001169 unsigned long flags;
1170
1171 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001172 list_del(&its_dev->entry);
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00001173 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00001174 kfree(its_dev->itt);
1175 kfree(its_dev);
1176}
Marc Zyngierb48ac832014-11-24 14:35:16 +00001177
1178static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
1179{
1180 int idx;
1181
Marc Zyngier591e5be2015-07-17 10:46:42 +01001182 idx = find_first_zero_bit(dev->event_map.lpi_map,
1183 dev->event_map.nr_lpis);
1184 if (idx == dev->event_map.nr_lpis)
Marc Zyngierb48ac832014-11-24 14:35:16 +00001185 return -ENOSPC;
1186
Marc Zyngier591e5be2015-07-17 10:46:42 +01001187 *hwirq = dev->event_map.lpi_base + idx;
1188 set_bit(idx, dev->event_map.lpi_map);
Marc Zyngierb48ac832014-11-24 14:35:16 +00001189
Marc Zyngierb48ac832014-11-24 14:35:16 +00001190 return 0;
1191}
1192
Marc Zyngier54456db2015-07-28 14:46:21 +01001193static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
1194 int nvec, msi_alloc_info_t *info)
Marc Zyngiere8137f42015-03-06 16:37:42 +00001195{
Marc Zyngierb48ac832014-11-24 14:35:16 +00001196 struct its_node *its;
Marc Zyngierb48ac832014-11-24 14:35:16 +00001197 struct its_device *its_dev;
Marc Zyngier54456db2015-07-28 14:46:21 +01001198 struct msi_domain_info *msi_info;
1199 u32 dev_id;
Marc Zyngierb48ac832014-11-24 14:35:16 +00001200
Marc Zyngier54456db2015-07-28 14:46:21 +01001201 /*
1202 * We ignore "dev" entierely, and rely on the dev_id that has
1203 * been passed via the scratchpad. This limits this domain's
1204 * usefulness to upper layers that definitely know that they
1205 * are built on top of the ITS.
1206 */
1207 dev_id = info->scratchpad[0].ul;
1208
1209 msi_info = msi_get_domain_info(domain);
1210 its = msi_info->data;
1211
Marc Zyngierf1304202015-07-28 14:46:18 +01001212 its_dev = its_find_device(its, dev_id);
Marc Zyngiere8137f42015-03-06 16:37:42 +00001213 if (its_dev) {
1214 /*
1215 * We already have seen this ID, probably through
1216 * another alias (PCI bridge of some sort). No need to
1217 * create the device.
1218 */
Marc Zyngierf1304202015-07-28 14:46:18 +01001219 pr_debug("Reusing ITT for devID %x\n", dev_id);
Marc Zyngiere8137f42015-03-06 16:37:42 +00001220 goto out;
1221 }
Marc Zyngierb48ac832014-11-24 14:35:16 +00001222
Marc Zyngierf1304202015-07-28 14:46:18 +01001223 its_dev = its_create_device(its, dev_id, nvec);
Marc Zyngierb48ac832014-11-24 14:35:16 +00001224 if (!its_dev)
1225 return -ENOMEM;
1226
Marc Zyngierf1304202015-07-28 14:46:18 +01001227 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
Marc Zyngiere8137f42015-03-06 16:37:42 +00001228out:
Marc Zyngierb48ac832014-11-24 14:35:16 +00001229 info->scratchpad[0].ptr = its_dev;
Marc Zyngierb48ac832014-11-24 14:35:16 +00001230 return 0;
1231}
1232
Marc Zyngier54456db2015-07-28 14:46:21 +01001233static struct msi_domain_ops its_msi_domain_ops = {
1234 .msi_prepare = its_msi_prepare,
1235};
1236
Marc Zyngierb48ac832014-11-24 14:35:16 +00001237static int its_irq_gic_domain_alloc(struct irq_domain *domain,
1238 unsigned int virq,
1239 irq_hw_number_t hwirq)
1240{
1241 struct of_phandle_args args;
1242
1243 args.np = domain->parent->of_node;
1244 args.args_count = 3;
1245 args.args[0] = GIC_IRQ_TYPE_LPI;
1246 args.args[1] = hwirq;
1247 args.args[2] = IRQ_TYPE_EDGE_RISING;
1248
1249 return irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
1250}
1251
1252static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1253 unsigned int nr_irqs, void *args)
1254{
1255 msi_alloc_info_t *info = args;
1256 struct its_device *its_dev = info->scratchpad[0].ptr;
1257 irq_hw_number_t hwirq;
1258 int err;
1259 int i;
1260
1261 for (i = 0; i < nr_irqs; i++) {
1262 err = its_alloc_device_irq(its_dev, &hwirq);
1263 if (err)
1264 return err;
1265
1266 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
1267 if (err)
1268 return err;
1269
1270 irq_domain_set_hwirq_and_chip(domain, virq + i,
1271 hwirq, &its_irq_chip, its_dev);
Marc Zyngierf1304202015-07-28 14:46:18 +01001272 pr_debug("ID:%d pID:%d vID:%d\n",
1273 (int)(hwirq - its_dev->event_map.lpi_base),
1274 (int) hwirq, virq + i);
Marc Zyngierb48ac832014-11-24 14:35:16 +00001275 }
1276
1277 return 0;
1278}
1279
Marc Zyngieraca268d2014-12-12 10:51:23 +00001280static void its_irq_domain_activate(struct irq_domain *domain,
1281 struct irq_data *d)
1282{
1283 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1284 u32 event = its_get_event_id(d);
1285
Marc Zyngier591e5be2015-07-17 10:46:42 +01001286 /* Bind the LPI to the first possible CPU */
1287 its_dev->event_map.col_map[event] = cpumask_first(cpu_online_mask);
1288
Marc Zyngieraca268d2014-12-12 10:51:23 +00001289 /* Map the GIC IRQ and event to the device */
1290 its_send_mapvi(its_dev, d->hwirq, event);
1291}
1292
1293static void its_irq_domain_deactivate(struct irq_domain *domain,
1294 struct irq_data *d)
1295{
1296 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1297 u32 event = its_get_event_id(d);
1298
1299 /* Stop the delivery of interrupts */
1300 its_send_discard(its_dev, event);
1301}
1302
Marc Zyngierb48ac832014-11-24 14:35:16 +00001303static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1304 unsigned int nr_irqs)
1305{
1306 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1307 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1308 int i;
1309
1310 for (i = 0; i < nr_irqs; i++) {
1311 struct irq_data *data = irq_domain_get_irq_data(domain,
1312 virq + i);
Marc Zyngieraca268d2014-12-12 10:51:23 +00001313 u32 event = its_get_event_id(data);
Marc Zyngierb48ac832014-11-24 14:35:16 +00001314
1315 /* Mark interrupt index as unused */
Marc Zyngier591e5be2015-07-17 10:46:42 +01001316 clear_bit(event, its_dev->event_map.lpi_map);
Marc Zyngierb48ac832014-11-24 14:35:16 +00001317
1318 /* Nuke the entry in the domain */
Marc Zyngier2da399492014-12-12 10:51:22 +00001319 irq_domain_reset_irq_data(data);
Marc Zyngierb48ac832014-11-24 14:35:16 +00001320 }
1321
1322 /* If all interrupts have been freed, start mopping the floor */
Marc Zyngier591e5be2015-07-17 10:46:42 +01001323 if (bitmap_empty(its_dev->event_map.lpi_map,
1324 its_dev->event_map.nr_lpis)) {
1325 its_lpi_free(&its_dev->event_map);
Marc Zyngierb48ac832014-11-24 14:35:16 +00001326
1327 /* Unmap device/itt */
1328 its_send_mapd(its_dev, 0);
1329 its_free_device(its_dev);
1330 }
1331
1332 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
1333}
1334
1335static const struct irq_domain_ops its_domain_ops = {
1336 .alloc = its_irq_domain_alloc,
1337 .free = its_irq_domain_free,
Marc Zyngieraca268d2014-12-12 10:51:23 +00001338 .activate = its_irq_domain_activate,
1339 .deactivate = its_irq_domain_deactivate,
Marc Zyngierb48ac832014-11-24 14:35:16 +00001340};
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001341
Yun Wu4559fbb2015-03-06 16:37:50 +00001342static int its_force_quiescent(void __iomem *base)
1343{
1344 u32 count = 1000000; /* 1s */
1345 u32 val;
1346
1347 val = readl_relaxed(base + GITS_CTLR);
1348 if (val & GITS_CTLR_QUIESCENT)
1349 return 0;
1350
1351 /* Disable the generation of all interrupts to this ITS */
1352 val &= ~GITS_CTLR_ENABLE;
1353 writel_relaxed(val, base + GITS_CTLR);
1354
1355 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1356 while (1) {
1357 val = readl_relaxed(base + GITS_CTLR);
1358 if (val & GITS_CTLR_QUIESCENT)
1359 return 0;
1360
1361 count--;
1362 if (!count)
1363 return -EBUSY;
1364
1365 cpu_relax();
1366 udelay(1);
1367 }
1368}
1369
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001370static int its_probe(struct device_node *node, struct irq_domain *parent)
1371{
1372 struct resource res;
1373 struct its_node *its;
1374 void __iomem *its_base;
Marc Zyngier54456db2015-07-28 14:46:21 +01001375 struct irq_domain *inner_domain;
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001376 u32 val;
1377 u64 baser, tmp;
1378 int err;
1379
1380 err = of_address_to_resource(node, 0, &res);
1381 if (err) {
1382 pr_warn("%s: no regs?\n", node->full_name);
1383 return -ENXIO;
1384 }
1385
1386 its_base = ioremap(res.start, resource_size(&res));
1387 if (!its_base) {
1388 pr_warn("%s: unable to map registers\n", node->full_name);
1389 return -ENOMEM;
1390 }
1391
1392 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
1393 if (val != 0x30 && val != 0x40) {
1394 pr_warn("%s: no ITS detected, giving up\n", node->full_name);
1395 err = -ENODEV;
1396 goto out_unmap;
1397 }
1398
Yun Wu4559fbb2015-03-06 16:37:50 +00001399 err = its_force_quiescent(its_base);
1400 if (err) {
1401 pr_warn("%s: failed to quiesce, giving up\n",
1402 node->full_name);
1403 goto out_unmap;
1404 }
1405
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001406 pr_info("ITS: %s\n", node->full_name);
1407
1408 its = kzalloc(sizeof(*its), GFP_KERNEL);
1409 if (!its) {
1410 err = -ENOMEM;
1411 goto out_unmap;
1412 }
1413
1414 raw_spin_lock_init(&its->lock);
1415 INIT_LIST_HEAD(&its->entry);
1416 INIT_LIST_HEAD(&its->its_device_list);
1417 its->base = its_base;
1418 its->phys_base = res.start;
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001419 its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1420
1421 its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
1422 if (!its->cmd_base) {
1423 err = -ENOMEM;
1424 goto out_free_its;
1425 }
1426 its->cmd_write = its->cmd_base;
1427
Marc Zyngier841514a2015-07-28 14:46:20 +01001428 err = its_alloc_tables(node->full_name, its);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001429 if (err)
1430 goto out_free_cmd;
1431
1432 err = its_alloc_collections(its);
1433 if (err)
1434 goto out_free_tables;
1435
1436 baser = (virt_to_phys(its->cmd_base) |
1437 GITS_CBASER_WaWb |
1438 GITS_CBASER_InnerShareable |
1439 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
1440 GITS_CBASER_VALID);
1441
1442 writeq_relaxed(baser, its->base + GITS_CBASER);
1443 tmp = readq_relaxed(its->base + GITS_CBASER);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001444
Marc Zyngier4ad3e362015-03-27 14:15:04 +00001445 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
Marc Zyngier241a3862015-03-27 14:15:05 +00001446 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
1447 /*
1448 * The HW reports non-shareable, we must
1449 * remove the cacheability attributes as
1450 * well.
1451 */
1452 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
1453 GITS_CBASER_CACHEABILITY_MASK);
1454 baser |= GITS_CBASER_nC;
1455 writeq_relaxed(baser, its->base + GITS_CBASER);
1456 }
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001457 pr_info("ITS: using cache flushing for cmd queue\n");
1458 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
1459 }
1460
Marc Zyngier241a3862015-03-27 14:15:05 +00001461 writeq_relaxed(0, its->base + GITS_CWRITER);
1462 writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
1463
Marc Zyngier841514a2015-07-28 14:46:20 +01001464 if (of_property_read_bool(node, "msi-controller")) {
Marc Zyngier54456db2015-07-28 14:46:21 +01001465 struct msi_domain_info *info;
1466
1467 info = kzalloc(sizeof(*info), GFP_KERNEL);
1468 if (!info) {
1469 err = -ENOMEM;
1470 goto out_free_tables;
1471 }
1472
Marc Zyngier841514a2015-07-28 14:46:20 +01001473 inner_domain = irq_domain_add_tree(node, &its_domain_ops, its);
1474 if (!inner_domain) {
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001475 err = -ENOMEM;
Marc Zyngier54456db2015-07-28 14:46:21 +01001476 kfree(info);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001477 goto out_free_tables;
1478 }
1479
Marc Zyngier841514a2015-07-28 14:46:20 +01001480 inner_domain->parent = parent;
1481 inner_domain->bus_token = DOMAIN_BUS_NEXUS;
Marc Zyngier54456db2015-07-28 14:46:21 +01001482 info->ops = &its_msi_domain_ops;
1483 info->data = its;
1484 inner_domain->host_data = info;
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001485 }
1486
1487 spin_lock(&its_lock);
1488 list_add(&its->entry, &its_nodes);
1489 spin_unlock(&its_lock);
1490
1491 return 0;
1492
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001493out_free_tables:
1494 its_free_tables(its);
1495out_free_cmd:
1496 kfree(its->cmd_base);
1497out_free_its:
1498 kfree(its);
1499out_unmap:
1500 iounmap(its_base);
1501 pr_err("ITS: failed probing %s (%d)\n", node->full_name, err);
1502 return err;
1503}
1504
1505static bool gic_rdists_supports_plpis(void)
1506{
1507 return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
1508}
1509
1510int its_cpu_init(void)
1511{
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001512 if (!list_empty(&its_nodes)) {
Vladimir Murzin16acae72015-03-06 16:37:40 +00001513 if (!gic_rdists_supports_plpis()) {
1514 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1515 return -ENXIO;
1516 }
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00001517 its_cpu_init_lpis();
1518 its_cpu_init_collection();
1519 }
1520
1521 return 0;
1522}
1523
1524static struct of_device_id its_device_id[] = {
1525 { .compatible = "arm,gic-v3-its", },
1526 {},
1527};
1528
1529int its_init(struct device_node *node, struct rdists *rdists,
1530 struct irq_domain *parent_domain)
1531{
1532 struct device_node *np;
1533
1534 for (np = of_find_matching_node(node, its_device_id); np;
1535 np = of_find_matching_node(np, its_device_id)) {
1536 its_probe(np, parent_domain);
1537 }
1538
1539 if (list_empty(&its_nodes)) {
1540 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1541 return -ENXIO;
1542 }
1543
1544 gic_rdists = rdists;
1545 gic_root_node = node;
1546
1547 its_alloc_lpi_tables();
1548 its_lpi_init(rdists->id_bits);
1549
1550 return 0;
1551}