blob: 20d66e5e4663bf230ecc9a23340026adce2c3cda [file] [log] [blame]
Vladimir Barinov3d9edf02007-07-10 13:03:43 +01001/*
2 * TI DaVinci GPIO Support
3 *
David Brownelldce11152008-09-07 23:41:04 -07004 * Copyright (c) 2006-2007 David Brownell
Vladimir Barinov3d9edf02007-07-10 13:03:43 +01005 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/errno.h>
14#include <linux/kernel.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010015#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010018
Russell Kinga09e64f2008-08-05 16:14:15 +010019#include <mach/gpio.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010020
21#include <asm/mach/irq.h>
22
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040023struct davinci_gpio_regs {
24 u32 dir;
25 u32 out_data;
26 u32 set_data;
27 u32 clr_data;
28 u32 in_data;
29 u32 set_rising;
30 u32 clr_rising;
31 u32 set_falling;
32 u32 clr_falling;
33 u32 intstat;
34};
35
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040036#define chip2controller(chip) \
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040037 container_of(chip, struct davinci_gpio_controller, chip)
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040038
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040039static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040040static void __iomem *gpio_base;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010041
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040042static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010043{
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040044 void __iomem *ptr;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040045
46 if (gpio < 32 * 1)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040047 ptr = gpio_base + 0x10;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040048 else if (gpio < 32 * 2)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040049 ptr = gpio_base + 0x38;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040050 else if (gpio < 32 * 3)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040051 ptr = gpio_base + 0x60;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040052 else if (gpio < 32 * 4)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040053 ptr = gpio_base + 0x88;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040054 else if (gpio < 32 * 5)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040055 ptr = gpio_base + 0xb0;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040056 else
57 ptr = NULL;
58 return ptr;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010059}
60
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040061static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
Kevin Hilman21ce8732010-02-25 16:49:56 -080062{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040063 struct davinci_gpio_regs __iomem *g;
Kevin Hilman21ce8732010-02-25 16:49:56 -080064
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040065 g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
Kevin Hilman21ce8732010-02-25 16:49:56 -080066
67 return g;
68}
69
Kevin Hilmandc756022009-05-11 11:04:53 -070070static int __init davinci_gpio_irq_setup(void);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010071
72/*--------------------------------------------------------------------------*/
73
Cyril Chemparathy5b3a05c2010-05-01 18:38:27 -040074/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040075static inline int __davinci_direction(struct gpio_chip *chip,
76 unsigned offset, bool out, int value)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010077{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040078 struct davinci_gpio_controller *d = chip2controller(chip);
79 struct davinci_gpio_regs __iomem *g = d->regs;
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040080 unsigned long flags;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010081 u32 temp;
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040082 u32 mask = 1 << offset;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010083
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040084 spin_lock_irqsave(&d->lock, flags);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010085 temp = __raw_readl(&g->dir);
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040086 if (out) {
87 temp &= ~mask;
88 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
89 } else {
90 temp |= mask;
91 }
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010092 __raw_writel(temp, &g->dir);
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040093 spin_unlock_irqrestore(&d->lock, flags);
David Brownelldce11152008-09-07 23:41:04 -070094
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010095 return 0;
96}
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010097
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040098static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
99{
100 return __davinci_direction(chip, offset, false, 0);
101}
102
103static int
104davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
105{
106 return __davinci_direction(chip, offset, true, value);
107}
108
David Brownelldce11152008-09-07 23:41:04 -0700109/*
110 * Read the pin's value (works even if it's set up as output);
111 * returns zero/nonzero.
112 *
113 * Note that changes are synched to the GPIO clock, so reading values back
114 * right after you've set them may give old values.
115 */
116static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100117{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400118 struct davinci_gpio_controller *d = chip2controller(chip);
119 struct davinci_gpio_regs __iomem *g = d->regs;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100120
David Brownelldce11152008-09-07 23:41:04 -0700121 return (1 << offset) & __raw_readl(&g->in_data);
122}
123
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100124/*
David Brownelldce11152008-09-07 23:41:04 -0700125 * Assuming the pin is muxed as a gpio output, set its output value.
126 */
127static void
128davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
129{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400130 struct davinci_gpio_controller *d = chip2controller(chip);
131 struct davinci_gpio_regs __iomem *g = d->regs;
David Brownelldce11152008-09-07 23:41:04 -0700132
133 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
134}
135
136static int __init davinci_gpio_setup(void)
137{
138 int i, base;
Mark A. Greera9949552009-04-15 12:40:35 -0700139 unsigned ngpio;
140 struct davinci_soc_info *soc_info = &davinci_soc_info;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -0400141 struct davinci_gpio_regs *regs;
David Brownelldce11152008-09-07 23:41:04 -0700142
Cyril Chemparathy686b6342010-05-01 18:37:54 -0400143 if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
144 return 0;
145
Mark A. Greera9949552009-04-15 12:40:35 -0700146 /*
147 * The gpio banks conceptually expose a segmented bitmap,
David Brownell474dad52008-12-07 11:46:23 -0800148 * and "ngpio" is one more than the largest zero-based
149 * bit index that's valid.
150 */
Mark A. Greera9949552009-04-15 12:40:35 -0700151 ngpio = soc_info->gpio_num;
152 if (ngpio == 0) {
David Brownell474dad52008-12-07 11:46:23 -0800153 pr_err("GPIO setup: how many GPIOs?\n");
154 return -EINVAL;
155 }
156
157 if (WARN_ON(DAVINCI_N_GPIO < ngpio))
158 ngpio = DAVINCI_N_GPIO;
159
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400160 gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
161 if (WARN_ON(!gpio_base))
162 return -ENOMEM;
163
David Brownell474dad52008-12-07 11:46:23 -0800164 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
David Brownelldce11152008-09-07 23:41:04 -0700165 chips[i].chip.label = "DaVinci";
166
167 chips[i].chip.direction_input = davinci_direction_in;
168 chips[i].chip.get = davinci_gpio_get;
169 chips[i].chip.direction_output = davinci_direction_out;
170 chips[i].chip.set = davinci_gpio_set;
171
172 chips[i].chip.base = base;
David Brownell474dad52008-12-07 11:46:23 -0800173 chips[i].chip.ngpio = ngpio - base;
David Brownelldce11152008-09-07 23:41:04 -0700174 if (chips[i].chip.ngpio > 32)
175 chips[i].chip.ngpio = 32;
176
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -0400177 spin_lock_init(&chips[i].lock);
178
Cyril Chemparathyc12f4152010-05-01 18:37:53 -0400179 regs = gpio2regs(base);
180 chips[i].regs = regs;
181 chips[i].set_data = &regs->set_data;
182 chips[i].clr_data = &regs->clr_data;
183 chips[i].in_data = &regs->in_data;
David Brownelldce11152008-09-07 23:41:04 -0700184
185 gpiochip_add(&chips[i].chip);
186 }
187
Cyril Chemparathyc12f4152010-05-01 18:37:53 -0400188 soc_info->gpio_ctlrs = chips;
189 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
190
Kevin Hilmandc756022009-05-11 11:04:53 -0700191 davinci_gpio_irq_setup();
David Brownelldce11152008-09-07 23:41:04 -0700192 return 0;
193}
194pure_initcall(davinci_gpio_setup);
195
196/*--------------------------------------------------------------------------*/
197/*
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100198 * We expect irqs will normally be set up as input pins, but they can also be
199 * used as output pins ... which is convenient for testing.
200 *
David Brownell474dad52008-12-07 11:46:23 -0800201 * NOTE: The first few GPIOs also have direct INTC hookups in addition
David Brownell7a360712009-06-25 17:01:31 -0700202 * to their GPIOBNK0 irq, with a bit less overhead.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100203 *
David Brownell474dad52008-12-07 11:46:23 -0800204 * All those INTC hookups (direct, plus several IRQ banks) can also
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100205 * serve as EDMA event triggers.
206 */
207
Lennert Buytenhek23265442010-11-29 10:27:27 +0100208static void gpio_irq_disable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100209{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100210 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
211 u32 mask = (u32) irq_data_get_irq_data(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100212
213 __raw_writel(mask, &g->clr_falling);
214 __raw_writel(mask, &g->clr_rising);
215}
216
Lennert Buytenhek23265442010-11-29 10:27:27 +0100217static void gpio_irq_enable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100218{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100219 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
220 u32 mask = (u32) irq_data_get_irq_data(d);
221 unsigned status = irq_desc[d->irq].status;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100222
David Brownelldf4aab42009-05-04 13:14:27 -0700223 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
224 if (!status)
225 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
226
227 if (status & IRQ_TYPE_EDGE_FALLING)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100228 __raw_writel(mask, &g->set_falling);
David Brownelldf4aab42009-05-04 13:14:27 -0700229 if (status & IRQ_TYPE_EDGE_RISING)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100230 __raw_writel(mask, &g->set_rising);
231}
232
Lennert Buytenhek23265442010-11-29 10:27:27 +0100233static int gpio_irq_type(struct irq_data *d, unsigned trigger)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100234{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100235 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
236 u32 mask = (u32) irq_data_get_irq_data(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100237
238 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
239 return -EINVAL;
240
Lennert Buytenhek23265442010-11-29 10:27:27 +0100241 irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK;
242 irq_desc[d->irq].status |= trigger;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100243
David Brownelldf4aab42009-05-04 13:14:27 -0700244 /* don't enable the IRQ if it's currently disabled */
Lennert Buytenhek23265442010-11-29 10:27:27 +0100245 if (irq_desc[d->irq].depth == 0) {
David Brownelldf4aab42009-05-04 13:14:27 -0700246 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
247 ? &g->set_falling : &g->clr_falling);
248 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
249 ? &g->set_rising : &g->clr_rising);
250 }
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100251 return 0;
252}
253
254static struct irq_chip gpio_irqchip = {
255 .name = "GPIO",
Lennert Buytenhek23265442010-11-29 10:27:27 +0100256 .irq_enable = gpio_irq_enable,
257 .irq_disable = gpio_irq_disable,
258 .irq_set_type = gpio_irq_type,
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100259};
260
261static void
262gpio_irq_handler(unsigned irq, struct irq_desc *desc)
263{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400264 struct davinci_gpio_regs __iomem *g = irq2regs(irq);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100265 u32 mask = 0xffff;
266
267 /* we only care about one bank */
268 if (irq & 1)
269 mask <<= 16;
270
271 /* temporarily mask (level sensitive) parent IRQ */
Lennert Buytenhek23265442010-11-29 10:27:27 +0100272 desc->irq_data.chip->irq_mask(&desc->irq_data);
273 desc->irq_data.chip->irq_ack(&desc->irq_data);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100274 while (1) {
275 u32 status;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100276 int n;
277 int res;
278
279 /* ack any irqs */
280 status = __raw_readl(&g->intstat) & mask;
281 if (!status)
282 break;
283 __raw_writel(status, &g->intstat);
284 if (irq & 1)
285 status >>= 16;
286
287 /* now demux them to the right lowlevel handler */
288 n = (int)get_irq_data(irq);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100289 while (status) {
290 res = ffs(status);
291 n += res;
Dmitry Baryshkovd8aa0252008-10-09 13:36:24 +0100292 generic_handle_irq(n - 1);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100293 status >>= res;
294 }
295 }
Lennert Buytenhek23265442010-11-29 10:27:27 +0100296 desc->irq_data.chip->irq_unmask(&desc->irq_data);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100297 /* now it may re-trigger */
298}
299
David Brownell7a360712009-06-25 17:01:31 -0700300static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
301{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400302 struct davinci_gpio_controller *d = chip2controller(chip);
David Brownell7a360712009-06-25 17:01:31 -0700303
304 if (d->irq_base >= 0)
305 return d->irq_base + offset;
306 else
307 return -ENODEV;
308}
309
310static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
311{
312 struct davinci_soc_info *soc_info = &davinci_soc_info;
313
314 /* NOTE: we assume for now that only irqs in the first gpio_chip
315 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
316 */
317 if (offset < soc_info->gpio_unbanked)
318 return soc_info->gpio_irq + offset;
319 else
320 return -ENODEV;
321}
322
Lennert Buytenhek23265442010-11-29 10:27:27 +0100323static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
David Brownell7a360712009-06-25 17:01:31 -0700324{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100325 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
326 u32 mask = (u32) irq_data_get_irq_data(d);
David Brownell7a360712009-06-25 17:01:31 -0700327
328 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
329 return -EINVAL;
330
331 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
332 ? &g->set_falling : &g->clr_falling);
333 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
334 ? &g->set_rising : &g->clr_rising);
335
336 return 0;
337}
338
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100339/*
David Brownell474dad52008-12-07 11:46:23 -0800340 * NOTE: for suspend/resume, probably best to make a platform_device with
341 * suspend_late/resume_resume calls hooking into results of the set_wake()
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100342 * calls ... so if no gpios are wakeup events the clock can be disabled,
343 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
David Brownell474dad52008-12-07 11:46:23 -0800344 * (dm6446) can be set appropriately for GPIOV33 pins.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100345 */
346
347static int __init davinci_gpio_irq_setup(void)
348{
349 unsigned gpio, irq, bank;
350 struct clk *clk;
David Brownell474dad52008-12-07 11:46:23 -0800351 u32 binten = 0;
Mark A. Greera9949552009-04-15 12:40:35 -0700352 unsigned ngpio, bank_irq;
353 struct davinci_soc_info *soc_info = &davinci_soc_info;
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400354 struct davinci_gpio_regs __iomem *g;
David Brownell474dad52008-12-07 11:46:23 -0800355
Mark A. Greera9949552009-04-15 12:40:35 -0700356 ngpio = soc_info->gpio_num;
357
358 bank_irq = soc_info->gpio_irq;
359 if (bank_irq == 0) {
David Brownell474dad52008-12-07 11:46:23 -0800360 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
361 return -EINVAL;
362 }
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100363
364 clk = clk_get(NULL, "gpio");
365 if (IS_ERR(clk)) {
366 printk(KERN_ERR "Error %ld getting gpio clock?\n",
367 PTR_ERR(clk));
David Brownell474dad52008-12-07 11:46:23 -0800368 return PTR_ERR(clk);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100369 }
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100370 clk_enable(clk);
371
David Brownell7a360712009-06-25 17:01:31 -0700372 /* Arrange gpio_to_irq() support, handling either direct IRQs or
373 * banked IRQs. Having GPIOs in the first GPIO bank use direct
374 * IRQs, while the others use banked IRQs, would need some setup
375 * tweaks to recognize hardware which can do that.
376 */
377 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
378 chips[bank].chip.to_irq = gpio_to_irq_banked;
379 chips[bank].irq_base = soc_info->gpio_unbanked
380 ? -EINVAL
381 : (soc_info->intc_irq_num + gpio);
382 }
383
384 /*
385 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
386 * controller only handling trigger modes. We currently assume no
387 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
388 */
389 if (soc_info->gpio_unbanked) {
390 static struct irq_chip gpio_irqchip_unbanked;
391
392 /* pass "bank 0" GPIO IRQs to AINTC */
393 chips[0].chip.to_irq = gpio_to_irq_unbanked;
394 binten = BIT(0);
395
396 /* AINTC handles mask/unmask; GPIO handles triggering */
397 irq = bank_irq;
398 gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
399 gpio_irqchip_unbanked.name = "GPIO-AINTC";
Lennert Buytenhek23265442010-11-29 10:27:27 +0100400 gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
David Brownell7a360712009-06-25 17:01:31 -0700401
402 /* default trigger: both edges */
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400403 g = gpio2regs(0);
David Brownell7a360712009-06-25 17:01:31 -0700404 __raw_writel(~0, &g->set_falling);
405 __raw_writel(~0, &g->set_rising);
406
407 /* set the direct IRQs up to use that irqchip */
408 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
409 set_irq_chip(irq, &gpio_irqchip_unbanked);
410 set_irq_data(irq, (void *) __gpio_mask(gpio));
Kevin Hilman21ce8732010-02-25 16:49:56 -0800411 set_irq_chip_data(irq, (__force void *) g);
David Brownell7a360712009-06-25 17:01:31 -0700412 irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
413 }
414
415 goto done;
416 }
417
418 /*
419 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
420 * then chain through our own handler.
421 */
David Brownell474dad52008-12-07 11:46:23 -0800422 for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
423 gpio < ngpio;
424 bank++, bank_irq++) {
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100425 unsigned i;
426
David Brownell7a360712009-06-25 17:01:31 -0700427 /* disabled by default, enabled only as needed */
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400428 g = gpio2regs(gpio);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100429 __raw_writel(~0, &g->clr_falling);
430 __raw_writel(~0, &g->clr_rising);
431
432 /* set up all irqs in this bank */
David Brownell474dad52008-12-07 11:46:23 -0800433 set_irq_chained_handler(bank_irq, gpio_irq_handler);
Kevin Hilman21ce8732010-02-25 16:49:56 -0800434 set_irq_chip_data(bank_irq, (__force void *) g);
435 set_irq_data(bank_irq, (void *) irq);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100436
David Brownell474dad52008-12-07 11:46:23 -0800437 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100438 set_irq_chip(irq, &gpio_irqchip);
Kevin Hilman21ce8732010-02-25 16:49:56 -0800439 set_irq_chip_data(irq, (__force void *) g);
David Brownell7a360712009-06-25 17:01:31 -0700440 set_irq_data(irq, (void *) __gpio_mask(gpio));
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100441 set_irq_handler(irq, handle_simple_irq);
442 set_irq_flags(irq, IRQF_VALID);
443 }
David Brownell474dad52008-12-07 11:46:23 -0800444
445 binten |= BIT(bank);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100446 }
447
David Brownell7a360712009-06-25 17:01:31 -0700448done:
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100449 /* BINTEN -- per-bank interrupt enable. genirq would also let these
450 * bits be set/cleared dynamically.
451 */
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400452 __raw_writel(binten, gpio_base + 0x08);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100453
454 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
455
456 return 0;
457}