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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04002 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
Alan Coxd96212e2005-12-08 19:19:50 +000040 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
Alan2c5ff672006-12-04 16:33:20 +000043 * driver the list of errata that are relevant is below, going back to
Alan Coxd96212e2005-12-08 19:19:50 +000044 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
Jeff Garzik6248e642005-10-30 06:42:18 -050091#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070092#include <scsi/scsi_host.h>
93#include <linux/libata.h>
Tejun Heob8b275e2007-07-10 15:55:43 +090094#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070095
96#define DRV_NAME "ata_piix"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040097#define DRV_VERSION "2.12"
Linus Torvalds1da177e2005-04-16 15:20:36 -070098
99enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
Tejun Heoc7290722008-01-18 18:36:30 +0900103 PIIX_SIDPR_BAR = 5,
104 PIIX_SIDPR_LEN = 16,
105 PIIX_SIDPR_IDX = 0,
106 PIIX_SIDPR_DATA = 4,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107
Tejun Heoff0fc142005-12-18 17:17:07 +0900108 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
Tejun Heoc7290722008-01-18 18:36:30 +0900109 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
Tejun Heo800b3992006-12-03 21:34:13 +0900111 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
112 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
Tejun Heob3362f82006-11-10 18:08:10 +0900113
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 PIIX_80C_PRI = (1 << 5) | (1 << 4),
115 PIIX_80C_SEC = (1 << 7) | (1 << 6),
116
Tejun Heod33f58b2006-03-01 01:25:39 +0900117 /* constants for mapping table */
118 P0 = 0, /* port 0 */
119 P1 = 1, /* port 1 */
120 P2 = 2, /* port 2 */
121 P3 = 3, /* port 3 */
122 IDE = -1, /* IDE */
123 NA = -2, /* not avaliable */
124 RV = -3, /* reserved */
125
Greg Felix7b6dbd62005-07-28 15:54:15 -0400126 PIIX_AHCI_DEVICE = 6,
Tejun Heob8b275e2007-07-10 15:55:43 +0900127
128 /* host->flags bits */
129 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130};
131
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900132enum piix_controller_ids {
133 /* controller IDs */
134 piix_pata_mwdma, /* PIIX3 MWDMA only */
135 piix_pata_33, /* PIIX4 at 33Mhz */
136 ich_pata_33, /* ICH up to UDMA 33 only */
137 ich_pata_66, /* ICH up to 66 Mhz */
138 ich_pata_100, /* ICH up to UDMA 100 */
139 ich5_sata,
140 ich6_sata,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900141 ich6m_sata,
142 ich8_sata,
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900143 ich8_2port_sata,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900144 ich8m_apple_sata, /* locks up on second port enable */
145 tolapai_sata,
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900146 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
147};
148
Tejun Heod33f58b2006-03-01 01:25:39 +0900149struct piix_map_db {
150 const u32 mask;
Jeff Garzik73291a12006-07-11 13:11:17 -0400151 const u16 port_enable;
Tejun Heod33f58b2006-03-01 01:25:39 +0900152 const int map[][4];
153};
154
Tejun Heod96715c2006-06-29 01:58:28 +0900155struct piix_host_priv {
156 const int *map;
Tejun Heoc7290722008-01-18 18:36:30 +0900157 void __iomem *sidpr;
Tejun Heod96715c2006-06-29 01:58:28 +0900158};
159
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400160static int piix_init_one(struct pci_dev *pdev,
161 const struct pci_device_id *ent);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900162static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400163static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
164static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
165static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
Alan Coxeb4a2c72007-04-11 00:04:20 +0100166static int ich_pata_cable_detect(struct ata_port *ap);
Tejun Heo25f98132008-01-07 19:38:53 +0900167static u8 piix_vmw_bmdma_status(struct ata_port *ap);
Tejun Heoc7290722008-01-18 18:36:30 +0900168static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val);
169static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val);
Tejun Heob8b275e2007-07-10 15:55:43 +0900170#ifdef CONFIG_PM
171static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
172static int piix_pci_device_resume(struct pci_dev *pdev);
173#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174
175static unsigned int in_module_init = 1;
176
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500177static const struct pci_device_id piix_pci_tbl[] = {
Aland2cdfc02007-01-10 17:13:38 +0000178 /* Intel PIIX3 for the 430HX etc */
179 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
Tejun Heo25f98132008-01-07 19:38:53 +0900180 /* VMware ICH4 */
181 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400182 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
183 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
184 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400185 /* Intel PIIX4 */
186 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
187 /* Intel PIIX4 */
188 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
189 /* Intel PIIX */
190 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191 /* Intel ICH (i810, i815, i840) UDMA 66*/
192 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
193 /* Intel ICH0 : UDMA 33*/
194 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
195 /* Intel ICH2M */
196 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
198 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* Intel ICH3M */
200 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH3 (E7500/1) UDMA 100 */
202 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
204 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* Intel ICH5 */
Christian Lamparter2eb829e2007-08-10 13:59:51 -0700207 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400208 /* C-ICH (i810E2) */
209 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik85cd7252006-08-31 00:03:49 -0400210 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400211 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* ICH6 (and 6) (i915) UDMA 100 */
213 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 /* ICH7/7-R (i945, i975) UDMA 100*/
Christian Lamparter2eb829e2007-08-10 13:59:51 -0700215 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400216 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Christian Lamparterc1e6f282007-07-03 10:19:20 -0400217 /* ICH8 Mobile PATA Controller */
218 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219
220 /* NOTE: The following PCI ids must be kept in sync with the
221 * list in drivers/pci/quirks.c.
222 */
223
Tejun Heo1d076e52006-03-01 01:25:39 +0900224 /* 82801EB (ICH5) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900226 /* 82801EB (ICH5) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900228 /* 6300ESB (ICH5 variant with broken PCS present bits) */
Tejun Heo5e56a372006-11-10 18:08:10 +0900229 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900230 /* 6300ESB pretending RAID */
Tejun Heo5e56a372006-11-10 18:08:10 +0900231 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900232 /* 82801FB/FW (ICH6/ICH6W) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900234 /* 82801FR/FRW (ICH6R/ICH6RW) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900235 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo5016d7d2008-03-26 15:46:58 +0900236 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
237 * Attach iff the controller is in IDE mode. */
238 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900239 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900240 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900241 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900242 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900243 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800244 /* Enterprise Southbridge 2 (631xESB/632xESB) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900245 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800246 /* SATA Controller 1 IDE (ICH8) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900247 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800248 /* SATA Controller 2 IDE (ICH8) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900249 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900250 /* Mobile SATA Controller IDE (ICH8M), Apple */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900251 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
Tejun Heo23cf2962008-05-29 22:04:22 +0900252 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
253 /* Mobile SATA Controller IDE (ICH8M) */
254 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800255 /* SATA Controller IDE (ICH9) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900256 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800257 /* SATA Controller IDE (ICH9) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900258 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800259 /* SATA Controller IDE (ICH9) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900260 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800261 /* SATA Controller IDE (ICH9M) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900262 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800263 /* SATA Controller IDE (ICH9M) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900264 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800265 /* SATA Controller IDE (ICH9M) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900266 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700267 /* SATA Controller IDE (Tolapai) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900268 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800269 /* SATA Controller IDE (ICH10) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900270 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800271 /* SATA Controller IDE (ICH10) */
272 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
273 /* SATA Controller IDE (ICH10) */
Tejun Heo9c0bf672008-03-26 16:00:58 +0900274 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800275 /* SATA Controller IDE (ICH10) */
276 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277
278 { } /* terminate list */
279};
280
281static struct pci_driver piix_pci_driver = {
282 .name = DRV_NAME,
283 .id_table = piix_pci_tbl,
284 .probe = piix_init_one,
285 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900286#ifdef CONFIG_PM
Tejun Heob8b275e2007-07-10 15:55:43 +0900287 .suspend = piix_pci_device_suspend,
288 .resume = piix_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900289#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290};
291
Jeff Garzik193515d2005-11-07 00:59:37 -0500292static struct scsi_host_template piix_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900293 ATA_BMDMA_SHT(DRV_NAME),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294};
295
Tejun Heo029cfd62008-03-25 12:22:49 +0900296static struct ata_port_operations piix_pata_ops = {
297 .inherits = &ata_bmdma_port_ops,
Alan Coxeb4a2c72007-04-11 00:04:20 +0100298 .cable_detect = ata_cable_40wire,
Tejun Heo25f98132008-01-07 19:38:53 +0900299 .set_piomode = piix_set_piomode,
300 .set_dmamode = piix_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900301 .prereset = piix_pata_prereset,
Tejun Heo029cfd62008-03-25 12:22:49 +0900302};
Tejun Heo25f98132008-01-07 19:38:53 +0900303
Tejun Heo029cfd62008-03-25 12:22:49 +0900304static struct ata_port_operations piix_vmw_ops = {
305 .inherits = &piix_pata_ops,
Tejun Heo25f98132008-01-07 19:38:53 +0900306 .bmdma_status = piix_vmw_bmdma_status,
Tejun Heo25f98132008-01-07 19:38:53 +0900307};
308
Tejun Heo029cfd62008-03-25 12:22:49 +0900309static struct ata_port_operations ich_pata_ops = {
310 .inherits = &piix_pata_ops,
311 .cable_detect = ich_pata_cable_detect,
312 .set_dmamode = ich_set_dmamode,
313};
Tejun Heoc7290722008-01-18 18:36:30 +0900314
Tejun Heo029cfd62008-03-25 12:22:49 +0900315static struct ata_port_operations piix_sata_ops = {
316 .inherits = &ata_bmdma_port_ops,
317};
Tejun Heoc7290722008-01-18 18:36:30 +0900318
Tejun Heo029cfd62008-03-25 12:22:49 +0900319static struct ata_port_operations piix_sidpr_sata_ops = {
320 .inherits = &piix_sata_ops,
Tejun Heo57c9efd2008-04-07 22:47:19 +0900321 .hardreset = sata_std_hardreset,
Tejun Heoc7290722008-01-18 18:36:30 +0900322 .scr_read = piix_sidpr_scr_read,
323 .scr_write = piix_sidpr_scr_write,
Tejun Heoc7290722008-01-18 18:36:30 +0900324};
325
Tejun Heod96715c2006-06-29 01:58:28 +0900326static const struct piix_map_db ich5_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900327 .mask = 0x7,
Jeff Garzikea35d292006-07-11 11:48:50 -0400328 .port_enable = 0x3,
Tejun Heod33f58b2006-03-01 01:25:39 +0900329 .map = {
330 /* PM PS SM SS MAP */
331 { P0, NA, P1, NA }, /* 000b */
332 { P1, NA, P0, NA }, /* 001b */
333 { RV, RV, RV, RV },
334 { RV, RV, RV, RV },
335 { P0, P1, IDE, IDE }, /* 100b */
336 { P1, P0, IDE, IDE }, /* 101b */
337 { IDE, IDE, P0, P1 }, /* 110b */
338 { IDE, IDE, P1, P0 }, /* 111b */
339 },
340};
341
Tejun Heod96715c2006-06-29 01:58:28 +0900342static const struct piix_map_db ich6_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900343 .mask = 0x3,
Jeff Garzikea35d292006-07-11 11:48:50 -0400344 .port_enable = 0xf,
Tejun Heod33f58b2006-03-01 01:25:39 +0900345 .map = {
346 /* PM PS SM SS MAP */
Tejun Heo79ea24e2006-03-31 20:01:50 +0900347 { P0, P2, P1, P3 }, /* 00b */
Tejun Heod33f58b2006-03-01 01:25:39 +0900348 { IDE, IDE, P1, P3 }, /* 01b */
349 { P0, P2, IDE, IDE }, /* 10b */
350 { RV, RV, RV, RV },
351 },
352};
353
Tejun Heod96715c2006-06-29 01:58:28 +0900354static const struct piix_map_db ich6m_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900355 .mask = 0x3,
Jeff Garzikea35d292006-07-11 11:48:50 -0400356 .port_enable = 0x5,
Tejun Heo67083742006-09-11 06:29:03 +0900357
358 /* Map 01b isn't specified in the doc but some notebooks use
Tejun Heoc6446a42006-10-09 13:23:58 +0900359 * it anyway. MAP 01b have been spotted on both ICH6M and
360 * ICH7M.
Tejun Heo67083742006-09-11 06:29:03 +0900361 */
362 .map = {
363 /* PM PS SM SS MAP */
Tejun Heoe04b3b92007-07-10 17:58:21 +0900364 { P0, P2, NA, NA }, /* 00b */
Tejun Heo67083742006-09-11 06:29:03 +0900365 { IDE, IDE, P1, P3 }, /* 01b */
366 { P0, P2, IDE, IDE }, /* 10b */
367 { RV, RV, RV, RV },
368 },
369};
370
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400371static const struct piix_map_db ich8_map_db = {
372 .mask = 0x3,
Tejun Heoa0ce9ac2007-11-19 12:06:37 +0900373 .port_enable = 0xf,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400374 .map = {
375 /* PM PS SM SS MAP */
Kristen Carlson Accardi158f30c82006-10-19 13:27:39 -0700376 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400377 { RV, RV, RV, RV },
Tejun Heoac2b0432007-08-07 02:43:27 +0900378 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400379 { RV, RV, RV, RV },
380 },
381};
382
Tejun Heo00242ec2007-11-19 11:24:25 +0900383static const struct piix_map_db ich8_2port_map_db = {
Jason Gastone2d352a2007-09-07 17:21:03 -0700384 .mask = 0x3,
385 .port_enable = 0x3,
386 .map = {
387 /* PM PS SM SS MAP */
388 { P0, NA, P1, NA }, /* 00b */
389 { RV, RV, RV, RV }, /* 01b */
390 { RV, RV, RV, RV }, /* 10b */
391 { RV, RV, RV, RV },
392 },
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700393};
394
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900395static const struct piix_map_db ich8m_apple_map_db = {
396 .mask = 0x3,
397 .port_enable = 0x1,
398 .map = {
399 /* PM PS SM SS MAP */
400 { P0, NA, NA, NA }, /* 00b */
401 { RV, RV, RV, RV },
402 { P0, P2, IDE, IDE }, /* 10b */
403 { RV, RV, RV, RV },
404 },
405};
406
Tejun Heo00242ec2007-11-19 11:24:25 +0900407static const struct piix_map_db tolapai_map_db = {
Jason Gaston8f73a682007-10-11 16:05:15 -0700408 .mask = 0x3,
409 .port_enable = 0x3,
410 .map = {
411 /* PM PS SM SS MAP */
412 { P0, NA, P1, NA }, /* 00b */
413 { RV, RV, RV, RV }, /* 01b */
414 { RV, RV, RV, RV }, /* 10b */
415 { RV, RV, RV, RV },
416 },
417};
418
Tejun Heod96715c2006-06-29 01:58:28 +0900419static const struct piix_map_db *piix_map_db_table[] = {
420 [ich5_sata] = &ich5_map_db,
Tejun Heod96715c2006-06-29 01:58:28 +0900421 [ich6_sata] = &ich6_map_db,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900422 [ich6m_sata] = &ich6m_map_db,
423 [ich8_sata] = &ich8_map_db,
Tejun Heo00242ec2007-11-19 11:24:25 +0900424 [ich8_2port_sata] = &ich8_2port_map_db,
Tejun Heo9c0bf672008-03-26 16:00:58 +0900425 [ich8m_apple_sata] = &ich8m_apple_map_db,
426 [tolapai_sata] = &tolapai_map_db,
Tejun Heod96715c2006-06-29 01:58:28 +0900427};
428
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429static struct ata_port_info piix_port_info[] = {
Tejun Heo00242ec2007-11-19 11:24:25 +0900430 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
431 {
Tejun Heo00242ec2007-11-19 11:24:25 +0900432 .flags = PIIX_PATA_FLAGS,
433 .pio_mask = 0x1f, /* pio0-4 */
434 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
435 .port_ops = &piix_pata_ops,
436 },
437
Jeff Garzikec300d92007-09-01 07:17:36 -0400438 [piix_pata_33] = /* PIIX4 at 33MHz */
Tejun Heo1d076e52006-03-01 01:25:39 +0900439 {
Tejun Heob3362f82006-11-10 18:08:10 +0900440 .flags = PIIX_PATA_FLAGS,
Tejun Heo1d076e52006-03-01 01:25:39 +0900441 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400442 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
Tejun Heo1d076e52006-03-01 01:25:39 +0900443 .udma_mask = ATA_UDMA_MASK_40C,
444 .port_ops = &piix_pata_ops,
445 },
446
Jeff Garzikec300d92007-09-01 07:17:36 -0400447 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448 {
Tejun Heob3362f82006-11-10 18:08:10 +0900449 .flags = PIIX_PATA_FLAGS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400450 .pio_mask = 0x1f, /* pio 0-4 */
451 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
452 .udma_mask = ATA_UDMA2, /* UDMA33 */
453 .port_ops = &ich_pata_ops,
454 },
Jeff Garzikec300d92007-09-01 07:17:36 -0400455
456 [ich_pata_66] = /* ICH controllers up to 66MHz */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400457 {
Tejun Heob3362f82006-11-10 18:08:10 +0900458 .flags = PIIX_PATA_FLAGS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400459 .pio_mask = 0x1f, /* pio 0-4 */
460 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
461 .udma_mask = ATA_UDMA4,
462 .port_ops = &ich_pata_ops,
463 },
Jeff Garzik85cd7252006-08-31 00:03:49 -0400464
Jeff Garzikec300d92007-09-01 07:17:36 -0400465 [ich_pata_100] =
Jeff Garzik669a5db2006-08-29 18:12:40 -0400466 {
Tejun Heob3362f82006-11-10 18:08:10 +0900467 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468 .pio_mask = 0x1f, /* pio0-4 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469 .mwdma_mask = 0x06, /* mwdma1-2 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400470 .udma_mask = ATA_UDMA5, /* udma0-5 */
471 .port_ops = &ich_pata_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472 },
473
Jeff Garzikec300d92007-09-01 07:17:36 -0400474 [ich5_sata] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475 {
Tejun Heo228c1592006-11-10 18:08:10 +0900476 .flags = PIIX_SATA_FLAGS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477 .pio_mask = 0x1f, /* pio0-4 */
478 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400479 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480 .port_ops = &piix_sata_ops,
481 },
482
Jeff Garzikec300d92007-09-01 07:17:36 -0400483 [ich6_sata] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484 {
Tejun Heo723159c2008-01-04 18:42:20 +0900485 .flags = PIIX_SATA_FLAGS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486 .pio_mask = 0x1f, /* pio0-4 */
487 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400488 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489 .port_ops = &piix_sata_ops,
490 },
491
Tejun Heo9c0bf672008-03-26 16:00:58 +0900492 [ich6m_sata] =
Jason Gastonc368ca42005-04-16 15:24:44 -0700493 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900494 .flags = PIIX_SATA_FLAGS,
Jason Gastonc368ca42005-04-16 15:24:44 -0700495 .pio_mask = 0x1f, /* pio0-4 */
496 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400497 .udma_mask = ATA_UDMA6,
Jason Gastonc368ca42005-04-16 15:24:44 -0700498 .port_ops = &piix_sata_ops,
499 },
Tejun Heo1d076e52006-03-01 01:25:39 +0900500
Tejun Heo9c0bf672008-03-26 16:00:58 +0900501 [ich8_sata] =
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400502 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900503 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400504 .pio_mask = 0x1f, /* pio0-4 */
505 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400506 .udma_mask = ATA_UDMA6,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400507 .port_ops = &piix_sata_ops,
508 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400509
Tejun Heo00242ec2007-11-19 11:24:25 +0900510 [ich8_2port_sata] =
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700511 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900512 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700513 .pio_mask = 0x1f, /* pio0-4 */
514 .mwdma_mask = 0x07, /* mwdma0-2 */
515 .udma_mask = ATA_UDMA6,
516 .port_ops = &piix_sata_ops,
517 },
Jason Gaston8f73a682007-10-11 16:05:15 -0700518
Tejun Heo9c0bf672008-03-26 16:00:58 +0900519 [tolapai_sata] =
Jason Gaston8f73a682007-10-11 16:05:15 -0700520 {
Tejun Heo5016d7d2008-03-26 15:46:58 +0900521 .flags = PIIX_SATA_FLAGS,
Jason Gaston8f73a682007-10-11 16:05:15 -0700522 .pio_mask = 0x1f, /* pio0-4 */
523 .mwdma_mask = 0x07, /* mwdma0-2 */
524 .udma_mask = ATA_UDMA6,
525 .port_ops = &piix_sata_ops,
526 },
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900527
Tejun Heo9c0bf672008-03-26 16:00:58 +0900528 [ich8m_apple_sata] =
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900529 {
Tejun Heo23cf2962008-05-29 22:04:22 +0900530 .flags = PIIX_SATA_FLAGS,
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900531 .pio_mask = 0x1f, /* pio0-4 */
532 .mwdma_mask = 0x07, /* mwdma0-2 */
533 .udma_mask = ATA_UDMA6,
534 .port_ops = &piix_sata_ops,
535 },
536
Tejun Heo25f98132008-01-07 19:38:53 +0900537 [piix_pata_vmw] =
538 {
Tejun Heo25f98132008-01-07 19:38:53 +0900539 .flags = PIIX_PATA_FLAGS,
540 .pio_mask = 0x1f, /* pio0-4 */
541 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
542 .udma_mask = ATA_UDMA_MASK_40C,
543 .port_ops = &piix_vmw_ops,
544 },
545
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546};
547
548static struct pci_bits piix_enable_bits[] = {
549 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
550 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
551};
552
553MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
554MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
555MODULE_LICENSE("GPL");
556MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
557MODULE_VERSION(DRV_VERSION);
558
Alan Coxfc085152006-10-10 14:28:11 -0700559struct ich_laptop {
560 u16 device;
561 u16 subvendor;
562 u16 subdevice;
563};
564
565/*
566 * List of laptops that use short cables rather than 80 wire
567 */
568
569static const struct ich_laptop ich_laptop[] = {
570 /* devid, subvendor, subdev */
571 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
Alan Cox2655e2c2007-11-05 22:51:09 +0000572 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
J Jbabfb682007-01-09 02:26:30 +0900573 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
Robin H\. Johnson12340102007-03-28 18:02:07 -0700574 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
Jeff Garzik54174db2007-09-29 04:01:43 -0400575 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
Tejun Heob33620f2007-05-22 11:34:22 +0200576 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
Dan McGee01ce2602008-04-20 22:03:27 -0500577 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
Alan Coxfc085152006-10-10 14:28:11 -0700578 /* end marker */
579 { 0, }
580};
581
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582/**
Alan Coxeb4a2c72007-04-11 00:04:20 +0100583 * ich_pata_cable_detect - Probe host controller cable detect info
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584 * @ap: Port for which cable detect info is desired
585 *
586 * Read 80c cable indicator from ATA PCI device's PCI config
587 * register. This register is normally set by firmware (BIOS).
588 *
589 * LOCKING:
590 * None (inherited from caller).
591 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400592
Alan Coxeb4a2c72007-04-11 00:04:20 +0100593static int ich_pata_cable_detect(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594{
Jeff Garzikcca39742006-08-24 03:19:22 -0400595 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan Coxfc085152006-10-10 14:28:11 -0700596 const struct ich_laptop *lap = &ich_laptop[0];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597 u8 tmp, mask;
598
Alan Coxfc085152006-10-10 14:28:11 -0700599 /* Check for specials - Acer Aspire 5602WLMi */
600 while (lap->device) {
601 if (lap->device == pdev->device &&
602 lap->subvendor == pdev->subsystem_vendor &&
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400603 lap->subdevice == pdev->subsystem_device)
Alan Coxeb4a2c72007-04-11 00:04:20 +0100604 return ATA_CBL_PATA40_SHORT;
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400605
Alan Coxfc085152006-10-10 14:28:11 -0700606 lap++;
607 }
608
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609 /* check BIOS cable detect results */
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900610 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
612 if ((tmp & mask) == 0)
Alan Coxeb4a2c72007-04-11 00:04:20 +0100613 return ATA_CBL_PATA40;
614 return ATA_CBL_PATA80;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615}
616
617/**
Tejun Heoccc46722006-05-31 18:28:14 +0900618 * piix_pata_prereset - prereset for PATA host controller
Tejun Heocc0680a2007-08-06 18:36:23 +0900619 * @link: Target link
Tejun Heod4b2bab2007-02-02 16:50:52 +0900620 * @deadline: deadline jiffies for the operation
Linus Torvalds1da177e2005-04-16 15:20:36 -0700621 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622 * LOCKING:
623 * None (inherited from caller).
624 */
Tejun Heocc0680a2007-08-06 18:36:23 +0900625static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626{
Tejun Heocc0680a2007-08-06 18:36:23 +0900627 struct ata_port *ap = link->ap;
Jeff Garzikcca39742006-08-24 03:19:22 -0400628 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629
Alan Coxc9619222006-09-26 17:53:38 +0100630 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
631 return -ENOENT;
Tejun Heo9363c382008-04-07 22:47:16 +0900632 return ata_sff_prereset(link, deadline);
Tejun Heoccc46722006-05-31 18:28:14 +0900633}
634
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635/**
636 * piix_set_piomode - Initialize host controller PATA PIO timings
637 * @ap: Port whose timings we are configuring
638 * @adev: um
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639 *
640 * Set PIO mode for device, in host controller PCI config space.
641 *
642 * LOCKING:
643 * None (inherited from caller).
644 */
645
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400646static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647{
648 unsigned int pio = adev->pio_mode - XFER_PIO_0;
Jeff Garzikcca39742006-08-24 03:19:22 -0400649 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650 unsigned int is_slave = (adev->devno != 0);
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900651 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652 unsigned int slave_port = 0x44;
653 u16 master_data;
654 u8 slave_data;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400655 u8 udma_enable;
656 int control = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400657
Jeff Garzik669a5db2006-08-29 18:12:40 -0400658 /*
659 * See Intel Document 298600-004 for the timing programing rules
660 * for ICH controllers.
661 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662
663 static const /* ISP RTC */
664 u8 timings[][2] = { { 0, 0 },
665 { 0, 0 },
666 { 1, 0 },
667 { 2, 1 },
668 { 2, 3 }, };
669
Jeff Garzik669a5db2006-08-29 18:12:40 -0400670 if (pio >= 2)
671 control |= 1; /* TIME1 enable */
672 if (ata_pio_need_iordy(adev))
673 control |= 2; /* IE enable */
674
Jeff Garzik85cd7252006-08-31 00:03:49 -0400675 /* Intel specifies that the PPE functionality is for disk only */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400676 if (adev->class == ATA_DEV_ATA)
677 control |= 4; /* PPE enable */
678
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200679 /* PIO configuration clears DTE unconditionally. It will be
680 * programmed in set_dmamode which is guaranteed to be called
681 * after set_piomode if any DMA mode is available.
682 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 pci_read_config_word(dev, master_port, &master_data);
684 if (is_slave) {
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200685 /* clear TIME1|IE1|PPE1|DTE1 */
686 master_data &= 0xff0f;
Joe Perches1967b7f2008-02-03 17:08:11 +0200687 /* Enable SITRE (separate slave timing register) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 master_data |= 0x4000;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400689 /* enable PPE1, IE1 and TIME1 as needed */
690 master_data |= (control << 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691 pci_read_config_byte(dev, slave_port, &slave_data);
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900692 slave_data &= (ap->port_no ? 0x0f : 0xf0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400693 /* Load the timing nibble for this slave */
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200694 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
695 << (ap->port_no ? 4 : 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696 } else {
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200697 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
698 master_data &= 0xccf0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400699 /* Enable PPE, IE and TIME as appropriate */
700 master_data |= control;
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200701 /* load ISP and RCT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 master_data |=
703 (timings[pio][0] << 12) |
704 (timings[pio][1] << 8);
705 }
706 pci_write_config_word(dev, master_port, master_data);
707 if (is_slave)
708 pci_write_config_byte(dev, slave_port, slave_data);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400709
710 /* Ensure the UDMA bit is off - it will be turned back on if
711 UDMA is selected */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400712
Jeff Garzik669a5db2006-08-29 18:12:40 -0400713 if (ap->udma_mask) {
714 pci_read_config_byte(dev, 0x48, &udma_enable);
715 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
716 pci_write_config_byte(dev, 0x48, udma_enable);
717 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718}
719
720/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400721 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722 * @ap: Port whose timings we are configuring
Jeff Garzik669a5db2006-08-29 18:12:40 -0400723 * @adev: Drive in question
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724 * @udma: udma mode, 0 - 6
Hennec32a8fd2006-09-25 22:00:46 +0200725 * @isich: set if the chip is an ICH device
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726 *
727 * Set UDMA mode for device, in host controller PCI config space.
728 *
729 * LOCKING:
730 * None (inherited from caller).
731 */
732
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400733static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734{
Jeff Garzikcca39742006-08-24 03:19:22 -0400735 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400736 u8 master_port = ap->port_no ? 0x42 : 0x40;
737 u16 master_data;
738 u8 speed = adev->dma_mode;
739 int devid = adev->devno + 2 * ap->port_no;
Andrew Mortondedf61db2007-01-10 17:20:34 -0800740 u8 udma_enable = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400741
Jeff Garzik669a5db2006-08-29 18:12:40 -0400742 static const /* ISP RTC */
743 u8 timings[][2] = { { 0, 0 },
744 { 0, 0 },
745 { 1, 0 },
746 { 2, 1 },
747 { 2, 3 }, };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748
Jeff Garzik669a5db2006-08-29 18:12:40 -0400749 pci_read_config_word(dev, master_port, &master_data);
Aland2cdfc02007-01-10 17:13:38 +0000750 if (ap->udma_mask)
751 pci_read_config_byte(dev, 0x48, &udma_enable);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752
753 if (speed >= XFER_UDMA_0) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400754 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
755 u16 udma_timing;
756 u16 ideconf;
757 int u_clock, u_speed;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400758
Jeff Garzik669a5db2006-08-29 18:12:40 -0400759 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400760 * UDMA is handled by a combination of clock switching and
Jeff Garzik85cd7252006-08-31 00:03:49 -0400761 * selection of dividers
762 *
Jeff Garzik669a5db2006-08-29 18:12:40 -0400763 * Handy rule: Odd modes are UDMATIMx 01, even are 02
Jeff Garzik85cd7252006-08-31 00:03:49 -0400764 * except UDMA0 which is 00
Jeff Garzik669a5db2006-08-29 18:12:40 -0400765 */
766 u_speed = min(2 - (udma & 1), udma);
767 if (udma == 5)
768 u_clock = 0x1000; /* 100Mhz */
769 else if (udma > 2)
770 u_clock = 1; /* 66Mhz */
771 else
772 u_clock = 0; /* 33Mhz */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400773
Jeff Garzik669a5db2006-08-29 18:12:40 -0400774 udma_enable |= (1 << devid);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400775
Jeff Garzik669a5db2006-08-29 18:12:40 -0400776 /* Load the CT/RP selection */
777 pci_read_config_word(dev, 0x4A, &udma_timing);
778 udma_timing &= ~(3 << (4 * devid));
779 udma_timing |= u_speed << (4 * devid);
780 pci_write_config_word(dev, 0x4A, udma_timing);
781
Jeff Garzik85cd7252006-08-31 00:03:49 -0400782 if (isich) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400783 /* Select a 33/66/100Mhz clock */
784 pci_read_config_word(dev, 0x54, &ideconf);
785 ideconf &= ~(0x1001 << devid);
786 ideconf |= u_clock << devid;
787 /* For ICH or later we should set bit 10 for better
788 performance (WR_PingPong_En) */
789 pci_write_config_word(dev, 0x54, ideconf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700791 } else {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400792 /*
793 * MWDMA is driven by the PIO timings. We must also enable
794 * IORDY unconditionally along with TIME1. PPE has already
795 * been set when the PIO timing was set.
796 */
797 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
798 unsigned int control;
799 u8 slave_data;
800 const unsigned int needed_pio[3] = {
801 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
802 };
803 int pio = needed_pio[mwdma] - XFER_PIO_0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400804
Jeff Garzik669a5db2006-08-29 18:12:40 -0400805 control = 3; /* IORDY|TIME1 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400806
Jeff Garzik669a5db2006-08-29 18:12:40 -0400807 /* If the drive MWDMA is faster than it can do PIO then
808 we must force PIO into PIO0 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400809
Jeff Garzik669a5db2006-08-29 18:12:40 -0400810 if (adev->pio_mode < needed_pio[mwdma])
811 /* Enable DMA timing only */
812 control |= 8; /* PIO cycles in PIO0 */
813
814 if (adev->devno) { /* Slave */
815 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
816 master_data |= control << 4;
817 pci_read_config_byte(dev, 0x44, &slave_data);
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200818 slave_data &= (ap->port_no ? 0x0f : 0xf0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400819 /* Load the matching timing */
820 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
821 pci_write_config_byte(dev, 0x44, slave_data);
822 } else { /* Master */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400823 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
Jeff Garzik669a5db2006-08-29 18:12:40 -0400824 and master timing bits */
825 master_data |= control;
826 master_data |=
827 (timings[pio][0] << 12) |
828 (timings[pio][1] << 8);
829 }
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200830
831 if (ap->udma_mask) {
832 udma_enable &= ~(1 << devid);
833 pci_write_config_word(dev, master_port, master_data);
834 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400836 /* Don't scribble on 0x48 if the controller does not support UDMA */
837 if (ap->udma_mask)
838 pci_write_config_byte(dev, 0x48, udma_enable);
839}
840
841/**
842 * piix_set_dmamode - Initialize host controller PATA DMA timings
843 * @ap: Port whose timings we are configuring
844 * @adev: um
845 *
846 * Set MW/UDMA mode for device, in host controller PCI config space.
847 *
848 * LOCKING:
849 * None (inherited from caller).
850 */
851
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400852static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400853{
854 do_pata_set_dmamode(ap, adev, 0);
855}
856
857/**
858 * ich_set_dmamode - Initialize host controller PATA DMA timings
859 * @ap: Port whose timings we are configuring
860 * @adev: um
861 *
862 * Set MW/UDMA mode for device, in host controller PCI config space.
863 *
864 * LOCKING:
865 * None (inherited from caller).
866 */
867
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400868static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400869{
870 do_pata_set_dmamode(ap, adev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871}
872
Tejun Heoc7290722008-01-18 18:36:30 +0900873/*
874 * Serial ATA Index/Data Pair Superset Registers access
875 *
876 * Beginning from ICH8, there's a sane way to access SCRs using index
877 * and data register pair located at BAR5. This creates an
878 * interesting problem of mapping two SCRs to one port.
879 *
880 * Although they have separate SCRs, the master and slave aren't
881 * independent enough to be treated as separate links - e.g. softreset
882 * resets both. Also, there's no protocol defined for hard resetting
883 * singled device sharing the virtual port (no defined way to acquire
884 * device signature). This is worked around by merging the SCR values
885 * into one sensible value and requesting follow-up SRST after
886 * hardreset.
887 *
888 * SCR merging is perfomed in nibbles which is the unit contents in
889 * SCRs are organized. If two values are equal, the value is used.
890 * When they differ, merge table which lists precedence of possible
891 * values is consulted and the first match or the last entry when
892 * nothing matches is used. When there's no merge table for the
893 * specific nibble, value from the first port is used.
894 */
895static const int piix_sidx_map[] = {
896 [SCR_STATUS] = 0,
897 [SCR_ERROR] = 2,
898 [SCR_CONTROL] = 1,
899};
900
901static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg)
902{
903 struct ata_port *ap = dev->link->ap;
904 struct piix_host_priv *hpriv = ap->host->private_data;
905
906 iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg],
907 hpriv->sidpr + PIIX_SIDPR_IDX);
908}
909
910static int piix_sidpr_read(struct ata_device *dev, unsigned int reg)
911{
912 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
913
914 piix_sidpr_sel(dev, reg);
915 return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
916}
917
918static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val)
919{
920 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
921
922 piix_sidpr_sel(dev, reg);
923 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
924}
925
Adrian Bunk4a537a552008-01-29 00:10:19 +0200926static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)
Tejun Heoc7290722008-01-18 18:36:30 +0900927{
928 u32 val = 0;
929 int i, mi;
930
931 for (i = 0, mi = 0; i < 32 / 4; i++) {
932 u8 c0 = (val0 >> (i * 4)) & 0xf;
933 u8 c1 = (val1 >> (i * 4)) & 0xf;
934 u8 merged = c0;
935 const int *cur;
936
937 /* if no merge preference, assume the first value */
938 cur = merge_tbl[mi];
939 if (!cur)
940 goto done;
941 mi++;
942
943 /* if two values equal, use it */
944 if (c0 == c1)
945 goto done;
946
947 /* choose the first match or the last from the merge table */
948 while (*cur != -1) {
949 if (c0 == *cur || c1 == *cur)
950 break;
951 cur++;
952 }
953 if (*cur == -1)
954 cur--;
955 merged = *cur;
956 done:
957 val |= merged << (i * 4);
958 }
959
960 return val;
961}
962
963static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val)
964{
965 const int * const sstatus_merge_tbl[] = {
966 /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
967 /* SPD */ (const int []){ 2, 1, 0, -1 },
968 /* IPM */ (const int []){ 6, 2, 1, 0, -1 },
969 NULL,
970 };
971 const int * const scontrol_merge_tbl[] = {
972 /* DET */ (const int []){ 1, 0, 4, 0, -1 },
973 /* SPD */ (const int []){ 0, 2, 1, 0, -1 },
974 /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 },
975 NULL,
976 };
977 u32 v0, v1;
978
979 if (reg >= ARRAY_SIZE(piix_sidx_map))
980 return -EINVAL;
981
982 if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) {
983 *val = piix_sidpr_read(&ap->link.device[0], reg);
984 return 0;
985 }
986
987 v0 = piix_sidpr_read(&ap->link.device[0], reg);
988 v1 = piix_sidpr_read(&ap->link.device[1], reg);
989
990 switch (reg) {
991 case SCR_STATUS:
992 *val = piix_merge_scr(v0, v1, sstatus_merge_tbl);
993 break;
994 case SCR_ERROR:
995 *val = v0 | v1;
996 break;
997 case SCR_CONTROL:
998 *val = piix_merge_scr(v0, v1, scontrol_merge_tbl);
999 break;
1000 }
1001
1002 return 0;
1003}
1004
1005static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val)
1006{
1007 if (reg >= ARRAY_SIZE(piix_sidx_map))
1008 return -EINVAL;
1009
1010 piix_sidpr_write(&ap->link.device[0], reg, val);
1011
1012 if (ap->flags & ATA_FLAG_SLAVE_POSS)
1013 piix_sidpr_write(&ap->link.device[1], reg, val);
1014
1015 return 0;
1016}
1017
Tejun Heob8b275e2007-07-10 15:55:43 +09001018#ifdef CONFIG_PM
Tejun Heo8c3832e2007-07-27 14:53:28 +09001019static int piix_broken_suspend(void)
1020{
Jeff Garzik18552562007-10-03 15:15:40 -04001021 static const struct dmi_system_id sysids[] = {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001022 {
Tejun Heo4c74d4e2007-09-30 01:11:20 -07001023 .ident = "TECRA M3",
1024 .matches = {
1025 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1026 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1027 },
1028 },
1029 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001030 .ident = "TECRA M3",
1031 .matches = {
1032 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1033 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1034 },
1035 },
1036 {
Peter Schwenked1aa6902007-12-05 10:39:49 +09001037 .ident = "TECRA M4",
1038 .matches = {
1039 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1040 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1041 },
1042 },
1043 {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001044 .ident = "TECRA M5",
1045 .matches = {
1046 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1047 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1048 },
Tejun Heob8b275e2007-07-10 15:55:43 +09001049 },
Tejun Heo8c3832e2007-07-27 14:53:28 +09001050 {
Peter Schwenkeffe188d2008-01-17 23:08:55 +10001051 .ident = "TECRA M6",
1052 .matches = {
1053 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1054 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1055 },
1056 },
1057 {
Tejun Heo5c08ea02007-08-14 19:56:04 +09001058 .ident = "TECRA M7",
1059 .matches = {
1060 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1061 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1062 },
1063 },
1064 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001065 .ident = "TECRA A8",
1066 .matches = {
1067 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1068 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1069 },
1070 },
1071 {
Peter Schwenkeffe188d2008-01-17 23:08:55 +10001072 .ident = "Satellite R20",
1073 .matches = {
1074 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1075 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1076 },
1077 },
1078 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001079 .ident = "Satellite R25",
1080 .matches = {
1081 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1082 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1083 },
1084 },
1085 {
Tejun Heo3cc0b9d2007-08-25 08:31:02 +09001086 .ident = "Satellite U200",
1087 .matches = {
1088 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1089 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1090 },
1091 },
1092 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001093 .ident = "Satellite U200",
1094 .matches = {
1095 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1096 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1097 },
1098 },
1099 {
Yann Chachkoff62320e22007-11-07 12:02:27 +09001100 .ident = "Satellite Pro U200",
1101 .matches = {
1102 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1103 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1104 },
1105 },
1106 {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001107 .ident = "Satellite U205",
1108 .matches = {
1109 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1110 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1111 },
Tejun Heob8b275e2007-07-10 15:55:43 +09001112 },
Tejun Heo8c3832e2007-07-27 14:53:28 +09001113 {
Tejun Heode753e52007-11-12 17:56:24 +09001114 .ident = "SATELLITE U205",
1115 .matches = {
1116 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1117 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1118 },
1119 },
1120 {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001121 .ident = "Portege M500",
1122 .matches = {
1123 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1124 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1125 },
Tejun Heob8b275e2007-07-10 15:55:43 +09001126 },
Jeff Garzik7d051542007-09-01 06:48:52 -04001127
1128 { } /* terminate list */
Tejun Heo8c3832e2007-07-27 14:53:28 +09001129 };
Tejun Heo7abe79c2007-07-27 14:55:07 +09001130 static const char *oemstrs[] = {
1131 "Tecra M3,",
1132 };
1133 int i;
Tejun Heo8c3832e2007-07-27 14:53:28 +09001134
1135 if (dmi_check_system(sysids))
1136 return 1;
1137
Tejun Heo7abe79c2007-07-27 14:55:07 +09001138 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1139 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1140 return 1;
1141
Tejun Heo8c3832e2007-07-27 14:53:28 +09001142 return 0;
1143}
Tejun Heob8b275e2007-07-10 15:55:43 +09001144
1145static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1146{
1147 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1148 unsigned long flags;
1149 int rc = 0;
1150
1151 rc = ata_host_suspend(host, mesg);
1152 if (rc)
1153 return rc;
1154
1155 /* Some braindamaged ACPI suspend implementations expect the
1156 * controller to be awake on entry; otherwise, it burns cpu
1157 * cycles and power trying to do something to the sleeping
1158 * beauty.
1159 */
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01001160 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
Tejun Heob8b275e2007-07-10 15:55:43 +09001161 pci_save_state(pdev);
1162
1163 /* mark its power state as "unknown", since we don't
1164 * know if e.g. the BIOS will change its device state
1165 * when we suspend.
1166 */
1167 if (pdev->current_state == PCI_D0)
1168 pdev->current_state = PCI_UNKNOWN;
1169
1170 /* tell resume that it's waking up from broken suspend */
1171 spin_lock_irqsave(&host->lock, flags);
1172 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1173 spin_unlock_irqrestore(&host->lock, flags);
1174 } else
1175 ata_pci_device_do_suspend(pdev, mesg);
1176
1177 return 0;
1178}
1179
1180static int piix_pci_device_resume(struct pci_dev *pdev)
1181{
1182 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1183 unsigned long flags;
1184 int rc;
1185
1186 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1187 spin_lock_irqsave(&host->lock, flags);
1188 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1189 spin_unlock_irqrestore(&host->lock, flags);
1190
1191 pci_set_power_state(pdev, PCI_D0);
1192 pci_restore_state(pdev);
1193
1194 /* PCI device wasn't disabled during suspend. Use
Tejun Heo0b62e132007-07-27 14:43:35 +09001195 * pci_reenable_device() to avoid affecting the enable
1196 * count.
Tejun Heob8b275e2007-07-10 15:55:43 +09001197 */
Tejun Heo0b62e132007-07-27 14:43:35 +09001198 rc = pci_reenable_device(pdev);
Tejun Heob8b275e2007-07-10 15:55:43 +09001199 if (rc)
1200 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1201 "device after resume (%d)\n", rc);
1202 } else
1203 rc = ata_pci_device_do_resume(pdev);
1204
1205 if (rc == 0)
1206 ata_host_resume(host);
1207
1208 return rc;
1209}
1210#endif
1211
Tejun Heo25f98132008-01-07 19:38:53 +09001212static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1213{
1214 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1215}
1216
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217#define AHCI_PCI_BAR 5
1218#define AHCI_GLOBAL_CTL 0x04
1219#define AHCI_ENABLE (1 << 31)
1220static int piix_disable_ahci(struct pci_dev *pdev)
1221{
Jeff Garzikea6ba102005-08-30 05:18:18 -04001222 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001223 u32 tmp;
1224 int rc = 0;
1225
1226 /* BUG: pci_enable_device has not yet been called. This
1227 * works because this device is usually set up by BIOS.
1228 */
1229
Jeff Garzik374b1872005-08-30 05:42:52 -04001230 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1231 !pci_resource_len(pdev, AHCI_PCI_BAR))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001232 return 0;
Greg Felix7b6dbd62005-07-28 15:54:15 -04001233
Jeff Garzik374b1872005-08-30 05:42:52 -04001234 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001235 if (!mmio)
1236 return -ENOMEM;
Greg Felix7b6dbd62005-07-28 15:54:15 -04001237
Alan Coxc47a6312007-11-19 14:28:28 +00001238 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239 if (tmp & AHCI_ENABLE) {
1240 tmp &= ~AHCI_ENABLE;
Alan Coxc47a6312007-11-19 14:28:28 +00001241 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001242
Alan Coxc47a6312007-11-19 14:28:28 +00001243 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244 if (tmp & AHCI_ENABLE)
1245 rc = -EIO;
1246 }
Greg Felix7b6dbd62005-07-28 15:54:15 -04001247
Jeff Garzik374b1872005-08-30 05:42:52 -04001248 pci_iounmap(pdev, mmio);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249 return rc;
1250}
1251
1252/**
Alan Coxc621b142005-12-08 19:22:28 +00001253 * piix_check_450nx_errata - Check for problem 450NX setup
Randy Dunlapc893a3a2006-01-28 13:15:32 -05001254 * @ata_dev: the PCI device to check
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001255 *
Alan Coxc621b142005-12-08 19:22:28 +00001256 * Check for the present of 450NX errata #19 and errata #25. If
1257 * they are found return an error code so we can turn off DMA
1258 */
1259
1260static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1261{
1262 struct pci_dev *pdev = NULL;
1263 u16 cfg;
Alan Coxc621b142005-12-08 19:22:28 +00001264 int no_piix_dma = 0;
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001265
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001266 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
Alan Coxc621b142005-12-08 19:22:28 +00001267 /* Look for 450NX PXB. Check for problem configurations
1268 A PCI quirk checks bit 6 already */
Alan Coxc621b142005-12-08 19:22:28 +00001269 pci_read_config_word(pdev, 0x41, &cfg);
1270 /* Only on the original revision: IDE DMA can hang */
Auke Kok44c10132007-06-08 15:46:36 -07001271 if (pdev->revision == 0x00)
Alan Coxc621b142005-12-08 19:22:28 +00001272 no_piix_dma = 1;
1273 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
Auke Kok44c10132007-06-08 15:46:36 -07001274 else if (cfg & (1<<14) && pdev->revision < 5)
Alan Coxc621b142005-12-08 19:22:28 +00001275 no_piix_dma = 2;
1276 }
Alan Cox31a34fe2006-05-22 22:58:14 +01001277 if (no_piix_dma)
Alan Coxc621b142005-12-08 19:22:28 +00001278 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
Alan Cox31a34fe2006-05-22 22:58:14 +01001279 if (no_piix_dma == 2)
Alan Coxc621b142005-12-08 19:22:28 +00001280 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1281 return no_piix_dma;
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001282}
Alan Coxc621b142005-12-08 19:22:28 +00001283
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001284static void __devinit piix_init_pcs(struct ata_host *host,
Jeff Garzikea35d292006-07-11 11:48:50 -04001285 const struct piix_map_db *map_db)
1286{
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001287 struct pci_dev *pdev = to_pci_dev(host->dev);
Jeff Garzikea35d292006-07-11 11:48:50 -04001288 u16 pcs, new_pcs;
1289
1290 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1291
1292 new_pcs = pcs | map_db->port_enable;
1293
1294 if (new_pcs != pcs) {
1295 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1296 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1297 msleep(150);
1298 }
1299}
1300
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001301static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1302 struct ata_port_info *pinfo,
1303 const struct piix_map_db *map_db)
Tejun Heod33f58b2006-03-01 01:25:39 +09001304{
Al Virob4482a42007-10-14 19:35:40 +01001305 const int *map;
Tejun Heod33f58b2006-03-01 01:25:39 +09001306 int i, invalid_map = 0;
1307 u8 map_value;
1308
1309 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1310
1311 map = map_db->map[map_value & map_db->mask];
1312
1313 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1314 for (i = 0; i < 4; i++) {
1315 switch (map[i]) {
1316 case RV:
1317 invalid_map = 1;
1318 printk(" XX");
1319 break;
1320
1321 case NA:
1322 printk(" --");
1323 break;
1324
1325 case IDE:
1326 WARN_ON((i & 1) || map[i + 1] != IDE);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001327 pinfo[i / 2] = piix_port_info[ich_pata_100];
Tejun Heod33f58b2006-03-01 01:25:39 +09001328 i++;
1329 printk(" IDE IDE");
1330 break;
1331
1332 default:
1333 printk(" P%d", map[i]);
1334 if (i & 1)
Jeff Garzikcca39742006-08-24 03:19:22 -04001335 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
Tejun Heod33f58b2006-03-01 01:25:39 +09001336 break;
1337 }
1338 }
1339 printk(" ]\n");
1340
1341 if (invalid_map)
1342 dev_printk(KERN_ERR, &pdev->dev,
1343 "invalid MAP value %u\n", map_value);
1344
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001345 return map;
Tejun Heod33f58b2006-03-01 01:25:39 +09001346}
1347
Tejun Heoc7290722008-01-18 18:36:30 +09001348static void __devinit piix_init_sidpr(struct ata_host *host)
1349{
1350 struct pci_dev *pdev = to_pci_dev(host->dev);
1351 struct piix_host_priv *hpriv = host->private_data;
Tejun Heocb6716c2008-05-01 10:03:08 +09001352 struct ata_device *dev0 = &host->ports[0]->link.device[0];
1353 u32 scontrol;
Tejun Heoc7290722008-01-18 18:36:30 +09001354 int i;
1355
1356 /* check for availability */
1357 for (i = 0; i < 4; i++)
1358 if (hpriv->map[i] == IDE)
1359 return;
1360
1361 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1362 return;
1363
1364 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1365 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1366 return;
1367
1368 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1369 return;
1370
1371 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
Tejun Heocb6716c2008-05-01 10:03:08 +09001372
1373 /* SCR access via SIDPR doesn't work on some configurations.
1374 * Give it a test drive by inhibiting power save modes which
1375 * we'll do anyway.
1376 */
1377 scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
1378
1379 /* if IPM is already 3, SCR access is probably working. Don't
1380 * un-inhibit power save modes as BIOS might have inhibited
1381 * them for a reason.
1382 */
1383 if ((scontrol & 0xf00) != 0x300) {
1384 scontrol |= 0x300;
1385 piix_sidpr_write(dev0, SCR_CONTROL, scontrol);
1386 scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
1387
1388 if ((scontrol & 0xf00) != 0x300) {
1389 dev_printk(KERN_INFO, host->dev, "SCR access via "
1390 "SIDPR is available but doesn't work\n");
1391 return;
1392 }
1393 }
1394
Tejun Heoc7290722008-01-18 18:36:30 +09001395 host->ports[0]->ops = &piix_sidpr_sata_ops;
1396 host->ports[1]->ops = &piix_sidpr_sata_ops;
1397}
1398
Tejun Heo43a98f02007-08-23 10:15:18 +09001399static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1400{
Jeff Garzik18552562007-10-03 15:15:40 -04001401 static const struct dmi_system_id sysids[] = {
Tejun Heo43a98f02007-08-23 10:15:18 +09001402 {
1403 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1404 * isn't used to boot the system which
1405 * disables the channel.
1406 */
1407 .ident = "M570U",
1408 .matches = {
1409 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1410 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1411 },
1412 },
Jeff Garzik7d051542007-09-01 06:48:52 -04001413
1414 { } /* terminate list */
Tejun Heo43a98f02007-08-23 10:15:18 +09001415 };
1416 u32 iocfg;
1417
1418 if (!dmi_check_system(sysids))
1419 return;
1420
1421 /* The datasheet says that bit 18 is NOOP but certain systems
1422 * seem to use it to disable a channel. Clear the bit on the
1423 * affected systems.
1424 */
1425 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1426 if (iocfg & (1 << 18)) {
1427 dev_printk(KERN_INFO, &pdev->dev,
1428 "applying IOCFG bit18 quirk\n");
1429 iocfg &= ~(1 << 18);
1430 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1431 }
1432}
1433
Alan Coxc621b142005-12-08 19:22:28 +00001434/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001435 * piix_init_one - Register PIIX ATA PCI device with kernel services
1436 * @pdev: PCI device to register
1437 * @ent: Entry in piix_pci_tbl matching with @pdev
1438 *
1439 * Called from kernel PCI layer. We probe for combined mode (sigh),
1440 * and then hand over control to libata, for it to do the rest.
1441 *
1442 * LOCKING:
1443 * Inherited from PCI layer (may sleep).
1444 *
1445 * RETURNS:
1446 * Zero on success, or -ERRNO value.
1447 */
1448
Adrian Bunkbc5468f2008-01-30 22:02:02 +02001449static int __devinit piix_init_one(struct pci_dev *pdev,
1450 const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001451{
1452 static int printed_version;
Tejun Heo24dc5f32007-01-20 16:00:28 +09001453 struct device *dev = &pdev->dev;
Tejun Heod33f58b2006-03-01 01:25:39 +09001454 struct ata_port_info port_info[2];
Tejun Heo1626aeb2007-05-04 12:43:58 +02001455 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
Jeff Garzikcca39742006-08-24 03:19:22 -04001456 unsigned long port_flags;
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001457 struct ata_host *host;
1458 struct piix_host_priv *hpriv;
1459 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001460
1461 if (!printed_version++)
Jeff Garzik6248e642005-10-30 06:42:18 -05001462 dev_printk(KERN_DEBUG, &pdev->dev,
1463 "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464
1465 /* no hotplugging support (FIXME) */
1466 if (!in_module_init)
1467 return -ENODEV;
1468
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001469 port_info[0] = piix_port_info[ent->driver_data];
1470 port_info[1] = piix_port_info[ent->driver_data];
1471
1472 port_flags = port_info[0].flags;
1473
1474 /* enable device and prepare host */
1475 rc = pcim_enable_device(pdev);
1476 if (rc)
1477 return rc;
1478
Tejun Heo5016d7d2008-03-26 15:46:58 +09001479 /* ICH6R may be driven by either ata_piix or ahci driver
1480 * regardless of BIOS configuration. Make sure AHCI mode is
1481 * off.
1482 */
1483 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1484 int rc = piix_disable_ahci(pdev);
1485 if (rc)
1486 return rc;
1487 }
1488
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001489 /* SATA map init can change port_info, do it before prepping host */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001490 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
Tejun Heod96715c2006-06-29 01:58:28 +09001491 if (!hpriv)
1492 return -ENOMEM;
1493
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001494 if (port_flags & ATA_FLAG_SATA)
1495 hpriv->map = piix_init_sata_map(pdev, port_info,
1496 piix_map_db_table[ent->driver_data]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001497
Tejun Heo9363c382008-04-07 22:47:16 +09001498 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001499 if (rc)
1500 return rc;
1501 host->private_data = hpriv;
Tejun Heoff0fc142005-12-18 17:17:07 +09001502
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001503 /* initialize controller */
Tejun Heoc7290722008-01-18 18:36:30 +09001504 if (port_flags & ATA_FLAG_SATA) {
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001505 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
Tejun Heoc7290722008-01-18 18:36:30 +09001506 piix_init_sidpr(host);
1507 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001508
Tejun Heo43a98f02007-08-23 10:15:18 +09001509 /* apply IOCFG bit18 quirk */
1510 piix_iocfg_bit18_quirk(pdev);
1511
Linus Torvalds1da177e2005-04-16 15:20:36 -07001512 /* On ICH5, some BIOSen disable the interrupt using the
1513 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1514 * On ICH6, this bit has the same effect, but only when
1515 * MSI is disabled (and it is disabled, as we don't use
1516 * message-signalled interrupts currently).
1517 */
Jeff Garzikcca39742006-08-24 03:19:22 -04001518 if (port_flags & PIIX_FLAG_CHECKINTR)
Brett M Russa04ce0f2005-08-15 15:23:41 -04001519 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001520
Alan Coxc621b142005-12-08 19:22:28 +00001521 if (piix_check_450nx_errata(pdev)) {
1522 /* This writes into the master table but it does not
1523 really matter for this errata as we will apply it to
1524 all the PIIX devices on the board */
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001525 host->ports[0]->mwdma_mask = 0;
1526 host->ports[0]->udma_mask = 0;
1527 host->ports[1]->mwdma_mask = 0;
1528 host->ports[1]->udma_mask = 0;
Alan Coxc621b142005-12-08 19:22:28 +00001529 }
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001530
1531 pci_set_master(pdev);
Tejun Heo9363c382008-04-07 22:47:16 +09001532 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001533}
1534
Linus Torvalds1da177e2005-04-16 15:20:36 -07001535static int __init piix_init(void)
1536{
1537 int rc;
1538
Pavel Roskinb7887192006-08-10 18:13:18 +09001539 DPRINTK("pci_register_driver\n");
1540 rc = pci_register_driver(&piix_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001541 if (rc)
1542 return rc;
1543
1544 in_module_init = 0;
1545
1546 DPRINTK("done\n");
1547 return 0;
1548}
1549
Linus Torvalds1da177e2005-04-16 15:20:36 -07001550static void __exit piix_exit(void)
1551{
1552 pci_unregister_driver(&piix_pci_driver);
1553}
1554
1555module_init(piix_init);
1556module_exit(piix_exit);