Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2015 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "intel_drv.h" |
| 25 | |
| 26 | static void |
Pandiyan, Dhinakaran | 8ab5de2 | 2016-08-04 13:48:36 -0700 | [diff] [blame] | 27 | intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
| 28 | { |
| 29 | |
| 30 | DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x", |
| 31 | link_status[0], link_status[1], link_status[2], |
| 32 | link_status[3], link_status[4], link_status[5]); |
| 33 | } |
| 34 | |
| 35 | static void |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 36 | intel_get_adjust_train(struct intel_dp *intel_dp, |
| 37 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
| 38 | { |
| 39 | uint8_t v = 0; |
| 40 | uint8_t p = 0; |
| 41 | int lane; |
| 42 | uint8_t voltage_max; |
| 43 | uint8_t preemph_max; |
| 44 | |
| 45 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
| 46 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
| 47 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
| 48 | |
| 49 | if (this_v > v) |
| 50 | v = this_v; |
| 51 | if (this_p > p) |
| 52 | p = this_p; |
| 53 | } |
| 54 | |
| 55 | voltage_max = intel_dp_voltage_max(intel_dp); |
| 56 | if (v >= voltage_max) |
| 57 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
| 58 | |
| 59 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
| 60 | if (p >= preemph_max) |
| 61 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
| 62 | |
| 63 | for (lane = 0; lane < 4; lane++) |
| 64 | intel_dp->train_set[lane] = v | p; |
| 65 | } |
| 66 | |
| 67 | static bool |
| 68 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
| 69 | uint8_t dp_train_pat) |
| 70 | { |
| 71 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
| 72 | int ret, len; |
| 73 | |
| 74 | intel_dp_program_link_training_pattern(intel_dp, dp_train_pat); |
| 75 | |
| 76 | buf[0] = dp_train_pat; |
| 77 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == |
| 78 | DP_TRAINING_PATTERN_DISABLE) { |
| 79 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
| 80 | len = 1; |
| 81 | } else { |
| 82 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
| 83 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
| 84 | len = intel_dp->lane_count + 1; |
| 85 | } |
| 86 | |
| 87 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
| 88 | buf, len); |
| 89 | |
| 90 | return ret == len; |
| 91 | } |
| 92 | |
| 93 | static bool |
| 94 | intel_dp_reset_link_train(struct intel_dp *intel_dp, |
| 95 | uint8_t dp_train_pat) |
| 96 | { |
Mika Kahola | 91df09d | 2016-06-20 11:10:26 +0300 | [diff] [blame] | 97 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 98 | intel_dp_set_signal_levels(intel_dp); |
| 99 | return intel_dp_set_link_train(intel_dp, dp_train_pat); |
| 100 | } |
| 101 | |
| 102 | static bool |
| 103 | intel_dp_update_link_train(struct intel_dp *intel_dp) |
| 104 | { |
| 105 | int ret; |
| 106 | |
| 107 | intel_dp_set_signal_levels(intel_dp); |
| 108 | |
| 109 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
| 110 | intel_dp->train_set, intel_dp->lane_count); |
| 111 | |
| 112 | return ret == intel_dp->lane_count; |
| 113 | } |
| 114 | |
| 115 | /* Enable corresponding port and start training pattern 1 */ |
| 116 | static void |
| 117 | intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) |
| 118 | { |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 119 | int i; |
| 120 | uint8_t voltage; |
| 121 | int voltage_tries, loop_tries; |
| 122 | uint8_t link_config[2]; |
| 123 | uint8_t link_bw, rate_select; |
| 124 | |
Ander Conselvan de Oliveira | ad64217 | 2015-10-23 13:01:49 +0300 | [diff] [blame] | 125 | if (intel_dp->prepare_link_retrain) |
| 126 | intel_dp->prepare_link_retrain(intel_dp); |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 127 | |
| 128 | intel_dp_compute_rate(intel_dp, intel_dp->link_rate, |
| 129 | &link_bw, &rate_select); |
| 130 | |
| 131 | /* Write the link configuration data */ |
| 132 | link_config[0] = link_bw; |
| 133 | link_config[1] = intel_dp->lane_count; |
| 134 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 135 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 136 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
| 137 | if (intel_dp->num_sink_rates) |
| 138 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, |
| 139 | &rate_select, 1); |
| 140 | |
| 141 | link_config[0] = 0; |
| 142 | link_config[1] = DP_SET_ANSI_8B10B; |
| 143 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
| 144 | |
| 145 | intel_dp->DP |= DP_PORT_EN; |
| 146 | |
| 147 | /* clock recovery */ |
| 148 | if (!intel_dp_reset_link_train(intel_dp, |
| 149 | DP_TRAINING_PATTERN_1 | |
| 150 | DP_LINK_SCRAMBLING_DISABLE)) { |
| 151 | DRM_ERROR("failed to enable link training\n"); |
| 152 | return; |
| 153 | } |
| 154 | |
| 155 | voltage = 0xff; |
| 156 | voltage_tries = 0; |
| 157 | loop_tries = 0; |
| 158 | for (;;) { |
| 159 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
| 160 | |
| 161 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
| 162 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 163 | DRM_ERROR("failed to get link status\n"); |
| 164 | break; |
| 165 | } |
| 166 | |
| 167 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
| 168 | DRM_DEBUG_KMS("clock recovery OK\n"); |
| 169 | break; |
| 170 | } |
| 171 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 172 | /* Check to see if we've tried the max voltage */ |
| 173 | for (i = 0; i < intel_dp->lane_count; i++) |
| 174 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 175 | break; |
| 176 | if (i == intel_dp->lane_count) { |
| 177 | ++loop_tries; |
| 178 | if (loop_tries == 5) { |
| 179 | DRM_ERROR("too many full retries, give up\n"); |
Pandiyan, Dhinakaran | 8ab5de2 | 2016-08-04 13:48:36 -0700 | [diff] [blame] | 180 | intel_dp_dump_link_status(link_status); |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 181 | break; |
| 182 | } |
| 183 | intel_dp_reset_link_train(intel_dp, |
| 184 | DP_TRAINING_PATTERN_1 | |
| 185 | DP_LINK_SCRAMBLING_DISABLE); |
| 186 | voltage_tries = 0; |
| 187 | continue; |
| 188 | } |
| 189 | |
| 190 | /* Check to see if we've tried the same voltage 5 times */ |
| 191 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
| 192 | ++voltage_tries; |
| 193 | if (voltage_tries == 5) { |
| 194 | DRM_ERROR("too many voltage retries, give up\n"); |
| 195 | break; |
| 196 | } |
| 197 | } else |
| 198 | voltage_tries = 0; |
| 199 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
| 200 | |
| 201 | /* Update training set as requested by target */ |
| 202 | intel_get_adjust_train(intel_dp, link_status); |
| 203 | if (!intel_dp_update_link_train(intel_dp)) { |
| 204 | DRM_ERROR("failed to update link training\n"); |
| 205 | break; |
| 206 | } |
| 207 | } |
| 208 | } |
| 209 | |
Jani Nikula | 23a5110d | 2016-02-05 12:16:09 +0200 | [diff] [blame] | 210 | /* |
| 211 | * Pick training pattern for channel equalization. Training Pattern 3 for HBR2 |
| 212 | * or 1.2 devices that support it, Training Pattern 2 otherwise. |
| 213 | */ |
| 214 | static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 215 | { |
Jani Nikula | 23a5110d | 2016-02-05 12:16:09 +0200 | [diff] [blame] | 216 | u32 training_pattern = DP_TRAINING_PATTERN_2; |
Jani Nikula | bfcef5d | 2016-02-05 12:16:10 +0200 | [diff] [blame] | 217 | bool source_tps3, sink_tps3; |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 218 | |
| 219 | /* |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 220 | * Intel platforms that support HBR2 also support TPS3. TPS3 support is |
Jani Nikula | bfcef5d | 2016-02-05 12:16:10 +0200 | [diff] [blame] | 221 | * also mandatory for downstream devices that support HBR2. However, not |
| 222 | * all sinks follow the spec. |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 223 | * |
| 224 | * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is |
Jani Nikula | bfcef5d | 2016-02-05 12:16:10 +0200 | [diff] [blame] | 225 | * supported in source but still not enabled. |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 226 | */ |
Jani Nikula | bfcef5d | 2016-02-05 12:16:10 +0200 | [diff] [blame] | 227 | source_tps3 = intel_dp_source_supports_hbr2(intel_dp); |
| 228 | sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd); |
| 229 | |
| 230 | if (source_tps3 && sink_tps3) { |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 231 | training_pattern = DP_TRAINING_PATTERN_3; |
Jani Nikula | bfcef5d | 2016-02-05 12:16:10 +0200 | [diff] [blame] | 232 | } else if (intel_dp->link_rate == 540000) { |
| 233 | if (!source_tps3) |
| 234 | DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n"); |
| 235 | if (!sink_tps3) |
| 236 | DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n"); |
| 237 | } |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 238 | |
Jani Nikula | 23a5110d | 2016-02-05 12:16:09 +0200 | [diff] [blame] | 239 | return training_pattern; |
| 240 | } |
| 241 | |
| 242 | static void |
| 243 | intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) |
| 244 | { |
| 245 | bool channel_eq = false; |
| 246 | int tries, cr_tries; |
| 247 | u32 training_pattern; |
| 248 | |
| 249 | training_pattern = intel_dp_training_pattern(intel_dp); |
| 250 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 251 | /* channel equalization */ |
| 252 | if (!intel_dp_set_link_train(intel_dp, |
| 253 | training_pattern | |
| 254 | DP_LINK_SCRAMBLING_DISABLE)) { |
| 255 | DRM_ERROR("failed to start channel equalization\n"); |
| 256 | return; |
| 257 | } |
| 258 | |
| 259 | tries = 0; |
| 260 | cr_tries = 0; |
| 261 | channel_eq = false; |
| 262 | for (;;) { |
| 263 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
| 264 | |
| 265 | if (cr_tries > 5) { |
| 266 | DRM_ERROR("failed to train DP, aborting\n"); |
Pandiyan, Dhinakaran | 8ab5de2 | 2016-08-04 13:48:36 -0700 | [diff] [blame] | 267 | intel_dp_dump_link_status(link_status); |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 268 | break; |
| 269 | } |
| 270 | |
| 271 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
| 272 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 273 | DRM_ERROR("failed to get link status\n"); |
| 274 | break; |
| 275 | } |
| 276 | |
| 277 | /* Make sure clock is still ok */ |
| 278 | if (!drm_dp_clock_recovery_ok(link_status, |
| 279 | intel_dp->lane_count)) { |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 280 | intel_dp_link_training_clock_recovery(intel_dp); |
| 281 | intel_dp_set_link_train(intel_dp, |
| 282 | training_pattern | |
| 283 | DP_LINK_SCRAMBLING_DISABLE); |
| 284 | cr_tries++; |
| 285 | continue; |
| 286 | } |
| 287 | |
| 288 | if (drm_dp_channel_eq_ok(link_status, |
| 289 | intel_dp->lane_count)) { |
| 290 | channel_eq = true; |
| 291 | break; |
| 292 | } |
| 293 | |
| 294 | /* Try 5 times, then try clock recovery if that fails */ |
| 295 | if (tries > 5) { |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 296 | intel_dp_link_training_clock_recovery(intel_dp); |
| 297 | intel_dp_set_link_train(intel_dp, |
| 298 | training_pattern | |
| 299 | DP_LINK_SCRAMBLING_DISABLE); |
| 300 | tries = 0; |
| 301 | cr_tries++; |
| 302 | continue; |
| 303 | } |
| 304 | |
| 305 | /* Update training set as requested by target */ |
| 306 | intel_get_adjust_train(intel_dp, link_status); |
| 307 | if (!intel_dp_update_link_train(intel_dp)) { |
| 308 | DRM_ERROR("failed to update link training\n"); |
| 309 | break; |
| 310 | } |
| 311 | ++tries; |
| 312 | } |
| 313 | |
| 314 | intel_dp_set_idle_link_train(intel_dp); |
| 315 | |
Mika Kahola | 91df09d | 2016-06-20 11:10:26 +0300 | [diff] [blame] | 316 | if (channel_eq) |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 317 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 318 | } |
| 319 | |
| 320 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) |
| 321 | { |
| 322 | intel_dp_set_link_train(intel_dp, |
| 323 | DP_TRAINING_PATTERN_DISABLE); |
| 324 | } |
| 325 | |
| 326 | void |
| 327 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
| 328 | { |
| 329 | intel_dp_link_training_clock_recovery(intel_dp); |
| 330 | intel_dp_link_training_channel_equalization(intel_dp); |
| 331 | } |