Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 1 | /* |
| 2 | * pdc_adma.c - Pacific Digital Corporation ADMA |
| 3 | * |
| 4 | * Maintained by: Mark Lord <mlord@pobox.com> |
| 5 | * |
| 6 | * Copyright 2005 Mark Lord |
| 7 | * |
Jeff Garzik | 68399bb | 2005-10-11 01:44:14 -0400 | [diff] [blame] | 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2, or (at your option) |
| 11 | * any later version. |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 12 | * |
Jeff Garzik | 68399bb | 2005-10-11 01:44:14 -0400 | [diff] [blame] | 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; see the file COPYING. If not, write to |
| 20 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | * |
| 22 | * |
| 23 | * libata documentation is available via 'make {ps|pdf}docs', |
| 24 | * as Documentation/DocBook/libata.* |
| 25 | * |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 26 | * |
| 27 | * Supports ATA disks in single-packet ADMA mode. |
| 28 | * Uses PIO for everything else. |
| 29 | * |
| 30 | * TODO: Use ADMA transfers for ATAPI devices, when possible. |
| 31 | * This requires careful attention to a number of quirks of the chip. |
| 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/blkdev.h> |
| 40 | #include <linux/delay.h> |
| 41 | #include <linux/interrupt.h> |
| 42 | #include <linux/sched.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 43 | #include <linux/device.h> |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 44 | #include <scsi/scsi_host.h> |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 45 | #include <linux/libata.h> |
| 46 | |
| 47 | #define DRV_NAME "pdc_adma" |
Jeff Garzik | af64371 | 2006-04-02 20:41:36 -0400 | [diff] [blame] | 48 | #define DRV_VERSION "0.04" |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 49 | |
| 50 | /* macro to calculate base address for ATA regs */ |
| 51 | #define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40)) |
| 52 | |
| 53 | /* macro to calculate base address for ADMA regs */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 54 | #define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20)) |
| 55 | |
| 56 | /* macro to obtain addresses from ata_host */ |
| 57 | #define ADMA_HOST_REGS(host,port_no) \ |
| 58 | ADMA_REGS((host)->iomap[ADMA_MMIO_BAR], port_no) |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 59 | |
| 60 | enum { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 61 | ADMA_MMIO_BAR = 4, |
| 62 | |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 63 | ADMA_PORTS = 2, |
| 64 | ADMA_CPB_BYTES = 40, |
| 65 | ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16, |
| 66 | ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES, |
| 67 | |
| 68 | ADMA_DMA_BOUNDARY = 0xffffffff, |
| 69 | |
| 70 | /* global register offsets */ |
| 71 | ADMA_MODE_LOCK = 0x00c7, |
| 72 | |
| 73 | /* per-channel register offsets */ |
| 74 | ADMA_CONTROL = 0x0000, /* ADMA control */ |
| 75 | ADMA_STATUS = 0x0002, /* ADMA status */ |
| 76 | ADMA_CPB_COUNT = 0x0004, /* CPB count */ |
| 77 | ADMA_CPB_CURRENT = 0x000c, /* current CPB address */ |
| 78 | ADMA_CPB_NEXT = 0x000c, /* next CPB address */ |
| 79 | ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */ |
| 80 | ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */ |
| 81 | ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */ |
| 82 | |
| 83 | /* ADMA_CONTROL register bits */ |
| 84 | aNIEN = (1 << 8), /* irq mask: 1==masked */ |
| 85 | aGO = (1 << 7), /* packet trigger ("Go!") */ |
| 86 | aRSTADM = (1 << 5), /* ADMA logic reset */ |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 87 | aPIOMD4 = 0x0003, /* PIO mode 4 */ |
| 88 | |
| 89 | /* ADMA_STATUS register bits */ |
| 90 | aPSD = (1 << 6), |
| 91 | aUIRQ = (1 << 4), |
| 92 | aPERR = (1 << 0), |
| 93 | |
| 94 | /* CPB bits */ |
| 95 | cDONE = (1 << 0), |
| 96 | cVLD = (1 << 0), |
| 97 | cDAT = (1 << 2), |
| 98 | cIEN = (1 << 3), |
| 99 | |
| 100 | /* PRD bits */ |
| 101 | pORD = (1 << 4), |
| 102 | pDIRO = (1 << 5), |
| 103 | pEND = (1 << 7), |
| 104 | |
| 105 | /* ATA register flags */ |
| 106 | rIGN = (1 << 5), |
| 107 | rEND = (1 << 7), |
| 108 | |
| 109 | /* ATA register addresses */ |
| 110 | ADMA_REGS_CONTROL = 0x0e, |
| 111 | ADMA_REGS_SECTOR_COUNT = 0x12, |
| 112 | ADMA_REGS_LBA_LOW = 0x13, |
| 113 | ADMA_REGS_LBA_MID = 0x14, |
| 114 | ADMA_REGS_LBA_HIGH = 0x15, |
| 115 | ADMA_REGS_DEVICE = 0x16, |
| 116 | ADMA_REGS_COMMAND = 0x17, |
| 117 | |
| 118 | /* PCI device IDs */ |
| 119 | board_1841_idx = 0, /* ADMA 2-port controller */ |
| 120 | }; |
| 121 | |
| 122 | typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t; |
| 123 | |
| 124 | struct adma_port_priv { |
| 125 | u8 *pkt; |
| 126 | dma_addr_t pkt_dma; |
| 127 | adma_state_t state; |
| 128 | }; |
| 129 | |
| 130 | static int adma_ata_init_one (struct pci_dev *pdev, |
| 131 | const struct pci_device_id *ent); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 132 | static irqreturn_t adma_intr (int irq, void *dev_instance); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 133 | static int adma_port_start(struct ata_port *ap); |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 134 | static void adma_host_stop(struct ata_host *host); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 135 | static void adma_port_stop(struct ata_port *ap); |
| 136 | static void adma_phy_reset(struct ata_port *ap); |
| 137 | static void adma_qc_prep(struct ata_queued_cmd *qc); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 138 | static unsigned int adma_qc_issue(struct ata_queued_cmd *qc); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 139 | static int adma_check_atapi_dma(struct ata_queued_cmd *qc); |
| 140 | static void adma_bmdma_stop(struct ata_queued_cmd *qc); |
| 141 | static u8 adma_bmdma_status(struct ata_port *ap); |
| 142 | static void adma_irq_clear(struct ata_port *ap); |
| 143 | static void adma_eng_timeout(struct ata_port *ap); |
| 144 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 145 | static struct scsi_host_template adma_ata_sht = { |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 146 | .module = THIS_MODULE, |
| 147 | .name = DRV_NAME, |
| 148 | .ioctl = ata_scsi_ioctl, |
| 149 | .queuecommand = ata_scsi_queuecmd, |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 150 | .can_queue = ATA_DEF_QUEUE, |
| 151 | .this_id = ATA_SHT_THIS_ID, |
| 152 | .sg_tablesize = LIBATA_MAX_PRD, |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 153 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 154 | .emulated = ATA_SHT_EMULATED, |
| 155 | .use_clustering = ENABLE_CLUSTERING, |
| 156 | .proc_name = DRV_NAME, |
| 157 | .dma_boundary = ADMA_DMA_BOUNDARY, |
| 158 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 159 | .slave_destroy = ata_scsi_slave_destroy, |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 160 | .bios_param = ata_std_bios_param, |
| 161 | }; |
| 162 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 163 | static const struct ata_port_operations adma_ata_ops = { |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 164 | .port_disable = ata_port_disable, |
| 165 | .tf_load = ata_tf_load, |
| 166 | .tf_read = ata_tf_read, |
| 167 | .check_status = ata_check_status, |
| 168 | .check_atapi_dma = adma_check_atapi_dma, |
| 169 | .exec_command = ata_exec_command, |
| 170 | .dev_select = ata_std_dev_select, |
| 171 | .phy_reset = adma_phy_reset, |
| 172 | .qc_prep = adma_qc_prep, |
| 173 | .qc_issue = adma_qc_issue, |
| 174 | .eng_timeout = adma_eng_timeout, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 175 | .data_xfer = ata_data_xfer, |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 176 | .irq_handler = adma_intr, |
| 177 | .irq_clear = adma_irq_clear, |
| 178 | .port_start = adma_port_start, |
| 179 | .port_stop = adma_port_stop, |
| 180 | .host_stop = adma_host_stop, |
| 181 | .bmdma_stop = adma_bmdma_stop, |
| 182 | .bmdma_status = adma_bmdma_status, |
| 183 | }; |
| 184 | |
| 185 | static struct ata_port_info adma_port_info[] = { |
| 186 | /* board_1841_idx */ |
| 187 | { |
| 188 | .sht = &adma_ata_sht, |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 189 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | |
Albert Lee | 51704c6 | 2006-08-09 18:36:22 +0800 | [diff] [blame] | 190 | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | |
| 191 | ATA_FLAG_PIO_POLLING, |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 192 | .pio_mask = 0x10, /* pio4 */ |
| 193 | .udma_mask = 0x1f, /* udma0-4 */ |
| 194 | .port_ops = &adma_ata_ops, |
| 195 | }, |
| 196 | }; |
| 197 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 198 | static const struct pci_device_id adma_ata_pci_tbl[] = { |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 199 | { PCI_VDEVICE(PDC, 0x1841), board_1841_idx }, |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 200 | |
| 201 | { } /* terminate list */ |
| 202 | }; |
| 203 | |
| 204 | static struct pci_driver adma_ata_pci_driver = { |
| 205 | .name = DRV_NAME, |
| 206 | .id_table = adma_ata_pci_tbl, |
| 207 | .probe = adma_ata_init_one, |
| 208 | .remove = ata_pci_remove_one, |
| 209 | }; |
| 210 | |
| 211 | static int adma_check_atapi_dma(struct ata_queued_cmd *qc) |
| 212 | { |
| 213 | return 1; /* ATAPI DMA not yet supported */ |
| 214 | } |
| 215 | |
| 216 | static void adma_bmdma_stop(struct ata_queued_cmd *qc) |
| 217 | { |
| 218 | /* nothing */ |
| 219 | } |
| 220 | |
| 221 | static u8 adma_bmdma_status(struct ata_port *ap) |
| 222 | { |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | static void adma_irq_clear(struct ata_port *ap) |
| 227 | { |
| 228 | /* nothing */ |
| 229 | } |
| 230 | |
| 231 | static void adma_reset_engine(void __iomem *chan) |
| 232 | { |
| 233 | /* reset ADMA to idle state */ |
| 234 | writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); |
| 235 | udelay(2); |
| 236 | writew(aPIOMD4, chan + ADMA_CONTROL); |
| 237 | udelay(2); |
| 238 | } |
| 239 | |
| 240 | static void adma_reinit_engine(struct ata_port *ap) |
| 241 | { |
| 242 | struct adma_port_priv *pp = ap->private_data; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 243 | void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 244 | |
| 245 | /* mask/clear ATA interrupts */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 246 | writeb(ATA_NIEN, ap->ioaddr.ctl_addr); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 247 | ata_check_status(ap); |
| 248 | |
| 249 | /* reset the ADMA engine */ |
| 250 | adma_reset_engine(chan); |
| 251 | |
| 252 | /* set in-FIFO threshold to 0x100 */ |
| 253 | writew(0x100, chan + ADMA_FIFO_IN); |
| 254 | |
| 255 | /* set CPB pointer */ |
| 256 | writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT); |
| 257 | |
| 258 | /* set out-FIFO threshold to 0x100 */ |
| 259 | writew(0x100, chan + ADMA_FIFO_OUT); |
| 260 | |
| 261 | /* set CPB count */ |
| 262 | writew(1, chan + ADMA_CPB_COUNT); |
| 263 | |
| 264 | /* read/discard ADMA status */ |
| 265 | readb(chan + ADMA_STATUS); |
| 266 | } |
| 267 | |
| 268 | static inline void adma_enter_reg_mode(struct ata_port *ap) |
| 269 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 270 | void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 271 | |
| 272 | writew(aPIOMD4, chan + ADMA_CONTROL); |
| 273 | readb(chan + ADMA_STATUS); /* flush */ |
| 274 | } |
| 275 | |
| 276 | static void adma_phy_reset(struct ata_port *ap) |
| 277 | { |
| 278 | struct adma_port_priv *pp = ap->private_data; |
| 279 | |
| 280 | pp->state = adma_state_idle; |
| 281 | adma_reinit_engine(ap); |
| 282 | ata_port_probe(ap); |
| 283 | ata_bus_reset(ap); |
| 284 | } |
| 285 | |
| 286 | static void adma_eng_timeout(struct ata_port *ap) |
| 287 | { |
| 288 | struct adma_port_priv *pp = ap->private_data; |
| 289 | |
| 290 | if (pp->state != adma_state_idle) /* healthy paranoia */ |
| 291 | pp->state = adma_state_mmio; |
| 292 | adma_reinit_engine(ap); |
| 293 | ata_eng_timeout(ap); |
| 294 | } |
| 295 | |
| 296 | static int adma_fill_sg(struct ata_queued_cmd *qc) |
| 297 | { |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 298 | struct scatterlist *sg; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 299 | struct ata_port *ap = qc->ap; |
| 300 | struct adma_port_priv *pp = ap->private_data; |
| 301 | u8 *buf = pp->pkt; |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 302 | int i = (2 + buf[3]) * 8; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 303 | u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0); |
| 304 | |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 305 | ata_for_each_sg(sg, qc) { |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 306 | u32 addr; |
| 307 | u32 len; |
| 308 | |
| 309 | addr = (u32)sg_dma_address(sg); |
| 310 | *(__le32 *)(buf + i) = cpu_to_le32(addr); |
| 311 | i += 4; |
| 312 | |
| 313 | len = sg_dma_len(sg) >> 3; |
| 314 | *(__le32 *)(buf + i) = cpu_to_le32(len); |
| 315 | i += 4; |
| 316 | |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 317 | if (ata_sg_is_last(sg, qc)) |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 318 | pFLAGS |= pEND; |
| 319 | buf[i++] = pFLAGS; |
| 320 | buf[i++] = qc->dev->dma_mode & 0xf; |
| 321 | buf[i++] = 0; /* pPKLW */ |
| 322 | buf[i++] = 0; /* reserved */ |
| 323 | |
| 324 | *(__le32 *)(buf + i) |
| 325 | = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4); |
| 326 | i += 4; |
| 327 | |
Alan Cox | db7f44d | 2006-03-21 15:54:24 +0000 | [diff] [blame] | 328 | VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4, |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 329 | (unsigned long)addr, len); |
| 330 | } |
| 331 | return i; |
| 332 | } |
| 333 | |
| 334 | static void adma_qc_prep(struct ata_queued_cmd *qc) |
| 335 | { |
| 336 | struct adma_port_priv *pp = qc->ap->private_data; |
| 337 | u8 *buf = pp->pkt; |
| 338 | u32 pkt_dma = (u32)pp->pkt_dma; |
| 339 | int i = 0; |
| 340 | |
| 341 | VPRINTK("ENTER\n"); |
| 342 | |
| 343 | adma_enter_reg_mode(qc->ap); |
| 344 | if (qc->tf.protocol != ATA_PROT_DMA) { |
| 345 | ata_qc_prep(qc); |
| 346 | return; |
| 347 | } |
| 348 | |
| 349 | buf[i++] = 0; /* Response flags */ |
| 350 | buf[i++] = 0; /* reserved */ |
| 351 | buf[i++] = cVLD | cDAT | cIEN; |
| 352 | i++; /* cLEN, gets filled in below */ |
| 353 | |
| 354 | *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */ |
| 355 | i += 4; /* cNCPB */ |
| 356 | i += 4; /* cPRD, gets filled in below */ |
| 357 | |
| 358 | buf[i++] = 0; /* reserved */ |
| 359 | buf[i++] = 0; /* reserved */ |
| 360 | buf[i++] = 0; /* reserved */ |
| 361 | buf[i++] = 0; /* reserved */ |
| 362 | |
| 363 | /* ATA registers; must be a multiple of 4 */ |
| 364 | buf[i++] = qc->tf.device; |
| 365 | buf[i++] = ADMA_REGS_DEVICE; |
| 366 | if ((qc->tf.flags & ATA_TFLAG_LBA48)) { |
| 367 | buf[i++] = qc->tf.hob_nsect; |
| 368 | buf[i++] = ADMA_REGS_SECTOR_COUNT; |
| 369 | buf[i++] = qc->tf.hob_lbal; |
| 370 | buf[i++] = ADMA_REGS_LBA_LOW; |
| 371 | buf[i++] = qc->tf.hob_lbam; |
| 372 | buf[i++] = ADMA_REGS_LBA_MID; |
| 373 | buf[i++] = qc->tf.hob_lbah; |
| 374 | buf[i++] = ADMA_REGS_LBA_HIGH; |
| 375 | } |
| 376 | buf[i++] = qc->tf.nsect; |
| 377 | buf[i++] = ADMA_REGS_SECTOR_COUNT; |
| 378 | buf[i++] = qc->tf.lbal; |
| 379 | buf[i++] = ADMA_REGS_LBA_LOW; |
| 380 | buf[i++] = qc->tf.lbam; |
| 381 | buf[i++] = ADMA_REGS_LBA_MID; |
| 382 | buf[i++] = qc->tf.lbah; |
| 383 | buf[i++] = ADMA_REGS_LBA_HIGH; |
| 384 | buf[i++] = 0; |
| 385 | buf[i++] = ADMA_REGS_CONTROL; |
| 386 | buf[i++] = rIGN; |
| 387 | buf[i++] = 0; |
| 388 | buf[i++] = qc->tf.command; |
| 389 | buf[i++] = ADMA_REGS_COMMAND | rEND; |
| 390 | |
| 391 | buf[3] = (i >> 3) - 2; /* cLEN */ |
| 392 | *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */ |
| 393 | |
| 394 | i = adma_fill_sg(qc); |
| 395 | wmb(); /* flush PRDs and pkt to memory */ |
| 396 | #if 0 |
| 397 | /* dump out CPB + PRDs for debug */ |
| 398 | { |
| 399 | int j, len = 0; |
| 400 | static char obuf[2048]; |
| 401 | for (j = 0; j < i; ++j) { |
| 402 | len += sprintf(obuf+len, "%02x ", buf[j]); |
| 403 | if ((j & 7) == 7) { |
| 404 | printk("%s\n", obuf); |
| 405 | len = 0; |
| 406 | } |
| 407 | } |
| 408 | if (len) |
| 409 | printk("%s\n", obuf); |
| 410 | } |
| 411 | #endif |
| 412 | } |
| 413 | |
| 414 | static inline void adma_packet_start(struct ata_queued_cmd *qc) |
| 415 | { |
| 416 | struct ata_port *ap = qc->ap; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 417 | void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 418 | |
| 419 | VPRINTK("ENTER, ap %p\n", ap); |
| 420 | |
| 421 | /* fire up the ADMA engine */ |
Jeff Garzik | 68399bb | 2005-10-11 01:44:14 -0400 | [diff] [blame] | 422 | writew(aPIOMD4 | aGO, chan + ADMA_CONTROL); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 423 | } |
| 424 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 425 | static unsigned int adma_qc_issue(struct ata_queued_cmd *qc) |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 426 | { |
| 427 | struct adma_port_priv *pp = qc->ap->private_data; |
| 428 | |
| 429 | switch (qc->tf.protocol) { |
| 430 | case ATA_PROT_DMA: |
| 431 | pp->state = adma_state_pkt; |
| 432 | adma_packet_start(qc); |
| 433 | return 0; |
| 434 | |
| 435 | case ATA_PROT_ATAPI_DMA: |
| 436 | BUG(); |
| 437 | break; |
| 438 | |
| 439 | default: |
| 440 | break; |
| 441 | } |
| 442 | |
| 443 | pp->state = adma_state_mmio; |
| 444 | return ata_qc_issue_prot(qc); |
| 445 | } |
| 446 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 447 | static inline unsigned int adma_intr_pkt(struct ata_host *host) |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 448 | { |
| 449 | unsigned int handled = 0, port_no; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 450 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 451 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
| 452 | struct ata_port *ap = host->ports[port_no]; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 453 | struct adma_port_priv *pp; |
| 454 | struct ata_queued_cmd *qc; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 455 | void __iomem *chan = ADMA_HOST_REGS(host, port_no); |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 456 | u8 status = readb(chan + ADMA_STATUS); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 457 | |
| 458 | if (status == 0) |
| 459 | continue; |
| 460 | handled = 1; |
| 461 | adma_enter_reg_mode(ap); |
Jeff Garzik | 029f546 | 2006-04-02 10:30:40 -0400 | [diff] [blame] | 462 | if (ap->flags & ATA_FLAG_DISABLED) |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 463 | continue; |
| 464 | pp = ap->private_data; |
| 465 | if (!pp || pp->state != adma_state_pkt) |
| 466 | continue; |
| 467 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Jeff Garzik | 94ec1ef | 2005-10-30 02:15:08 -0500 | [diff] [blame] | 468 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
Jeff Garzik | a21a84a | 2005-10-28 15:43:16 -0400 | [diff] [blame] | 469 | if ((status & (aPERR | aPSD | aUIRQ))) |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 470 | qc->err_mask |= AC_ERR_OTHER; |
Jeff Garzik | a21a84a | 2005-10-28 15:43:16 -0400 | [diff] [blame] | 471 | else if (pp->pkt[0] != cDONE) |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 472 | qc->err_mask |= AC_ERR_OTHER; |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 473 | |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 474 | ata_qc_complete(qc); |
Jeff Garzik | a21a84a | 2005-10-28 15:43:16 -0400 | [diff] [blame] | 475 | } |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 476 | } |
| 477 | return handled; |
| 478 | } |
| 479 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 480 | static inline unsigned int adma_intr_mmio(struct ata_host *host) |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 481 | { |
| 482 | unsigned int handled = 0, port_no; |
| 483 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 484 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 485 | struct ata_port *ap; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 486 | ap = host->ports[port_no]; |
Jeff Garzik | 029f546 | 2006-04-02 10:30:40 -0400 | [diff] [blame] | 487 | if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) { |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 488 | struct ata_queued_cmd *qc; |
| 489 | struct adma_port_priv *pp = ap->private_data; |
| 490 | if (!pp || pp->state != adma_state_mmio) |
| 491 | continue; |
| 492 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Jeff Garzik | be697c3 | 2005-10-18 21:27:34 -0400 | [diff] [blame] | 493 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 494 | |
| 495 | /* check main status, clearing INTRQ */ |
Jeff Garzik | ac19bff | 2005-10-29 13:58:21 -0400 | [diff] [blame] | 496 | u8 status = ata_check_status(ap); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 497 | if ((status & ATA_BUSY)) |
| 498 | continue; |
| 499 | DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n", |
| 500 | ap->id, qc->tf.protocol, status); |
Jeff Garzik | 9bec2e3 | 2006-08-31 00:02:15 -0400 | [diff] [blame] | 501 | |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 502 | /* complete taskfile transaction */ |
| 503 | pp->state = adma_state_idle; |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 504 | qc->err_mask |= ac_err_mask(status); |
| 505 | ata_qc_complete(qc); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 506 | handled = 1; |
| 507 | } |
| 508 | } |
| 509 | } |
| 510 | return handled; |
| 511 | } |
| 512 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 513 | static irqreturn_t adma_intr(int irq, void *dev_instance) |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 514 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 515 | struct ata_host *host = dev_instance; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 516 | unsigned int handled = 0; |
| 517 | |
| 518 | VPRINTK("ENTER\n"); |
| 519 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 520 | spin_lock(&host->lock); |
| 521 | handled = adma_intr_pkt(host) | adma_intr_mmio(host); |
| 522 | spin_unlock(&host->lock); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 523 | |
| 524 | VPRINTK("EXIT\n"); |
| 525 | |
| 526 | return IRQ_RETVAL(handled); |
| 527 | } |
| 528 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 529 | static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base) |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 530 | { |
| 531 | port->cmd_addr = |
| 532 | port->data_addr = base + 0x000; |
| 533 | port->error_addr = |
| 534 | port->feature_addr = base + 0x004; |
| 535 | port->nsect_addr = base + 0x008; |
| 536 | port->lbal_addr = base + 0x00c; |
| 537 | port->lbam_addr = base + 0x010; |
| 538 | port->lbah_addr = base + 0x014; |
| 539 | port->device_addr = base + 0x018; |
| 540 | port->status_addr = |
| 541 | port->command_addr = base + 0x01c; |
| 542 | port->altstatus_addr = |
| 543 | port->ctl_addr = base + 0x038; |
| 544 | } |
| 545 | |
| 546 | static int adma_port_start(struct ata_port *ap) |
| 547 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 548 | struct device *dev = ap->host->dev; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 549 | struct adma_port_priv *pp; |
| 550 | int rc; |
| 551 | |
| 552 | rc = ata_port_start(ap); |
| 553 | if (rc) |
| 554 | return rc; |
| 555 | adma_enter_reg_mode(ap); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 556 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 557 | if (!pp) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 558 | return -ENOMEM; |
| 559 | pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma, |
| 560 | GFP_KERNEL); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 561 | if (!pp->pkt) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 562 | return -ENOMEM; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 563 | /* paranoia? */ |
| 564 | if ((pp->pkt_dma & 7) != 0) { |
| 565 | printk("bad alignment for pp->pkt_dma: %08x\n", |
| 566 | (u32)pp->pkt_dma); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 567 | return -ENOMEM; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 568 | } |
| 569 | memset(pp->pkt, 0, ADMA_PKT_BYTES); |
| 570 | ap->private_data = pp; |
| 571 | adma_reinit_engine(ap); |
| 572 | return 0; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 573 | } |
| 574 | |
| 575 | static void adma_port_stop(struct ata_port *ap) |
| 576 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 577 | adma_reset_engine(ADMA_HOST_REGS(ap->host, ap->port_no)); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 578 | } |
| 579 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 580 | static void adma_host_stop(struct ata_host *host) |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 581 | { |
| 582 | unsigned int port_no; |
| 583 | |
| 584 | for (port_no = 0; port_no < ADMA_PORTS; ++port_no) |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 585 | adma_reset_engine(ADMA_HOST_REGS(host, port_no)); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 586 | } |
| 587 | |
| 588 | static void adma_host_init(unsigned int chip_id, |
| 589 | struct ata_probe_ent *probe_ent) |
| 590 | { |
| 591 | unsigned int port_no; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 592 | void __iomem *mmio_base = probe_ent->iomap[ADMA_MMIO_BAR]; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 593 | |
| 594 | /* enable/lock aGO operation */ |
| 595 | writeb(7, mmio_base + ADMA_MODE_LOCK); |
| 596 | |
| 597 | /* reset the ADMA logic */ |
| 598 | for (port_no = 0; port_no < ADMA_PORTS; ++port_no) |
| 599 | adma_reset_engine(ADMA_REGS(mmio_base, port_no)); |
| 600 | } |
| 601 | |
| 602 | static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) |
| 603 | { |
| 604 | int rc; |
| 605 | |
| 606 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 607 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 608 | dev_printk(KERN_ERR, &pdev->dev, |
| 609 | "32-bit DMA enable failed\n"); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 610 | return rc; |
| 611 | } |
| 612 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 613 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 614 | dev_printk(KERN_ERR, &pdev->dev, |
| 615 | "32-bit consistent DMA enable failed\n"); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 616 | return rc; |
| 617 | } |
| 618 | return 0; |
| 619 | } |
| 620 | |
| 621 | static int adma_ata_init_one(struct pci_dev *pdev, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 622 | const struct pci_device_id *ent) |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 623 | { |
| 624 | static int printed_version; |
| 625 | struct ata_probe_ent *probe_ent = NULL; |
| 626 | void __iomem *mmio_base; |
| 627 | unsigned int board_idx = (unsigned int) ent->driver_data; |
| 628 | int rc, port_no; |
| 629 | |
| 630 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 631 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 632 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 633 | rc = pcim_enable_device(pdev); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 634 | if (rc) |
| 635 | return rc; |
| 636 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 637 | if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) |
| 638 | return -ENODEV; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 639 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 640 | rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME); |
| 641 | if (rc) |
| 642 | return rc; |
| 643 | mmio_base = pcim_iomap_table(pdev)[ADMA_MMIO_BAR]; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 644 | |
| 645 | rc = adma_set_dma_masks(pdev, mmio_base); |
| 646 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 647 | return rc; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 648 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 649 | probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL); |
| 650 | if (probe_ent == NULL) |
| 651 | return -ENOMEM; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 652 | |
| 653 | probe_ent->dev = pci_dev_to_dev(pdev); |
| 654 | INIT_LIST_HEAD(&probe_ent->node); |
| 655 | |
| 656 | probe_ent->sht = adma_port_info[board_idx].sht; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 657 | probe_ent->port_flags = adma_port_info[board_idx].flags; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 658 | probe_ent->pio_mask = adma_port_info[board_idx].pio_mask; |
| 659 | probe_ent->mwdma_mask = adma_port_info[board_idx].mwdma_mask; |
| 660 | probe_ent->udma_mask = adma_port_info[board_idx].udma_mask; |
| 661 | probe_ent->port_ops = adma_port_info[board_idx].port_ops; |
| 662 | |
| 663 | probe_ent->irq = pdev->irq; |
Thomas Gleixner | 1d6f359 | 2006-07-01 19:29:42 -0700 | [diff] [blame] | 664 | probe_ent->irq_flags = IRQF_SHARED; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 665 | probe_ent->n_ports = ADMA_PORTS; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 666 | probe_ent->iomap = pcim_iomap_table(pdev); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 667 | |
| 668 | for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) { |
| 669 | adma_ata_setup_port(&probe_ent->port[port_no], |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 670 | ADMA_ATA_REGS(mmio_base, port_no)); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 671 | } |
| 672 | |
| 673 | pci_set_master(pdev); |
| 674 | |
| 675 | /* initialize adapter */ |
| 676 | adma_host_init(board_idx, probe_ent); |
| 677 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 678 | if (!ata_device_add(probe_ent)) |
| 679 | return -ENODEV; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 680 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 681 | devm_kfree(&pdev->dev, probe_ent); |
| 682 | return 0; |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 683 | } |
| 684 | |
| 685 | static int __init adma_ata_init(void) |
| 686 | { |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 687 | return pci_register_driver(&adma_ata_pci_driver); |
Mark Lord | edea3ab | 2005-10-10 17:53:58 -0400 | [diff] [blame] | 688 | } |
| 689 | |
| 690 | static void __exit adma_ata_exit(void) |
| 691 | { |
| 692 | pci_unregister_driver(&adma_ata_pci_driver); |
| 693 | } |
| 694 | |
| 695 | MODULE_AUTHOR("Mark Lord"); |
| 696 | MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver"); |
| 697 | MODULE_LICENSE("GPL"); |
| 698 | MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl); |
| 699 | MODULE_VERSION(DRV_VERSION); |
| 700 | |
| 701 | module_init(adma_ata_init); |
| 702 | module_exit(adma_ata_exit); |