Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP2 McSPI controller driver |
| 3 | * |
| 4 | * Copyright (C) 2005, 2006 Nokia Corporation |
| 5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/device.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/dma-mapping.h> |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 31 | #include <linux/dmaengine.h> |
| 32 | #include <linux/omap-dma.h> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 33 | #include <linux/platform_device.h> |
| 34 | #include <linux/err.h> |
| 35 | #include <linux/clk.h> |
| 36 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 37 | #include <linux/slab.h> |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 38 | #include <linux/pm_runtime.h> |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 39 | #include <linux/of.h> |
| 40 | #include <linux/of_device.h> |
Matt Porter | ec155af | 2012-09-18 08:01:25 -0400 | [diff] [blame] | 41 | #include <linux/pinctrl/consumer.h> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 42 | |
| 43 | #include <linux/spi/spi.h> |
| 44 | |
Arnd Bergmann | 2203747 | 2012-08-24 15:21:06 +0200 | [diff] [blame] | 45 | #include <linux/platform_data/spi-omap2-mcspi.h> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 46 | |
| 47 | #define OMAP2_MCSPI_MAX_FREQ 48000000 |
Shubhrajyoti D | 27b5284 | 2012-03-26 17:04:22 +0530 | [diff] [blame] | 48 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 49 | |
| 50 | #define OMAP2_MCSPI_REVISION 0x00 |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 51 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
| 52 | #define OMAP2_MCSPI_IRQSTATUS 0x18 |
| 53 | #define OMAP2_MCSPI_IRQENABLE 0x1c |
| 54 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 |
| 55 | #define OMAP2_MCSPI_SYST 0x24 |
| 56 | #define OMAP2_MCSPI_MODULCTRL 0x28 |
| 57 | |
| 58 | /* per-channel banks, 0x14 bytes each, first is: */ |
| 59 | #define OMAP2_MCSPI_CHCONF0 0x2c |
| 60 | #define OMAP2_MCSPI_CHSTAT0 0x30 |
| 61 | #define OMAP2_MCSPI_CHCTRL0 0x34 |
| 62 | #define OMAP2_MCSPI_TX0 0x38 |
| 63 | #define OMAP2_MCSPI_RX0 0x3c |
| 64 | |
| 65 | /* per-register bitmasks: */ |
| 66 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 67 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
| 68 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) |
| 69 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 70 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 71 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
| 72 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 73 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 74 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 75 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 76 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
| 77 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 78 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 79 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
| 80 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) |
| 81 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) |
| 82 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) |
| 83 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) |
| 84 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) |
| 85 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 86 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 87 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
| 88 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) |
| 89 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 90 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 91 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 92 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 93 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 94 | |
| 95 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
| 96 | struct omap2_mcspi_dma { |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 97 | struct dma_chan *dma_tx; |
| 98 | struct dma_chan *dma_rx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 99 | |
| 100 | int dma_tx_sync_dev; |
| 101 | int dma_rx_sync_dev; |
| 102 | |
| 103 | struct completion dma_tx_completion; |
| 104 | struct completion dma_rx_completion; |
| 105 | }; |
| 106 | |
| 107 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and |
| 108 | * cache operations; better heuristics consider wordsize and bitrate. |
| 109 | */ |
Roman Tereshonkov | 8b66c13 | 2010-04-12 09:07:54 +0000 | [diff] [blame] | 110 | #define DMA_MIN_BYTES 160 |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 111 | |
| 112 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 113 | /* |
| 114 | * Used for context save and restore, structure members to be updated whenever |
| 115 | * corresponding registers are modified. |
| 116 | */ |
| 117 | struct omap2_mcspi_regs { |
| 118 | u32 modulctrl; |
| 119 | u32 wakeupenable; |
| 120 | struct list_head cs; |
| 121 | }; |
| 122 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 123 | struct omap2_mcspi { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 124 | struct spi_master *master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 125 | /* Virtual base address of the controller */ |
| 126 | void __iomem *base; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 127 | unsigned long phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 128 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
| 129 | struct omap2_mcspi_dma *dma_channels; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 130 | struct device *dev; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 131 | struct omap2_mcspi_regs ctx; |
Daniel Mack | 0384e90 | 2012-10-07 18:19:44 +0200 | [diff] [blame] | 132 | unsigned int pin_dir:1; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 133 | }; |
| 134 | |
| 135 | struct omap2_mcspi_cs { |
| 136 | void __iomem *base; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 137 | unsigned long phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 138 | int word_len; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 139 | struct list_head node; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 140 | /* Context save and restore shadow register */ |
| 141 | u32 chconf0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 142 | }; |
| 143 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 144 | static inline void mcspi_write_reg(struct spi_master *master, |
| 145 | int idx, u32 val) |
| 146 | { |
| 147 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 148 | |
| 149 | __raw_writel(val, mcspi->base + idx); |
| 150 | } |
| 151 | |
| 152 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) |
| 153 | { |
| 154 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 155 | |
| 156 | return __raw_readl(mcspi->base + idx); |
| 157 | } |
| 158 | |
| 159 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, |
| 160 | int idx, u32 val) |
| 161 | { |
| 162 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 163 | |
| 164 | __raw_writel(val, cs->base + idx); |
| 165 | } |
| 166 | |
| 167 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) |
| 168 | { |
| 169 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 170 | |
| 171 | return __raw_readl(cs->base + idx); |
| 172 | } |
| 173 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 174 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
| 175 | { |
| 176 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 177 | |
| 178 | return cs->chconf0; |
| 179 | } |
| 180 | |
| 181 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) |
| 182 | { |
| 183 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 184 | |
| 185 | cs->chconf0 = val; |
| 186 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); |
Roman Tereshonkov | a330ce2 | 2010-03-15 09:06:28 +0000 | [diff] [blame] | 187 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 188 | } |
| 189 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 190 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
| 191 | int is_read, int enable) |
| 192 | { |
| 193 | u32 l, rw; |
| 194 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 195 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 196 | |
| 197 | if (is_read) /* 1 is read, 0 write */ |
| 198 | rw = OMAP2_MCSPI_CHCONF_DMAR; |
| 199 | else |
| 200 | rw = OMAP2_MCSPI_CHCONF_DMAW; |
| 201 | |
Shubhrajyoti D | af4e944 | 2012-08-22 11:35:13 +0530 | [diff] [blame] | 202 | if (enable) |
| 203 | l |= rw; |
| 204 | else |
| 205 | l &= ~rw; |
| 206 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 207 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) |
| 211 | { |
| 212 | u32 l; |
| 213 | |
| 214 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; |
| 215 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 216 | /* Flash post-writes */ |
| 217 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) |
| 221 | { |
| 222 | u32 l; |
| 223 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 224 | l = mcspi_cached_chconf0(spi); |
Shubhrajyoti D | af4e944 | 2012-08-22 11:35:13 +0530 | [diff] [blame] | 225 | if (cs_active) |
| 226 | l |= OMAP2_MCSPI_CHCONF_FORCE; |
| 227 | else |
| 228 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; |
| 229 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 230 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | static void omap2_mcspi_set_master_mode(struct spi_master *master) |
| 234 | { |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 235 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 236 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 237 | u32 l; |
| 238 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 239 | /* |
| 240 | * Setup when switching from (reset default) slave mode |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 241 | * to single-channel master mode |
| 242 | */ |
| 243 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); |
Shubhrajyoti D | af4e944 | 2012-08-22 11:35:13 +0530 | [diff] [blame] | 244 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
| 245 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 246 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 247 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 248 | ctx->modulctrl = l; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
| 252 | { |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 253 | struct spi_master *spi_cntrl = mcspi->master; |
| 254 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
| 255 | struct omap2_mcspi_cs *cs; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 256 | |
| 257 | /* McSPI: context restore */ |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 258 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
| 259 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 260 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 261 | list_for_each_entry(cs, &ctx->cs, node) |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 262 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 263 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 264 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 265 | static int omap2_prepare_transfer(struct spi_master *master) |
| 266 | { |
| 267 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 268 | |
| 269 | pm_runtime_get_sync(mcspi->dev); |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | static int omap2_unprepare_transfer(struct spi_master *master) |
| 274 | { |
| 275 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 276 | |
| 277 | pm_runtime_mark_last_busy(mcspi->dev); |
| 278 | pm_runtime_put_autosuspend(mcspi->dev); |
| 279 | return 0; |
| 280 | } |
| 281 | |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 282 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
| 283 | { |
| 284 | unsigned long timeout; |
| 285 | |
| 286 | timeout = jiffies + msecs_to_jiffies(1000); |
| 287 | while (!(__raw_readl(reg) & bit)) { |
Sebastian Andrzej Siewior | ff23fa3 | 2013-03-21 13:22:48 +0100 | [diff] [blame] | 288 | if (time_after(jiffies, timeout)) { |
| 289 | if (!(__raw_readl(reg) & bit)) |
| 290 | return -ETIMEDOUT; |
| 291 | else |
| 292 | return 0; |
| 293 | } |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 294 | cpu_relax(); |
| 295 | } |
| 296 | return 0; |
| 297 | } |
| 298 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 299 | static void omap2_mcspi_rx_callback(void *data) |
| 300 | { |
| 301 | struct spi_device *spi = data; |
| 302 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
| 303 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 304 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 305 | /* We must disable the DMA RX request */ |
| 306 | omap2_mcspi_set_dma_req(spi, 1, 0); |
Felipe Balbi | 830379e | 2012-12-12 10:45:59 +0200 | [diff] [blame] | 307 | |
| 308 | complete(&mcspi_dma->dma_rx_completion); |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 309 | } |
| 310 | |
| 311 | static void omap2_mcspi_tx_callback(void *data) |
| 312 | { |
| 313 | struct spi_device *spi = data; |
| 314 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
| 315 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 316 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 317 | /* We must disable the DMA TX request */ |
| 318 | omap2_mcspi_set_dma_req(spi, 0, 0); |
Felipe Balbi | 830379e | 2012-12-12 10:45:59 +0200 | [diff] [blame] | 319 | |
| 320 | complete(&mcspi_dma->dma_tx_completion); |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 321 | } |
| 322 | |
Shubhrajyoti D | d7b4394 | 2012-09-11 12:13:20 +0530 | [diff] [blame] | 323 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
| 324 | struct spi_transfer *xfer, |
| 325 | struct dma_slave_config cfg) |
| 326 | { |
| 327 | struct omap2_mcspi *mcspi; |
| 328 | struct omap2_mcspi_dma *mcspi_dma; |
| 329 | unsigned int count; |
Shubhrajyoti D | d7b4394 | 2012-09-11 12:13:20 +0530 | [diff] [blame] | 330 | |
| 331 | mcspi = spi_master_get_devdata(spi->master); |
| 332 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 333 | count = xfer->len; |
| 334 | |
Shubhrajyoti D | d7b4394 | 2012-09-11 12:13:20 +0530 | [diff] [blame] | 335 | if (mcspi_dma->dma_tx) { |
| 336 | struct dma_async_tx_descriptor *tx; |
| 337 | struct scatterlist sg; |
| 338 | |
| 339 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); |
| 340 | |
| 341 | sg_init_table(&sg, 1); |
| 342 | sg_dma_address(&sg) = xfer->tx_dma; |
| 343 | sg_dma_len(&sg) = xfer->len; |
| 344 | |
| 345 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, |
| 346 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 347 | if (tx) { |
| 348 | tx->callback = omap2_mcspi_tx_callback; |
| 349 | tx->callback_param = spi; |
| 350 | dmaengine_submit(tx); |
| 351 | } else { |
| 352 | /* FIXME: fall back to PIO? */ |
| 353 | } |
| 354 | } |
| 355 | dma_async_issue_pending(mcspi_dma->dma_tx); |
| 356 | omap2_mcspi_set_dma_req(spi, 0, 1); |
| 357 | |
Shubhrajyoti D | d7b4394 | 2012-09-11 12:13:20 +0530 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | static unsigned |
| 361 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, |
| 362 | struct dma_slave_config cfg, |
| 363 | unsigned es) |
| 364 | { |
| 365 | struct omap2_mcspi *mcspi; |
| 366 | struct omap2_mcspi_dma *mcspi_dma; |
| 367 | unsigned int count; |
| 368 | u32 l; |
| 369 | int elements = 0; |
| 370 | int word_len, element_count; |
| 371 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 372 | mcspi = spi_master_get_devdata(spi->master); |
| 373 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 374 | count = xfer->len; |
| 375 | word_len = cs->word_len; |
| 376 | l = mcspi_cached_chconf0(spi); |
| 377 | |
| 378 | if (word_len <= 8) |
| 379 | element_count = count; |
| 380 | else if (word_len <= 16) |
| 381 | element_count = count >> 1; |
| 382 | else /* word_len <= 32 */ |
| 383 | element_count = count >> 2; |
| 384 | |
| 385 | if (mcspi_dma->dma_rx) { |
| 386 | struct dma_async_tx_descriptor *tx; |
| 387 | struct scatterlist sg; |
| 388 | size_t len = xfer->len - es; |
| 389 | |
| 390 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); |
| 391 | |
| 392 | if (l & OMAP2_MCSPI_CHCONF_TURBO) |
| 393 | len -= es; |
| 394 | |
| 395 | sg_init_table(&sg, 1); |
| 396 | sg_dma_address(&sg) = xfer->rx_dma; |
| 397 | sg_dma_len(&sg) = len; |
| 398 | |
| 399 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, |
| 400 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | |
| 401 | DMA_CTRL_ACK); |
| 402 | if (tx) { |
| 403 | tx->callback = omap2_mcspi_rx_callback; |
| 404 | tx->callback_param = spi; |
| 405 | dmaengine_submit(tx); |
| 406 | } else { |
| 407 | /* FIXME: fall back to PIO? */ |
| 408 | } |
| 409 | } |
| 410 | |
| 411 | dma_async_issue_pending(mcspi_dma->dma_rx); |
| 412 | omap2_mcspi_set_dma_req(spi, 1, 1); |
| 413 | |
| 414 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
| 415 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, |
| 416 | DMA_FROM_DEVICE); |
| 417 | omap2_mcspi_set_enable(spi, 0); |
| 418 | |
| 419 | elements = element_count - 1; |
| 420 | |
| 421 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
| 422 | elements--; |
| 423 | |
| 424 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
| 425 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
| 426 | u32 w; |
| 427 | |
| 428 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); |
| 429 | if (word_len <= 8) |
| 430 | ((u8 *)xfer->rx_buf)[elements++] = w; |
| 431 | else if (word_len <= 16) |
| 432 | ((u16 *)xfer->rx_buf)[elements++] = w; |
| 433 | else /* word_len <= 32 */ |
| 434 | ((u32 *)xfer->rx_buf)[elements++] = w; |
| 435 | } else { |
| 436 | dev_err(&spi->dev, "DMA RX penultimate word empty"); |
| 437 | count -= (word_len <= 8) ? 2 : |
| 438 | (word_len <= 16) ? 4 : |
| 439 | /* word_len <= 32 */ 8; |
| 440 | omap2_mcspi_set_enable(spi, 1); |
| 441 | return count; |
| 442 | } |
| 443 | } |
| 444 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
| 445 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
| 446 | u32 w; |
| 447 | |
| 448 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); |
| 449 | if (word_len <= 8) |
| 450 | ((u8 *)xfer->rx_buf)[elements] = w; |
| 451 | else if (word_len <= 16) |
| 452 | ((u16 *)xfer->rx_buf)[elements] = w; |
| 453 | else /* word_len <= 32 */ |
| 454 | ((u32 *)xfer->rx_buf)[elements] = w; |
| 455 | } else { |
| 456 | dev_err(&spi->dev, "DMA RX last word empty"); |
| 457 | count -= (word_len <= 8) ? 1 : |
| 458 | (word_len <= 16) ? 2 : |
| 459 | /* word_len <= 32 */ 4; |
| 460 | } |
| 461 | omap2_mcspi_set_enable(spi, 1); |
| 462 | return count; |
| 463 | } |
| 464 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 465 | static unsigned |
| 466 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) |
| 467 | { |
| 468 | struct omap2_mcspi *mcspi; |
| 469 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 470 | struct omap2_mcspi_dma *mcspi_dma; |
Russell King | 8c7494a | 2012-04-23 13:56:25 +0100 | [diff] [blame] | 471 | unsigned int count; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 472 | u32 l; |
Shubhrajyoti D | d7b4394 | 2012-09-11 12:13:20 +0530 | [diff] [blame] | 473 | u8 *rx; |
| 474 | const u8 *tx; |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 475 | struct dma_slave_config cfg; |
| 476 | enum dma_slave_buswidth width; |
| 477 | unsigned es; |
Shubhrajyoti D | e47a682 | 2012-11-06 14:30:19 +0530 | [diff] [blame] | 478 | void __iomem *chstat_reg; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 479 | |
| 480 | mcspi = spi_master_get_devdata(spi->master); |
| 481 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 482 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 483 | |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 484 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 485 | if (cs->word_len <= 8) { |
| 486 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
| 487 | es = 1; |
| 488 | } else if (cs->word_len <= 16) { |
| 489 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
| 490 | es = 2; |
| 491 | } else { |
| 492 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 493 | es = 4; |
| 494 | } |
| 495 | |
| 496 | memset(&cfg, 0, sizeof(cfg)); |
| 497 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; |
| 498 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; |
| 499 | cfg.src_addr_width = width; |
| 500 | cfg.dst_addr_width = width; |
| 501 | cfg.src_maxburst = 1; |
| 502 | cfg.dst_maxburst = 1; |
| 503 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 504 | rx = xfer->rx_buf; |
| 505 | tx = xfer->tx_buf; |
| 506 | |
Shubhrajyoti D | d7b4394 | 2012-09-11 12:13:20 +0530 | [diff] [blame] | 507 | count = xfer->len; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 508 | |
Shubhrajyoti D | d7b4394 | 2012-09-11 12:13:20 +0530 | [diff] [blame] | 509 | if (tx != NULL) |
| 510 | omap2_mcspi_tx_dma(spi, xfer, cfg); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 511 | |
Shubhrajyoti D | d7b4394 | 2012-09-11 12:13:20 +0530 | [diff] [blame] | 512 | if (rx != NULL) |
Shubhrajyoti D | e47a682 | 2012-11-06 14:30:19 +0530 | [diff] [blame] | 513 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 514 | |
Shubhrajyoti D | e47a682 | 2012-11-06 14:30:19 +0530 | [diff] [blame] | 515 | if (tx != NULL) { |
| 516 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
| 517 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
| 518 | dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, |
| 519 | DMA_TO_DEVICE); |
| 520 | |
| 521 | /* for TX_ONLY mode, be sure all words have shifted out */ |
| 522 | if (rx == NULL) { |
| 523 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 524 | OMAP2_MCSPI_CHSTAT_TXS) < 0) |
| 525 | dev_err(&spi->dev, "TXS timed out\n"); |
| 526 | else if (mcspi_wait_for_reg_bit(chstat_reg, |
| 527 | OMAP2_MCSPI_CHSTAT_EOT) < 0) |
| 528 | dev_err(&spi->dev, "EOT timed out\n"); |
| 529 | } |
| 530 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 531 | return count; |
| 532 | } |
| 533 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 534 | static unsigned |
| 535 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) |
| 536 | { |
| 537 | struct omap2_mcspi *mcspi; |
| 538 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 539 | unsigned int count, c; |
| 540 | u32 l; |
| 541 | void __iomem *base = cs->base; |
| 542 | void __iomem *tx_reg; |
| 543 | void __iomem *rx_reg; |
| 544 | void __iomem *chstat_reg; |
| 545 | int word_len; |
| 546 | |
| 547 | mcspi = spi_master_get_devdata(spi->master); |
| 548 | count = xfer->len; |
| 549 | c = count; |
| 550 | word_len = cs->word_len; |
| 551 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 552 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 553 | |
| 554 | /* We store the pre-calculated register addresses on stack to speed |
| 555 | * up the transfer loop. */ |
| 556 | tx_reg = base + OMAP2_MCSPI_TX0; |
| 557 | rx_reg = base + OMAP2_MCSPI_RX0; |
| 558 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; |
| 559 | |
Michael Jones | adef658 | 2011-02-25 16:55:11 +0100 | [diff] [blame] | 560 | if (c < (word_len>>3)) |
| 561 | return 0; |
| 562 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 563 | if (word_len <= 8) { |
| 564 | u8 *rx; |
| 565 | const u8 *tx; |
| 566 | |
| 567 | rx = xfer->rx_buf; |
| 568 | tx = xfer->tx_buf; |
| 569 | |
| 570 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 571 | c -= 1; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 572 | if (tx != NULL) { |
| 573 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 574 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 575 | dev_err(&spi->dev, "TXS timed out\n"); |
| 576 | goto out; |
| 577 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 578 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 579 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 580 | __raw_writel(*tx++, tx_reg); |
| 581 | } |
| 582 | if (rx != NULL) { |
| 583 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 584 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 585 | dev_err(&spi->dev, "RXS timed out\n"); |
| 586 | goto out; |
| 587 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 588 | |
| 589 | if (c == 1 && tx == NULL && |
| 590 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 591 | omap2_mcspi_set_enable(spi, 0); |
| 592 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 593 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 594 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 595 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 596 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 597 | dev_err(&spi->dev, |
| 598 | "RXS timed out\n"); |
| 599 | goto out; |
| 600 | } |
| 601 | c = 0; |
| 602 | } else if (c == 0 && tx == NULL) { |
| 603 | omap2_mcspi_set_enable(spi, 0); |
| 604 | } |
| 605 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 606 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 607 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 608 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 609 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 610 | } while (c); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 611 | } else if (word_len <= 16) { |
| 612 | u16 *rx; |
| 613 | const u16 *tx; |
| 614 | |
| 615 | rx = xfer->rx_buf; |
| 616 | tx = xfer->tx_buf; |
| 617 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 618 | c -= 2; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 619 | if (tx != NULL) { |
| 620 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 621 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 622 | dev_err(&spi->dev, "TXS timed out\n"); |
| 623 | goto out; |
| 624 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 625 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 626 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 627 | __raw_writel(*tx++, tx_reg); |
| 628 | } |
| 629 | if (rx != NULL) { |
| 630 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 631 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 632 | dev_err(&spi->dev, "RXS timed out\n"); |
| 633 | goto out; |
| 634 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 635 | |
| 636 | if (c == 2 && tx == NULL && |
| 637 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 638 | omap2_mcspi_set_enable(spi, 0); |
| 639 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 640 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 641 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 642 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 643 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 644 | dev_err(&spi->dev, |
| 645 | "RXS timed out\n"); |
| 646 | goto out; |
| 647 | } |
| 648 | c = 0; |
| 649 | } else if (c == 0 && tx == NULL) { |
| 650 | omap2_mcspi_set_enable(spi, 0); |
| 651 | } |
| 652 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 653 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 654 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 655 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 656 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 657 | } while (c >= 2); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 658 | } else if (word_len <= 32) { |
| 659 | u32 *rx; |
| 660 | const u32 *tx; |
| 661 | |
| 662 | rx = xfer->rx_buf; |
| 663 | tx = xfer->tx_buf; |
| 664 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 665 | c -= 4; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 666 | if (tx != NULL) { |
| 667 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 668 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 669 | dev_err(&spi->dev, "TXS timed out\n"); |
| 670 | goto out; |
| 671 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 672 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 673 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 674 | __raw_writel(*tx++, tx_reg); |
| 675 | } |
| 676 | if (rx != NULL) { |
| 677 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 678 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 679 | dev_err(&spi->dev, "RXS timed out\n"); |
| 680 | goto out; |
| 681 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 682 | |
| 683 | if (c == 4 && tx == NULL && |
| 684 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 685 | omap2_mcspi_set_enable(spi, 0); |
| 686 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 687 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 688 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 689 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 690 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 691 | dev_err(&spi->dev, |
| 692 | "RXS timed out\n"); |
| 693 | goto out; |
| 694 | } |
| 695 | c = 0; |
| 696 | } else if (c == 0 && tx == NULL) { |
| 697 | omap2_mcspi_set_enable(spi, 0); |
| 698 | } |
| 699 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 700 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 701 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 702 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 703 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 704 | } while (c >= 4); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 705 | } |
| 706 | |
| 707 | /* for TX_ONLY mode, be sure all words have shifted out */ |
| 708 | if (xfer->rx_buf == NULL) { |
| 709 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 710 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 711 | dev_err(&spi->dev, "TXS timed out\n"); |
| 712 | } else if (mcspi_wait_for_reg_bit(chstat_reg, |
| 713 | OMAP2_MCSPI_CHSTAT_EOT) < 0) |
| 714 | dev_err(&spi->dev, "EOT timed out\n"); |
Jason Wang | e1993ed | 2010-10-19 18:03:27 +0800 | [diff] [blame] | 715 | |
| 716 | /* disable chan to purge rx datas received in TX_ONLY transfer, |
| 717 | * otherwise these rx datas will affect the direct following |
| 718 | * RX_ONLY transfer. |
| 719 | */ |
| 720 | omap2_mcspi_set_enable(spi, 0); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 721 | } |
| 722 | out: |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 723 | omap2_mcspi_set_enable(spi, 1); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 724 | return count - c; |
| 725 | } |
| 726 | |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 727 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
| 728 | { |
| 729 | u32 div; |
| 730 | |
| 731 | for (div = 0; div < 15; div++) |
| 732 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) |
| 733 | return div; |
| 734 | |
| 735 | return 15; |
| 736 | } |
| 737 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 738 | /* called only when no transfer is active to this device */ |
| 739 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, |
| 740 | struct spi_transfer *t) |
| 741 | { |
| 742 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 743 | struct omap2_mcspi *mcspi; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 744 | struct spi_master *spi_cntrl; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 745 | u32 l = 0, div = 0; |
| 746 | u8 word_len = spi->bits_per_word; |
Scott Ellis | 9bd4517 | 2010-03-10 14:23:13 -0700 | [diff] [blame] | 747 | u32 speed_hz = spi->max_speed_hz; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 748 | |
| 749 | mcspi = spi_master_get_devdata(spi->master); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 750 | spi_cntrl = mcspi->master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 751 | |
| 752 | if (t != NULL && t->bits_per_word) |
| 753 | word_len = t->bits_per_word; |
| 754 | |
| 755 | cs->word_len = word_len; |
| 756 | |
Scott Ellis | 9bd4517 | 2010-03-10 14:23:13 -0700 | [diff] [blame] | 757 | if (t && t->speed_hz) |
| 758 | speed_hz = t->speed_hz; |
| 759 | |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 760 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
| 761 | div = omap2_mcspi_calc_divisor(speed_hz); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 762 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 763 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 764 | |
| 765 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS |
| 766 | * REVISIT: this controller could support SPI_3WIRE mode. |
| 767 | */ |
Daniel Mack | 2cd4517 | 2012-11-14 11:14:26 +0800 | [diff] [blame] | 768 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { |
Daniel Mack | 0384e90 | 2012-10-07 18:19:44 +0200 | [diff] [blame] | 769 | l &= ~OMAP2_MCSPI_CHCONF_IS; |
| 770 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; |
| 771 | l |= OMAP2_MCSPI_CHCONF_DPE0; |
| 772 | } else { |
| 773 | l |= OMAP2_MCSPI_CHCONF_IS; |
| 774 | l |= OMAP2_MCSPI_CHCONF_DPE1; |
| 775 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; |
| 776 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 777 | |
| 778 | /* wordlength */ |
| 779 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; |
| 780 | l |= (word_len - 1) << 7; |
| 781 | |
| 782 | /* set chipselect polarity; manage with FORCE */ |
| 783 | if (!(spi->mode & SPI_CS_HIGH)) |
| 784 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ |
| 785 | else |
| 786 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; |
| 787 | |
| 788 | /* set clock divisor */ |
| 789 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; |
| 790 | l |= div << 2; |
| 791 | |
| 792 | /* set SPI mode 0..3 */ |
| 793 | if (spi->mode & SPI_CPOL) |
| 794 | l |= OMAP2_MCSPI_CHCONF_POL; |
| 795 | else |
| 796 | l &= ~OMAP2_MCSPI_CHCONF_POL; |
| 797 | if (spi->mode & SPI_CPHA) |
| 798 | l |= OMAP2_MCSPI_CHCONF_PHA; |
| 799 | else |
| 800 | l &= ~OMAP2_MCSPI_CHCONF_PHA; |
| 801 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 802 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 803 | |
| 804 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 805 | OMAP2_MCSPI_MAX_FREQ >> div, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 806 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
| 807 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); |
| 808 | |
| 809 | return 0; |
| 810 | } |
| 811 | |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 812 | /* |
| 813 | * Note that we currently allow DMA only if we get a channel |
| 814 | * for both rx and tx. Otherwise we'll do PIO for both rx and tx. |
| 815 | */ |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 816 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
| 817 | { |
| 818 | struct spi_master *master = spi->master; |
| 819 | struct omap2_mcspi *mcspi; |
| 820 | struct omap2_mcspi_dma *mcspi_dma; |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 821 | dma_cap_mask_t mask; |
| 822 | unsigned sig; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 823 | |
| 824 | mcspi = spi_master_get_devdata(master); |
| 825 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
| 826 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 827 | init_completion(&mcspi_dma->dma_rx_completion); |
| 828 | init_completion(&mcspi_dma->dma_tx_completion); |
| 829 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 830 | dma_cap_zero(mask); |
| 831 | dma_cap_set(DMA_SLAVE, mask); |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 832 | sig = mcspi_dma->dma_rx_sync_dev; |
| 833 | mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 834 | if (!mcspi_dma->dma_rx) |
| 835 | goto no_dma; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 836 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 837 | sig = mcspi_dma->dma_tx_sync_dev; |
| 838 | mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); |
| 839 | if (!mcspi_dma->dma_tx) { |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 840 | dma_release_channel(mcspi_dma->dma_rx); |
| 841 | mcspi_dma->dma_rx = NULL; |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 842 | goto no_dma; |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 843 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 844 | |
| 845 | return 0; |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 846 | |
| 847 | no_dma: |
| 848 | dev_warn(&spi->dev, "not using DMA for McSPI\n"); |
| 849 | return -EAGAIN; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 850 | } |
| 851 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 852 | static int omap2_mcspi_setup(struct spi_device *spi) |
| 853 | { |
| 854 | int ret; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 855 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
| 856 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 857 | struct omap2_mcspi_dma *mcspi_dma; |
| 858 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 859 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 860 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 861 | |
| 862 | if (!cs) { |
Russell King | 10aa5a3 | 2012-06-18 11:27:04 +0100 | [diff] [blame] | 863 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 864 | if (!cs) |
| 865 | return -ENOMEM; |
| 866 | cs->base = mcspi->base + spi->chip_select * 0x14; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 867 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 868 | cs->chconf0 = 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 869 | spi->controller_state = cs; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 870 | /* Link this to context save list */ |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 871 | list_add_tail(&cs->node, &ctx->cs); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 872 | } |
| 873 | |
Russell King | 8c7494a | 2012-04-23 13:56:25 +0100 | [diff] [blame] | 874 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 875 | ret = omap2_mcspi_request_dma(spi); |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 876 | if (ret < 0 && ret != -EAGAIN) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 877 | return ret; |
| 878 | } |
| 879 | |
Shubhrajyoti D | 034d3dc | 2012-08-22 11:35:12 +0530 | [diff] [blame] | 880 | ret = pm_runtime_get_sync(mcspi->dev); |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 881 | if (ret < 0) |
| 882 | return ret; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 883 | |
Kyungmin Park | 86eeb6f | 2007-10-16 01:27:45 -0700 | [diff] [blame] | 884 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
Shubhrajyoti D | 034d3dc | 2012-08-22 11:35:12 +0530 | [diff] [blame] | 885 | pm_runtime_mark_last_busy(mcspi->dev); |
| 886 | pm_runtime_put_autosuspend(mcspi->dev); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 887 | |
| 888 | return ret; |
| 889 | } |
| 890 | |
| 891 | static void omap2_mcspi_cleanup(struct spi_device *spi) |
| 892 | { |
| 893 | struct omap2_mcspi *mcspi; |
| 894 | struct omap2_mcspi_dma *mcspi_dma; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 895 | struct omap2_mcspi_cs *cs; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 896 | |
| 897 | mcspi = spi_master_get_devdata(spi->master); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 898 | |
Scott Ellis | 5e77494 | 2010-03-10 14:22:45 -0700 | [diff] [blame] | 899 | if (spi->controller_state) { |
| 900 | /* Unlink controller state from context save list */ |
| 901 | cs = spi->controller_state; |
| 902 | list_del(&cs->node); |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 903 | |
Russell King | 10aa5a3 | 2012-06-18 11:27:04 +0100 | [diff] [blame] | 904 | kfree(cs); |
Scott Ellis | 5e77494 | 2010-03-10 14:22:45 -0700 | [diff] [blame] | 905 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 906 | |
Scott Ellis | 99f1a43 | 2010-05-24 14:20:27 +0000 | [diff] [blame] | 907 | if (spi->chip_select < spi->master->num_chipselect) { |
| 908 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 909 | |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 910 | if (mcspi_dma->dma_rx) { |
| 911 | dma_release_channel(mcspi_dma->dma_rx); |
| 912 | mcspi_dma->dma_rx = NULL; |
Scott Ellis | 99f1a43 | 2010-05-24 14:20:27 +0000 | [diff] [blame] | 913 | } |
Russell King | 53741ed | 2012-04-23 13:51:48 +0100 | [diff] [blame] | 914 | if (mcspi_dma->dma_tx) { |
| 915 | dma_release_channel(mcspi_dma->dma_tx); |
| 916 | mcspi_dma->dma_tx = NULL; |
Scott Ellis | 99f1a43 | 2010-05-24 14:20:27 +0000 | [diff] [blame] | 917 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 918 | } |
| 919 | } |
| 920 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 921 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 922 | { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 923 | |
| 924 | /* We only enable one channel at a time -- the one whose message is |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 925 | * -- although this controller would gladly |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 926 | * arbitrate among multiple channels. This corresponds to "single |
| 927 | * channel" master mode. As a side effect, we need to manage the |
| 928 | * chipselect with the FORCE bit ... CS != channel enable. |
| 929 | */ |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 930 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 931 | struct spi_device *spi; |
| 932 | struct spi_transfer *t = NULL; |
Matthias Brugger | 5cbc7ca | 2013-01-24 13:40:41 +0100 | [diff] [blame] | 933 | struct spi_master *master; |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 934 | struct omap2_mcspi_dma *mcspi_dma; |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 935 | int cs_active = 0; |
| 936 | struct omap2_mcspi_cs *cs; |
| 937 | struct omap2_mcspi_device_config *cd; |
| 938 | int par_override = 0; |
| 939 | int status = 0; |
| 940 | u32 chconf; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 941 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 942 | spi = m->spi; |
Matthias Brugger | 5cbc7ca | 2013-01-24 13:40:41 +0100 | [diff] [blame] | 943 | master = spi->master; |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 944 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 945 | cs = spi->controller_state; |
| 946 | cd = spi->controller_data; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 947 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 948 | omap2_mcspi_set_enable(spi, 1); |
| 949 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 950 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { |
| 951 | status = -EINVAL; |
| 952 | break; |
| 953 | } |
| 954 | if (par_override || t->speed_hz || t->bits_per_word) { |
| 955 | par_override = 1; |
| 956 | status = omap2_mcspi_setup_transfer(spi, t); |
| 957 | if (status < 0) |
| 958 | break; |
| 959 | if (!t->speed_hz && !t->bits_per_word) |
| 960 | par_override = 0; |
| 961 | } |
Matthias Brugger | 5cbc7ca | 2013-01-24 13:40:41 +0100 | [diff] [blame] | 962 | if (cd && cd->cs_per_word) { |
| 963 | chconf = mcspi->ctx.modulctrl; |
| 964 | chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; |
| 965 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); |
| 966 | mcspi->ctx.modulctrl = |
| 967 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); |
| 968 | } |
| 969 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 970 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 971 | if (!cs_active) { |
| 972 | omap2_mcspi_force_cs(spi, 1); |
| 973 | cs_active = 1; |
| 974 | } |
| 975 | |
| 976 | chconf = mcspi_cached_chconf0(spi); |
| 977 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; |
| 978 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; |
| 979 | |
| 980 | if (t->tx_buf == NULL) |
| 981 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; |
| 982 | else if (t->rx_buf == NULL) |
| 983 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; |
| 984 | |
| 985 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
| 986 | /* Turbo mode is for more than one word */ |
| 987 | if (t->len > ((cs->word_len + 7) >> 3)) |
| 988 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; |
| 989 | } |
| 990 | |
| 991 | mcspi_write_chconf0(spi, chconf); |
| 992 | |
| 993 | if (t->len) { |
| 994 | unsigned count; |
| 995 | |
| 996 | /* RX_ONLY mode needs dummy data in TX reg */ |
| 997 | if (t->tx_buf == NULL) |
| 998 | __raw_writel(0, cs->base |
| 999 | + OMAP2_MCSPI_TX0); |
| 1000 | |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 1001 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
| 1002 | (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1003 | count = omap2_mcspi_txrx_dma(spi, t); |
| 1004 | else |
| 1005 | count = omap2_mcspi_txrx_pio(spi, t); |
| 1006 | m->actual_length += count; |
| 1007 | |
| 1008 | if (count != t->len) { |
| 1009 | status = -EIO; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1010 | break; |
| 1011 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1012 | } |
| 1013 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1014 | if (t->delay_usecs) |
| 1015 | udelay(t->delay_usecs); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1016 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1017 | /* ignore the "leave it on after last xfer" hint */ |
| 1018 | if (t->cs_change) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1019 | omap2_mcspi_force_cs(spi, 0); |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1020 | cs_active = 0; |
| 1021 | } |
| 1022 | } |
| 1023 | /* Restore defaults if they were overriden */ |
| 1024 | if (par_override) { |
| 1025 | par_override = 0; |
| 1026 | status = omap2_mcspi_setup_transfer(spi, NULL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1027 | } |
| 1028 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1029 | if (cs_active) |
| 1030 | omap2_mcspi_force_cs(spi, 0); |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1031 | |
Matthias Brugger | 5cbc7ca | 2013-01-24 13:40:41 +0100 | [diff] [blame] | 1032 | if (cd && cd->cs_per_word) { |
| 1033 | chconf = mcspi->ctx.modulctrl; |
| 1034 | chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; |
| 1035 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); |
| 1036 | mcspi->ctx.modulctrl = |
| 1037 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); |
| 1038 | } |
| 1039 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1040 | omap2_mcspi_set_enable(spi, 0); |
| 1041 | |
| 1042 | m->status = status; |
| 1043 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1044 | } |
| 1045 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1046 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
Matthias Brugger | 18dd619 | 2013-01-24 13:28:58 +0100 | [diff] [blame] | 1047 | struct spi_message *m) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1048 | { |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 1049 | struct spi_device *spi; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1050 | struct omap2_mcspi *mcspi; |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 1051 | struct omap2_mcspi_dma *mcspi_dma; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1052 | struct spi_transfer *t; |
| 1053 | |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 1054 | spi = m->spi; |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1055 | mcspi = spi_master_get_devdata(master); |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 1056 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1057 | m->actual_length = 0; |
| 1058 | m->status = 0; |
| 1059 | |
| 1060 | /* reject invalid messages and transfers */ |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1061 | if (list_empty(&m->transfers)) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1062 | return -EINVAL; |
| 1063 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 1064 | const void *tx_buf = t->tx_buf; |
| 1065 | void *rx_buf = t->rx_buf; |
| 1066 | unsigned len = t->len; |
| 1067 | |
| 1068 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame^] | 1069 | || (len && !(rx_buf || tx_buf))) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1070 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1071 | t->speed_hz, |
| 1072 | len, |
| 1073 | tx_buf ? "tx" : "", |
| 1074 | rx_buf ? "rx" : "", |
| 1075 | t->bits_per_word); |
| 1076 | return -EINVAL; |
| 1077 | } |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 1078 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1079 | dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", |
Matthias Brugger | 18dd619 | 2013-01-24 13:28:58 +0100 | [diff] [blame] | 1080 | t->speed_hz, |
| 1081 | OMAP2_MCSPI_MAX_FREQ >> 15); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1082 | return -EINVAL; |
| 1083 | } |
| 1084 | |
| 1085 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) |
| 1086 | continue; |
| 1087 | |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 1088 | if (mcspi_dma->dma_tx && tx_buf != NULL) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1089 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1090 | len, DMA_TO_DEVICE); |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1091 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { |
| 1092 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1093 | 'T', len); |
| 1094 | return -EINVAL; |
| 1095 | } |
| 1096 | } |
Tony Lindgren | ddc5cdf | 2013-04-12 17:25:07 -0700 | [diff] [blame] | 1097 | if (mcspi_dma->dma_rx && rx_buf != NULL) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1098 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1099 | DMA_FROM_DEVICE); |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1100 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { |
| 1101 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1102 | 'R', len); |
| 1103 | if (tx_buf != NULL) |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1104 | dma_unmap_single(mcspi->dev, t->tx_dma, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1105 | len, DMA_TO_DEVICE); |
| 1106 | return -EINVAL; |
| 1107 | } |
| 1108 | } |
| 1109 | } |
| 1110 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1111 | omap2_mcspi_work(mcspi, m); |
| 1112 | spi_finalize_current_message(master); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1113 | return 0; |
| 1114 | } |
| 1115 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1116 | static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1117 | { |
| 1118 | struct spi_master *master = mcspi->master; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1119 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1120 | int ret = 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1121 | |
Shubhrajyoti D | 034d3dc | 2012-08-22 11:35:12 +0530 | [diff] [blame] | 1122 | ret = pm_runtime_get_sync(mcspi->dev); |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1123 | if (ret < 0) |
| 1124 | return ret; |
Jouni Hogander | ddb2219 | 2009-07-29 15:02:11 -0700 | [diff] [blame] | 1125 | |
Shubhrajyoti D | 39f8052 | 2012-03-29 22:11:07 +0530 | [diff] [blame] | 1126 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
Matthias Brugger | 18dd619 | 2013-01-24 13:28:58 +0100 | [diff] [blame] | 1127 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
Shubhrajyoti D | 39f8052 | 2012-03-29 22:11:07 +0530 | [diff] [blame] | 1128 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1129 | |
| 1130 | omap2_mcspi_set_master_mode(master); |
Shubhrajyoti D | 034d3dc | 2012-08-22 11:35:12 +0530 | [diff] [blame] | 1131 | pm_runtime_mark_last_busy(mcspi->dev); |
| 1132 | pm_runtime_put_autosuspend(mcspi->dev); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1133 | return 0; |
| 1134 | } |
| 1135 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1136 | static int omap_mcspi_runtime_resume(struct device *dev) |
| 1137 | { |
| 1138 | struct omap2_mcspi *mcspi; |
| 1139 | struct spi_master *master; |
| 1140 | |
| 1141 | master = dev_get_drvdata(dev); |
| 1142 | mcspi = spi_master_get_devdata(master); |
| 1143 | omap2_mcspi_restore_ctx(mcspi); |
| 1144 | |
| 1145 | return 0; |
| 1146 | } |
| 1147 | |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1148 | static struct omap2_mcspi_platform_config omap2_pdata = { |
| 1149 | .regs_offset = 0, |
| 1150 | }; |
| 1151 | |
| 1152 | static struct omap2_mcspi_platform_config omap4_pdata = { |
| 1153 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, |
| 1154 | }; |
| 1155 | |
| 1156 | static const struct of_device_id omap_mcspi_of_match[] = { |
| 1157 | { |
| 1158 | .compatible = "ti,omap2-mcspi", |
| 1159 | .data = &omap2_pdata, |
| 1160 | }, |
| 1161 | { |
| 1162 | .compatible = "ti,omap4-mcspi", |
| 1163 | .data = &omap4_pdata, |
| 1164 | }, |
| 1165 | { }, |
| 1166 | }; |
| 1167 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); |
Girish | ccc7bae | 2008-02-06 01:38:16 -0800 | [diff] [blame] | 1168 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1169 | static int omap2_mcspi_probe(struct platform_device *pdev) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1170 | { |
| 1171 | struct spi_master *master; |
Uwe Kleine-König | 83a01e7 | 2012-05-21 21:57:39 +0200 | [diff] [blame] | 1172 | const struct omap2_mcspi_platform_config *pdata; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1173 | struct omap2_mcspi *mcspi; |
| 1174 | struct resource *r; |
| 1175 | int status = 0, i; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1176 | u32 regs_offset = 0; |
| 1177 | static int bus_num = 1; |
| 1178 | struct device_node *node = pdev->dev.of_node; |
| 1179 | const struct of_device_id *match; |
Matt Porter | ec155af | 2012-09-18 08:01:25 -0400 | [diff] [blame] | 1180 | struct pinctrl *pinctrl; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1181 | |
| 1182 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); |
| 1183 | if (master == NULL) { |
| 1184 | dev_dbg(&pdev->dev, "master allocation failed\n"); |
| 1185 | return -ENOMEM; |
| 1186 | } |
| 1187 | |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 1188 | /* the spi->mode bits understood by this driver: */ |
| 1189 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame^] | 1190 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1191 | master->setup = omap2_mcspi_setup; |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1192 | master->prepare_transfer_hardware = omap2_prepare_transfer; |
| 1193 | master->unprepare_transfer_hardware = omap2_unprepare_transfer; |
| 1194 | master->transfer_one_message = omap2_mcspi_transfer_one_message; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1195 | master->cleanup = omap2_mcspi_cleanup; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1196 | master->dev.of_node = node; |
| 1197 | |
Daniel Mack | 0384e90 | 2012-10-07 18:19:44 +0200 | [diff] [blame] | 1198 | dev_set_drvdata(&pdev->dev, master); |
| 1199 | |
| 1200 | mcspi = spi_master_get_devdata(master); |
| 1201 | mcspi->master = master; |
| 1202 | |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1203 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
| 1204 | if (match) { |
| 1205 | u32 num_cs = 1; /* default number of chipselect */ |
| 1206 | pdata = match->data; |
| 1207 | |
| 1208 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); |
| 1209 | master->num_chipselect = num_cs; |
| 1210 | master->bus_num = bus_num++; |
Daniel Mack | 2cd4517 | 2012-11-14 11:14:26 +0800 | [diff] [blame] | 1211 | if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) |
| 1212 | mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1213 | } else { |
| 1214 | pdata = pdev->dev.platform_data; |
| 1215 | master->num_chipselect = pdata->num_cs; |
| 1216 | if (pdev->id != -1) |
| 1217 | master->bus_num = pdev->id; |
Daniel Mack | 0384e90 | 2012-10-07 18:19:44 +0200 | [diff] [blame] | 1218 | mcspi->pin_dir = pdata->pin_dir; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1219 | } |
| 1220 | regs_offset = pdata->regs_offset; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1221 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1222 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1223 | if (r == NULL) { |
| 1224 | status = -ENODEV; |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1225 | goto free_master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1226 | } |
Shubhrajyoti D | 1458d16 | 2011-10-24 15:54:24 +0530 | [diff] [blame] | 1227 | |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1228 | r->start += regs_offset; |
| 1229 | r->end += regs_offset; |
Shubhrajyoti D | 1458d16 | 2011-10-24 15:54:24 +0530 | [diff] [blame] | 1230 | mcspi->phys = r->start; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1231 | |
Thierry Reding | b0ee560 | 2013-01-21 11:09:18 +0100 | [diff] [blame] | 1232 | mcspi->base = devm_ioremap_resource(&pdev->dev, r); |
| 1233 | if (IS_ERR(mcspi->base)) { |
| 1234 | status = PTR_ERR(mcspi->base); |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 1235 | goto free_master; |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1236 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1237 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1238 | mcspi->dev = &pdev->dev; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1239 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1240 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1241 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1242 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
| 1243 | sizeof(struct omap2_mcspi_dma), |
| 1244 | GFP_KERNEL); |
| 1245 | |
| 1246 | if (mcspi->dma_channels == NULL) |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 1247 | goto free_master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1248 | |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1249 | for (i = 0; i < master->num_chipselect; i++) { |
| 1250 | char dma_ch_name[14]; |
| 1251 | struct resource *dma_res; |
| 1252 | |
| 1253 | sprintf(dma_ch_name, "rx%d", i); |
| 1254 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
Matthias Brugger | 18dd619 | 2013-01-24 13:28:58 +0100 | [diff] [blame] | 1255 | dma_ch_name); |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1256 | if (!dma_res) { |
| 1257 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); |
| 1258 | status = -ENODEV; |
| 1259 | break; |
| 1260 | } |
| 1261 | |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1262 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
| 1263 | sprintf(dma_ch_name, "tx%d", i); |
| 1264 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
Matthias Brugger | 18dd619 | 2013-01-24 13:28:58 +0100 | [diff] [blame] | 1265 | dma_ch_name); |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1266 | if (!dma_res) { |
| 1267 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); |
| 1268 | status = -ENODEV; |
| 1269 | break; |
| 1270 | } |
| 1271 | |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1272 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1273 | } |
| 1274 | |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1275 | if (status < 0) |
| 1276 | goto dma_chnl_free; |
| 1277 | |
Matt Porter | ec155af | 2012-09-18 08:01:25 -0400 | [diff] [blame] | 1278 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
| 1279 | if (IS_ERR(pinctrl)) |
| 1280 | dev_warn(&pdev->dev, |
Matthias Brugger | 18dd619 | 2013-01-24 13:28:58 +0100 | [diff] [blame] | 1281 | "pins are not configured from the driver\n"); |
Matt Porter | ec155af | 2012-09-18 08:01:25 -0400 | [diff] [blame] | 1282 | |
Shubhrajyoti D | 27b5284 | 2012-03-26 17:04:22 +0530 | [diff] [blame] | 1283 | pm_runtime_use_autosuspend(&pdev->dev); |
| 1284 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1285 | pm_runtime_enable(&pdev->dev); |
| 1286 | |
Wei Yongjun | 142e07b | 2013-04-18 11:14:59 +0800 | [diff] [blame] | 1287 | status = omap2_mcspi_master_setup(mcspi); |
| 1288 | if (status < 0) |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1289 | goto disable_pm; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1290 | |
| 1291 | status = spi_register_master(master); |
| 1292 | if (status < 0) |
Shubhrajyoti D | 37a2d84 | 2012-08-02 16:41:25 +0530 | [diff] [blame] | 1293 | goto disable_pm; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1294 | |
| 1295 | return status; |
| 1296 | |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1297 | disable_pm: |
Shubhrajyoti D | 751c925 | 2011-10-28 17:14:18 +0530 | [diff] [blame] | 1298 | pm_runtime_disable(&pdev->dev); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1299 | dma_chnl_free: |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1300 | kfree(mcspi->dma_channels); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1301 | free_master: |
Shubhrajyoti D | 37a2d84 | 2012-08-02 16:41:25 +0530 | [diff] [blame] | 1302 | spi_master_put(master); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1303 | return status; |
| 1304 | } |
| 1305 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1306 | static int omap2_mcspi_remove(struct platform_device *pdev) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1307 | { |
| 1308 | struct spi_master *master; |
| 1309 | struct omap2_mcspi *mcspi; |
| 1310 | struct omap2_mcspi_dma *dma_channels; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1311 | |
| 1312 | master = dev_get_drvdata(&pdev->dev); |
| 1313 | mcspi = spi_master_get_devdata(master); |
| 1314 | dma_channels = mcspi->dma_channels; |
| 1315 | |
Shubhrajyoti D | a93a202 | 2012-08-22 11:35:14 +0530 | [diff] [blame] | 1316 | pm_runtime_put_sync(mcspi->dev); |
Shubhrajyoti D | 751c925 | 2011-10-28 17:14:18 +0530 | [diff] [blame] | 1317 | pm_runtime_disable(&pdev->dev); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1318 | |
| 1319 | spi_unregister_master(master); |
| 1320 | kfree(dma_channels); |
| 1321 | |
| 1322 | return 0; |
| 1323 | } |
| 1324 | |
Kay Sievers | 7e38c3c | 2008-04-10 21:29:20 -0700 | [diff] [blame] | 1325 | /* work with hotplug and coldplug */ |
| 1326 | MODULE_ALIAS("platform:omap2_mcspi"); |
| 1327 | |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1328 | #ifdef CONFIG_SUSPEND |
| 1329 | /* |
| 1330 | * When SPI wake up from off-mode, CS is in activate state. If it was in |
| 1331 | * unactive state when driver was suspend, then force it to unactive state at |
| 1332 | * wake up. |
| 1333 | */ |
| 1334 | static int omap2_mcspi_resume(struct device *dev) |
| 1335 | { |
| 1336 | struct spi_master *master = dev_get_drvdata(dev); |
| 1337 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1338 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
| 1339 | struct omap2_mcspi_cs *cs; |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1340 | |
Shubhrajyoti D | 034d3dc | 2012-08-22 11:35:12 +0530 | [diff] [blame] | 1341 | pm_runtime_get_sync(mcspi->dev); |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1342 | list_for_each_entry(cs, &ctx->cs, node) { |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1343 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1344 | /* |
| 1345 | * We need to toggle CS state for OMAP take this |
| 1346 | * change in account. |
| 1347 | */ |
Shubhrajyoti D | af4e944 | 2012-08-22 11:35:13 +0530 | [diff] [blame] | 1348 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1349 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
Shubhrajyoti D | af4e944 | 2012-08-22 11:35:13 +0530 | [diff] [blame] | 1350 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1351 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
| 1352 | } |
| 1353 | } |
Shubhrajyoti D | 034d3dc | 2012-08-22 11:35:12 +0530 | [diff] [blame] | 1354 | pm_runtime_mark_last_busy(mcspi->dev); |
| 1355 | pm_runtime_put_autosuspend(mcspi->dev); |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1356 | return 0; |
| 1357 | } |
| 1358 | #else |
| 1359 | #define omap2_mcspi_resume NULL |
| 1360 | #endif |
| 1361 | |
| 1362 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { |
| 1363 | .resume = omap2_mcspi_resume, |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1364 | .runtime_resume = omap_mcspi_runtime_resume, |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1365 | }; |
| 1366 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1367 | static struct platform_driver omap2_mcspi_driver = { |
| 1368 | .driver = { |
| 1369 | .name = "omap2_mcspi", |
| 1370 | .owner = THIS_MODULE, |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1371 | .pm = &omap2_mcspi_pm_ops, |
| 1372 | .of_match_table = omap_mcspi_of_match, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1373 | }, |
Felipe Balbi | 7d6b6d8 | 2012-03-14 11:18:30 +0200 | [diff] [blame] | 1374 | .probe = omap2_mcspi_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1375 | .remove = omap2_mcspi_remove, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1376 | }; |
| 1377 | |
Felipe Balbi | 9fdca9d | 2012-03-14 11:18:31 +0200 | [diff] [blame] | 1378 | module_platform_driver(omap2_mcspi_driver); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1379 | MODULE_LICENSE("GPL"); |