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Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
Charulatha V1a5d8192011-02-02 17:52:14 +05306 * Juha Yrj�l� <juha.yrjola@nokia.com>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/device.h>
29#include <linux/delay.h>
30#include <linux/dma-mapping.h>
Russell King53741ed2012-04-23 13:51:48 +010031#include <linux/dmaengine.h>
32#include <linux/omap-dma.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070033#include <linux/platform_device.h>
34#include <linux/err.h>
35#include <linux/clk.h>
36#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090037#include <linux/slab.h>
Govindraj.R1f1a4382011-02-02 17:52:15 +053038#include <linux/pm_runtime.h>
Benoit Coussond5a80032012-02-15 18:37:34 +010039#include <linux/of.h>
40#include <linux/of_device.h>
Matt Porterec155af2012-09-18 08:01:25 -040041#include <linux/pinctrl/consumer.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070042
43#include <linux/spi/spi.h>
44
Arnd Bergmann22037472012-08-24 15:21:06 +020045#include <linux/platform_data/spi-omap2-mcspi.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070046
47#define OMAP2_MCSPI_MAX_FREQ 48000000
Shubhrajyoti D27b52842012-03-26 17:04:22 +053048#define SPI_AUTOSUSPEND_TIMEOUT 2000
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070049
50#define OMAP2_MCSPI_REVISION 0x00
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070051#define OMAP2_MCSPI_SYSSTATUS 0x14
52#define OMAP2_MCSPI_IRQSTATUS 0x18
53#define OMAP2_MCSPI_IRQENABLE 0x1c
54#define OMAP2_MCSPI_WAKEUPENABLE 0x20
55#define OMAP2_MCSPI_SYST 0x24
56#define OMAP2_MCSPI_MODULCTRL 0x28
57
58/* per-channel banks, 0x14 bytes each, first is: */
59#define OMAP2_MCSPI_CHCONF0 0x2c
60#define OMAP2_MCSPI_CHSTAT0 0x30
61#define OMAP2_MCSPI_CHCTRL0 0x34
62#define OMAP2_MCSPI_TX0 0x38
63#define OMAP2_MCSPI_RX0 0x3c
64
65/* per-register bitmasks: */
66
Jouni Hogander7a8fa722009-09-22 16:45:58 -070067#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070070
Jouni Hogander7a8fa722009-09-22 16:45:58 -070071#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72#define OMAP2_MCSPI_CHCONF_POL BIT(1)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070073#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070074#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070075#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070076#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070078#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070079#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83#define OMAP2_MCSPI_CHCONF_IS BIT(18)
84#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070086
Jouni Hogander7a8fa722009-09-22 16:45:58 -070087#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
88#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
89#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070090
Jouni Hogander7a8fa722009-09-22 16:45:58 -070091#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070092
Jouni Hogander7a8fa722009-09-22 16:45:58 -070093#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070094
95/* We have 2 DMA channels per CS, one for RX and one for TX */
96struct omap2_mcspi_dma {
Russell King53741ed2012-04-23 13:51:48 +010097 struct dma_chan *dma_tx;
98 struct dma_chan *dma_rx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070099
100 int dma_tx_sync_dev;
101 int dma_rx_sync_dev;
102
103 struct completion dma_tx_completion;
104 struct completion dma_rx_completion;
105};
106
107/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
108 * cache operations; better heuristics consider wordsize and bitrate.
109 */
Roman Tereshonkov8b66c132010-04-12 09:07:54 +0000110#define DMA_MIN_BYTES 160
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700111
112
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530113/*
114 * Used for context save and restore, structure members to be updated whenever
115 * corresponding registers are modified.
116 */
117struct omap2_mcspi_regs {
118 u32 modulctrl;
119 u32 wakeupenable;
120 struct list_head cs;
121};
122
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700123struct omap2_mcspi {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700124 struct spi_master *master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700125 /* Virtual base address of the controller */
126 void __iomem *base;
Russell Kinge5480b732008-09-01 21:51:50 +0100127 unsigned long phys;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700128 /* SPI1 has 4 channels, while SPI2 has 2 */
129 struct omap2_mcspi_dma *dma_channels;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530130 struct device *dev;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530131 struct omap2_mcspi_regs ctx;
Daniel Mack0384e902012-10-07 18:19:44 +0200132 unsigned int pin_dir:1;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700133};
134
135struct omap2_mcspi_cs {
136 void __iomem *base;
Russell Kinge5480b732008-09-01 21:51:50 +0100137 unsigned long phys;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700138 int word_len;
Tero Kristo89c05372009-09-22 16:46:17 -0700139 struct list_head node;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700140 /* Context save and restore shadow register */
141 u32 chconf0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700142};
143
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700144static inline void mcspi_write_reg(struct spi_master *master,
145 int idx, u32 val)
146{
147 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
148
149 __raw_writel(val, mcspi->base + idx);
150}
151
152static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
153{
154 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
155
156 return __raw_readl(mcspi->base + idx);
157}
158
159static inline void mcspi_write_cs_reg(const struct spi_device *spi,
160 int idx, u32 val)
161{
162 struct omap2_mcspi_cs *cs = spi->controller_state;
163
164 __raw_writel(val, cs->base + idx);
165}
166
167static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
168{
169 struct omap2_mcspi_cs *cs = spi->controller_state;
170
171 return __raw_readl(cs->base + idx);
172}
173
Hemanth Va41ae1a2009-09-22 16:46:16 -0700174static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
175{
176 struct omap2_mcspi_cs *cs = spi->controller_state;
177
178 return cs->chconf0;
179}
180
181static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
182{
183 struct omap2_mcspi_cs *cs = spi->controller_state;
184
185 cs->chconf0 = val;
186 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
Roman Tereshonkova330ce22010-03-15 09:06:28 +0000187 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700188}
189
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700190static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
191 int is_read, int enable)
192{
193 u32 l, rw;
194
Hemanth Va41ae1a2009-09-22 16:46:16 -0700195 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700196
197 if (is_read) /* 1 is read, 0 write */
198 rw = OMAP2_MCSPI_CHCONF_DMAR;
199 else
200 rw = OMAP2_MCSPI_CHCONF_DMAW;
201
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530202 if (enable)
203 l |= rw;
204 else
205 l &= ~rw;
206
Hemanth Va41ae1a2009-09-22 16:46:16 -0700207 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700208}
209
210static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
211{
212 u32 l;
213
214 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
215 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000216 /* Flash post-writes */
217 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700218}
219
220static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
221{
222 u32 l;
223
Hemanth Va41ae1a2009-09-22 16:46:16 -0700224 l = mcspi_cached_chconf0(spi);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530225 if (cs_active)
226 l |= OMAP2_MCSPI_CHCONF_FORCE;
227 else
228 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
229
Hemanth Va41ae1a2009-09-22 16:46:16 -0700230 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700231}
232
233static void omap2_mcspi_set_master_mode(struct spi_master *master)
234{
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530235 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
236 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700237 u32 l;
238
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530239 /*
240 * Setup when switching from (reset default) slave mode
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700241 * to single-channel master mode
242 */
243 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530244 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
245 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700246 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700247
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530248 ctx->modulctrl = l;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700249}
250
251static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
252{
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530253 struct spi_master *spi_cntrl = mcspi->master;
254 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
255 struct omap2_mcspi_cs *cs;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700256
257 /* McSPI: context restore */
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530258 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
259 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700260
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530261 list_for_each_entry(cs, &ctx->cs, node)
Tero Kristo89c05372009-09-22 16:46:17 -0700262 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700263}
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700264
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530265static int omap2_prepare_transfer(struct spi_master *master)
266{
267 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
268
269 pm_runtime_get_sync(mcspi->dev);
270 return 0;
271}
272
273static int omap2_unprepare_transfer(struct spi_master *master)
274{
275 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
276
277 pm_runtime_mark_last_busy(mcspi->dev);
278 pm_runtime_put_autosuspend(mcspi->dev);
279 return 0;
280}
281
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300282static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
283{
284 unsigned long timeout;
285
286 timeout = jiffies + msecs_to_jiffies(1000);
287 while (!(__raw_readl(reg) & bit)) {
Sebastian Andrzej Siewiorff23fa32013-03-21 13:22:48 +0100288 if (time_after(jiffies, timeout)) {
289 if (!(__raw_readl(reg) & bit))
290 return -ETIMEDOUT;
291 else
292 return 0;
293 }
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300294 cpu_relax();
295 }
296 return 0;
297}
298
Russell King53741ed2012-04-23 13:51:48 +0100299static void omap2_mcspi_rx_callback(void *data)
300{
301 struct spi_device *spi = data;
302 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
303 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
304
Russell King53741ed2012-04-23 13:51:48 +0100305 /* We must disable the DMA RX request */
306 omap2_mcspi_set_dma_req(spi, 1, 0);
Felipe Balbi830379e2012-12-12 10:45:59 +0200307
308 complete(&mcspi_dma->dma_rx_completion);
Russell King53741ed2012-04-23 13:51:48 +0100309}
310
311static void omap2_mcspi_tx_callback(void *data)
312{
313 struct spi_device *spi = data;
314 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
315 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
316
Russell King53741ed2012-04-23 13:51:48 +0100317 /* We must disable the DMA TX request */
318 omap2_mcspi_set_dma_req(spi, 0, 0);
Felipe Balbi830379e2012-12-12 10:45:59 +0200319
320 complete(&mcspi_dma->dma_tx_completion);
Russell King53741ed2012-04-23 13:51:48 +0100321}
322
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530323static void omap2_mcspi_tx_dma(struct spi_device *spi,
324 struct spi_transfer *xfer,
325 struct dma_slave_config cfg)
326{
327 struct omap2_mcspi *mcspi;
328 struct omap2_mcspi_dma *mcspi_dma;
329 unsigned int count;
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530330
331 mcspi = spi_master_get_devdata(spi->master);
332 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
333 count = xfer->len;
334
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530335 if (mcspi_dma->dma_tx) {
336 struct dma_async_tx_descriptor *tx;
337 struct scatterlist sg;
338
339 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
340
341 sg_init_table(&sg, 1);
342 sg_dma_address(&sg) = xfer->tx_dma;
343 sg_dma_len(&sg) = xfer->len;
344
345 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
346 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
347 if (tx) {
348 tx->callback = omap2_mcspi_tx_callback;
349 tx->callback_param = spi;
350 dmaengine_submit(tx);
351 } else {
352 /* FIXME: fall back to PIO? */
353 }
354 }
355 dma_async_issue_pending(mcspi_dma->dma_tx);
356 omap2_mcspi_set_dma_req(spi, 0, 1);
357
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530358}
359
360static unsigned
361omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
362 struct dma_slave_config cfg,
363 unsigned es)
364{
365 struct omap2_mcspi *mcspi;
366 struct omap2_mcspi_dma *mcspi_dma;
367 unsigned int count;
368 u32 l;
369 int elements = 0;
370 int word_len, element_count;
371 struct omap2_mcspi_cs *cs = spi->controller_state;
372 mcspi = spi_master_get_devdata(spi->master);
373 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
374 count = xfer->len;
375 word_len = cs->word_len;
376 l = mcspi_cached_chconf0(spi);
377
378 if (word_len <= 8)
379 element_count = count;
380 else if (word_len <= 16)
381 element_count = count >> 1;
382 else /* word_len <= 32 */
383 element_count = count >> 2;
384
385 if (mcspi_dma->dma_rx) {
386 struct dma_async_tx_descriptor *tx;
387 struct scatterlist sg;
388 size_t len = xfer->len - es;
389
390 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
391
392 if (l & OMAP2_MCSPI_CHCONF_TURBO)
393 len -= es;
394
395 sg_init_table(&sg, 1);
396 sg_dma_address(&sg) = xfer->rx_dma;
397 sg_dma_len(&sg) = len;
398
399 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
400 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
401 DMA_CTRL_ACK);
402 if (tx) {
403 tx->callback = omap2_mcspi_rx_callback;
404 tx->callback_param = spi;
405 dmaengine_submit(tx);
406 } else {
407 /* FIXME: fall back to PIO? */
408 }
409 }
410
411 dma_async_issue_pending(mcspi_dma->dma_rx);
412 omap2_mcspi_set_dma_req(spi, 1, 1);
413
414 wait_for_completion(&mcspi_dma->dma_rx_completion);
415 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
416 DMA_FROM_DEVICE);
417 omap2_mcspi_set_enable(spi, 0);
418
419 elements = element_count - 1;
420
421 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
422 elements--;
423
424 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
425 & OMAP2_MCSPI_CHSTAT_RXS)) {
426 u32 w;
427
428 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
429 if (word_len <= 8)
430 ((u8 *)xfer->rx_buf)[elements++] = w;
431 else if (word_len <= 16)
432 ((u16 *)xfer->rx_buf)[elements++] = w;
433 else /* word_len <= 32 */
434 ((u32 *)xfer->rx_buf)[elements++] = w;
435 } else {
436 dev_err(&spi->dev, "DMA RX penultimate word empty");
437 count -= (word_len <= 8) ? 2 :
438 (word_len <= 16) ? 4 :
439 /* word_len <= 32 */ 8;
440 omap2_mcspi_set_enable(spi, 1);
441 return count;
442 }
443 }
444 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
445 & OMAP2_MCSPI_CHSTAT_RXS)) {
446 u32 w;
447
448 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
449 if (word_len <= 8)
450 ((u8 *)xfer->rx_buf)[elements] = w;
451 else if (word_len <= 16)
452 ((u16 *)xfer->rx_buf)[elements] = w;
453 else /* word_len <= 32 */
454 ((u32 *)xfer->rx_buf)[elements] = w;
455 } else {
456 dev_err(&spi->dev, "DMA RX last word empty");
457 count -= (word_len <= 8) ? 1 :
458 (word_len <= 16) ? 2 :
459 /* word_len <= 32 */ 4;
460 }
461 omap2_mcspi_set_enable(spi, 1);
462 return count;
463}
464
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700465static unsigned
466omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
467{
468 struct omap2_mcspi *mcspi;
469 struct omap2_mcspi_cs *cs = spi->controller_state;
470 struct omap2_mcspi_dma *mcspi_dma;
Russell King8c7494a2012-04-23 13:56:25 +0100471 unsigned int count;
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000472 u32 l;
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530473 u8 *rx;
474 const u8 *tx;
Russell King53741ed2012-04-23 13:51:48 +0100475 struct dma_slave_config cfg;
476 enum dma_slave_buswidth width;
477 unsigned es;
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530478 void __iomem *chstat_reg;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700479
480 mcspi = spi_master_get_devdata(spi->master);
481 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000482 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700483
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300484
Russell King53741ed2012-04-23 13:51:48 +0100485 if (cs->word_len <= 8) {
486 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
487 es = 1;
488 } else if (cs->word_len <= 16) {
489 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
490 es = 2;
491 } else {
492 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
493 es = 4;
494 }
495
496 memset(&cfg, 0, sizeof(cfg));
497 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
498 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
499 cfg.src_addr_width = width;
500 cfg.dst_addr_width = width;
501 cfg.src_maxburst = 1;
502 cfg.dst_maxburst = 1;
503
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700504 rx = xfer->rx_buf;
505 tx = xfer->tx_buf;
506
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530507 count = xfer->len;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700508
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530509 if (tx != NULL)
510 omap2_mcspi_tx_dma(spi, xfer, cfg);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700511
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530512 if (rx != NULL)
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530513 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700514
Shubhrajyoti De47a6822012-11-06 14:30:19 +0530515 if (tx != NULL) {
516 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
517 wait_for_completion(&mcspi_dma->dma_tx_completion);
518 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
519 DMA_TO_DEVICE);
520
521 /* for TX_ONLY mode, be sure all words have shifted out */
522 if (rx == NULL) {
523 if (mcspi_wait_for_reg_bit(chstat_reg,
524 OMAP2_MCSPI_CHSTAT_TXS) < 0)
525 dev_err(&spi->dev, "TXS timed out\n");
526 else if (mcspi_wait_for_reg_bit(chstat_reg,
527 OMAP2_MCSPI_CHSTAT_EOT) < 0)
528 dev_err(&spi->dev, "EOT timed out\n");
529 }
530 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700531 return count;
532}
533
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700534static unsigned
535omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
536{
537 struct omap2_mcspi *mcspi;
538 struct omap2_mcspi_cs *cs = spi->controller_state;
539 unsigned int count, c;
540 u32 l;
541 void __iomem *base = cs->base;
542 void __iomem *tx_reg;
543 void __iomem *rx_reg;
544 void __iomem *chstat_reg;
545 int word_len;
546
547 mcspi = spi_master_get_devdata(spi->master);
548 count = xfer->len;
549 c = count;
550 word_len = cs->word_len;
551
Hemanth Va41ae1a2009-09-22 16:46:16 -0700552 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700553
554 /* We store the pre-calculated register addresses on stack to speed
555 * up the transfer loop. */
556 tx_reg = base + OMAP2_MCSPI_TX0;
557 rx_reg = base + OMAP2_MCSPI_RX0;
558 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
559
Michael Jonesadef6582011-02-25 16:55:11 +0100560 if (c < (word_len>>3))
561 return 0;
562
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700563 if (word_len <= 8) {
564 u8 *rx;
565 const u8 *tx;
566
567 rx = xfer->rx_buf;
568 tx = xfer->tx_buf;
569
570 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800571 c -= 1;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700572 if (tx != NULL) {
573 if (mcspi_wait_for_reg_bit(chstat_reg,
574 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
575 dev_err(&spi->dev, "TXS timed out\n");
576 goto out;
577 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900578 dev_vdbg(&spi->dev, "write-%d %02x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700579 word_len, *tx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700580 __raw_writel(*tx++, tx_reg);
581 }
582 if (rx != NULL) {
583 if (mcspi_wait_for_reg_bit(chstat_reg,
584 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
585 dev_err(&spi->dev, "RXS timed out\n");
586 goto out;
587 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000588
589 if (c == 1 && tx == NULL &&
590 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
591 omap2_mcspi_set_enable(spi, 0);
592 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900593 dev_vdbg(&spi->dev, "read-%d %02x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000594 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000595 if (mcspi_wait_for_reg_bit(chstat_reg,
596 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
597 dev_err(&spi->dev,
598 "RXS timed out\n");
599 goto out;
600 }
601 c = 0;
602 } else if (c == 0 && tx == NULL) {
603 omap2_mcspi_set_enable(spi, 0);
604 }
605
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700606 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900607 dev_vdbg(&spi->dev, "read-%d %02x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700608 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700609 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200610 } while (c);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700611 } else if (word_len <= 16) {
612 u16 *rx;
613 const u16 *tx;
614
615 rx = xfer->rx_buf;
616 tx = xfer->tx_buf;
617 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800618 c -= 2;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700619 if (tx != NULL) {
620 if (mcspi_wait_for_reg_bit(chstat_reg,
621 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
622 dev_err(&spi->dev, "TXS timed out\n");
623 goto out;
624 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900625 dev_vdbg(&spi->dev, "write-%d %04x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700626 word_len, *tx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700627 __raw_writel(*tx++, tx_reg);
628 }
629 if (rx != NULL) {
630 if (mcspi_wait_for_reg_bit(chstat_reg,
631 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
632 dev_err(&spi->dev, "RXS timed out\n");
633 goto out;
634 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000635
636 if (c == 2 && tx == NULL &&
637 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
638 omap2_mcspi_set_enable(spi, 0);
639 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900640 dev_vdbg(&spi->dev, "read-%d %04x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000641 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000642 if (mcspi_wait_for_reg_bit(chstat_reg,
643 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
644 dev_err(&spi->dev,
645 "RXS timed out\n");
646 goto out;
647 }
648 c = 0;
649 } else if (c == 0 && tx == NULL) {
650 omap2_mcspi_set_enable(spi, 0);
651 }
652
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700653 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900654 dev_vdbg(&spi->dev, "read-%d %04x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700655 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700656 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200657 } while (c >= 2);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700658 } else if (word_len <= 32) {
659 u32 *rx;
660 const u32 *tx;
661
662 rx = xfer->rx_buf;
663 tx = xfer->tx_buf;
664 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800665 c -= 4;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700666 if (tx != NULL) {
667 if (mcspi_wait_for_reg_bit(chstat_reg,
668 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
669 dev_err(&spi->dev, "TXS timed out\n");
670 goto out;
671 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900672 dev_vdbg(&spi->dev, "write-%d %08x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700673 word_len, *tx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700674 __raw_writel(*tx++, tx_reg);
675 }
676 if (rx != NULL) {
677 if (mcspi_wait_for_reg_bit(chstat_reg,
678 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
679 dev_err(&spi->dev, "RXS timed out\n");
680 goto out;
681 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000682
683 if (c == 4 && tx == NULL &&
684 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
685 omap2_mcspi_set_enable(spi, 0);
686 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900687 dev_vdbg(&spi->dev, "read-%d %08x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000688 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000689 if (mcspi_wait_for_reg_bit(chstat_reg,
690 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
691 dev_err(&spi->dev,
692 "RXS timed out\n");
693 goto out;
694 }
695 c = 0;
696 } else if (c == 0 && tx == NULL) {
697 omap2_mcspi_set_enable(spi, 0);
698 }
699
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700700 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900701 dev_vdbg(&spi->dev, "read-%d %08x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700702 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700703 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200704 } while (c >= 4);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700705 }
706
707 /* for TX_ONLY mode, be sure all words have shifted out */
708 if (xfer->rx_buf == NULL) {
709 if (mcspi_wait_for_reg_bit(chstat_reg,
710 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
711 dev_err(&spi->dev, "TXS timed out\n");
712 } else if (mcspi_wait_for_reg_bit(chstat_reg,
713 OMAP2_MCSPI_CHSTAT_EOT) < 0)
714 dev_err(&spi->dev, "EOT timed out\n");
Jason Wange1993ed2010-10-19 18:03:27 +0800715
716 /* disable chan to purge rx datas received in TX_ONLY transfer,
717 * otherwise these rx datas will affect the direct following
718 * RX_ONLY transfer.
719 */
720 omap2_mcspi_set_enable(spi, 0);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700721 }
722out:
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000723 omap2_mcspi_set_enable(spi, 1);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700724 return count - c;
725}
726
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200727static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
728{
729 u32 div;
730
731 for (div = 0; div < 15; div++)
732 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
733 return div;
734
735 return 15;
736}
737
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700738/* called only when no transfer is active to this device */
739static int omap2_mcspi_setup_transfer(struct spi_device *spi,
740 struct spi_transfer *t)
741{
742 struct omap2_mcspi_cs *cs = spi->controller_state;
743 struct omap2_mcspi *mcspi;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700744 struct spi_master *spi_cntrl;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700745 u32 l = 0, div = 0;
746 u8 word_len = spi->bits_per_word;
Scott Ellis9bd45172010-03-10 14:23:13 -0700747 u32 speed_hz = spi->max_speed_hz;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700748
749 mcspi = spi_master_get_devdata(spi->master);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700750 spi_cntrl = mcspi->master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700751
752 if (t != NULL && t->bits_per_word)
753 word_len = t->bits_per_word;
754
755 cs->word_len = word_len;
756
Scott Ellis9bd45172010-03-10 14:23:13 -0700757 if (t && t->speed_hz)
758 speed_hz = t->speed_hz;
759
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200760 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
761 div = omap2_mcspi_calc_divisor(speed_hz);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700762
Hemanth Va41ae1a2009-09-22 16:46:16 -0700763 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700764
765 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
766 * REVISIT: this controller could support SPI_3WIRE mode.
767 */
Daniel Mack2cd45172012-11-14 11:14:26 +0800768 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
Daniel Mack0384e902012-10-07 18:19:44 +0200769 l &= ~OMAP2_MCSPI_CHCONF_IS;
770 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
771 l |= OMAP2_MCSPI_CHCONF_DPE0;
772 } else {
773 l |= OMAP2_MCSPI_CHCONF_IS;
774 l |= OMAP2_MCSPI_CHCONF_DPE1;
775 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
776 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700777
778 /* wordlength */
779 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
780 l |= (word_len - 1) << 7;
781
782 /* set chipselect polarity; manage with FORCE */
783 if (!(spi->mode & SPI_CS_HIGH))
784 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
785 else
786 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
787
788 /* set clock divisor */
789 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
790 l |= div << 2;
791
792 /* set SPI mode 0..3 */
793 if (spi->mode & SPI_CPOL)
794 l |= OMAP2_MCSPI_CHCONF_POL;
795 else
796 l &= ~OMAP2_MCSPI_CHCONF_POL;
797 if (spi->mode & SPI_CPHA)
798 l |= OMAP2_MCSPI_CHCONF_PHA;
799 else
800 l &= ~OMAP2_MCSPI_CHCONF_PHA;
801
Hemanth Va41ae1a2009-09-22 16:46:16 -0700802 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700803
804 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200805 OMAP2_MCSPI_MAX_FREQ >> div,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700806 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
807 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
808
809 return 0;
810}
811
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700812/*
813 * Note that we currently allow DMA only if we get a channel
814 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
815 */
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700816static int omap2_mcspi_request_dma(struct spi_device *spi)
817{
818 struct spi_master *master = spi->master;
819 struct omap2_mcspi *mcspi;
820 struct omap2_mcspi_dma *mcspi_dma;
Russell King53741ed2012-04-23 13:51:48 +0100821 dma_cap_mask_t mask;
822 unsigned sig;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700823
824 mcspi = spi_master_get_devdata(master);
825 mcspi_dma = mcspi->dma_channels + spi->chip_select;
826
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700827 init_completion(&mcspi_dma->dma_rx_completion);
828 init_completion(&mcspi_dma->dma_tx_completion);
829
Russell King53741ed2012-04-23 13:51:48 +0100830 dma_cap_zero(mask);
831 dma_cap_set(DMA_SLAVE, mask);
Russell King53741ed2012-04-23 13:51:48 +0100832 sig = mcspi_dma->dma_rx_sync_dev;
833 mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700834 if (!mcspi_dma->dma_rx)
835 goto no_dma;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700836
Russell King53741ed2012-04-23 13:51:48 +0100837 sig = mcspi_dma->dma_tx_sync_dev;
838 mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
839 if (!mcspi_dma->dma_tx) {
Russell King53741ed2012-04-23 13:51:48 +0100840 dma_release_channel(mcspi_dma->dma_rx);
841 mcspi_dma->dma_rx = NULL;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700842 goto no_dma;
Russell King53741ed2012-04-23 13:51:48 +0100843 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700844
845 return 0;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700846
847no_dma:
848 dev_warn(&spi->dev, "not using DMA for McSPI\n");
849 return -EAGAIN;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700850}
851
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700852static int omap2_mcspi_setup(struct spi_device *spi)
853{
854 int ret;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530855 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
856 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700857 struct omap2_mcspi_dma *mcspi_dma;
858 struct omap2_mcspi_cs *cs = spi->controller_state;
859
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700860 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
861
862 if (!cs) {
Russell King10aa5a32012-06-18 11:27:04 +0100863 cs = kzalloc(sizeof *cs, GFP_KERNEL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700864 if (!cs)
865 return -ENOMEM;
866 cs->base = mcspi->base + spi->chip_select * 0x14;
Russell Kinge5480b732008-09-01 21:51:50 +0100867 cs->phys = mcspi->phys + spi->chip_select * 0x14;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700868 cs->chconf0 = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700869 spi->controller_state = cs;
Tero Kristo89c05372009-09-22 16:46:17 -0700870 /* Link this to context save list */
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530871 list_add_tail(&cs->node, &ctx->cs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700872 }
873
Russell King8c7494a2012-04-23 13:56:25 +0100874 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700875 ret = omap2_mcspi_request_dma(spi);
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700876 if (ret < 0 && ret != -EAGAIN)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700877 return ret;
878 }
879
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +0530880 ret = pm_runtime_get_sync(mcspi->dev);
Govindraj.R1f1a4382011-02-02 17:52:15 +0530881 if (ret < 0)
882 return ret;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700883
Kyungmin Park86eeb6f2007-10-16 01:27:45 -0700884 ret = omap2_mcspi_setup_transfer(spi, NULL);
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +0530885 pm_runtime_mark_last_busy(mcspi->dev);
886 pm_runtime_put_autosuspend(mcspi->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700887
888 return ret;
889}
890
891static void omap2_mcspi_cleanup(struct spi_device *spi)
892{
893 struct omap2_mcspi *mcspi;
894 struct omap2_mcspi_dma *mcspi_dma;
Tero Kristo89c05372009-09-22 16:46:17 -0700895 struct omap2_mcspi_cs *cs;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700896
897 mcspi = spi_master_get_devdata(spi->master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700898
Scott Ellis5e774942010-03-10 14:22:45 -0700899 if (spi->controller_state) {
900 /* Unlink controller state from context save list */
901 cs = spi->controller_state;
902 list_del(&cs->node);
Tero Kristo89c05372009-09-22 16:46:17 -0700903
Russell King10aa5a32012-06-18 11:27:04 +0100904 kfree(cs);
Scott Ellis5e774942010-03-10 14:22:45 -0700905 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700906
Scott Ellis99f1a432010-05-24 14:20:27 +0000907 if (spi->chip_select < spi->master->num_chipselect) {
908 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
909
Russell King53741ed2012-04-23 13:51:48 +0100910 if (mcspi_dma->dma_rx) {
911 dma_release_channel(mcspi_dma->dma_rx);
912 mcspi_dma->dma_rx = NULL;
Scott Ellis99f1a432010-05-24 14:20:27 +0000913 }
Russell King53741ed2012-04-23 13:51:48 +0100914 if (mcspi_dma->dma_tx) {
915 dma_release_channel(mcspi_dma->dma_tx);
916 mcspi_dma->dma_tx = NULL;
Scott Ellis99f1a432010-05-24 14:20:27 +0000917 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700918 }
919}
920
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530921static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700922{
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700923
924 /* We only enable one channel at a time -- the one whose message is
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530925 * -- although this controller would gladly
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700926 * arbitrate among multiple channels. This corresponds to "single
927 * channel" master mode. As a side effect, we need to manage the
928 * chipselect with the FORCE bit ... CS != channel enable.
929 */
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700930
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530931 struct spi_device *spi;
932 struct spi_transfer *t = NULL;
Matthias Brugger5cbc7ca2013-01-24 13:40:41 +0100933 struct spi_master *master;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700934 struct omap2_mcspi_dma *mcspi_dma;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530935 int cs_active = 0;
936 struct omap2_mcspi_cs *cs;
937 struct omap2_mcspi_device_config *cd;
938 int par_override = 0;
939 int status = 0;
940 u32 chconf;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700941
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530942 spi = m->spi;
Matthias Brugger5cbc7ca2013-01-24 13:40:41 +0100943 master = spi->master;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -0700944 mcspi_dma = mcspi->dma_channels + spi->chip_select;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530945 cs = spi->controller_state;
946 cd = spi->controller_data;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700947
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530948 omap2_mcspi_set_enable(spi, 1);
949 list_for_each_entry(t, &m->transfers, transfer_list) {
950 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
951 status = -EINVAL;
952 break;
953 }
954 if (par_override || t->speed_hz || t->bits_per_word) {
955 par_override = 1;
956 status = omap2_mcspi_setup_transfer(spi, t);
957 if (status < 0)
958 break;
959 if (!t->speed_hz && !t->bits_per_word)
960 par_override = 0;
961 }
Matthias Brugger5cbc7ca2013-01-24 13:40:41 +0100962 if (cd && cd->cs_per_word) {
963 chconf = mcspi->ctx.modulctrl;
964 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
965 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
966 mcspi->ctx.modulctrl =
967 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
968 }
969
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700970
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530971 if (!cs_active) {
972 omap2_mcspi_force_cs(spi, 1);
973 cs_active = 1;
974 }
975
976 chconf = mcspi_cached_chconf0(spi);
977 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
978 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
979
980 if (t->tx_buf == NULL)
981 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
982 else if (t->rx_buf == NULL)
983 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
984
985 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
986 /* Turbo mode is for more than one word */
987 if (t->len > ((cs->word_len + 7) >> 3))
988 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
989 }
990
991 mcspi_write_chconf0(spi, chconf);
992
993 if (t->len) {
994 unsigned count;
995
996 /* RX_ONLY mode needs dummy data in TX reg */
997 if (t->tx_buf == NULL)
998 __raw_writel(0, cs->base
999 + OMAP2_MCSPI_TX0);
1000
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001001 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1002 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301003 count = omap2_mcspi_txrx_dma(spi, t);
1004 else
1005 count = omap2_mcspi_txrx_pio(spi, t);
1006 m->actual_length += count;
1007
1008 if (count != t->len) {
1009 status = -EIO;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001010 break;
1011 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001012 }
1013
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301014 if (t->delay_usecs)
1015 udelay(t->delay_usecs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001016
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301017 /* ignore the "leave it on after last xfer" hint */
1018 if (t->cs_change) {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001019 omap2_mcspi_force_cs(spi, 0);
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301020 cs_active = 0;
1021 }
1022 }
1023 /* Restore defaults if they were overriden */
1024 if (par_override) {
1025 par_override = 0;
1026 status = omap2_mcspi_setup_transfer(spi, NULL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001027 }
1028
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301029 if (cs_active)
1030 omap2_mcspi_force_cs(spi, 0);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301031
Matthias Brugger5cbc7ca2013-01-24 13:40:41 +01001032 if (cd && cd->cs_per_word) {
1033 chconf = mcspi->ctx.modulctrl;
1034 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1035 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1036 mcspi->ctx.modulctrl =
1037 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1038 }
1039
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301040 omap2_mcspi_set_enable(spi, 0);
1041
1042 m->status = status;
1043
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001044}
1045
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301046static int omap2_mcspi_transfer_one_message(struct spi_master *master,
Matthias Brugger18dd6192013-01-24 13:28:58 +01001047 struct spi_message *m)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001048{
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001049 struct spi_device *spi;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001050 struct omap2_mcspi *mcspi;
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001051 struct omap2_mcspi_dma *mcspi_dma;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001052 struct spi_transfer *t;
1053
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001054 spi = m->spi;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301055 mcspi = spi_master_get_devdata(master);
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001056 mcspi_dma = mcspi->dma_channels + spi->chip_select;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001057 m->actual_length = 0;
1058 m->status = 0;
1059
1060 /* reject invalid messages and transfers */
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301061 if (list_empty(&m->transfers))
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001062 return -EINVAL;
1063 list_for_each_entry(t, &m->transfers, transfer_list) {
1064 const void *tx_buf = t->tx_buf;
1065 void *rx_buf = t->rx_buf;
1066 unsigned len = t->len;
1067
1068 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
Stephen Warren24778be2013-05-21 20:36:35 -06001069 || (len && !(rx_buf || tx_buf))) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301070 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001071 t->speed_hz,
1072 len,
1073 tx_buf ? "tx" : "",
1074 rx_buf ? "rx" : "",
1075 t->bits_per_word);
1076 return -EINVAL;
1077 }
Hannu Heikkinen57d9c102011-02-24 21:31:33 +02001078 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301079 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
Matthias Brugger18dd6192013-01-24 13:28:58 +01001080 t->speed_hz,
1081 OMAP2_MCSPI_MAX_FREQ >> 15);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001082 return -EINVAL;
1083 }
1084
1085 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1086 continue;
1087
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001088 if (mcspi_dma->dma_tx && tx_buf != NULL) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301089 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001090 len, DMA_TO_DEVICE);
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301091 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1092 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001093 'T', len);
1094 return -EINVAL;
1095 }
1096 }
Tony Lindgrenddc5cdf2013-04-12 17:25:07 -07001097 if (mcspi_dma->dma_rx && rx_buf != NULL) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301098 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001099 DMA_FROM_DEVICE);
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301100 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1101 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001102 'R', len);
1103 if (tx_buf != NULL)
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301104 dma_unmap_single(mcspi->dev, t->tx_dma,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001105 len, DMA_TO_DEVICE);
1106 return -EINVAL;
1107 }
1108 }
1109 }
1110
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301111 omap2_mcspi_work(mcspi, m);
1112 spi_finalize_current_message(master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001113 return 0;
1114}
1115
Grant Likelyfd4a3192012-12-07 16:57:14 +00001116static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001117{
1118 struct spi_master *master = mcspi->master;
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301119 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301120 int ret = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001121
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301122 ret = pm_runtime_get_sync(mcspi->dev);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301123 if (ret < 0)
1124 return ret;
Jouni Hoganderddb22192009-07-29 15:02:11 -07001125
Shubhrajyoti D39f80522012-03-29 22:11:07 +05301126 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
Matthias Brugger18dd6192013-01-24 13:28:58 +01001127 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
Shubhrajyoti D39f80522012-03-29 22:11:07 +05301128 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001129
1130 omap2_mcspi_set_master_mode(master);
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301131 pm_runtime_mark_last_busy(mcspi->dev);
1132 pm_runtime_put_autosuspend(mcspi->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001133 return 0;
1134}
1135
Govindraj.R1f1a4382011-02-02 17:52:15 +05301136static int omap_mcspi_runtime_resume(struct device *dev)
1137{
1138 struct omap2_mcspi *mcspi;
1139 struct spi_master *master;
1140
1141 master = dev_get_drvdata(dev);
1142 mcspi = spi_master_get_devdata(master);
1143 omap2_mcspi_restore_ctx(mcspi);
1144
1145 return 0;
1146}
1147
Benoit Coussond5a80032012-02-15 18:37:34 +01001148static struct omap2_mcspi_platform_config omap2_pdata = {
1149 .regs_offset = 0,
1150};
1151
1152static struct omap2_mcspi_platform_config omap4_pdata = {
1153 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1154};
1155
1156static const struct of_device_id omap_mcspi_of_match[] = {
1157 {
1158 .compatible = "ti,omap2-mcspi",
1159 .data = &omap2_pdata,
1160 },
1161 {
1162 .compatible = "ti,omap4-mcspi",
1163 .data = &omap4_pdata,
1164 },
1165 { },
1166};
1167MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
Girishccc7bae2008-02-06 01:38:16 -08001168
Grant Likelyfd4a3192012-12-07 16:57:14 +00001169static int omap2_mcspi_probe(struct platform_device *pdev)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001170{
1171 struct spi_master *master;
Uwe Kleine-König83a01e72012-05-21 21:57:39 +02001172 const struct omap2_mcspi_platform_config *pdata;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001173 struct omap2_mcspi *mcspi;
1174 struct resource *r;
1175 int status = 0, i;
Benoit Coussond5a80032012-02-15 18:37:34 +01001176 u32 regs_offset = 0;
1177 static int bus_num = 1;
1178 struct device_node *node = pdev->dev.of_node;
1179 const struct of_device_id *match;
Matt Porterec155af2012-09-18 08:01:25 -04001180 struct pinctrl *pinctrl;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001181
1182 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1183 if (master == NULL) {
1184 dev_dbg(&pdev->dev, "master allocation failed\n");
1185 return -ENOMEM;
1186 }
1187
David Brownelle7db06b2009-06-17 16:26:04 -07001188 /* the spi->mode bits understood by this driver: */
1189 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
Stephen Warren24778be2013-05-21 20:36:35 -06001190 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001191 master->setup = omap2_mcspi_setup;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301192 master->prepare_transfer_hardware = omap2_prepare_transfer;
1193 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1194 master->transfer_one_message = omap2_mcspi_transfer_one_message;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001195 master->cleanup = omap2_mcspi_cleanup;
Benoit Coussond5a80032012-02-15 18:37:34 +01001196 master->dev.of_node = node;
1197
Daniel Mack0384e902012-10-07 18:19:44 +02001198 dev_set_drvdata(&pdev->dev, master);
1199
1200 mcspi = spi_master_get_devdata(master);
1201 mcspi->master = master;
1202
Benoit Coussond5a80032012-02-15 18:37:34 +01001203 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1204 if (match) {
1205 u32 num_cs = 1; /* default number of chipselect */
1206 pdata = match->data;
1207
1208 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1209 master->num_chipselect = num_cs;
1210 master->bus_num = bus_num++;
Daniel Mack2cd45172012-11-14 11:14:26 +08001211 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1212 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
Benoit Coussond5a80032012-02-15 18:37:34 +01001213 } else {
1214 pdata = pdev->dev.platform_data;
1215 master->num_chipselect = pdata->num_cs;
1216 if (pdev->id != -1)
1217 master->bus_num = pdev->id;
Daniel Mack0384e902012-10-07 18:19:44 +02001218 mcspi->pin_dir = pdata->pin_dir;
Benoit Coussond5a80032012-02-15 18:37:34 +01001219 }
1220 regs_offset = pdata->regs_offset;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001221
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001222 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1223 if (r == NULL) {
1224 status = -ENODEV;
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301225 goto free_master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001226 }
Shubhrajyoti D1458d162011-10-24 15:54:24 +05301227
Benoit Coussond5a80032012-02-15 18:37:34 +01001228 r->start += regs_offset;
1229 r->end += regs_offset;
Shubhrajyoti D1458d162011-10-24 15:54:24 +05301230 mcspi->phys = r->start;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001231
Thierry Redingb0ee5602013-01-21 11:09:18 +01001232 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1233 if (IS_ERR(mcspi->base)) {
1234 status = PTR_ERR(mcspi->base);
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301235 goto free_master;
Russell King55c381e2008-09-04 14:07:22 +01001236 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001237
Govindraj.R1f1a4382011-02-02 17:52:15 +05301238 mcspi->dev = &pdev->dev;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001239
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301240 INIT_LIST_HEAD(&mcspi->ctx.cs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001241
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001242 mcspi->dma_channels = kcalloc(master->num_chipselect,
1243 sizeof(struct omap2_mcspi_dma),
1244 GFP_KERNEL);
1245
1246 if (mcspi->dma_channels == NULL)
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301247 goto free_master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001248
Charulatha V1a5d8192011-02-02 17:52:14 +05301249 for (i = 0; i < master->num_chipselect; i++) {
1250 char dma_ch_name[14];
1251 struct resource *dma_res;
1252
1253 sprintf(dma_ch_name, "rx%d", i);
1254 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
Matthias Brugger18dd6192013-01-24 13:28:58 +01001255 dma_ch_name);
Charulatha V1a5d8192011-02-02 17:52:14 +05301256 if (!dma_res) {
1257 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1258 status = -ENODEV;
1259 break;
1260 }
1261
Charulatha V1a5d8192011-02-02 17:52:14 +05301262 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1263 sprintf(dma_ch_name, "tx%d", i);
1264 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
Matthias Brugger18dd6192013-01-24 13:28:58 +01001265 dma_ch_name);
Charulatha V1a5d8192011-02-02 17:52:14 +05301266 if (!dma_res) {
1267 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1268 status = -ENODEV;
1269 break;
1270 }
1271
Charulatha V1a5d8192011-02-02 17:52:14 +05301272 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001273 }
1274
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301275 if (status < 0)
1276 goto dma_chnl_free;
1277
Matt Porterec155af2012-09-18 08:01:25 -04001278 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1279 if (IS_ERR(pinctrl))
1280 dev_warn(&pdev->dev,
Matthias Brugger18dd6192013-01-24 13:28:58 +01001281 "pins are not configured from the driver\n");
Matt Porterec155af2012-09-18 08:01:25 -04001282
Shubhrajyoti D27b52842012-03-26 17:04:22 +05301283 pm_runtime_use_autosuspend(&pdev->dev);
1284 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301285 pm_runtime_enable(&pdev->dev);
1286
Wei Yongjun142e07b2013-04-18 11:14:59 +08001287 status = omap2_mcspi_master_setup(mcspi);
1288 if (status < 0)
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301289 goto disable_pm;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001290
1291 status = spi_register_master(master);
1292 if (status < 0)
Shubhrajyoti D37a2d842012-08-02 16:41:25 +05301293 goto disable_pm;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001294
1295 return status;
1296
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301297disable_pm:
Shubhrajyoti D751c9252011-10-28 17:14:18 +05301298 pm_runtime_disable(&pdev->dev);
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301299dma_chnl_free:
Govindraj.R1f1a4382011-02-02 17:52:15 +05301300 kfree(mcspi->dma_channels);
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301301free_master:
Shubhrajyoti D37a2d842012-08-02 16:41:25 +05301302 spi_master_put(master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001303 return status;
1304}
1305
Grant Likelyfd4a3192012-12-07 16:57:14 +00001306static int omap2_mcspi_remove(struct platform_device *pdev)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001307{
1308 struct spi_master *master;
1309 struct omap2_mcspi *mcspi;
1310 struct omap2_mcspi_dma *dma_channels;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001311
1312 master = dev_get_drvdata(&pdev->dev);
1313 mcspi = spi_master_get_devdata(master);
1314 dma_channels = mcspi->dma_channels;
1315
Shubhrajyoti Da93a2022012-08-22 11:35:14 +05301316 pm_runtime_put_sync(mcspi->dev);
Shubhrajyoti D751c9252011-10-28 17:14:18 +05301317 pm_runtime_disable(&pdev->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001318
1319 spi_unregister_master(master);
1320 kfree(dma_channels);
1321
1322 return 0;
1323}
1324
Kay Sievers7e38c3c2008-04-10 21:29:20 -07001325/* work with hotplug and coldplug */
1326MODULE_ALIAS("platform:omap2_mcspi");
1327
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001328#ifdef CONFIG_SUSPEND
1329/*
1330 * When SPI wake up from off-mode, CS is in activate state. If it was in
1331 * unactive state when driver was suspend, then force it to unactive state at
1332 * wake up.
1333 */
1334static int omap2_mcspi_resume(struct device *dev)
1335{
1336 struct spi_master *master = dev_get_drvdata(dev);
1337 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301338 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1339 struct omap2_mcspi_cs *cs;
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001340
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301341 pm_runtime_get_sync(mcspi->dev);
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301342 list_for_each_entry(cs, &ctx->cs, node) {
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001343 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001344 /*
1345 * We need to toggle CS state for OMAP take this
1346 * change in account.
1347 */
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +05301348 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001349 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +05301350 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001351 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1352 }
1353 }
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301354 pm_runtime_mark_last_busy(mcspi->dev);
1355 pm_runtime_put_autosuspend(mcspi->dev);
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001356 return 0;
1357}
1358#else
1359#define omap2_mcspi_resume NULL
1360#endif
1361
1362static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1363 .resume = omap2_mcspi_resume,
Govindraj.R1f1a4382011-02-02 17:52:15 +05301364 .runtime_resume = omap_mcspi_runtime_resume,
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001365};
1366
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001367static struct platform_driver omap2_mcspi_driver = {
1368 .driver = {
1369 .name = "omap2_mcspi",
1370 .owner = THIS_MODULE,
Benoit Coussond5a80032012-02-15 18:37:34 +01001371 .pm = &omap2_mcspi_pm_ops,
1372 .of_match_table = omap_mcspi_of_match,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001373 },
Felipe Balbi7d6b6d82012-03-14 11:18:30 +02001374 .probe = omap2_mcspi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +00001375 .remove = omap2_mcspi_remove,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001376};
1377
Felipe Balbi9fdca9d2012-03-14 11:18:31 +02001378module_platform_driver(omap2_mcspi_driver);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001379MODULE_LICENSE("GPL");