blob: 96373ab46f8cff6f30e1207f5a44b3c0b44e6f67 [file] [log] [blame]
Mark Browna4b12992014-03-12 23:04:35 +00001/*
2 * Intel SST Haswell/Broadwell IPC Support
3 *
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/list.h>
20#include <linux/device.h>
21#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/export.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
Mark Browna4b12992014-03-12 23:04:35 +000028#include <linux/platform_device.h>
29#include <linux/kthread.h>
30#include <linux/firmware.h>
31#include <linux/dma-mapping.h>
32#include <linux/debugfs.h>
33
34#include "sst-haswell-ipc.h"
35#include "sst-dsp.h"
36#include "sst-dsp-priv.h"
37
38/* Global Message - Generic */
39#define IPC_GLB_TYPE_SHIFT 24
40#define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
41#define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
42
43/* Global Message - Reply */
44#define IPC_GLB_REPLY_SHIFT 0
45#define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
46#define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
47
48/* Stream Message - Generic */
49#define IPC_STR_TYPE_SHIFT 20
50#define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
51#define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
52#define IPC_STR_ID_SHIFT 16
53#define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
54#define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
55
56/* Stream Message - Reply */
57#define IPC_STR_REPLY_SHIFT 0
58#define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
59
60/* Stream Stage Message - Generic */
61#define IPC_STG_TYPE_SHIFT 12
62#define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
63#define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
64#define IPC_STG_ID_SHIFT 10
65#define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
66#define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
67
68/* Stream Stage Message - Reply */
69#define IPC_STG_REPLY_SHIFT 0
70#define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
71
72/* Debug Log Message - Generic */
73#define IPC_LOG_OP_SHIFT 20
74#define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
75#define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
76#define IPC_LOG_ID_SHIFT 16
77#define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
78#define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
79
80/* IPC message timeout (msecs) */
81#define IPC_TIMEOUT_MSECS 300
82#define IPC_BOOT_MSECS 200
83#define IPC_MSG_WAIT 0
84#define IPC_MSG_NOWAIT 1
85
86/* Firmware Ready Message */
87#define IPC_FW_READY (0x1 << 29)
88#define IPC_STATUS_MASK (0x3 << 30)
89
90#define IPC_EMPTY_LIST_SIZE 8
91#define IPC_MAX_STREAMS 4
92
93/* Mailbox */
94#define IPC_MAX_MAILBOX_BYTES 256
95
96/* Global Message - Types and Replies */
97enum ipc_glb_type {
98 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
99 IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
100 IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
101 IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
102 IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
103 IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
104 /* Request to store firmware context during D0->D3 transition */
105 IPC_GLB_REQUEST_DUMP = 7,
106 /* Request to restore firmware context during D3->D0 transition */
107 IPC_GLB_RESTORE_CONTEXT = 8,
108 IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
109 IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
110 IPC_GLB_SHORT_REPLY = 11,
111 IPC_GLB_ENTER_DX_STATE = 12,
112 IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
113 IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
114 IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
115 IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
116};
117
118enum ipc_glb_reply {
119 IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
120 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
121 IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
122 IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
123 IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
124 IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
125 IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
126 IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
127 IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
128 IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
129 IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
130};
131
132/* Stream Message - Types */
133enum ipc_str_operation {
134 IPC_STR_RESET = 0,
135 IPC_STR_PAUSE = 1,
136 IPC_STR_RESUME = 2,
137 IPC_STR_STAGE_MESSAGE = 3,
138 IPC_STR_NOTIFICATION = 4,
139 IPC_STR_MAX_MESSAGE
140};
141
142/* Stream Stage Message Types */
143enum ipc_stg_operation {
144 IPC_STG_GET_VOLUME = 0,
145 IPC_STG_SET_VOLUME,
146 IPC_STG_SET_WRITE_POSITION,
147 IPC_STG_SET_FX_ENABLE,
148 IPC_STG_SET_FX_DISABLE,
149 IPC_STG_SET_FX_GET_PARAM,
150 IPC_STG_SET_FX_SET_PARAM,
151 IPC_STG_SET_FX_GET_INFO,
152 IPC_STG_MUTE_LOOPBACK,
153 IPC_STG_MAX_MESSAGE
154};
155
156/* Stream Stage Message Types For Notification*/
157enum ipc_stg_operation_notify {
158 IPC_POSITION_CHANGED = 0,
159 IPC_STG_GLITCH,
160 IPC_STG_MAX_NOTIFY
161};
162
163enum ipc_glitch_type {
164 IPC_GLITCH_UNDERRUN = 1,
165 IPC_GLITCH_DECODER_ERROR,
166 IPC_GLITCH_DOUBLED_WRITE_POS,
167 IPC_GLITCH_MAX
168};
169
170/* Debug Control */
171enum ipc_debug_operation {
172 IPC_DEBUG_ENABLE_LOG = 0,
173 IPC_DEBUG_DISABLE_LOG = 1,
174 IPC_DEBUG_REQUEST_LOG_DUMP = 2,
175 IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
176 IPC_DEBUG_MAX_DEBUG_LOG
177};
178
179/* Firmware Ready */
180struct sst_hsw_ipc_fw_ready {
181 u32 inbox_offset;
182 u32 outbox_offset;
183 u32 inbox_size;
184 u32 outbox_size;
185 u32 fw_info_size;
Jie Yang249addd2014-07-15 08:51:12 +0800186 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
Mark Browna4b12992014-03-12 23:04:35 +0000187} __attribute__((packed));
188
189struct ipc_message {
190 struct list_head list;
191 u32 header;
192
193 /* direction wrt host CPU */
194 char tx_data[IPC_MAX_MAILBOX_BYTES];
195 size_t tx_size;
196 char rx_data[IPC_MAX_MAILBOX_BYTES];
197 size_t rx_size;
198
199 wait_queue_head_t waitq;
200 bool pending;
201 bool complete;
202 bool wait;
203 int errno;
204};
205
206struct sst_hsw_stream;
207struct sst_hsw;
208
209/* Stream infomation */
210struct sst_hsw_stream {
211 /* configuration */
212 struct sst_hsw_ipc_stream_alloc_req request;
213 struct sst_hsw_ipc_stream_alloc_reply reply;
214 struct sst_hsw_ipc_stream_free_req free_req;
215
216 /* Mixer info */
217 u32 mute_volume[SST_HSW_NO_CHANNELS];
218 u32 mute[SST_HSW_NO_CHANNELS];
219
220 /* runtime info */
221 struct sst_hsw *hsw;
222 int host_id;
223 bool commited;
224 bool running;
225
226 /* Notification work */
227 struct work_struct notify_work;
228 u32 header;
229
230 /* Position info from DSP */
231 struct sst_hsw_ipc_stream_set_position wpos;
232 struct sst_hsw_ipc_stream_get_position rpos;
233 struct sst_hsw_ipc_stream_glitch_position glitch;
234
235 /* Volume info */
236 struct sst_hsw_ipc_volume_req vol_req;
237
238 /* driver callback */
239 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
240 void *pdata;
241
242 struct list_head node;
243};
244
245/* FW log ring information */
246struct sst_hsw_log_stream {
247 dma_addr_t dma_addr;
248 unsigned char *dma_area;
249 unsigned char *ring_descr;
250 int pages;
251 int size;
252
253 /* Notification work */
254 struct work_struct notify_work;
255 wait_queue_head_t readers_wait_q;
256 struct mutex rw_mutex;
257
258 u32 last_pos;
259 u32 curr_pos;
260 u32 reader_pos;
261
262 /* fw log config */
263 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
264
265 struct sst_hsw *hsw;
266};
267
268/* SST Haswell IPC data */
269struct sst_hsw {
270 struct device *dev;
271 struct sst_dsp *dsp;
272 struct platform_device *pdev_pcm;
273
274 /* FW config */
275 struct sst_hsw_ipc_fw_ready fw_ready;
276 struct sst_hsw_ipc_fw_version version;
277 struct sst_module *scratch;
278 bool fw_done;
279
280 /* stream */
281 struct list_head stream_list;
282
283 /* global mixer */
284 struct sst_hsw_ipc_stream_info_reply mixer_info;
285 enum sst_hsw_volume_curve curve_type;
286 u32 curve_duration;
287 u32 mute[SST_HSW_NO_CHANNELS];
288 u32 mute_volume[SST_HSW_NO_CHANNELS];
289
290 /* DX */
291 struct sst_hsw_ipc_dx_reply dx;
292
293 /* boot */
294 wait_queue_head_t boot_wait;
295 bool boot_complete;
296 bool shutdown;
297
298 /* IPC messaging */
299 struct list_head tx_list;
300 struct list_head rx_list;
301 struct list_head empty_list;
302 wait_queue_head_t wait_txq;
303 struct task_struct *tx_thread;
304 struct kthread_worker kworker;
305 struct kthread_work kwork;
306 bool pending;
307 struct ipc_message *msg;
308
309 /* FW log stream */
310 struct sst_hsw_log_stream log_stream;
311};
312
313#define CREATE_TRACE_POINTS
314#include <trace/events/hswadsp.h>
315
316static inline u32 msg_get_global_type(u32 msg)
317{
318 return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
319}
320
321static inline u32 msg_get_global_reply(u32 msg)
322{
323 return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
324}
325
326static inline u32 msg_get_stream_type(u32 msg)
327{
328 return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
329}
330
331static inline u32 msg_get_stage_type(u32 msg)
332{
333 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
334}
335
336static inline u32 msg_set_stage_type(u32 msg, u32 type)
337{
338 return (msg & ~IPC_STG_TYPE_MASK) +
339 (type << IPC_STG_TYPE_SHIFT);
340}
341
342static inline u32 msg_get_stream_id(u32 msg)
343{
344 return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
345}
346
347static inline u32 msg_get_notify_reason(u32 msg)
348{
349 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
350}
351
352u32 create_channel_map(enum sst_hsw_channel_config config)
353{
354 switch (config) {
355 case SST_HSW_CHANNEL_CONFIG_MONO:
356 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
357 case SST_HSW_CHANNEL_CONFIG_STEREO:
358 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
359 | (SST_HSW_CHANNEL_RIGHT << 4));
360 case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
361 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
362 | (SST_HSW_CHANNEL_RIGHT << 4)
363 | (SST_HSW_CHANNEL_LFE << 8 ));
364 case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
365 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
366 | (SST_HSW_CHANNEL_CENTER << 4)
367 | (SST_HSW_CHANNEL_RIGHT << 8));
368 case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
369 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
370 | (SST_HSW_CHANNEL_CENTER << 4)
371 | (SST_HSW_CHANNEL_RIGHT << 8)
372 | (SST_HSW_CHANNEL_LFE << 12));
373 case SST_HSW_CHANNEL_CONFIG_QUATRO:
374 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
375 | (SST_HSW_CHANNEL_RIGHT << 4)
376 | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
377 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
378 case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
379 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
380 | (SST_HSW_CHANNEL_CENTER << 4)
381 | (SST_HSW_CHANNEL_RIGHT << 8)
382 | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
383 case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
384 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
385 | (SST_HSW_CHANNEL_CENTER << 4)
386 | (SST_HSW_CHANNEL_RIGHT << 8)
387 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
388 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
389 case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
390 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
391 | (SST_HSW_CHANNEL_LEFT << 4)
392 | (SST_HSW_CHANNEL_RIGHT << 8)
393 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
394 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
395 | (SST_HSW_CHANNEL_LFE << 20));
396 case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
397 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
398 | (SST_HSW_CHANNEL_LEFT << 4));
399 default:
400 return 0xFFFFFFFF;
401 }
402}
403
404static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
405 int stream_id)
406{
407 struct sst_hsw_stream *stream;
408
409 list_for_each_entry(stream, &hsw->stream_list, node) {
410 if (stream->reply.stream_hw_id == stream_id)
411 return stream;
412 }
413
414 return NULL;
415}
416
417static void ipc_shim_dbg(struct sst_hsw *hsw, const char *text)
418{
419 struct sst_dsp *sst = hsw->dsp;
420 u32 isr, ipcd, imrx, ipcx;
421
422 ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
423 isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
424 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
425 imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
426
427 dev_err(hsw->dev, "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
428 text, ipcx, isr, ipcd, imrx);
429}
430
431/* locks held by caller */
432static struct ipc_message *msg_get_empty(struct sst_hsw *hsw)
433{
434 struct ipc_message *msg = NULL;
435
436 if (!list_empty(&hsw->empty_list)) {
437 msg = list_first_entry(&hsw->empty_list, struct ipc_message,
438 list);
439 list_del(&msg->list);
440 }
441
442 return msg;
443}
444
445static void ipc_tx_msgs(struct kthread_work *work)
446{
447 struct sst_hsw *hsw =
448 container_of(work, struct sst_hsw, kwork);
449 struct ipc_message *msg;
450 unsigned long flags;
451 u32 ipcx;
452
453 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
454
455 if (list_empty(&hsw->tx_list) || hsw->pending) {
456 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
457 return;
458 }
459
460 /* if the DSP is busy we will TX messages after IRQ */
461 ipcx = sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX);
462 if (ipcx & SST_IPCX_BUSY) {
463 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
464 return;
465 }
466
467 msg = list_first_entry(&hsw->tx_list, struct ipc_message, list);
468
469 list_move(&msg->list, &hsw->rx_list);
470
471 /* send the message */
472 sst_dsp_outbox_write(hsw->dsp, msg->tx_data, msg->tx_size);
473 sst_dsp_ipc_msg_tx(hsw->dsp, msg->header | SST_IPCX_BUSY);
474
475 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
476}
477
478/* locks held by caller */
479static void tx_msg_reply_complete(struct sst_hsw *hsw, struct ipc_message *msg)
480{
481 msg->complete = true;
482 trace_ipc_reply("completed", msg->header);
483
484 if (!msg->wait)
485 list_add_tail(&msg->list, &hsw->empty_list);
486 else
487 wake_up(&msg->waitq);
488}
489
490static int tx_wait_done(struct sst_hsw *hsw, struct ipc_message *msg,
491 void *rx_data)
492{
493 unsigned long flags;
494 int ret;
495
496 /* wait for DSP completion (in all cases atm inc pending) */
497 ret = wait_event_timeout(msg->waitq, msg->complete,
498 msecs_to_jiffies(IPC_TIMEOUT_MSECS));
499
500 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
501 if (ret == 0) {
502 ipc_shim_dbg(hsw, "message timeout");
503
504 trace_ipc_error("error message timeout for", msg->header);
505 ret = -ETIMEDOUT;
506 } else {
507
508 /* copy the data returned from DSP */
509 if (msg->rx_size)
510 memcpy(rx_data, msg->rx_data, msg->rx_size);
511 ret = msg->errno;
512 }
513
514 list_add_tail(&msg->list, &hsw->empty_list);
515 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
516 return ret;
517}
518
519static int ipc_tx_message(struct sst_hsw *hsw, u32 header, void *tx_data,
520 size_t tx_bytes, void *rx_data, size_t rx_bytes, int wait)
521{
522 struct ipc_message *msg;
523 unsigned long flags;
524
525 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
526
527 msg = msg_get_empty(hsw);
528 if (msg == NULL) {
529 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
530 return -EBUSY;
531 }
532
533 if (tx_bytes)
534 memcpy(msg->tx_data, tx_data, tx_bytes);
535
536 msg->header = header;
537 msg->tx_size = tx_bytes;
538 msg->rx_size = rx_bytes;
539 msg->wait = wait;
540 msg->errno = 0;
541 msg->pending = false;
542 msg->complete = false;
543
544 list_add_tail(&msg->list, &hsw->tx_list);
545 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
546
547 queue_kthread_work(&hsw->kworker, &hsw->kwork);
548
549 if (wait)
550 return tx_wait_done(hsw, msg, rx_data);
551 else
552 return 0;
553}
554
555static inline int ipc_tx_message_wait(struct sst_hsw *hsw, u32 header,
556 void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes)
557{
558 return ipc_tx_message(hsw, header, tx_data, tx_bytes, rx_data,
559 rx_bytes, 1);
560}
561
562static inline int ipc_tx_message_nowait(struct sst_hsw *hsw, u32 header,
563 void *tx_data, size_t tx_bytes)
564{
565 return ipc_tx_message(hsw, header, tx_data, tx_bytes, NULL, 0, 0);
566}
567
568static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
569{
570 struct sst_hsw_ipc_fw_ready fw_ready;
571 u32 offset;
Jie Yang249addd2014-07-15 08:51:12 +0800572 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
573 char *tmp[5], *pinfo;
574 int i = 0;
Mark Browna4b12992014-03-12 23:04:35 +0000575
576 offset = (header & 0x1FFFFFFF) << 3;
577
578 dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
579 header, offset);
580
581 /* copy data from the DSP FW ready offset */
582 sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
583
584 sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
585 fw_ready.inbox_size, fw_ready.outbox_offset,
586 fw_ready.outbox_size);
587
588 hsw->boot_complete = true;
589 wake_up(&hsw->boot_wait);
590
591 dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
592 fw_ready.inbox_offset, fw_ready.inbox_size);
593 dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
594 fw_ready.outbox_offset, fw_ready.outbox_size);
Jie Yang249addd2014-07-15 08:51:12 +0800595 if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
596 fw_ready.fw_info[fw_ready.fw_info_size] = 0;
597 dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
598
599 /* log the FW version info got from the mailbox here. */
600 memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
601 pinfo = &fw_info[0];
602 for (i = 0; i < sizeof(tmp) / sizeof(char *); i++)
603 tmp[i] = strsep(&pinfo, " ");
604 dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
605 "version: %s.%s, build %s, source commit id: %s\n",
606 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
607 }
Mark Browna4b12992014-03-12 23:04:35 +0000608}
609
610static void hsw_notification_work(struct work_struct *work)
611{
612 struct sst_hsw_stream *stream = container_of(work,
613 struct sst_hsw_stream, notify_work);
614 struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
615 struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
616 struct sst_hsw *hsw = stream->hsw;
617 u32 reason;
618
619 reason = msg_get_notify_reason(stream->header);
620
621 switch (reason) {
622 case IPC_STG_GLITCH:
623 trace_ipc_notification("DSP stream under/overrun",
624 stream->reply.stream_hw_id);
625 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
626
627 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
628 glitch->glitch_type, glitch->present_pos,
629 glitch->write_pos);
630 break;
631
632 case IPC_POSITION_CHANGED:
633 trace_ipc_notification("DSP stream position changed for",
634 stream->reply.stream_hw_id);
Dan Carpenter7897ab72014-04-16 18:38:11 +0300635 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
Mark Browna4b12992014-03-12 23:04:35 +0000636
637 if (stream->notify_position)
638 stream->notify_position(stream, stream->pdata);
639
640 break;
641 default:
642 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
643 stream->header);
644 break;
645 }
646
647 /* tell DSP that notification has been handled */
648 sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IPCD,
649 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
650
651 /* unmask busy interrupt */
652 sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
653}
654
655static struct ipc_message *reply_find_msg(struct sst_hsw *hsw, u32 header)
656{
657 struct ipc_message *msg;
658
659 /* clear reply bits & status bits */
660 header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
661
662 if (list_empty(&hsw->rx_list)) {
663 dev_err(hsw->dev, "error: rx list empty but received 0x%x\n",
664 header);
665 return NULL;
666 }
667
668 list_for_each_entry(msg, &hsw->rx_list, list) {
669 if (msg->header == header)
670 return msg;
671 }
672
673 return NULL;
674}
675
676static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
677{
678 struct sst_hsw_stream *stream;
679 u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
680 u32 stream_id = msg_get_stream_id(header);
681 u32 stream_msg = msg_get_stream_type(header);
682
683 stream = get_stream_by_id(hsw, stream_id);
684 if (stream == NULL)
685 return;
686
687 switch (stream_msg) {
688 case IPC_STR_STAGE_MESSAGE:
689 case IPC_STR_NOTIFICATION:
690 case IPC_STR_RESET:
691 break;
692 case IPC_STR_PAUSE:
693 stream->running = false;
694 trace_ipc_notification("stream paused",
695 stream->reply.stream_hw_id);
696 break;
697 case IPC_STR_RESUME:
698 stream->running = true;
699 trace_ipc_notification("stream running",
700 stream->reply.stream_hw_id);
701 break;
702 }
703}
704
705static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
706{
707 struct ipc_message *msg;
708 u32 reply = msg_get_global_reply(header);
709
710 trace_ipc_reply("processing -->", header);
711
712 msg = reply_find_msg(hsw, header);
713 if (msg == NULL) {
714 trace_ipc_error("error: can't find message header", header);
715 return -EIO;
716 }
717
718 /* first process the header */
719 switch (reply) {
720 case IPC_GLB_REPLY_PENDING:
721 trace_ipc_pending_reply("received", header);
722 msg->pending = true;
723 hsw->pending = true;
724 return 1;
725 case IPC_GLB_REPLY_SUCCESS:
726 if (msg->pending) {
727 trace_ipc_pending_reply("completed", header);
728 sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
729 msg->rx_size);
730 hsw->pending = false;
731 } else {
732 /* copy data from the DSP */
733 sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
734 msg->rx_size);
735 }
736 break;
737 /* these will be rare - but useful for debug */
738 case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
739 trace_ipc_error("error: unknown message type", header);
740 msg->errno = -EBADMSG;
741 break;
742 case IPC_GLB_REPLY_OUT_OF_RESOURCES:
743 trace_ipc_error("error: out of resources", header);
744 msg->errno = -ENOMEM;
745 break;
746 case IPC_GLB_REPLY_BUSY:
747 trace_ipc_error("error: reply busy", header);
748 msg->errno = -EBUSY;
749 break;
750 case IPC_GLB_REPLY_FAILURE:
751 trace_ipc_error("error: reply failure", header);
752 msg->errno = -EINVAL;
753 break;
754 case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
755 trace_ipc_error("error: stage uninitialized", header);
756 msg->errno = -EINVAL;
757 break;
758 case IPC_GLB_REPLY_NOT_FOUND:
759 trace_ipc_error("error: reply not found", header);
760 msg->errno = -EINVAL;
761 break;
762 case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
763 trace_ipc_error("error: source not started", header);
764 msg->errno = -EINVAL;
765 break;
766 case IPC_GLB_REPLY_INVALID_REQUEST:
767 trace_ipc_error("error: invalid request", header);
768 msg->errno = -EINVAL;
769 break;
770 case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
771 trace_ipc_error("error: invalid parameter", header);
772 msg->errno = -EINVAL;
773 break;
774 default:
775 trace_ipc_error("error: unknown reply", header);
776 msg->errno = -EINVAL;
777 break;
778 }
779
780 /* update any stream states */
781 hsw_stream_update(hsw, msg);
782
783 /* wake up and return the error if we have waiters on this message ? */
784 list_del(&msg->list);
785 tx_msg_reply_complete(hsw, msg);
786
787 return 1;
788}
789
790static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
791{
792 u32 stream_msg, stream_id, stage_type;
793 struct sst_hsw_stream *stream;
794 int handled = 0;
795
796 stream_msg = msg_get_stream_type(header);
797 stream_id = msg_get_stream_id(header);
798 stage_type = msg_get_stage_type(header);
799
800 stream = get_stream_by_id(hsw, stream_id);
801 if (stream == NULL)
802 return handled;
803
804 stream->header = header;
805
806 switch (stream_msg) {
807 case IPC_STR_STAGE_MESSAGE:
808 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
809 header);
810 break;
811 case IPC_STR_NOTIFICATION:
812 schedule_work(&stream->notify_work);
813 break;
814 default:
815 /* handle pending message complete request */
816 handled = hsw_process_reply(hsw, header);
817 break;
818 }
819
820 return handled;
821}
822
823static int hsw_log_message(struct sst_hsw *hsw, u32 header)
824{
825 u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
826 struct sst_hsw_log_stream *stream = &hsw->log_stream;
827 int ret = 1;
828
829 if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
830 dev_err(hsw->dev,
831 "error: log msg not implemented 0x%8.8x\n", header);
832 return 0;
833 }
834
835 mutex_lock(&stream->rw_mutex);
836 stream->last_pos = stream->curr_pos;
837 sst_dsp_inbox_read(
838 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
839 mutex_unlock(&stream->rw_mutex);
840
841 schedule_work(&stream->notify_work);
842
843 return ret;
844}
845
846static int hsw_process_notification(struct sst_hsw *hsw)
847{
848 struct sst_dsp *sst = hsw->dsp;
849 u32 type, header;
850 int handled = 1;
851
852 header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
853 type = msg_get_global_type(header);
854
855 trace_ipc_request("processing -->", header);
856
857 /* FW Ready is a special case */
858 if (!hsw->boot_complete && header & IPC_FW_READY) {
859 hsw_fw_ready(hsw, header);
860 return handled;
861 }
862
863 switch (type) {
864 case IPC_GLB_GET_FW_VERSION:
865 case IPC_GLB_ALLOCATE_STREAM:
866 case IPC_GLB_FREE_STREAM:
867 case IPC_GLB_GET_FW_CAPABILITIES:
868 case IPC_GLB_REQUEST_DUMP:
869 case IPC_GLB_GET_DEVICE_FORMATS:
870 case IPC_GLB_SET_DEVICE_FORMATS:
871 case IPC_GLB_ENTER_DX_STATE:
872 case IPC_GLB_GET_MIXER_STREAM_INFO:
873 case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
874 case IPC_GLB_RESTORE_CONTEXT:
875 case IPC_GLB_SHORT_REPLY:
876 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
877 type, header);
878 break;
879 case IPC_GLB_STREAM_MESSAGE:
880 handled = hsw_stream_message(hsw, header);
881 break;
882 case IPC_GLB_DEBUG_LOG_MESSAGE:
883 handled = hsw_log_message(hsw, header);
884 break;
885 default:
886 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
887 type, header);
888 break;
889 }
890
891 return handled;
892}
893
894static irqreturn_t hsw_irq_thread(int irq, void *context)
895{
896 struct sst_dsp *sst = (struct sst_dsp *) context;
897 struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
898 u32 ipcx, ipcd;
899 int handled;
900 unsigned long flags;
901
902 spin_lock_irqsave(&sst->spinlock, flags);
903
904 ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
905 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
906
907 /* reply message from DSP */
908 if (ipcx & SST_IPCX_DONE) {
909
910 /* Handle Immediate reply from DSP Core */
911 handled = hsw_process_reply(hsw, ipcx);
912
913 if (handled > 0) {
914 /* clear DONE bit - tell DSP we have completed */
915 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
916 SST_IPCX_DONE, 0);
917
918 /* unmask Done interrupt */
919 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
920 SST_IMRX_DONE, 0);
921 }
922 }
923
924 /* new message from DSP */
925 if (ipcd & SST_IPCD_BUSY) {
926
927 /* Handle Notification and Delayed reply from DSP Core */
928 handled = hsw_process_notification(hsw);
929
930 /* clear BUSY bit and set DONE bit - accept new messages */
931 if (handled > 0) {
932 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
933 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
934
935 /* unmask busy interrupt */
936 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
937 SST_IMRX_BUSY, 0);
938 }
939 }
940
941 spin_unlock_irqrestore(&sst->spinlock, flags);
942
943 /* continue to send any remaining messages... */
944 queue_kthread_work(&hsw->kworker, &hsw->kwork);
945
946 return IRQ_HANDLED;
947}
948
949int sst_hsw_fw_get_version(struct sst_hsw *hsw,
950 struct sst_hsw_ipc_fw_version *version)
951{
952 int ret;
953
954 ret = ipc_tx_message_wait(hsw, IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
955 NULL, 0, version, sizeof(*version));
956 if (ret < 0)
957 dev_err(hsw->dev, "error: get version failed\n");
958
959 return ret;
960}
961
962/* Mixer Controls */
963int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
964 u32 stage_id, u32 channel)
965{
966 int ret;
967
968 ret = sst_hsw_stream_get_volume(hsw, stream, stage_id, channel,
969 &stream->mute_volume[channel]);
970 if (ret < 0)
971 return ret;
972
973 ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel, 0);
974 if (ret < 0) {
975 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
976 stream->reply.stream_hw_id, channel);
977 return ret;
978 }
979
980 stream->mute[channel] = 1;
981 return 0;
982}
983
984int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
985 u32 stage_id, u32 channel)
986
987{
988 int ret;
989
990 stream->mute[channel] = 0;
991 ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel,
992 stream->mute_volume[channel]);
993 if (ret < 0) {
994 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
995 stream->reply.stream_hw_id, channel);
996 return ret;
997 }
998
999 return 0;
1000}
1001
1002int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1003 u32 stage_id, u32 channel, u32 *volume)
1004{
1005 if (channel > 1)
1006 return -EINVAL;
1007
1008 sst_dsp_read(hsw->dsp, volume,
Christian Engelmayerbf657d22014-04-13 19:56:36 +02001009 stream->reply.volume_register_address[channel],
1010 sizeof(*volume));
Mark Browna4b12992014-03-12 23:04:35 +00001011
1012 return 0;
1013}
1014
1015int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw,
1016 struct sst_hsw_stream *stream, u64 curve_duration,
1017 enum sst_hsw_volume_curve curve)
1018{
1019 /* curve duration in steps of 100ns */
1020 stream->vol_req.curve_duration = curve_duration;
1021 stream->vol_req.curve_type = curve;
1022
1023 return 0;
1024}
1025
1026/* stream volume */
1027int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
1028 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
1029{
1030 struct sst_hsw_ipc_volume_req *req;
1031 u32 header;
1032 int ret;
1033
1034 trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
1035
1036 if (channel > 1)
1037 return -EINVAL;
1038
1039 if (stream->mute[channel]) {
1040 stream->mute_volume[channel] = volume;
1041 return 0;
1042 }
1043
1044 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1045 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1046 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1047 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1048 header |= (stage_id << IPC_STG_ID_SHIFT);
1049
1050 req = &stream->vol_req;
1051 req->channel = channel;
1052 req->target_volume = volume;
1053
1054 ret = ipc_tx_message_wait(hsw, header, req, sizeof(*req), NULL, 0);
1055 if (ret < 0) {
1056 dev_err(hsw->dev, "error: set stream volume failed\n");
1057 return ret;
1058 }
1059
1060 return 0;
1061}
1062
1063int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1064{
1065 int ret;
1066
1067 ret = sst_hsw_mixer_get_volume(hsw, stage_id, channel,
1068 &hsw->mute_volume[channel]);
1069 if (ret < 0)
1070 return ret;
1071
1072 ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel, 0);
1073 if (ret < 0) {
1074 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1075 channel);
1076 return ret;
1077 }
1078
1079 hsw->mute[channel] = 1;
1080 return 0;
1081}
1082
1083int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1084{
1085 int ret;
1086
1087 ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel,
1088 hsw->mixer_info.volume_register_address[channel]);
1089 if (ret < 0) {
1090 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1091 channel);
1092 return ret;
1093 }
1094
1095 hsw->mute[channel] = 0;
1096 return 0;
1097}
1098
1099int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1100 u32 *volume)
1101{
1102 if (channel > 1)
1103 return -EINVAL;
1104
1105 sst_dsp_read(hsw->dsp, volume,
1106 hsw->mixer_info.volume_register_address[channel],
1107 sizeof(*volume));
1108
1109 return 0;
1110}
1111
1112int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw,
1113 u64 curve_duration, enum sst_hsw_volume_curve curve)
1114{
1115 /* curve duration in steps of 100ns */
1116 hsw->curve_duration = curve_duration;
1117 hsw->curve_type = curve;
1118
1119 return 0;
1120}
1121
1122/* global mixer volume */
1123int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1124 u32 volume)
1125{
1126 struct sst_hsw_ipc_volume_req req;
1127 u32 header;
1128 int ret;
1129
1130 trace_ipc_request("set mixer volume", volume);
1131
1132 /* set both at same time ? */
1133 if (channel == 2) {
1134 if (hsw->mute[0] && hsw->mute[1]) {
1135 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
1136 return 0;
1137 } else if (hsw->mute[0])
1138 req.channel = 1;
1139 else if (hsw->mute[1])
1140 req.channel = 0;
1141 else
1142 req.channel = 0xffffffff;
1143 } else {
1144 /* set only 1 channel */
1145 if (hsw->mute[channel]) {
1146 hsw->mute_volume[channel] = volume;
1147 return 0;
1148 }
1149 req.channel = channel;
1150 }
1151
1152 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1153 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1154 header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
1155 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1156 header |= (stage_id << IPC_STG_ID_SHIFT);
1157
1158 req.curve_duration = hsw->curve_duration;
1159 req.curve_type = hsw->curve_type;
1160 req.target_volume = volume;
1161
1162 ret = ipc_tx_message_wait(hsw, header, &req, sizeof(req), NULL, 0);
1163 if (ret < 0) {
1164 dev_err(hsw->dev, "error: set mixer volume failed\n");
1165 return ret;
1166 }
1167
1168 return 0;
1169}
1170
1171/* Stream API */
1172struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
1173 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
1174 void *data)
1175{
1176 struct sst_hsw_stream *stream;
Wenkai Dud132cb02014-04-23 13:29:30 +03001177 struct sst_dsp *sst = hsw->dsp;
1178 unsigned long flags;
Mark Browna4b12992014-03-12 23:04:35 +00001179
1180 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
1181 if (stream == NULL)
1182 return NULL;
1183
Wenkai Dud132cb02014-04-23 13:29:30 +03001184 spin_lock_irqsave(&sst->spinlock, flags);
Mark Browna4b12992014-03-12 23:04:35 +00001185 list_add(&stream->node, &hsw->stream_list);
1186 stream->notify_position = notify_position;
1187 stream->pdata = data;
1188 stream->hsw = hsw;
1189 stream->host_id = id;
1190
1191 /* work to process notification messages */
1192 INIT_WORK(&stream->notify_work, hsw_notification_work);
Wenkai Dud132cb02014-04-23 13:29:30 +03001193 spin_unlock_irqrestore(&sst->spinlock, flags);
Mark Browna4b12992014-03-12 23:04:35 +00001194
1195 return stream;
1196}
1197
1198int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1199{
1200 u32 header;
1201 int ret = 0;
Wenkai Dud132cb02014-04-23 13:29:30 +03001202 struct sst_dsp *sst = hsw->dsp;
1203 unsigned long flags;
Mark Browna4b12992014-03-12 23:04:35 +00001204
1205 /* dont free DSP streams that are not commited */
1206 if (!stream->commited)
1207 goto out;
1208
1209 trace_ipc_request("stream free", stream->host_id);
1210
1211 stream->free_req.stream_id = stream->reply.stream_hw_id;
1212 header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1213
1214 ret = ipc_tx_message_wait(hsw, header, &stream->free_req,
1215 sizeof(stream->free_req), NULL, 0);
1216 if (ret < 0) {
1217 dev_err(hsw->dev, "error: free stream %d failed\n",
1218 stream->free_req.stream_id);
1219 return -EAGAIN;
1220 }
1221
1222 trace_hsw_stream_free_req(stream, &stream->free_req);
1223
1224out:
Jarkko Nikulade30a2c2014-04-24 10:34:36 +03001225 cancel_work_sync(&stream->notify_work);
Wenkai Dud132cb02014-04-23 13:29:30 +03001226 spin_lock_irqsave(&sst->spinlock, flags);
Mark Browna4b12992014-03-12 23:04:35 +00001227 list_del(&stream->node);
1228 kfree(stream);
Wenkai Dud132cb02014-04-23 13:29:30 +03001229 spin_unlock_irqrestore(&sst->spinlock, flags);
Mark Browna4b12992014-03-12 23:04:35 +00001230
1231 return ret;
1232}
1233
1234int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1235 struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1236{
1237 if (stream->commited) {
1238 dev_err(hsw->dev, "error: stream committed for set bits\n");
1239 return -EINVAL;
1240 }
1241
1242 stream->request.format.bitdepth = bits;
1243 return 0;
1244}
1245
1246int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1247 struct sst_hsw_stream *stream, int channels)
1248{
1249 if (stream->commited) {
1250 dev_err(hsw->dev, "error: stream committed for set channels\n");
1251 return -EINVAL;
1252 }
1253
1254 /* stereo is only supported atm */
1255 if (channels != 2)
1256 return -EINVAL;
1257
1258 stream->request.format.ch_num = channels;
1259 return 0;
1260}
1261
1262int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1263 struct sst_hsw_stream *stream, int rate)
1264{
1265 if (stream->commited) {
1266 dev_err(hsw->dev, "error: stream committed for set rate\n");
1267 return -EINVAL;
1268 }
1269
1270 stream->request.format.frequency = rate;
1271 return 0;
1272}
1273
1274int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1275 struct sst_hsw_stream *stream, u32 map,
1276 enum sst_hsw_channel_config config)
1277{
1278 if (stream->commited) {
1279 dev_err(hsw->dev, "error: stream committed for set map\n");
1280 return -EINVAL;
1281 }
1282
1283 stream->request.format.map = map;
1284 stream->request.format.config = config;
1285 return 0;
1286}
1287
1288int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1289 struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1290{
1291 if (stream->commited) {
1292 dev_err(hsw->dev, "error: stream committed for set style\n");
1293 return -EINVAL;
1294 }
1295
1296 stream->request.format.style = style;
1297 return 0;
1298}
1299
1300int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1301 struct sst_hsw_stream *stream, u32 bits)
1302{
1303 if (stream->commited) {
1304 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1305 return -EINVAL;
1306 }
1307
1308 stream->request.format.valid_bit = bits;
1309 return 0;
1310}
1311
1312/* Stream Configuration */
1313int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1314 enum sst_hsw_stream_path_id path_id,
1315 enum sst_hsw_stream_type stream_type,
1316 enum sst_hsw_stream_format format_id)
1317{
1318 if (stream->commited) {
1319 dev_err(hsw->dev, "error: stream committed for set format\n");
1320 return -EINVAL;
1321 }
1322
1323 stream->request.path_id = path_id;
1324 stream->request.stream_type = stream_type;
1325 stream->request.format_id = format_id;
1326
1327 trace_hsw_stream_alloc_request(stream, &stream->request);
1328
1329 return 0;
1330}
1331
1332int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1333 u32 ring_pt_address, u32 num_pages,
1334 u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1335{
1336 if (stream->commited) {
1337 dev_err(hsw->dev, "error: stream committed for buffer\n");
1338 return -EINVAL;
1339 }
1340
1341 stream->request.ringinfo.ring_pt_address = ring_pt_address;
1342 stream->request.ringinfo.num_pages = num_pages;
1343 stream->request.ringinfo.ring_size = ring_size;
1344 stream->request.ringinfo.ring_offset = ring_offset;
1345 stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1346
1347 trace_hsw_stream_buffer(stream);
1348
1349 return 0;
1350}
1351
1352int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
1353 struct sst_hsw_stream *stream, enum sst_hsw_module_id module_id,
1354 u32 entry_point)
1355{
1356 struct sst_hsw_module_map *map = &stream->request.map;
1357
1358 if (stream->commited) {
1359 dev_err(hsw->dev, "error: stream committed for set module\n");
1360 return -EINVAL;
1361 }
1362
1363 /* only support initial module atm */
1364 map->module_entries_count = 1;
1365 map->module_entries[0].module_id = module_id;
1366 map->module_entries[0].entry_point = entry_point;
1367
1368 return 0;
1369}
1370
1371int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
1372 struct sst_hsw_stream *stream, u32 offset, u32 size)
1373{
1374 if (stream->commited) {
1375 dev_err(hsw->dev, "error: stream committed for set pmem\n");
1376 return -EINVAL;
1377 }
1378
1379 stream->request.persistent_mem.offset = offset;
1380 stream->request.persistent_mem.size = size;
1381
1382 return 0;
1383}
1384
1385int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
1386 struct sst_hsw_stream *stream, u32 offset, u32 size)
1387{
1388 if (stream->commited) {
1389 dev_err(hsw->dev, "error: stream committed for set smem\n");
1390 return -EINVAL;
1391 }
1392
1393 stream->request.scratch_mem.offset = offset;
1394 stream->request.scratch_mem.size = size;
1395
1396 return 0;
1397}
1398
1399int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1400{
1401 struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1402 struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1403 u32 header;
1404 int ret;
1405
1406 trace_ipc_request("stream alloc", stream->host_id);
1407
1408 header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1409
1410 ret = ipc_tx_message_wait(hsw, header, str_req, sizeof(*str_req),
1411 reply, sizeof(*reply));
1412 if (ret < 0) {
1413 dev_err(hsw->dev, "error: stream commit failed\n");
1414 return ret;
1415 }
1416
1417 stream->commited = 1;
1418 trace_hsw_stream_alloc_reply(stream);
1419
1420 return 0;
1421}
1422
1423/* Stream Information - these calls could be inline but we want the IPC
1424 ABI to be opaque to client PCM drivers to cope with any future ABI changes */
1425int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw,
1426 struct sst_hsw_stream *stream)
1427{
1428 return stream->reply.stream_hw_id;
1429}
1430
1431int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw,
1432 struct sst_hsw_stream *stream)
1433{
1434 return stream->reply.mixer_hw_id;
1435}
1436
1437u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw,
1438 struct sst_hsw_stream *stream)
1439{
1440 return stream->reply.read_position_register_address;
1441}
1442
1443u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw,
1444 struct sst_hsw_stream *stream)
1445{
1446 return stream->reply.presentation_position_register_address;
1447}
1448
1449u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw,
1450 struct sst_hsw_stream *stream, u32 channel)
1451{
1452 if (channel >= 2)
1453 return 0;
1454
1455 return stream->reply.peak_meter_register_address[channel];
1456}
1457
1458u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw,
1459 struct sst_hsw_stream *stream, u32 channel)
1460{
1461 if (channel >= 2)
1462 return 0;
1463
1464 return stream->reply.volume_register_address[channel];
1465}
1466
1467int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1468{
1469 struct sst_hsw_ipc_stream_info_reply *reply;
1470 u32 header;
1471 int ret;
1472
1473 reply = &hsw->mixer_info;
1474 header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1475
1476 trace_ipc_request("get global mixer info", 0);
1477
1478 ret = ipc_tx_message_wait(hsw, header, NULL, 0, reply, sizeof(*reply));
1479 if (ret < 0) {
1480 dev_err(hsw->dev, "error: get stream info failed\n");
1481 return ret;
1482 }
1483
1484 trace_hsw_mixer_info_reply(reply);
1485
1486 return 0;
1487}
1488
1489/* Send stream command */
1490static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1491 int stream_id, int wait)
1492{
1493 u32 header;
1494
1495 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1496 header |= (stream_id << IPC_STR_ID_SHIFT);
1497
1498 if (wait)
1499 return ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0);
1500 else
1501 return ipc_tx_message_nowait(hsw, header, NULL, 0);
1502}
1503
1504/* Stream ALSA trigger operations */
1505int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1506 int wait)
1507{
1508 int ret;
1509
1510 trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1511
1512 ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1513 stream->reply.stream_hw_id, wait);
1514 if (ret < 0)
1515 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1516 stream->reply.stream_hw_id);
1517
1518 return ret;
1519}
1520
1521int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1522 int wait)
1523{
1524 int ret;
1525
1526 trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1527
1528 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1529 stream->reply.stream_hw_id, wait);
1530 if (ret < 0)
1531 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1532 stream->reply.stream_hw_id);
1533
1534 return ret;
1535}
1536
1537int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1538{
1539 int ret, tries = 10;
1540
1541 /* dont reset streams that are not commited */
1542 if (!stream->commited)
1543 return 0;
1544
1545 /* wait for pause to complete before we reset the stream */
1546 while (stream->running && tries--)
1547 msleep(1);
1548 if (!tries) {
1549 dev_err(hsw->dev, "error: reset stream %d still running\n",
1550 stream->reply.stream_hw_id);
1551 return -EINVAL;
1552 }
1553
1554 trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1555
1556 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1557 stream->reply.stream_hw_id, 1);
1558 if (ret < 0)
1559 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1560 stream->reply.stream_hw_id);
1561 return ret;
1562}
1563
1564/* Stream pointer positions */
Liam Girdwood51b4e242014-05-02 16:56:33 +01001565u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
Mark Browna4b12992014-03-12 23:04:35 +00001566 struct sst_hsw_stream *stream)
1567{
Liam Girdwood51b4e242014-05-02 16:56:33 +01001568 u32 rpos;
1569
1570 sst_dsp_read(hsw->dsp, &rpos,
1571 stream->reply.read_position_register_address, sizeof(rpos));
1572
1573 return rpos;
1574}
1575
1576/* Stream presentation (monotonic) positions */
1577u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1578 struct sst_hsw_stream *stream)
1579{
1580 u64 ppos;
1581
1582 sst_dsp_read(hsw->dsp, &ppos,
1583 stream->reply.presentation_position_register_address,
1584 sizeof(ppos));
1585
1586 return ppos;
Mark Browna4b12992014-03-12 23:04:35 +00001587}
1588
1589int sst_hsw_stream_set_write_position(struct sst_hsw *hsw,
1590 struct sst_hsw_stream *stream, u32 stage_id, u32 position)
1591{
1592 u32 header;
1593 int ret;
1594
1595 trace_stream_write_position(stream->reply.stream_hw_id, position);
1596
1597 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1598 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1599 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1600 header |= (IPC_STG_SET_WRITE_POSITION << IPC_STG_TYPE_SHIFT);
1601 header |= (stage_id << IPC_STG_ID_SHIFT);
1602 stream->wpos.position = position;
1603
1604 ret = ipc_tx_message_nowait(hsw, header, &stream->wpos,
1605 sizeof(stream->wpos));
1606 if (ret < 0)
1607 dev_err(hsw->dev, "error: stream %d set position %d failed\n",
1608 stream->reply.stream_hw_id, position);
1609
1610 return ret;
1611}
1612
1613/* physical BE config */
1614int sst_hsw_device_set_config(struct sst_hsw *hsw,
1615 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1616 enum sst_hsw_device_mode mode, u32 clock_divider)
1617{
1618 struct sst_hsw_ipc_device_config_req config;
1619 u32 header;
1620 int ret;
1621
1622 trace_ipc_request("set device config", dev);
1623
1624 config.ssp_interface = dev;
1625 config.clock_frequency = mclk;
1626 config.mode = mode;
1627 config.clock_divider = clock_divider;
1628
1629 trace_hsw_device_config_req(&config);
1630
1631 header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1632
1633 ret = ipc_tx_message_wait(hsw, header, &config, sizeof(config),
1634 NULL, 0);
1635 if (ret < 0)
1636 dev_err(hsw->dev, "error: set device formats failed\n");
1637
1638 return ret;
1639}
1640EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1641
1642/* DX Config */
1643int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1644 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1645{
1646 u32 header, state_;
1647 int ret;
1648
1649 header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1650 state_ = state;
1651
1652 trace_ipc_request("PM enter Dx state", state);
1653
1654 ret = ipc_tx_message_wait(hsw, header, &state_, sizeof(state_),
Dan Carpenter7897ab72014-04-16 18:38:11 +03001655 dx, sizeof(*dx));
Mark Browna4b12992014-03-12 23:04:35 +00001656 if (ret < 0) {
1657 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1658 return ret;
1659 }
1660
1661 dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1662 dx->entries_no, state);
1663
1664 memcpy(&hsw->dx, dx, sizeof(*dx));
1665 return 0;
1666}
1667
1668/* Used to save state into hsw->dx_reply */
1669int sst_hsw_dx_get_state(struct sst_hsw *hsw, u32 item,
1670 u32 *offset, u32 *size, u32 *source)
1671{
1672 struct sst_hsw_ipc_dx_memory_item *dx_mem;
1673 struct sst_hsw_ipc_dx_reply *dx_reply;
1674 int entry_no;
1675
1676 dx_reply = &hsw->dx;
1677 entry_no = dx_reply->entries_no;
1678
1679 trace_ipc_request("PM get Dx state", entry_no);
1680
1681 if (item >= entry_no)
1682 return -EINVAL;
1683
1684 dx_mem = &dx_reply->mem_info[item];
1685 *offset = dx_mem->offset;
1686 *size = dx_mem->size;
1687 *source = dx_mem->source;
1688
1689 return 0;
1690}
1691
1692static int msg_empty_list_init(struct sst_hsw *hsw)
1693{
1694 int i;
1695
1696 hsw->msg = kzalloc(sizeof(struct ipc_message) *
1697 IPC_EMPTY_LIST_SIZE, GFP_KERNEL);
1698 if (hsw->msg == NULL)
1699 return -ENOMEM;
1700
1701 for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
1702 init_waitqueue_head(&hsw->msg[i].waitq);
1703 list_add(&hsw->msg[i].list, &hsw->empty_list);
1704 }
1705
1706 return 0;
1707}
1708
1709void sst_hsw_set_scratch_module(struct sst_hsw *hsw,
1710 struct sst_module *scratch)
1711{
1712 hsw->scratch = scratch;
1713}
1714
1715struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1716{
1717 return hsw->dsp;
1718}
1719
1720static struct sst_dsp_device hsw_dev = {
1721 .thread = hsw_irq_thread,
1722 .ops = &haswell_ops,
1723};
1724
1725int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
1726{
1727 struct sst_hsw_ipc_fw_version version;
1728 struct sst_hsw *hsw;
1729 struct sst_fw *hsw_sst_fw;
1730 int ret;
1731
1732 dev_dbg(dev, "initialising Audio DSP IPC\n");
1733
1734 hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
1735 if (hsw == NULL)
1736 return -ENOMEM;
1737
1738 hsw->dev = dev;
1739 INIT_LIST_HEAD(&hsw->stream_list);
1740 INIT_LIST_HEAD(&hsw->tx_list);
1741 INIT_LIST_HEAD(&hsw->rx_list);
1742 INIT_LIST_HEAD(&hsw->empty_list);
1743 init_waitqueue_head(&hsw->boot_wait);
1744 init_waitqueue_head(&hsw->wait_txq);
1745
1746 ret = msg_empty_list_init(hsw);
1747 if (ret < 0)
Imre Deak9cf0e452014-05-30 10:52:29 +03001748 return -ENOMEM;
Mark Browna4b12992014-03-12 23:04:35 +00001749
1750 /* start the IPC message thread */
1751 init_kthread_worker(&hsw->kworker);
1752 hsw->tx_thread = kthread_run(kthread_worker_fn,
Kees Cook35386322014-05-22 11:43:55 -07001753 &hsw->kworker, "%s",
Mark Browna4b12992014-03-12 23:04:35 +00001754 dev_name(hsw->dev));
1755 if (IS_ERR(hsw->tx_thread)) {
1756 ret = PTR_ERR(hsw->tx_thread);
1757 dev_err(hsw->dev, "error: failed to create message TX task\n");
Imre Deak9cf0e452014-05-30 10:52:29 +03001758 goto err_free_msg;
Mark Browna4b12992014-03-12 23:04:35 +00001759 }
1760 init_kthread_work(&hsw->kwork, ipc_tx_msgs);
1761
1762 hsw_dev.thread_context = hsw;
1763
1764 /* init SST shim */
1765 hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
1766 if (hsw->dsp == NULL) {
1767 ret = -ENODEV;
Imre Deak9cf0e452014-05-30 10:52:29 +03001768 goto dsp_err;
Mark Browna4b12992014-03-12 23:04:35 +00001769 }
1770
1771 /* keep the DSP in reset state for base FW loading */
1772 sst_dsp_reset(hsw->dsp);
1773
1774 hsw_sst_fw = sst_fw_new(hsw->dsp, pdata->fw, hsw);
1775
1776 if (hsw_sst_fw == NULL) {
1777 ret = -ENODEV;
1778 dev_err(dev, "error: failed to load firmware\n");
1779 goto fw_err;
1780 }
1781
1782 /* wait for DSP boot completion */
1783 sst_dsp_boot(hsw->dsp);
1784 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1785 msecs_to_jiffies(IPC_BOOT_MSECS));
1786 if (ret == 0) {
1787 ret = -EIO;
1788 dev_err(hsw->dev, "error: ADSP boot timeout\n");
1789 goto boot_err;
1790 }
1791
1792 /* get the FW version */
1793 sst_hsw_fw_get_version(hsw, &version);
Mark Browna4b12992014-03-12 23:04:35 +00001794
1795 /* get the globalmixer */
1796 ret = sst_hsw_mixer_get_info(hsw);
1797 if (ret < 0) {
1798 dev_err(hsw->dev, "error: failed to get stream info\n");
1799 goto boot_err;
1800 }
1801
1802 pdata->dsp = hsw;
1803 return 0;
1804
1805boot_err:
1806 sst_dsp_reset(hsw->dsp);
1807 sst_fw_free(hsw_sst_fw);
1808fw_err:
1809 sst_dsp_free(hsw->dsp);
Imre Deak9cf0e452014-05-30 10:52:29 +03001810dsp_err:
1811 kthread_stop(hsw->tx_thread);
1812err_free_msg:
Mark Browna4b12992014-03-12 23:04:35 +00001813 kfree(hsw->msg);
Imre Deak9cf0e452014-05-30 10:52:29 +03001814
Mark Browna4b12992014-03-12 23:04:35 +00001815 return ret;
1816}
1817EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
1818
1819void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
1820{
1821 struct sst_hsw *hsw = pdata->dsp;
1822
1823 sst_dsp_reset(hsw->dsp);
1824 sst_fw_free_all(hsw->dsp);
1825 sst_dsp_free(hsw->dsp);
1826 kfree(hsw->scratch);
Imre Deak9cf0e452014-05-30 10:52:29 +03001827 kthread_stop(hsw->tx_thread);
Mark Browna4b12992014-03-12 23:04:35 +00001828 kfree(hsw->msg);
1829}
1830EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);