Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * NAND Flash Controller Device Driver |
| 3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/wait.h> |
| 23 | #include <linux/mutex.h> |
David Miller | b8664b3 | 2010-08-04 22:57:51 -0700 | [diff] [blame] | 24 | #include <linux/slab.h> |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 25 | #include <linux/pci.h> |
| 26 | #include <linux/mtd/mtd.h> |
| 27 | #include <linux/module.h> |
| 28 | |
| 29 | #include "denali.h" |
| 30 | |
| 31 | MODULE_LICENSE("GPL"); |
| 32 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 33 | /* We define a module parameter that allows the user to override |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 34 | * the hardware and decide what timing mode should be used. |
| 35 | */ |
| 36 | #define NAND_DEFAULT_TIMINGS -1 |
| 37 | |
| 38 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; |
| 39 | module_param(onfi_timing_mode, int, S_IRUGO); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 40 | MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting." |
| 41 | " -1 indicates use default timings"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 42 | |
| 43 | #define DENALI_NAND_NAME "denali-nand" |
| 44 | |
| 45 | /* We define a macro here that combines all interrupts this driver uses into |
| 46 | * a single constant value, for convenience. */ |
| 47 | #define DENALI_IRQ_ALL (INTR_STATUS0__DMA_CMD_COMP | \ |
| 48 | INTR_STATUS0__ECC_TRANSACTION_DONE | \ |
| 49 | INTR_STATUS0__ECC_ERR | \ |
| 50 | INTR_STATUS0__PROGRAM_FAIL | \ |
| 51 | INTR_STATUS0__LOAD_COMP | \ |
| 52 | INTR_STATUS0__PROGRAM_COMP | \ |
| 53 | INTR_STATUS0__TIME_OUT | \ |
| 54 | INTR_STATUS0__ERASE_FAIL | \ |
| 55 | INTR_STATUS0__RST_COMP | \ |
| 56 | INTR_STATUS0__ERASE_COMP) |
| 57 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 58 | /* indicates whether or not the internal value for the flash bank is |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 59 | valid or not */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 60 | #define CHIP_SELECT_INVALID -1 |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 61 | |
| 62 | #define SUPPORT_8BITECC 1 |
| 63 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 64 | /* This macro divides two integers and rounds fractional values up |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 65 | * to the nearest integer value. */ |
| 66 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) |
| 67 | |
| 68 | /* this macro allows us to convert from an MTD structure to our own |
| 69 | * device context (denali) structure. |
| 70 | */ |
| 71 | #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd) |
| 72 | |
| 73 | /* These constants are defined by the driver to enable common driver |
| 74 | configuration options. */ |
| 75 | #define SPARE_ACCESS 0x41 |
| 76 | #define MAIN_ACCESS 0x42 |
| 77 | #define MAIN_SPARE_ACCESS 0x43 |
| 78 | |
| 79 | #define DENALI_READ 0 |
| 80 | #define DENALI_WRITE 0x100 |
| 81 | |
| 82 | /* types of device accesses. We can issue commands and get status */ |
| 83 | #define COMMAND_CYCLE 0 |
| 84 | #define ADDR_CYCLE 1 |
| 85 | #define STATUS_CYCLE 2 |
| 86 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 87 | /* this is a helper macro that allows us to |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 88 | * format the bank into the proper bits for the controller */ |
| 89 | #define BANK(x) ((x) << 24) |
| 90 | |
| 91 | /* List of platforms this NAND controller has be integrated into */ |
| 92 | static const struct pci_device_id denali_pci_ids[] = { |
| 93 | { PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 }, |
| 94 | { PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST }, |
| 95 | { /* end: all zeroes */ } |
| 96 | }; |
| 97 | |
| 98 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 99 | /* these are static lookup tables that give us easy access to |
| 100 | registers in the NAND controller. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 101 | */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 102 | static const uint32_t intr_status_addresses[4] = {INTR_STATUS0, |
| 103 | INTR_STATUS1, |
| 104 | INTR_STATUS2, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 105 | INTR_STATUS3}; |
| 106 | |
| 107 | static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0, |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 108 | DEVICE_RESET__BANK1, |
| 109 | DEVICE_RESET__BANK2, |
| 110 | DEVICE_RESET__BANK3}; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 111 | |
| 112 | static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT, |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 113 | INTR_STATUS1__TIME_OUT, |
| 114 | INTR_STATUS2__TIME_OUT, |
| 115 | INTR_STATUS3__TIME_OUT}; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 116 | |
| 117 | static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP, |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 118 | INTR_STATUS1__RST_COMP, |
| 119 | INTR_STATUS2__RST_COMP, |
| 120 | INTR_STATUS3__RST_COMP}; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 121 | |
| 122 | /* specifies the debug level of the driver */ |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 123 | static int nand_debug_level; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 124 | |
| 125 | /* forward declarations */ |
| 126 | static void clear_interrupts(struct denali_nand_info *denali); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 127 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
| 128 | uint32_t irq_mask); |
| 129 | static void denali_irq_enable(struct denali_nand_info *denali, |
| 130 | uint32_t int_mask); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 131 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
| 132 | |
| 133 | #define DEBUG_DENALI 0 |
| 134 | |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 135 | /* Certain operations for the denali NAND controller use |
| 136 | * an indexed mode to read/write data. The operation is |
| 137 | * performed by writing the address value of the command |
| 138 | * to the device memory followed by the data. This function |
| 139 | * abstracts this common operation. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 140 | */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 141 | static void index_addr(struct denali_nand_info *denali, |
| 142 | uint32_t address, uint32_t data) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 143 | { |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 144 | iowrite32(address, denali->flash_mem); |
| 145 | iowrite32(data, denali->flash_mem + 0x10); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | /* Perform an indexed read of the device */ |
| 149 | static void index_addr_read_data(struct denali_nand_info *denali, |
| 150 | uint32_t address, uint32_t *pdata) |
| 151 | { |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 152 | iowrite32(address, denali->flash_mem); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 153 | *pdata = ioread32(denali->flash_mem + 0x10); |
| 154 | } |
| 155 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 156 | /* We need to buffer some data for some of the NAND core routines. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 157 | * The operations manage buffering that data. */ |
| 158 | static void reset_buf(struct denali_nand_info *denali) |
| 159 | { |
| 160 | denali->buf.head = denali->buf.tail = 0; |
| 161 | } |
| 162 | |
| 163 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) |
| 164 | { |
| 165 | BUG_ON(denali->buf.tail >= sizeof(denali->buf.buf)); |
| 166 | denali->buf.buf[denali->buf.tail++] = byte; |
| 167 | } |
| 168 | |
| 169 | /* reads the status of the device */ |
| 170 | static void read_status(struct denali_nand_info *denali) |
| 171 | { |
| 172 | uint32_t cmd = 0x0; |
| 173 | |
| 174 | /* initialize the data buffer to store status */ |
| 175 | reset_buf(denali); |
| 176 | |
| 177 | /* initiate a device status read */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 178 | cmd = MODE_11 | BANK(denali->flash_bank); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 179 | index_addr(denali, cmd | COMMAND_CYCLE, 0x70); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 180 | iowrite32(cmd | STATUS_CYCLE, denali->flash_mem); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 181 | |
| 182 | /* update buffer with status value */ |
| 183 | write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10)); |
| 184 | |
| 185 | #if DEBUG_DENALI |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 186 | printk(KERN_INFO "device reporting status value of 0x%2x\n", |
| 187 | denali->buf.buf[0]); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 188 | #endif |
| 189 | } |
| 190 | |
| 191 | /* resets a specific device connected to the core */ |
| 192 | static void reset_bank(struct denali_nand_info *denali) |
| 193 | { |
| 194 | uint32_t irq_status = 0; |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 195 | uint32_t irq_mask = reset_complete[denali->flash_bank] | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 196 | operation_timeout[denali->flash_bank]; |
| 197 | int bank = 0; |
| 198 | |
| 199 | clear_interrupts(denali); |
| 200 | |
| 201 | bank = device_reset_banks[denali->flash_bank]; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 202 | iowrite32(bank, denali->flash_reg + DEVICE_RESET); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 203 | |
| 204 | irq_status = wait_for_irq(denali, irq_mask); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 205 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 206 | if (irq_status & operation_timeout[denali->flash_bank]) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 207 | printk(KERN_ERR "reset bank failed.\n"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | /* Reset the flash controller */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 211 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 212 | { |
| 213 | uint32_t i; |
| 214 | |
| 215 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", |
| 216 | __FILE__, __LINE__, __func__); |
| 217 | |
| 218 | for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 219 | iowrite32(reset_complete[i] | operation_timeout[i], |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 220 | denali->flash_reg + intr_status_addresses[i]); |
| 221 | |
| 222 | for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) { |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 223 | iowrite32(device_reset_banks[i], |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 224 | denali->flash_reg + DEVICE_RESET); |
| 225 | while (!(ioread32(denali->flash_reg + |
| 226 | intr_status_addresses[i]) & |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 227 | (reset_complete[i] | operation_timeout[i]))) |
| 228 | ; |
| 229 | if (ioread32(denali->flash_reg + intr_status_addresses[i]) & |
| 230 | operation_timeout[i]) |
| 231 | nand_dbg_print(NAND_DBG_WARN, |
| 232 | "NAND Reset operation timed out on bank %d\n", i); |
| 233 | } |
| 234 | |
| 235 | for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 236 | iowrite32(reset_complete[i] | operation_timeout[i], |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 237 | denali->flash_reg + intr_status_addresses[i]); |
| 238 | |
| 239 | return PASS; |
| 240 | } |
| 241 | |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 242 | /* this routine calculates the ONFI timing values for a given mode and |
| 243 | * programs the clocking register accordingly. The mode is determined by |
| 244 | * the get_onfi_nand_para routine. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 245 | */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 246 | static void nand_onfi_timing_set(struct denali_nand_info *denali, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 247 | uint16_t mode) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 248 | { |
| 249 | uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; |
| 250 | uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; |
| 251 | uint16_t Treh[6] = {30, 15, 15, 10, 10, 7}; |
| 252 | uint16_t Trc[6] = {100, 50, 35, 30, 25, 20}; |
| 253 | uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15}; |
| 254 | uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5}; |
| 255 | uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25}; |
| 256 | uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70}; |
| 257 | uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100}; |
| 258 | uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100}; |
| 259 | uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60}; |
| 260 | uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15}; |
| 261 | |
| 262 | uint16_t TclsRising = 1; |
| 263 | uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid; |
| 264 | uint16_t dv_window = 0; |
| 265 | uint16_t en_lo, en_hi; |
| 266 | uint16_t acc_clks; |
| 267 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; |
| 268 | |
| 269 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", |
| 270 | __FILE__, __LINE__, __func__); |
| 271 | |
| 272 | en_lo = CEIL_DIV(Trp[mode], CLK_X); |
| 273 | en_hi = CEIL_DIV(Treh[mode], CLK_X); |
| 274 | #if ONFI_BLOOM_TIME |
| 275 | if ((en_hi * CLK_X) < (Treh[mode] + 2)) |
| 276 | en_hi++; |
| 277 | #endif |
| 278 | |
| 279 | if ((en_lo + en_hi) * CLK_X < Trc[mode]) |
| 280 | en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X); |
| 281 | |
| 282 | if ((en_lo + en_hi) < CLK_MULTI) |
| 283 | en_lo += CLK_MULTI - en_lo - en_hi; |
| 284 | |
| 285 | while (dv_window < 8) { |
| 286 | data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode]; |
| 287 | |
| 288 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; |
| 289 | |
| 290 | data_invalid = |
| 291 | data_invalid_rhoh < |
| 292 | data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh; |
| 293 | |
| 294 | dv_window = data_invalid - Trea[mode]; |
| 295 | |
| 296 | if (dv_window < 8) |
| 297 | en_lo++; |
| 298 | } |
| 299 | |
| 300 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); |
| 301 | |
| 302 | while (((acc_clks * CLK_X) - Trea[mode]) < 3) |
| 303 | acc_clks++; |
| 304 | |
| 305 | if ((data_invalid - acc_clks * CLK_X) < 2) |
| 306 | nand_dbg_print(NAND_DBG_WARN, "%s, Line %d: Warning!\n", |
| 307 | __FILE__, __LINE__); |
| 308 | |
| 309 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); |
| 310 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); |
| 311 | re_2_re = CEIL_DIV(Trhz[mode], CLK_X); |
| 312 | we_2_re = CEIL_DIV(Twhr[mode], CLK_X); |
| 313 | cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X); |
| 314 | if (!TclsRising) |
| 315 | cs_cnt = CEIL_DIV(Tcs[mode], CLK_X); |
| 316 | if (cs_cnt == 0) |
| 317 | cs_cnt = 1; |
| 318 | |
| 319 | if (Tcea[mode]) { |
| 320 | while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode]) |
| 321 | cs_cnt++; |
| 322 | } |
| 323 | |
| 324 | #if MODE5_WORKAROUND |
| 325 | if (mode == 5) |
| 326 | acc_clks = 5; |
| 327 | #endif |
| 328 | |
| 329 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ |
| 330 | if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) && |
| 331 | (ioread32(denali->flash_reg + DEVICE_ID) == 0x88)) |
| 332 | acc_clks = 6; |
| 333 | |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 334 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); |
| 335 | iowrite32(re_2_we, denali->flash_reg + RE_2_WE); |
| 336 | iowrite32(re_2_re, denali->flash_reg + RE_2_RE); |
| 337 | iowrite32(we_2_re, denali->flash_reg + WE_2_RE); |
| 338 | iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); |
| 339 | iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); |
| 340 | iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); |
| 341 | iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 342 | } |
| 343 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 344 | /* queries the NAND device to see what ONFI modes it supports. */ |
| 345 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) |
| 346 | { |
| 347 | int i; |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 348 | /* we needn't to do a reset here because driver has already |
| 349 | * reset all the banks before |
| 350 | * */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 351 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
| 352 | ONFI_TIMING_MODE__VALUE)) |
| 353 | return FAIL; |
| 354 | |
| 355 | for (i = 5; i > 0; i--) { |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 356 | if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
| 357 | (0x01 << i)) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 358 | break; |
| 359 | } |
| 360 | |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 361 | nand_onfi_timing_set(denali, i); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 362 | |
| 363 | /* By now, all the ONFI devices we know support the page cache */ |
| 364 | /* rw feature. So here we enable the pipeline_rw_ahead feature */ |
| 365 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ |
| 366 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ |
| 367 | |
| 368 | return PASS; |
| 369 | } |
| 370 | |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 371 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
| 372 | uint8_t device_id) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 373 | { |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 374 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 375 | /* Set timing register values according to datasheet */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 376 | iowrite32(5, denali->flash_reg + ACC_CLKS); |
| 377 | iowrite32(20, denali->flash_reg + RE_2_WE); |
| 378 | iowrite32(12, denali->flash_reg + WE_2_RE); |
| 379 | iowrite32(14, denali->flash_reg + ADDR_2_DATA); |
| 380 | iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); |
| 381 | iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); |
| 382 | iowrite32(2, denali->flash_reg + CS_SETUP_CNT); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 383 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | static void get_toshiba_nand_para(struct denali_nand_info *denali) |
| 387 | { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 388 | uint32_t tmp; |
| 389 | |
| 390 | /* Workaround to fix a controller bug which reports a wrong */ |
| 391 | /* spare area size for some kind of Toshiba NAND device */ |
| 392 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && |
| 393 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 394 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 395 | tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * |
| 396 | ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 397 | iowrite32(tmp, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 398 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 399 | #if SUPPORT_15BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 400 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 401 | #elif SUPPORT_8BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 402 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 403 | #endif |
| 404 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 405 | } |
| 406 | |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 407 | static void get_hynix_nand_para(struct denali_nand_info *denali, |
| 408 | uint8_t device_id) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 409 | { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 410 | uint32_t main_size, spare_size; |
| 411 | |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 412 | switch (device_id) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 413 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ |
| 414 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 415 | iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); |
| 416 | iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); |
| 417 | iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 418 | main_size = 4096 * |
| 419 | ioread32(denali->flash_reg + DEVICES_CONNECTED); |
| 420 | spare_size = 224 * |
| 421 | ioread32(denali->flash_reg + DEVICES_CONNECTED); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 422 | iowrite32(main_size, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 423 | denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 424 | iowrite32(spare_size, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 425 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 426 | iowrite32(0, denali->flash_reg + DEVICE_WIDTH); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 427 | #if SUPPORT_15BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 428 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 429 | #elif SUPPORT_8BITECC |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 430 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 431 | #endif |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 432 | break; |
| 433 | default: |
| 434 | nand_dbg_print(NAND_DBG_WARN, |
| 435 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." |
| 436 | "Will use default parameter values instead.\n", |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 437 | device_id); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 438 | } |
| 439 | } |
| 440 | |
| 441 | /* determines how many NAND chips are connected to the controller. Note for |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 442 | Intel CE4100 devices we don't support more than one device. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 443 | */ |
| 444 | static void find_valid_banks(struct denali_nand_info *denali) |
| 445 | { |
| 446 | uint32_t id[LLD_MAX_FLASH_BANKS]; |
| 447 | int i; |
| 448 | |
| 449 | denali->total_used_banks = 1; |
| 450 | for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) { |
| 451 | index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90); |
| 452 | index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 453 | index_addr_read_data(denali, |
| 454 | (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 455 | |
| 456 | nand_dbg_print(NAND_DBG_DEBUG, |
| 457 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
| 458 | |
| 459 | if (i == 0) { |
| 460 | if (!(id[i] & 0x0ff)) |
| 461 | break; /* WTF? */ |
| 462 | } else { |
| 463 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) |
| 464 | denali->total_used_banks++; |
| 465 | else |
| 466 | break; |
| 467 | } |
| 468 | } |
| 469 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 470 | if (denali->platform == INTEL_CE4100) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 471 | /* Platform limitations of the CE4100 device limit |
| 472 | * users to a single chip solution for NAND. |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 473 | * Multichip support is not enabled. |
| 474 | */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 475 | if (denali->total_used_banks != 1) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 476 | printk(KERN_ERR "Sorry, Intel CE4100 only supports " |
| 477 | "a single NAND device.\n"); |
| 478 | BUG(); |
| 479 | } |
| 480 | } |
| 481 | nand_dbg_print(NAND_DBG_DEBUG, |
| 482 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
| 483 | } |
| 484 | |
| 485 | static void detect_partition_feature(struct denali_nand_info *denali) |
| 486 | { |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 487 | /* For MRST platform, denali->fwblks represent the |
| 488 | * number of blocks firmware is taken, |
| 489 | * FW is in protect partition and MTD driver has no |
| 490 | * permission to access it. So let driver know how many |
| 491 | * blocks it can't touch. |
| 492 | * */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 493 | if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { |
| 494 | if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) & |
| 495 | PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) { |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 496 | denali->fwblks = |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 497 | ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) & |
| 498 | MIN_MAX_BANK_1__MIN_VALUE) * |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 499 | denali->blksperchip) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 500 | + |
| 501 | (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) & |
| 502 | MIN_BLK_ADDR_1__VALUE); |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 503 | } else |
| 504 | denali->fwblks = SPECTRA_START_BLOCK; |
| 505 | } else |
| 506 | denali->fwblks = SPECTRA_START_BLOCK; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 507 | } |
| 508 | |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 509 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 510 | { |
| 511 | uint16_t status = PASS; |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 512 | uint32_t id_bytes[5], addr; |
| 513 | uint8_t i, maf_id, device_id; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 514 | |
| 515 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", |
| 516 | __FILE__, __LINE__, __func__); |
| 517 | |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 518 | /* Use read id method to get device ID and other |
| 519 | * params. For some NAND chips, controller can't |
| 520 | * report the correct device ID by reading from |
| 521 | * DEVICE_ID register |
| 522 | * */ |
| 523 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); |
| 524 | index_addr(denali, (uint32_t)addr | 0, 0x90); |
| 525 | index_addr(denali, (uint32_t)addr | 1, 0); |
| 526 | for (i = 0; i < 5; i++) |
| 527 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
| 528 | maf_id = id_bytes[0]; |
| 529 | device_id = id_bytes[1]; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 530 | |
| 531 | if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & |
| 532 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ |
| 533 | if (FAIL == get_onfi_nand_para(denali)) |
| 534 | return FAIL; |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 535 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
Chuanxiao Dong | 4c03bbd | 2010-08-06 15:45:19 +0800 | [diff] [blame] | 536 | get_samsung_nand_para(denali, device_id); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 537 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 538 | get_toshiba_nand_para(denali); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 539 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |
| 540 | get_hynix_nand_para(denali, device_id); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 541 | } |
| 542 | |
| 543 | nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:" |
| 544 | "acc_clks: %d, re_2_we: %d, we_2_re: %d," |
| 545 | "addr_2_data: %d, rdwr_en_lo_cnt: %d, " |
| 546 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
| 547 | ioread32(denali->flash_reg + ACC_CLKS), |
| 548 | ioread32(denali->flash_reg + RE_2_WE), |
| 549 | ioread32(denali->flash_reg + WE_2_RE), |
| 550 | ioread32(denali->flash_reg + ADDR_2_DATA), |
| 551 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), |
| 552 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), |
| 553 | ioread32(denali->flash_reg + CS_SETUP_CNT)); |
| 554 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 555 | find_valid_banks(denali); |
| 556 | |
| 557 | detect_partition_feature(denali); |
| 558 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 559 | /* If the user specified to override the default timings |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 560 | * with a specific ONFI mode, we apply those changes here. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 561 | */ |
| 562 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 563 | nand_onfi_timing_set(denali, onfi_timing_mode); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 564 | |
| 565 | return status; |
| 566 | } |
| 567 | |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 568 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 569 | uint16_t INT_ENABLE) |
| 570 | { |
| 571 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", |
| 572 | __FILE__, __LINE__, __func__); |
| 573 | |
| 574 | if (INT_ENABLE) |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 575 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 576 | else |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 577 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 578 | } |
| 579 | |
| 580 | /* validation function to verify that the controlling software is making |
| 581 | a valid request |
| 582 | */ |
| 583 | static inline bool is_flash_bank_valid(int flash_bank) |
| 584 | { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 585 | return (flash_bank >= 0 && flash_bank < 4); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 586 | } |
| 587 | |
| 588 | static void denali_irq_init(struct denali_nand_info *denali) |
| 589 | { |
| 590 | uint32_t int_mask = 0; |
| 591 | |
| 592 | /* Disable global interrupts */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 593 | denali_set_intr_modes(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 594 | |
| 595 | int_mask = DENALI_IRQ_ALL; |
| 596 | |
| 597 | /* Clear all status bits */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 598 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS0); |
| 599 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS1); |
| 600 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS2); |
| 601 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS3); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 602 | |
| 603 | denali_irq_enable(denali, int_mask); |
| 604 | } |
| 605 | |
| 606 | static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) |
| 607 | { |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 608 | denali_set_intr_modes(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 609 | free_irq(irqnum, denali); |
| 610 | } |
| 611 | |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 612 | static void denali_irq_enable(struct denali_nand_info *denali, |
| 613 | uint32_t int_mask) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 614 | { |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 615 | iowrite32(int_mask, denali->flash_reg + INTR_EN0); |
| 616 | iowrite32(int_mask, denali->flash_reg + INTR_EN1); |
| 617 | iowrite32(int_mask, denali->flash_reg + INTR_EN2); |
| 618 | iowrite32(int_mask, denali->flash_reg + INTR_EN3); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 619 | } |
| 620 | |
| 621 | /* This function only returns when an interrupt that this driver cares about |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 622 | * occurs. This is to reduce the overhead of servicing interrupts |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 623 | */ |
| 624 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) |
| 625 | { |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 626 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 627 | } |
| 628 | |
| 629 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 630 | static inline void clear_interrupt(struct denali_nand_info *denali, |
| 631 | uint32_t irq_mask) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 632 | { |
| 633 | uint32_t intr_status_reg = 0; |
| 634 | |
| 635 | intr_status_reg = intr_status_addresses[denali->flash_bank]; |
| 636 | |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 637 | iowrite32(irq_mask, denali->flash_reg + intr_status_reg); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 638 | } |
| 639 | |
| 640 | static void clear_interrupts(struct denali_nand_info *denali) |
| 641 | { |
| 642 | uint32_t status = 0x0; |
| 643 | spin_lock_irq(&denali->irq_lock); |
| 644 | |
| 645 | status = read_interrupt_status(denali); |
| 646 | |
| 647 | #if DEBUG_DENALI |
| 648 | denali->irq_debug_array[denali->idx++] = 0x30000000 | status; |
| 649 | denali->idx %= 32; |
| 650 | #endif |
| 651 | |
| 652 | denali->irq_status = 0x0; |
| 653 | spin_unlock_irq(&denali->irq_lock); |
| 654 | } |
| 655 | |
| 656 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) |
| 657 | { |
| 658 | uint32_t intr_status_reg = 0; |
| 659 | |
| 660 | intr_status_reg = intr_status_addresses[denali->flash_bank]; |
| 661 | |
| 662 | return ioread32(denali->flash_reg + intr_status_reg); |
| 663 | } |
| 664 | |
| 665 | #if DEBUG_DENALI |
| 666 | static void print_irq_log(struct denali_nand_info *denali) |
| 667 | { |
| 668 | int i = 0; |
| 669 | |
Chuanxiao Dong | bf1806d | 2010-07-27 10:48:34 +0800 | [diff] [blame] | 670 | printk(KERN_INFO "ISR debug log index = %X\n", denali->idx); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 671 | for (i = 0; i < 32; i++) |
Chuanxiao Dong | bf1806d | 2010-07-27 10:48:34 +0800 | [diff] [blame] | 672 | printk(KERN_INFO "%08X: %08X\n", i, denali->irq_debug_array[i]); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 673 | } |
| 674 | #endif |
| 675 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 676 | /* This is the interrupt service routine. It handles all interrupts |
| 677 | * sent to this device. Note that on CE4100, this is a shared |
| 678 | * interrupt. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 679 | */ |
| 680 | static irqreturn_t denali_isr(int irq, void *dev_id) |
| 681 | { |
| 682 | struct denali_nand_info *denali = dev_id; |
| 683 | uint32_t irq_status = 0x0; |
| 684 | irqreturn_t result = IRQ_NONE; |
| 685 | |
| 686 | spin_lock(&denali->irq_lock); |
| 687 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 688 | /* check to see if a valid NAND chip has |
| 689 | * been selected. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 690 | */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 691 | if (is_flash_bank_valid(denali->flash_bank)) { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 692 | /* check to see if controller generated |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 693 | * the interrupt, since this is a shared interrupt */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 694 | irq_status = denali_irq_detected(denali); |
| 695 | if (irq_status != 0) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 696 | #if DEBUG_DENALI |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 697 | denali->irq_debug_array[denali->idx++] = |
| 698 | 0x10000000 | irq_status; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 699 | denali->idx %= 32; |
| 700 | |
Chuanxiao Dong | bf1806d | 2010-07-27 10:48:34 +0800 | [diff] [blame] | 701 | printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 702 | #endif |
| 703 | /* handle interrupt */ |
| 704 | /* first acknowledge it */ |
| 705 | clear_interrupt(denali, irq_status); |
| 706 | /* store the status in the device context for someone |
| 707 | to read */ |
| 708 | denali->irq_status |= irq_status; |
| 709 | /* notify anyone who cares that it happened */ |
| 710 | complete(&denali->complete); |
| 711 | /* tell the OS that we've handled this */ |
| 712 | result = IRQ_HANDLED; |
| 713 | } |
| 714 | } |
| 715 | spin_unlock(&denali->irq_lock); |
| 716 | return result; |
| 717 | } |
| 718 | #define BANK(x) ((x) << 24) |
| 719 | |
| 720 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) |
| 721 | { |
| 722 | unsigned long comp_res = 0; |
| 723 | uint32_t intr_status = 0; |
| 724 | bool retry = false; |
| 725 | unsigned long timeout = msecs_to_jiffies(1000); |
| 726 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 727 | do { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 728 | #if DEBUG_DENALI |
Chuanxiao Dong | bf1806d | 2010-07-27 10:48:34 +0800 | [diff] [blame] | 729 | printk(KERN_INFO "waiting for 0x%x\n", irq_mask); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 730 | #endif |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 731 | comp_res = |
| 732 | wait_for_completion_timeout(&denali->complete, timeout); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 733 | spin_lock_irq(&denali->irq_lock); |
| 734 | intr_status = denali->irq_status; |
| 735 | |
| 736 | #if DEBUG_DENALI |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 737 | denali->irq_debug_array[denali->idx++] = |
| 738 | 0x20000000 | (irq_mask << 16) | intr_status; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 739 | denali->idx %= 32; |
| 740 | #endif |
| 741 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 742 | if (intr_status & irq_mask) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 743 | denali->irq_status &= ~irq_mask; |
| 744 | spin_unlock_irq(&denali->irq_lock); |
| 745 | #if DEBUG_DENALI |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 746 | if (retry) |
| 747 | printk(KERN_INFO "status on retry = 0x%x\n", |
| 748 | intr_status); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 749 | #endif |
| 750 | /* our interrupt was detected */ |
| 751 | break; |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 752 | } else { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 753 | /* these are not the interrupts you are looking for - |
| 754 | * need to wait again */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 755 | spin_unlock_irq(&denali->irq_lock); |
| 756 | #if DEBUG_DENALI |
| 757 | print_irq_log(denali); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 758 | printk(KERN_INFO "received irq nobody cared:" |
| 759 | " irq_status = 0x%x, irq_mask = 0x%x," |
| 760 | " timeout = %ld\n", intr_status, |
| 761 | irq_mask, comp_res); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 762 | #endif |
| 763 | retry = true; |
| 764 | } |
| 765 | } while (comp_res != 0); |
| 766 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 767 | if (comp_res == 0) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 768 | /* timeout */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 769 | printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n", |
| 770 | intr_status, irq_mask); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 771 | |
| 772 | intr_status = 0; |
| 773 | } |
| 774 | return intr_status; |
| 775 | } |
| 776 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 777 | /* This helper function setups the registers for ECC and whether or not |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 778 | the spare area will be transfered. */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 779 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 780 | bool transfer_spare) |
| 781 | { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 782 | int ecc_en_flag = 0, transfer_spare_flag = 0; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 783 | |
| 784 | /* set ECC, transfer spare bits if needed */ |
| 785 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; |
| 786 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; |
| 787 | |
| 788 | /* Enable spare area/ECC per user's request. */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 789 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); |
| 790 | iowrite32(transfer_spare_flag, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 791 | denali->flash_reg + TRANSFER_SPARE_REG); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 792 | } |
| 793 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 794 | /* sends a pipeline command operation to the controller. See the Denali NAND |
| 795 | controller's user guide for more information (section 4.2.3.6). |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 796 | */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 797 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
| 798 | bool ecc_en, |
| 799 | bool transfer_spare, |
| 800 | int access_type, |
| 801 | int op) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 802 | { |
| 803 | int status = PASS; |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 804 | uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 805 | irq_mask = 0; |
| 806 | |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 807 | if (op == DENALI_READ) |
| 808 | irq_mask = INTR_STATUS0__LOAD_COMP; |
| 809 | else if (op == DENALI_WRITE) |
| 810 | irq_mask = 0; |
| 811 | else |
| 812 | BUG(); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 813 | |
| 814 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); |
| 815 | |
| 816 | #if DEBUG_DENALI |
| 817 | spin_lock_irq(&denali->irq_lock); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 818 | denali->irq_debug_array[denali->idx++] = |
| 819 | 0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) | |
| 820 | (access_type << 4); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 821 | denali->idx %= 32; |
| 822 | spin_unlock_irq(&denali->irq_lock); |
| 823 | #endif |
| 824 | |
| 825 | |
| 826 | /* clear interrupts */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 827 | clear_interrupts(denali); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 828 | |
| 829 | addr = BANK(denali->flash_bank) | denali->page; |
| 830 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 831 | if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 832 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 833 | iowrite32(cmd, denali->flash_mem); |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 834 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 835 | /* read spare area */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 836 | cmd = MODE_10 | addr; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 837 | index_addr(denali, (uint32_t)cmd, access_type); |
| 838 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 839 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 840 | iowrite32(cmd, denali->flash_mem); |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 841 | } else if (op == DENALI_READ) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 842 | /* setup page read request for access type */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 843 | cmd = MODE_10 | addr; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 844 | index_addr(denali, (uint32_t)cmd, access_type); |
| 845 | |
| 846 | /* page 33 of the NAND controller spec indicates we should not |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 847 | use the pipeline commands in Spare area only mode. So we |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 848 | don't. |
| 849 | */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 850 | if (access_type == SPARE_ACCESS) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 851 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 852 | iowrite32(cmd, denali->flash_mem); |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 853 | } else { |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 854 | index_addr(denali, (uint32_t)cmd, |
| 855 | 0x2000 | op | page_count); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 856 | |
| 857 | /* wait for command to be accepted |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 858 | * can always use status0 bit as the |
| 859 | * mask is identical for each |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 860 | * bank. */ |
| 861 | irq_status = wait_for_irq(denali, irq_mask); |
| 862 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 863 | if (irq_status == 0) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 864 | printk(KERN_ERR "cmd, page, addr on timeout " |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 865 | "(0x%x, 0x%x, 0x%x)\n", cmd, |
| 866 | denali->page, addr); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 867 | status = FAIL; |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 868 | } else { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 869 | cmd = MODE_01 | addr; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 870 | iowrite32(cmd, denali->flash_mem); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 871 | } |
| 872 | } |
| 873 | } |
| 874 | return status; |
| 875 | } |
| 876 | |
| 877 | /* helper function that simply writes a buffer to the flash */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 878 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
| 879 | const uint8_t *buf, |
| 880 | int len) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 881 | { |
| 882 | uint32_t i = 0, *buf32; |
| 883 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 884 | /* verify that the len is a multiple of 4. see comment in |
| 885 | * read_data_from_flash_mem() */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 886 | BUG_ON((len % 4) != 0); |
| 887 | |
| 888 | /* write the data to the flash memory */ |
| 889 | buf32 = (uint32_t *)buf; |
| 890 | for (i = 0; i < len / 4; i++) |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 891 | iowrite32(*buf32++, denali->flash_mem + 0x10); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 892 | return i*4; /* intent is to return the number of bytes read */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 893 | } |
| 894 | |
| 895 | /* helper function that simply reads a buffer from the flash */ |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 896 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
| 897 | uint8_t *buf, |
| 898 | int len) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 899 | { |
| 900 | uint32_t i = 0, *buf32; |
| 901 | |
| 902 | /* we assume that len will be a multiple of 4, if not |
| 903 | * it would be nice to know about it ASAP rather than |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 904 | * have random failures... |
| 905 | * This assumption is based on the fact that this |
| 906 | * function is designed to be used to read flash pages, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 907 | * which are typically multiples of 4... |
| 908 | */ |
| 909 | |
| 910 | BUG_ON((len % 4) != 0); |
| 911 | |
| 912 | /* transfer the data from the flash */ |
| 913 | buf32 = (uint32_t *)buf; |
| 914 | for (i = 0; i < len / 4; i++) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 915 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 916 | return i*4; /* intent is to return the number of bytes read */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 917 | } |
| 918 | |
| 919 | /* writes OOB data to the device */ |
| 920 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) |
| 921 | { |
| 922 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 923 | uint32_t irq_status = 0; |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 924 | uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 925 | INTR_STATUS0__PROGRAM_FAIL; |
| 926 | int status = 0; |
| 927 | |
| 928 | denali->page = page; |
| 929 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 930 | if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 931 | DENALI_WRITE) == PASS) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 932 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
| 933 | |
| 934 | #if DEBUG_DENALI |
| 935 | spin_lock_irq(&denali->irq_lock); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 936 | denali->irq_debug_array[denali->idx++] = |
| 937 | 0x80000000 | mtd->oobsize; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 938 | denali->idx %= 32; |
| 939 | spin_unlock_irq(&denali->irq_lock); |
| 940 | #endif |
| 941 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 942 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 943 | /* wait for operation to complete */ |
| 944 | irq_status = wait_for_irq(denali, irq_mask); |
| 945 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 946 | if (irq_status == 0) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 947 | printk(KERN_ERR "OOB write failed\n"); |
| 948 | status = -EIO; |
| 949 | } |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 950 | } else { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 951 | printk(KERN_ERR "unable to send pipeline command\n"); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 952 | status = -EIO; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 953 | } |
| 954 | return status; |
| 955 | } |
| 956 | |
| 957 | /* reads OOB data from the device */ |
| 958 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) |
| 959 | { |
| 960 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 961 | uint32_t irq_mask = INTR_STATUS0__LOAD_COMP, |
| 962 | irq_status = 0, addr = 0x0, cmd = 0x0; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 963 | |
| 964 | denali->page = page; |
| 965 | |
| 966 | #if DEBUG_DENALI |
Chuanxiao Dong | bf1806d | 2010-07-27 10:48:34 +0800 | [diff] [blame] | 967 | printk(KERN_INFO "read_oob %d\n", page); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 968 | #endif |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 969 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 970 | DENALI_READ) == PASS) { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 971 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 972 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 973 | /* wait for command to be accepted |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 974 | * can always use status0 bit as the mask is identical for each |
| 975 | * bank. */ |
| 976 | irq_status = wait_for_irq(denali, irq_mask); |
| 977 | |
| 978 | if (irq_status == 0) |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 979 | printk(KERN_ERR "page on OOB timeout %d\n", |
| 980 | denali->page); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 981 | |
| 982 | /* We set the device back to MAIN_ACCESS here as I observed |
| 983 | * instability with the controller if you do a block erase |
| 984 | * and the last transaction was a SPARE_ACCESS. Block erase |
| 985 | * is reliable (according to the MTD test infrastructure) |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 986 | * if you are in MAIN_ACCESS. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 987 | */ |
| 988 | addr = BANK(denali->flash_bank) | denali->page; |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 989 | cmd = MODE_10 | addr; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 990 | index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); |
| 991 | |
| 992 | #if DEBUG_DENALI |
| 993 | spin_lock_irq(&denali->irq_lock); |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 994 | denali->irq_debug_array[denali->idx++] = |
| 995 | 0x60000000 | mtd->oobsize; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 996 | denali->idx %= 32; |
| 997 | spin_unlock_irq(&denali->irq_lock); |
| 998 | #endif |
| 999 | } |
| 1000 | } |
| 1001 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1002 | /* this function examines buffers to see if they contain data that |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1003 | * indicate that the buffer is part of an erased region of flash. |
| 1004 | */ |
| 1005 | bool is_erased(uint8_t *buf, int len) |
| 1006 | { |
| 1007 | int i = 0; |
| 1008 | for (i = 0; i < len; i++) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1009 | if (buf[i] != 0xFF) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1010 | return false; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1011 | return true; |
| 1012 | } |
| 1013 | #define ECC_SECTOR_SIZE 512 |
| 1014 | |
| 1015 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) |
| 1016 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) |
| 1017 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) |
| 1018 | #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO)) |
| 1019 | #define ECC_ERR_DEVICE(x) ((x) & ERR_CORRECTION_INFO__DEVICE_NR >> 8) |
| 1020 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) |
| 1021 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1022 | static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1023 | uint8_t *oobbuf, uint32_t irq_status) |
| 1024 | { |
| 1025 | bool check_erased_page = false; |
| 1026 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1027 | if (irq_status & INTR_STATUS0__ECC_ERR) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1028 | /* read the ECC errors. we'll ignore them for now */ |
| 1029 | uint32_t err_address = 0, err_correction_info = 0; |
| 1030 | uint32_t err_byte = 0, err_sector = 0, err_device = 0; |
| 1031 | uint32_t err_correction_value = 0; |
| 1032 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1033 | do { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1034 | err_address = ioread32(denali->flash_reg + |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1035 | ECC_ERROR_ADDRESS); |
| 1036 | err_sector = ECC_SECTOR(err_address); |
| 1037 | err_byte = ECC_BYTE(err_address); |
| 1038 | |
| 1039 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1040 | err_correction_info = ioread32(denali->flash_reg + |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1041 | ERR_CORRECTION_INFO); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1042 | err_correction_value = |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1043 | ECC_CORRECTION_VALUE(err_correction_info); |
| 1044 | err_device = ECC_ERR_DEVICE(err_correction_info); |
| 1045 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1046 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1047 | /* offset in our buffer is computed as: |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1048 | sector number * sector size + offset in |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1049 | sector |
| 1050 | */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1051 | int offset = err_sector * ECC_SECTOR_SIZE + |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1052 | err_byte; |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1053 | if (offset < denali->mtd.writesize) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1054 | /* correct the ECC error */ |
| 1055 | buf[offset] ^= err_correction_value; |
| 1056 | denali->mtd.ecc_stats.corrected++; |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1057 | } else { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1058 | /* bummer, couldn't correct the error */ |
| 1059 | printk(KERN_ERR "ECC offset invalid\n"); |
| 1060 | denali->mtd.ecc_stats.failed++; |
| 1061 | } |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1062 | } else { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1063 | /* if the error is not correctable, need to |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1064 | * look at the page to see if it is an erased |
| 1065 | * page. if so, then it's not a real ECC error |
| 1066 | * */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1067 | check_erased_page = true; |
| 1068 | } |
| 1069 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1070 | #if DEBUG_DENALI |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1071 | printk(KERN_INFO "Detected ECC error in page %d:" |
| 1072 | " err_addr = 0x%08x, info to fix is" |
| 1073 | " 0x%08x\n", denali->page, err_address, |
| 1074 | err_correction_info); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1075 | #endif |
| 1076 | } while (!ECC_LAST_ERR(err_correction_info)); |
| 1077 | } |
| 1078 | return check_erased_page; |
| 1079 | } |
| 1080 | |
| 1081 | /* programs the controller to either enable/disable DMA transfers */ |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1082 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1083 | { |
| 1084 | uint32_t reg_val = 0x0; |
| 1085 | |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 1086 | if (en) |
| 1087 | reg_val = DMA_ENABLE__FLAG; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1088 | |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 1089 | iowrite32(reg_val, denali->flash_reg + DMA_ENABLE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1090 | ioread32(denali->flash_reg + DMA_ENABLE); |
| 1091 | } |
| 1092 | |
| 1093 | /* setups the HW to perform the data DMA */ |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1094 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1095 | { |
| 1096 | uint32_t mode = 0x0; |
| 1097 | const int page_count = 1; |
| 1098 | dma_addr_t addr = denali->buf.dma_buf; |
| 1099 | |
| 1100 | mode = MODE_10 | BANK(denali->flash_bank); |
| 1101 | |
| 1102 | /* DMA is a four step process */ |
| 1103 | |
| 1104 | /* 1. setup transfer type and # of pages */ |
| 1105 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); |
| 1106 | |
| 1107 | /* 2. set memory high address bits 23:8 */ |
| 1108 | index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200); |
| 1109 | |
| 1110 | /* 3. set memory low address bits 23:8 */ |
| 1111 | index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300); |
| 1112 | |
| 1113 | /* 4. interrupt when complete, burst len = 64 bytes*/ |
| 1114 | index_addr(denali, mode | 0x14000, 0x2400); |
| 1115 | } |
| 1116 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1117 | /* writes a page. user specifies type, and this function handles the |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1118 | configuration details. */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1119 | static void write_page(struct mtd_info *mtd, struct nand_chip *chip, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1120 | const uint8_t *buf, bool raw_xfer) |
| 1121 | { |
| 1122 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1123 | struct pci_dev *pci_dev = denali->dev; |
| 1124 | |
| 1125 | dma_addr_t addr = denali->buf.dma_buf; |
| 1126 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
| 1127 | |
| 1128 | uint32_t irq_status = 0; |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1129 | uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1130 | INTR_STATUS0__PROGRAM_FAIL; |
| 1131 | |
| 1132 | /* if it is a raw xfer, we want to disable ecc, and send |
| 1133 | * the spare area. |
| 1134 | * !raw_xfer - enable ecc |
| 1135 | * raw_xfer - transfer spare |
| 1136 | */ |
| 1137 | setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); |
| 1138 | |
| 1139 | /* copy buffer into DMA buffer */ |
| 1140 | memcpy(denali->buf.buf, buf, mtd->writesize); |
| 1141 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1142 | if (raw_xfer) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1143 | /* transfer the data to the spare area */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1144 | memcpy(denali->buf.buf + mtd->writesize, |
| 1145 | chip->oob_poi, |
| 1146 | mtd->oobsize); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1147 | } |
| 1148 | |
| 1149 | pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE); |
| 1150 | |
| 1151 | clear_interrupts(denali); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1152 | denali_enable_dma(denali, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1153 | |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1154 | denali_setup_dma(denali, DENALI_WRITE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1155 | |
| 1156 | /* wait for operation to complete */ |
| 1157 | irq_status = wait_for_irq(denali, irq_mask); |
| 1158 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1159 | if (irq_status == 0) { |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1160 | printk(KERN_ERR "timeout on write_page" |
| 1161 | " (type = %d)\n", raw_xfer); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1162 | denali->status = |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1163 | (irq_status & INTR_STATUS0__PROGRAM_FAIL) ? |
| 1164 | NAND_STATUS_FAIL : PASS; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1165 | } |
| 1166 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1167 | denali_enable_dma(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1168 | pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE); |
| 1169 | } |
| 1170 | |
| 1171 | /* NAND core entry points */ |
| 1172 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1173 | /* this is the callback that the NAND core calls to write a page. Since |
| 1174 | writing a page with ECC or without is similar, all the work is done |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1175 | by write_page above. */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1176 | static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1177 | const uint8_t *buf) |
| 1178 | { |
| 1179 | /* for regular page writes, we let HW handle all the ECC |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1180 | * data written to the device. */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1181 | write_page(mtd, chip, buf, false); |
| 1182 | } |
| 1183 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1184 | /* This is the callback that the NAND core calls to write a page without ECC. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1185 | raw access is similiar to ECC page writes, so all the work is done in the |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1186 | write_page() function above. |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1187 | */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1188 | static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1189 | const uint8_t *buf) |
| 1190 | { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1191 | /* for raw page writes, we want to disable ECC and simply write |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1192 | whatever data is in the buffer. */ |
| 1193 | write_page(mtd, chip, buf, true); |
| 1194 | } |
| 1195 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1196 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1197 | int page) |
| 1198 | { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1199 | return write_oob_data(mtd, chip->oob_poi, page); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1200 | } |
| 1201 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1202 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1203 | int page, int sndcmd) |
| 1204 | { |
| 1205 | read_oob_data(mtd, chip->oob_poi, page); |
| 1206 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1207 | return 0; /* notify NAND core to send command to |
| 1208 | NAND device. */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1209 | } |
| 1210 | |
| 1211 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, |
| 1212 | uint8_t *buf, int page) |
| 1213 | { |
| 1214 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1215 | struct pci_dev *pci_dev = denali->dev; |
| 1216 | |
| 1217 | dma_addr_t addr = denali->buf.dma_buf; |
| 1218 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
| 1219 | |
| 1220 | uint32_t irq_status = 0; |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1221 | uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1222 | INTR_STATUS0__ECC_ERR; |
| 1223 | bool check_erased_page = false; |
| 1224 | |
| 1225 | setup_ecc_for_xfer(denali, true, false); |
| 1226 | |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1227 | denali_enable_dma(denali, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1228 | pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE); |
| 1229 | |
| 1230 | clear_interrupts(denali); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1231 | denali_setup_dma(denali, DENALI_READ); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1232 | |
| 1233 | /* wait for operation to complete */ |
| 1234 | irq_status = wait_for_irq(denali, irq_mask); |
| 1235 | |
| 1236 | pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE); |
| 1237 | |
| 1238 | memcpy(buf, denali->buf.buf, mtd->writesize); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1239 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1240 | check_erased_page = handle_ecc(denali, buf, chip->oob_poi, irq_status); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1241 | denali_enable_dma(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1242 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1243 | if (check_erased_page) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1244 | read_oob_data(&denali->mtd, chip->oob_poi, denali->page); |
| 1245 | |
| 1246 | /* check ECC failures that may have occurred on erased pages */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1247 | if (check_erased_page) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1248 | if (!is_erased(buf, denali->mtd.writesize)) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1249 | denali->mtd.ecc_stats.failed++; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1250 | if (!is_erased(buf, denali->mtd.oobsize)) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1251 | denali->mtd.ecc_stats.failed++; |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1252 | } |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1253 | } |
| 1254 | return 0; |
| 1255 | } |
| 1256 | |
| 1257 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
| 1258 | uint8_t *buf, int page) |
| 1259 | { |
| 1260 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1261 | struct pci_dev *pci_dev = denali->dev; |
| 1262 | |
| 1263 | dma_addr_t addr = denali->buf.dma_buf; |
| 1264 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
| 1265 | |
| 1266 | uint32_t irq_status = 0; |
| 1267 | uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP; |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1268 | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1269 | setup_ecc_for_xfer(denali, false, true); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1270 | denali_enable_dma(denali, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1271 | |
| 1272 | pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE); |
| 1273 | |
| 1274 | clear_interrupts(denali); |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1275 | denali_setup_dma(denali, DENALI_READ); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1276 | |
| 1277 | /* wait for operation to complete */ |
| 1278 | irq_status = wait_for_irq(denali, irq_mask); |
| 1279 | |
| 1280 | pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE); |
| 1281 | |
David Woodhouse | aadff49 | 2010-05-13 16:12:43 +0100 | [diff] [blame] | 1282 | denali_enable_dma(denali, false); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1283 | |
| 1284 | memcpy(buf, denali->buf.buf, mtd->writesize); |
| 1285 | memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); |
| 1286 | |
| 1287 | return 0; |
| 1288 | } |
| 1289 | |
| 1290 | static uint8_t denali_read_byte(struct mtd_info *mtd) |
| 1291 | { |
| 1292 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1293 | uint8_t result = 0xff; |
| 1294 | |
| 1295 | if (denali->buf.head < denali->buf.tail) |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1296 | result = denali->buf.buf[denali->buf.head++]; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1297 | |
| 1298 | #if DEBUG_DENALI |
Chuanxiao Dong | bf1806d | 2010-07-27 10:48:34 +0800 | [diff] [blame] | 1299 | printk(KERN_INFO "read byte -> 0x%02x\n", result); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1300 | #endif |
| 1301 | return result; |
| 1302 | } |
| 1303 | |
| 1304 | static void denali_select_chip(struct mtd_info *mtd, int chip) |
| 1305 | { |
| 1306 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1307 | #if DEBUG_DENALI |
Chuanxiao Dong | bf1806d | 2010-07-27 10:48:34 +0800 | [diff] [blame] | 1308 | printk(KERN_INFO "denali select chip %d\n", chip); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1309 | #endif |
| 1310 | spin_lock_irq(&denali->irq_lock); |
| 1311 | denali->flash_bank = chip; |
| 1312 | spin_unlock_irq(&denali->irq_lock); |
| 1313 | } |
| 1314 | |
| 1315 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) |
| 1316 | { |
| 1317 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1318 | int status = denali->status; |
| 1319 | denali->status = 0; |
| 1320 | |
| 1321 | #if DEBUG_DENALI |
Chuanxiao Dong | bf1806d | 2010-07-27 10:48:34 +0800 | [diff] [blame] | 1322 | printk(KERN_INFO "waitfunc %d\n", status); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1323 | #endif |
| 1324 | return status; |
| 1325 | } |
| 1326 | |
| 1327 | static void denali_erase(struct mtd_info *mtd, int page) |
| 1328 | { |
| 1329 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
| 1330 | |
| 1331 | uint32_t cmd = 0x0, irq_status = 0; |
| 1332 | |
| 1333 | #if DEBUG_DENALI |
Chuanxiao Dong | bf1806d | 2010-07-27 10:48:34 +0800 | [diff] [blame] | 1334 | printk(KERN_INFO "erase page: %d\n", page); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1335 | #endif |
| 1336 | /* clear interrupts */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1337 | clear_interrupts(denali); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1338 | |
| 1339 | /* setup page read request for access type */ |
| 1340 | cmd = MODE_10 | BANK(denali->flash_bank) | page; |
| 1341 | index_addr(denali, (uint32_t)cmd, 0x1); |
| 1342 | |
| 1343 | /* wait for erase to complete or failure to occur */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1344 | irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP | |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1345 | INTR_STATUS0__ERASE_FAIL); |
| 1346 | |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1347 | denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ? |
| 1348 | NAND_STATUS_FAIL : PASS; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1349 | } |
| 1350 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1351 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1352 | int page) |
| 1353 | { |
| 1354 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 1355 | uint32_t addr, id; |
| 1356 | int i; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1357 | |
| 1358 | #if DEBUG_DENALI |
Chuanxiao Dong | bf1806d | 2010-07-27 10:48:34 +0800 | [diff] [blame] | 1359 | printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1360 | #endif |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1361 | switch (cmd) { |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 1362 | case NAND_CMD_PAGEPROG: |
| 1363 | break; |
| 1364 | case NAND_CMD_STATUS: |
| 1365 | read_status(denali); |
| 1366 | break; |
| 1367 | case NAND_CMD_READID: |
| 1368 | reset_buf(denali); |
Chuanxiao Dong | ef41e1b | 2010-08-06 00:48:49 +0800 | [diff] [blame] | 1369 | /*sometimes ManufactureId read from register is not right |
| 1370 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips |
| 1371 | * So here we send READID cmd to NAND insteand |
| 1372 | * */ |
| 1373 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); |
| 1374 | index_addr(denali, (uint32_t)addr | 0, 0x90); |
| 1375 | index_addr(denali, (uint32_t)addr | 1, 0); |
| 1376 | for (i = 0; i < 5; i++) { |
| 1377 | index_addr_read_data(denali, |
| 1378 | (uint32_t)addr | 2, |
| 1379 | &id); |
| 1380 | write_byte_to_buf(denali, id); |
Chuanxiao Dong | a99d179 | 2010-07-27 11:32:21 +0800 | [diff] [blame] | 1381 | } |
| 1382 | break; |
| 1383 | case NAND_CMD_READ0: |
| 1384 | case NAND_CMD_SEQIN: |
| 1385 | denali->page = page; |
| 1386 | break; |
| 1387 | case NAND_CMD_RESET: |
| 1388 | reset_bank(denali); |
| 1389 | break; |
| 1390 | case NAND_CMD_READOOB: |
| 1391 | /* TODO: Read OOB data */ |
| 1392 | break; |
| 1393 | default: |
| 1394 | printk(KERN_ERR ": unsupported command" |
| 1395 | " received 0x%x\n", cmd); |
| 1396 | break; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1397 | } |
| 1398 | } |
| 1399 | |
| 1400 | /* stubs for ECC functions not used by the NAND core */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1401 | static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1402 | uint8_t *ecc_code) |
| 1403 | { |
| 1404 | printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n"); |
| 1405 | BUG(); |
| 1406 | return -EIO; |
| 1407 | } |
| 1408 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1409 | static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1410 | uint8_t *read_ecc, uint8_t *calc_ecc) |
| 1411 | { |
| 1412 | printk(KERN_ERR "denali_ecc_correct called unexpectedly\n"); |
| 1413 | BUG(); |
| 1414 | return -EIO; |
| 1415 | } |
| 1416 | |
| 1417 | static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) |
| 1418 | { |
| 1419 | printk(KERN_ERR "denali_ecc_hwctl called unexpectedly\n"); |
| 1420 | BUG(); |
| 1421 | } |
| 1422 | /* end NAND core entry points */ |
| 1423 | |
| 1424 | /* Initialization code to bring the device up to a known good state */ |
| 1425 | static void denali_hw_init(struct denali_nand_info *denali) |
| 1426 | { |
Chuanxiao Dong | db9a321 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1427 | /* tell driver how many bit controller will skip before |
| 1428 | * writing ECC code in OOB, this register may be already |
| 1429 | * set by firmware. So we read this value out. |
| 1430 | * if this value is 0, just let it be. |
| 1431 | * */ |
| 1432 | denali->bbtskipbytes = ioread32(denali->flash_reg + |
| 1433 | SPARE_AREA_SKIP_BYTES); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1434 | denali_irq_init(denali); |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 1435 | denali_nand_reset(denali); |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 1436 | iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); |
| 1437 | iowrite32(CHIP_EN_DONT_CARE__FLAG, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1438 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1439 | |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 1440 | iowrite32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES); |
| 1441 | iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1442 | |
| 1443 | /* Should set value for these registers when init */ |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 1444 | iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); |
| 1445 | iowrite32(1, denali->flash_reg + ECC_ENABLE); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1446 | } |
| 1447 | |
Chuanxiao Dong | db9a321 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1448 | /* Althogh controller spec said SLC ECC is forceb to be 4bit, |
| 1449 | * but denali controller in MRST only support 15bit and 8bit ECC |
| 1450 | * correction |
| 1451 | * */ |
| 1452 | #define ECC_8BITS 14 |
| 1453 | static struct nand_ecclayout nand_8bit_oob = { |
| 1454 | .eccbytes = 14, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1455 | }; |
| 1456 | |
Chuanxiao Dong | db9a321 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1457 | #define ECC_15BITS 26 |
| 1458 | static struct nand_ecclayout nand_15bit_oob = { |
| 1459 | .eccbytes = 26, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1460 | }; |
| 1461 | |
| 1462 | static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; |
| 1463 | static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; |
| 1464 | |
| 1465 | static struct nand_bbt_descr bbt_main_descr = { |
| 1466 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
| 1467 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, |
| 1468 | .offs = 8, |
| 1469 | .len = 4, |
| 1470 | .veroffs = 12, |
| 1471 | .maxblocks = 4, |
| 1472 | .pattern = bbt_pattern, |
| 1473 | }; |
| 1474 | |
| 1475 | static struct nand_bbt_descr bbt_mirror_descr = { |
| 1476 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
| 1477 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, |
| 1478 | .offs = 8, |
| 1479 | .len = 4, |
| 1480 | .veroffs = 12, |
| 1481 | .maxblocks = 4, |
| 1482 | .pattern = mirror_pattern, |
| 1483 | }; |
| 1484 | |
Uwe Kleine-König | 421f91d | 2010-06-11 12:17:00 +0200 | [diff] [blame] | 1485 | /* initialize driver data structures */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1486 | void denali_drv_init(struct denali_nand_info *denali) |
| 1487 | { |
| 1488 | denali->idx = 0; |
| 1489 | |
| 1490 | /* setup interrupt handler */ |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1491 | /* the completion object will be used to notify |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1492 | * the callee that the interrupt is done */ |
| 1493 | init_completion(&denali->complete); |
| 1494 | |
| 1495 | /* the spinlock will be used to synchronize the ISR |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1496 | * with any element that might be access shared |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1497 | * data (interrupt status) */ |
| 1498 | spin_lock_init(&denali->irq_lock); |
| 1499 | |
| 1500 | /* indicate that MTD has not selected a valid bank yet */ |
| 1501 | denali->flash_bank = CHIP_SELECT_INVALID; |
| 1502 | |
| 1503 | /* initialize our irq_status variable to indicate no interrupts */ |
| 1504 | denali->irq_status = 0; |
| 1505 | } |
| 1506 | |
| 1507 | /* driver entry point */ |
| 1508 | static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) |
| 1509 | { |
| 1510 | int ret = -ENODEV; |
| 1511 | resource_size_t csr_base, mem_base; |
| 1512 | unsigned long csr_len, mem_len; |
| 1513 | struct denali_nand_info *denali; |
| 1514 | |
| 1515 | nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", |
| 1516 | __FILE__, __LINE__, __func__); |
| 1517 | |
| 1518 | denali = kzalloc(sizeof(*denali), GFP_KERNEL); |
| 1519 | if (!denali) |
| 1520 | return -ENOMEM; |
| 1521 | |
| 1522 | ret = pci_enable_device(dev); |
| 1523 | if (ret) { |
| 1524 | printk(KERN_ERR "Spectra: pci_enable_device failed.\n"); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1525 | goto failed_alloc_memery; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1526 | } |
| 1527 | |
| 1528 | if (id->driver_data == INTEL_CE4100) { |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1529 | /* Due to a silicon limitation, we can only support |
| 1530 | * ONFI timing mode 1 and below. |
| 1531 | */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1532 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1533 | printk(KERN_ERR "Intel CE4100 only supports" |
| 1534 | " ONFI timing mode 1 or below\n"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1535 | ret = -EINVAL; |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1536 | goto failed_enable_dev; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1537 | } |
| 1538 | denali->platform = INTEL_CE4100; |
| 1539 | mem_base = pci_resource_start(dev, 0); |
| 1540 | mem_len = pci_resource_len(dev, 1); |
| 1541 | csr_base = pci_resource_start(dev, 1); |
| 1542 | csr_len = pci_resource_len(dev, 1); |
| 1543 | } else { |
| 1544 | denali->platform = INTEL_MRST; |
| 1545 | csr_base = pci_resource_start(dev, 0); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1546 | csr_len = pci_resource_len(dev, 0); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1547 | mem_base = pci_resource_start(dev, 1); |
| 1548 | mem_len = pci_resource_len(dev, 1); |
| 1549 | if (!mem_len) { |
| 1550 | mem_base = csr_base + csr_len; |
| 1551 | mem_len = csr_len; |
| 1552 | nand_dbg_print(NAND_DBG_WARN, |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1553 | "Spectra: No second" |
| 1554 | " BAR for PCI device;" |
| 1555 | " assuming %08Lx\n", |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1556 | (uint64_t)csr_base); |
| 1557 | } |
| 1558 | } |
| 1559 | |
| 1560 | /* Is 32-bit DMA supported? */ |
| 1561 | ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32)); |
| 1562 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1563 | if (ret) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1564 | printk(KERN_ERR "Spectra: no usable DMA configuration\n"); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1565 | goto failed_enable_dev; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1566 | } |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1567 | denali->buf.dma_buf = |
| 1568 | pci_map_single(dev, denali->buf.buf, |
| 1569 | DENALI_BUF_SIZE, |
| 1570 | PCI_DMA_BIDIRECTIONAL); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1571 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1572 | if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1573 | printk(KERN_ERR "Spectra: failed to map DMA buffer\n"); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1574 | goto failed_enable_dev; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1575 | } |
| 1576 | |
| 1577 | pci_set_master(dev); |
| 1578 | denali->dev = dev; |
| 1579 | |
| 1580 | ret = pci_request_regions(dev, DENALI_NAND_NAME); |
| 1581 | if (ret) { |
| 1582 | printk(KERN_ERR "Spectra: Unable to request memory regions\n"); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1583 | goto failed_dma_map; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1584 | } |
| 1585 | |
| 1586 | denali->flash_reg = ioremap_nocache(csr_base, csr_len); |
| 1587 | if (!denali->flash_reg) { |
| 1588 | printk(KERN_ERR "Spectra: Unable to remap memory region\n"); |
| 1589 | ret = -ENOMEM; |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1590 | goto failed_req_regions; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1591 | } |
| 1592 | nand_dbg_print(NAND_DBG_DEBUG, "Spectra: CSR 0x%08Lx -> 0x%p (0x%lx)\n", |
| 1593 | (uint64_t)csr_base, denali->flash_reg, csr_len); |
| 1594 | |
| 1595 | denali->flash_mem = ioremap_nocache(mem_base, mem_len); |
| 1596 | if (!denali->flash_mem) { |
| 1597 | printk(KERN_ERR "Spectra: ioremap_nocache failed!"); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1598 | ret = -ENOMEM; |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1599 | goto failed_remap_reg; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1600 | } |
| 1601 | |
| 1602 | nand_dbg_print(NAND_DBG_WARN, |
| 1603 | "Spectra: Remapped flash base address: " |
| 1604 | "0x%p, len: %ld\n", |
| 1605 | denali->flash_mem, csr_len); |
| 1606 | |
| 1607 | denali_hw_init(denali); |
| 1608 | denali_drv_init(denali); |
| 1609 | |
| 1610 | nand_dbg_print(NAND_DBG_DEBUG, "Spectra: IRQ %d\n", dev->irq); |
| 1611 | if (request_irq(dev->irq, denali_isr, IRQF_SHARED, |
| 1612 | DENALI_NAND_NAME, denali)) { |
| 1613 | printk(KERN_ERR "Spectra: Unable to allocate IRQ\n"); |
| 1614 | ret = -ENODEV; |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1615 | goto failed_remap_mem; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1616 | } |
| 1617 | |
| 1618 | /* now that our ISR is registered, we can enable interrupts */ |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 1619 | denali_set_intr_modes(denali, true); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1620 | |
| 1621 | pci_set_drvdata(dev, denali); |
| 1622 | |
Chuanxiao Dong | eda936e | 2010-07-27 14:17:37 +0800 | [diff] [blame] | 1623 | denali_nand_timing_set(denali); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1624 | |
| 1625 | nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:" |
| 1626 | "acc_clks: %d, re_2_we: %d, we_2_re: %d," |
| 1627 | "addr_2_data: %d, rdwr_en_lo_cnt: %d, " |
| 1628 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
| 1629 | ioread32(denali->flash_reg + ACC_CLKS), |
| 1630 | ioread32(denali->flash_reg + RE_2_WE), |
| 1631 | ioread32(denali->flash_reg + WE_2_RE), |
| 1632 | ioread32(denali->flash_reg + ADDR_2_DATA), |
| 1633 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), |
| 1634 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), |
| 1635 | ioread32(denali->flash_reg + CS_SETUP_CNT)); |
| 1636 | |
| 1637 | denali->mtd.name = "Denali NAND"; |
| 1638 | denali->mtd.owner = THIS_MODULE; |
| 1639 | denali->mtd.priv = &denali->nand; |
| 1640 | |
| 1641 | /* register the driver with the NAND core subsystem */ |
| 1642 | denali->nand.select_chip = denali_select_chip; |
| 1643 | denali->nand.cmdfunc = denali_cmdfunc; |
| 1644 | denali->nand.read_byte = denali_read_byte; |
| 1645 | denali->nand.waitfunc = denali_waitfunc; |
| 1646 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1647 | /* scan for NAND devices attached to the controller |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1648 | * this is the first stage in a two step process to register |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1649 | * with the nand subsystem */ |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1650 | if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1651 | ret = -ENXIO; |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1652 | goto failed_req_irq; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1653 | } |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1654 | |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 1655 | /* MTD supported page sizes vary by kernel. We validate our |
| 1656 | * kernel supports the device here. |
| 1657 | */ |
| 1658 | if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) { |
| 1659 | ret = -ENODEV; |
| 1660 | printk(KERN_ERR "Spectra: device size not supported by this " |
| 1661 | "version of MTD."); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1662 | goto failed_req_irq; |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 1663 | } |
| 1664 | |
Chuanxiao Dong | 08b9ab9 | 2010-08-06 18:19:09 +0800 | [diff] [blame] | 1665 | /* support for multi nand |
| 1666 | * MTD known nothing about multi nand, |
| 1667 | * so we should tell it the real pagesize |
| 1668 | * and anything necessery |
| 1669 | */ |
| 1670 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); |
| 1671 | denali->nand.chipsize <<= (denali->devnum - 1); |
| 1672 | denali->nand.page_shift += (denali->devnum - 1); |
| 1673 | denali->nand.pagemask = (denali->nand.chipsize >> |
| 1674 | denali->nand.page_shift) - 1; |
| 1675 | denali->nand.bbt_erase_shift += (denali->devnum - 1); |
| 1676 | denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; |
| 1677 | denali->nand.chip_shift += (denali->devnum - 1); |
| 1678 | denali->mtd.writesize <<= (denali->devnum - 1); |
| 1679 | denali->mtd.oobsize <<= (denali->devnum - 1); |
| 1680 | denali->mtd.erasesize <<= (denali->devnum - 1); |
| 1681 | denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; |
| 1682 | denali->bbtskipbytes *= denali->devnum; |
| 1683 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1684 | /* second stage of the NAND scan |
| 1685 | * this stage requires information regarding ECC and |
| 1686 | * bad block management. */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1687 | |
| 1688 | /* Bad block management */ |
| 1689 | denali->nand.bbt_td = &bbt_main_descr; |
| 1690 | denali->nand.bbt_md = &bbt_mirror_descr; |
| 1691 | |
| 1692 | /* skip the scan for now until we have OOB read and write support */ |
| 1693 | denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN; |
| 1694 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
| 1695 | |
Chuanxiao Dong | db9a321 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1696 | /* Denali Controller only support 15bit and 8bit ECC in MRST, |
| 1697 | * so just let controller do 15bit ECC for MLC and 8bit ECC for |
| 1698 | * SLC if possible. |
| 1699 | * */ |
| 1700 | if (denali->nand.cellinfo & 0xc && |
| 1701 | (denali->mtd.oobsize > (denali->bbtskipbytes + |
| 1702 | ECC_15BITS * (denali->mtd.writesize / |
| 1703 | ECC_SECTOR_SIZE)))) { |
| 1704 | /* if MLC OOB size is large enough, use 15bit ECC*/ |
| 1705 | denali->nand.ecc.layout = &nand_15bit_oob; |
| 1706 | denali->nand.ecc.bytes = ECC_15BITS; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 1707 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
Chuanxiao Dong | db9a321 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1708 | } else if (denali->mtd.oobsize < (denali->bbtskipbytes + |
| 1709 | ECC_8BITS * (denali->mtd.writesize / |
| 1710 | ECC_SECTOR_SIZE))) { |
| 1711 | printk(KERN_ERR "Your NAND chip OOB is not large enough to" |
| 1712 | " contain 8bit ECC correction codes"); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1713 | goto failed_req_irq; |
Chuanxiao Dong | db9a321 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1714 | } else { |
| 1715 | denali->nand.ecc.layout = &nand_8bit_oob; |
| 1716 | denali->nand.ecc.bytes = ECC_8BITS; |
Chuanxiao Dong | 24c3fa3 | 2010-08-09 23:59:23 +0800 | [diff] [blame^] | 1717 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1718 | } |
| 1719 | |
Chuanxiao Dong | 08b9ab9 | 2010-08-06 18:19:09 +0800 | [diff] [blame] | 1720 | denali->nand.ecc.bytes *= denali->devnum; |
Chuanxiao Dong | db9a321 | 2010-08-06 18:02:03 +0800 | [diff] [blame] | 1721 | denali->nand.ecc.layout->eccbytes *= |
| 1722 | denali->mtd.writesize / ECC_SECTOR_SIZE; |
| 1723 | denali->nand.ecc.layout->oobfree[0].offset = |
| 1724 | denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes; |
| 1725 | denali->nand.ecc.layout->oobfree[0].length = |
| 1726 | denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - |
| 1727 | denali->bbtskipbytes; |
| 1728 | |
Chuanxiao.Dong | 6640652 | 2010-08-06 18:48:21 +0800 | [diff] [blame] | 1729 | /* Let driver know the total blocks number and |
| 1730 | * how many blocks contained by each nand chip. |
| 1731 | * blksperchip will help driver to know how many |
| 1732 | * blocks is taken by FW. |
| 1733 | * */ |
| 1734 | denali->totalblks = denali->mtd.size >> |
| 1735 | denali->nand.phys_erase_shift; |
| 1736 | denali->blksperchip = denali->totalblks / denali->nand.numchips; |
| 1737 | |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1738 | /* These functions are required by the NAND core framework, otherwise, |
| 1739 | * the NAND core will assert. However, we don't need them, so we'll stub |
| 1740 | * them out. */ |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1741 | denali->nand.ecc.calculate = denali_ecc_calculate; |
| 1742 | denali->nand.ecc.correct = denali_ecc_correct; |
| 1743 | denali->nand.ecc.hwctl = denali_ecc_hwctl; |
| 1744 | |
| 1745 | /* override the default read operations */ |
Chuanxiao Dong | 08b9ab9 | 2010-08-06 18:19:09 +0800 | [diff] [blame] | 1746 | denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1747 | denali->nand.ecc.read_page = denali_read_page; |
| 1748 | denali->nand.ecc.read_page_raw = denali_read_page_raw; |
| 1749 | denali->nand.ecc.write_page = denali_write_page; |
| 1750 | denali->nand.ecc.write_page_raw = denali_write_page_raw; |
| 1751 | denali->nand.ecc.read_oob = denali_read_oob; |
| 1752 | denali->nand.ecc.write_oob = denali_write_oob; |
| 1753 | denali->nand.erase_cmd = denali_erase; |
| 1754 | |
Chuanxiao Dong | 345b1d3 | 2010-07-27 10:41:53 +0800 | [diff] [blame] | 1755 | if (nand_scan_tail(&denali->mtd)) { |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1756 | ret = -ENXIO; |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1757 | goto failed_req_irq; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1758 | } |
| 1759 | |
| 1760 | ret = add_mtd_device(&denali->mtd); |
| 1761 | if (ret) { |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1762 | printk(KERN_ERR "Spectra: Failed to register" |
| 1763 | " MTD device: %d\n", ret); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1764 | goto failed_req_irq; |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1765 | } |
| 1766 | return 0; |
| 1767 | |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1768 | failed_req_irq: |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1769 | denali_irq_cleanup(dev->irq, denali); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1770 | failed_remap_mem: |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1771 | iounmap(denali->flash_mem); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1772 | failed_remap_reg: |
| 1773 | iounmap(denali->flash_reg); |
| 1774 | failed_req_regions: |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1775 | pci_release_regions(dev); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1776 | failed_dma_map: |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1777 | pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1778 | PCI_DMA_BIDIRECTIONAL); |
Chuanxiao Dong | 5c0eb90 | 2010-08-09 18:37:00 +0800 | [diff] [blame] | 1779 | failed_enable_dev: |
| 1780 | pci_disable_device(dev); |
| 1781 | failed_alloc_memery: |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1782 | kfree(denali); |
| 1783 | return ret; |
| 1784 | } |
| 1785 | |
| 1786 | /* driver exit point */ |
| 1787 | static void denali_pci_remove(struct pci_dev *dev) |
| 1788 | { |
| 1789 | struct denali_nand_info *denali = pci_get_drvdata(dev); |
| 1790 | |
| 1791 | nand_dbg_print(NAND_DBG_WARN, "%s, Line %d, Function: %s\n", |
| 1792 | __FILE__, __LINE__, __func__); |
| 1793 | |
| 1794 | nand_release(&denali->mtd); |
| 1795 | del_mtd_device(&denali->mtd); |
| 1796 | |
| 1797 | denali_irq_cleanup(dev->irq, denali); |
| 1798 | |
| 1799 | iounmap(denali->flash_reg); |
| 1800 | iounmap(denali->flash_mem); |
| 1801 | pci_release_regions(dev); |
| 1802 | pci_disable_device(dev); |
Chuanxiao | 5bac3ac | 2010-08-05 23:06:04 +0800 | [diff] [blame] | 1803 | pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1804 | PCI_DMA_BIDIRECTIONAL); |
| 1805 | pci_set_drvdata(dev, NULL); |
| 1806 | kfree(denali); |
| 1807 | } |
| 1808 | |
| 1809 | MODULE_DEVICE_TABLE(pci, denali_pci_ids); |
| 1810 | |
| 1811 | static struct pci_driver denali_pci_driver = { |
| 1812 | .name = DENALI_NAND_NAME, |
| 1813 | .id_table = denali_pci_ids, |
| 1814 | .probe = denali_pci_probe, |
| 1815 | .remove = denali_pci_remove, |
| 1816 | }; |
| 1817 | |
| 1818 | static int __devinit denali_init(void) |
| 1819 | { |
Chuanxiao Dong | bdca6da | 2010-07-27 11:28:09 +0800 | [diff] [blame] | 1820 | printk(KERN_INFO "Spectra MTD driver built on %s @ %s\n", |
| 1821 | __DATE__, __TIME__); |
Jason Roberts | ce08259 | 2010-05-13 15:57:33 +0100 | [diff] [blame] | 1822 | return pci_register_driver(&denali_pci_driver); |
| 1823 | } |
| 1824 | |
| 1825 | /* Free memory */ |
| 1826 | static void __devexit denali_exit(void) |
| 1827 | { |
| 1828 | pci_unregister_driver(&denali_pci_driver); |
| 1829 | } |
| 1830 | |
| 1831 | module_init(denali_init); |
| 1832 | module_exit(denali_exit); |