blob: b4b6087f22343ac66727090356d9abedabd91d42 [file] [log] [blame]
Wu, Bryan8cc75c92007-05-06 14:50:32 -07001/*
2 * Blackfin On-Chip Real Time Clock Driver
Mike Frysinger99800602009-06-30 11:41:43 -07003 * Supports BF51x/BF52x/BF53[123]/BF53[467]/BF54x
Wu, Bryan8cc75c92007-05-06 14:50:32 -07004 *
Mike Frysingerd7c7ef92010-10-27 15:33:04 -07005 * Copyright 2004-2010 Analog Devices Inc.
Wu, Bryan8cc75c92007-05-06 14:50:32 -07006 *
7 * Enter bugs at http://blackfin.uclinux.org/
8 *
9 * Licensed under the GPL-2 or later.
10 */
11
12/* The biggest issue we deal with in this driver is that register writes are
13 * synced to the RTC frequency of 1Hz. So if you write to a register and
14 * attempt to write again before the first write has completed, the new write
15 * is simply discarded. This can easily be troublesome if userspace disables
16 * one event (say periodic) and then right after enables an event (say alarm).
17 * Since all events are maintained in the same interrupt mask register, if
18 * we wrote to it to disable the first event and then wrote to it again to
19 * enable the second event, that second event would not be enabled as the
20 * write would be discarded and things quickly fall apart.
21 *
22 * To keep this delay from significantly degrading performance (we, in theory,
23 * would have to sleep for up to 1 second everytime we wanted to write a
24 * register), we only check the write pending status before we start to issue
25 * a new write. We bank on the idea that it doesnt matter when the sync
26 * happens so long as we don't attempt another write before it does. The only
27 * time userspace would take this penalty is when they try and do multiple
28 * operations right after another ... but in this case, they need to take the
29 * sync penalty, so we should be OK.
30 *
31 * Also note that the RTC_ISTAT register does not suffer this penalty; its
32 * writes to clear status registers complete immediately.
33 */
34
Mike Frysinger26cb8bb2008-08-05 13:01:21 -070035/* It may seem odd that there is no SWCNT code in here (which would be exposed
36 * via the periodic interrupt event, or PIE). Since the Blackfin RTC peripheral
37 * runs in units of seconds (N/HZ) but the Linux framework runs in units of HZ
38 * (2^N HZ), there is no point in keeping code that only provides 1 HZ PIEs.
39 * The same exact behavior can be accomplished by using the update interrupt
40 * event (UIE). Maybe down the line the RTC peripheral will suck less in which
41 * case we can re-introduce PIE support.
42 */
43
Wu, Bryan8cc75c92007-05-06 14:50:32 -070044#include <linux/bcd.h>
Mike Frysinger095b9d52008-02-06 01:38:51 -080045#include <linux/completion.h>
Wu, Bryan8cc75c92007-05-06 14:50:32 -070046#include <linux/delay.h>
Mike Frysinger095b9d52008-02-06 01:38:51 -080047#include <linux/init.h>
48#include <linux/interrupt.h>
49#include <linux/kernel.h>
50#include <linux/module.h>
51#include <linux/platform_device.h>
52#include <linux/rtc.h>
53#include <linux/seq_file.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090054#include <linux/slab.h>
Wu, Bryan8cc75c92007-05-06 14:50:32 -070055
56#include <asm/blackfin.h>
57
Mike Frysinger5438de42008-02-06 01:38:49 -080058#define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)
Wu, Bryan8cc75c92007-05-06 14:50:32 -070059
60struct bfin_rtc {
61 struct rtc_device *rtc_dev;
62 struct rtc_time rtc_alarm;
Mike Frysinger095b9d52008-02-06 01:38:51 -080063 u16 rtc_wrote_regs;
Wu, Bryan8cc75c92007-05-06 14:50:32 -070064};
65
66/* Bit values for the ISTAT / ICTL registers */
67#define RTC_ISTAT_WRITE_COMPLETE 0x8000
68#define RTC_ISTAT_WRITE_PENDING 0x4000
69#define RTC_ISTAT_ALARM_DAY 0x0040
70#define RTC_ISTAT_24HR 0x0020
71#define RTC_ISTAT_HOUR 0x0010
72#define RTC_ISTAT_MIN 0x0008
73#define RTC_ISTAT_SEC 0x0004
74#define RTC_ISTAT_ALARM 0x0002
75#define RTC_ISTAT_STOPWATCH 0x0001
76
77/* Shift values for RTC_STAT register */
78#define DAY_BITS_OFF 17
79#define HOUR_BITS_OFF 12
80#define MIN_BITS_OFF 6
81#define SEC_BITS_OFF 0
82
83/* Some helper functions to convert between the common RTC notion of time
Mike Frysinger5c236342008-02-06 01:38:47 -080084 * and the internal Blackfin notion that is encoded in 32bits.
Wu, Bryan8cc75c92007-05-06 14:50:32 -070085 */
86static inline u32 rtc_time_to_bfin(unsigned long now)
87{
88 u32 sec = (now % 60);
89 u32 min = (now % (60 * 60)) / 60;
90 u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
91 u32 days = (now / (60 * 60 * 24));
92 return (sec << SEC_BITS_OFF) +
93 (min << MIN_BITS_OFF) +
94 (hour << HOUR_BITS_OFF) +
95 (days << DAY_BITS_OFF);
96}
97static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
98{
99 return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) +
100 (((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) +
101 (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
102 (((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24);
103}
104static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
105{
106 rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
107}
108
Mike Frysinger095b9d52008-02-06 01:38:51 -0800109/**
110 * bfin_rtc_sync_pending - make sure pending writes have complete
111 *
112 * Wait for the previous write to a RTC register to complete.
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700113 * Unfortunately, we can't sleep here as that introduces a race condition when
114 * turning on interrupt events. Consider this:
115 * - process sets alarm
116 * - process enables alarm
117 * - process sleeps while waiting for rtc write to sync
118 * - interrupt fires while process is sleeping
119 * - interrupt acks the event by writing to ISTAT
120 * - interrupt sets the WRITE PENDING bit
121 * - interrupt handler finishes
122 * - process wakes up, sees WRITE PENDING bit set, goes to sleep
123 * - interrupt fires while process is sleeping
124 * If anyone can point out the obvious solution here, i'm listening :). This
125 * shouldn't be an issue on an SMP or preempt system as this function should
126 * only be called with the rtc lock held.
Mike Frysinger5c236342008-02-06 01:38:47 -0800127 *
128 * Other options:
129 * - disable PREN so the sync happens at 32.768kHZ ... but this changes the
130 * inc rate for all RTC registers from 1HZ to 32.768kHZ ...
131 * - use the write complete IRQ
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700132 */
Mike Frysinger095b9d52008-02-06 01:38:51 -0800133/*
134static void bfin_rtc_sync_pending_polled(void)
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700135{
Mike Frysinger095b9d52008-02-06 01:38:51 -0800136 while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE))
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700137 if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
138 break;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700139 bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
140}
Mike Frysinger095b9d52008-02-06 01:38:51 -0800141*/
142static DECLARE_COMPLETION(bfin_write_complete);
143static void bfin_rtc_sync_pending(struct device *dev)
144{
145 dev_dbg_stamp(dev);
146 while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
147 wait_for_completion_timeout(&bfin_write_complete, HZ * 5);
148 dev_dbg_stamp(dev);
149}
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700150
Mike Frysinger095b9d52008-02-06 01:38:51 -0800151/**
152 * bfin_rtc_reset - set RTC to sane/known state
153 *
154 * Initialize the RTC. Enable pre-scaler to scale RTC clock
155 * to 1Hz and clear interrupt/status registers.
156 */
Mike Frysinger3b128fe2008-08-05 13:01:19 -0700157static void bfin_rtc_reset(struct device *dev, u16 rtc_ictl)
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700158{
Mike Frysinger5438de42008-02-06 01:38:49 -0800159 struct bfin_rtc *rtc = dev_get_drvdata(dev);
Mike Frysinger095b9d52008-02-06 01:38:51 -0800160 dev_dbg_stamp(dev);
161 bfin_rtc_sync_pending(dev);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700162 bfin_write_RTC_PREN(0x1);
Mike Frysinger3b128fe2008-08-05 13:01:19 -0700163 bfin_write_RTC_ICTL(rtc_ictl);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700164 bfin_write_RTC_ALARM(0);
165 bfin_write_RTC_ISTAT(0xFFFF);
Mike Frysinger095b9d52008-02-06 01:38:51 -0800166 rtc->rtc_wrote_regs = 0;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700167}
168
Mike Frysinger095b9d52008-02-06 01:38:51 -0800169/**
170 * bfin_rtc_interrupt - handle interrupt from RTC
171 *
172 * Since we handle all RTC events here, we have to make sure the requested
173 * interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT)
174 * always gets updated regardless of the interrupt being enabled. So when one
175 * even we care about (e.g. stopwatch) goes off, we don't want to turn around
176 * and say that other events have happened as well (e.g. second). We do not
177 * have to worry about pending writes to the RTC_ICTL register as interrupts
178 * only fire if they are enabled in the RTC_ICTL register.
179 */
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700180static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
181{
Mike Frysingerd7827d82008-02-06 01:38:47 -0800182 struct device *dev = dev_id;
183 struct bfin_rtc *rtc = dev_get_drvdata(dev);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700184 unsigned long events = 0;
Mike Frysinger095b9d52008-02-06 01:38:51 -0800185 bool write_complete = false;
Mike Frysinger286f9f92010-10-27 15:33:03 -0700186 u16 rtc_istat, rtc_istat_clear, rtc_ictl, bits;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700187
Mike Frysinger5438de42008-02-06 01:38:49 -0800188 dev_dbg_stamp(dev);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700189
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700190 rtc_istat = bfin_read_RTC_ISTAT();
Mike Frysinger095b9d52008-02-06 01:38:51 -0800191 rtc_ictl = bfin_read_RTC_ICTL();
Mike Frysinger286f9f92010-10-27 15:33:03 -0700192 rtc_istat_clear = 0;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700193
Mike Frysinger286f9f92010-10-27 15:33:03 -0700194 bits = RTC_ISTAT_WRITE_COMPLETE;
195 if (rtc_istat & bits) {
196 rtc_istat_clear |= bits;
Mike Frysinger095b9d52008-02-06 01:38:51 -0800197 write_complete = true;
198 complete(&bfin_write_complete);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700199 }
200
Mike Frysinger286f9f92010-10-27 15:33:03 -0700201 bits = (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY);
202 if (rtc_ictl & bits) {
203 if (rtc_istat & bits) {
204 rtc_istat_clear |= bits;
Mike Frysinger095b9d52008-02-06 01:38:51 -0800205 events |= RTC_AF | RTC_IRQF;
206 }
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700207 }
208
Mike Frysinger286f9f92010-10-27 15:33:03 -0700209 bits = RTC_ISTAT_SEC;
210 if (rtc_ictl & bits) {
211 if (rtc_istat & bits) {
212 rtc_istat_clear |= bits;
Mike Frysinger095b9d52008-02-06 01:38:51 -0800213 events |= RTC_UF | RTC_IRQF;
214 }
215 }
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700216
Mike Frysinger095b9d52008-02-06 01:38:51 -0800217 if (events)
218 rtc_update_irq(rtc->rtc_dev, 1, events);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700219
Mike Frysinger286f9f92010-10-27 15:33:03 -0700220 if (write_complete || events) {
221 bfin_write_RTC_ISTAT(rtc_istat_clear);
Mike Frysinger095b9d52008-02-06 01:38:51 -0800222 return IRQ_HANDLED;
Mike Frysinger286f9f92010-10-27 15:33:03 -0700223 } else
Mike Frysinger095b9d52008-02-06 01:38:51 -0800224 return IRQ_NONE;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700225}
226
Mike Frysinger605eb8b2008-08-05 13:01:18 -0700227static void bfin_rtc_int_set(u16 rtc_int)
Mike Frysinger095b9d52008-02-06 01:38:51 -0800228{
229 bfin_write_RTC_ISTAT(rtc_int);
230 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | rtc_int);
231}
Mike Frysinger605eb8b2008-08-05 13:01:18 -0700232static void bfin_rtc_int_clear(u16 rtc_int)
Mike Frysinger095b9d52008-02-06 01:38:51 -0800233{
234 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int);
235}
236static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc)
237{
238 /* Blackfin has different bits for whether the alarm is
239 * more than 24 hours away.
240 */
Mike Frysinger605eb8b2008-08-05 13:01:18 -0700241 bfin_rtc_int_set(rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY);
Mike Frysinger095b9d52008-02-06 01:38:51 -0800242}
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700243static int bfin_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
244{
245 struct bfin_rtc *rtc = dev_get_drvdata(dev);
Mike Frysinger095b9d52008-02-06 01:38:51 -0800246 int ret = 0;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700247
Mike Frysinger5438de42008-02-06 01:38:49 -0800248 dev_dbg_stamp(dev);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700249
Mike Frysinger095b9d52008-02-06 01:38:51 -0800250 bfin_rtc_sync_pending(dev);
251
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700252 switch (cmd) {
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700253 case RTC_UIE_ON:
Mike Frysinger5438de42008-02-06 01:38:49 -0800254 dev_dbg_stamp(dev);
Mike Frysinger605eb8b2008-08-05 13:01:18 -0700255 bfin_rtc_int_set(RTC_ISTAT_SEC);
Mike Frysinger095b9d52008-02-06 01:38:51 -0800256 break;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700257 case RTC_UIE_OFF:
Mike Frysinger5438de42008-02-06 01:38:49 -0800258 dev_dbg_stamp(dev);
Mike Frysinger605eb8b2008-08-05 13:01:18 -0700259 bfin_rtc_int_clear(~RTC_ISTAT_SEC);
Mike Frysinger095b9d52008-02-06 01:38:51 -0800260 break;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700261
Mike Frysinger095b9d52008-02-06 01:38:51 -0800262 case RTC_AIE_ON:
Mike Frysinger5438de42008-02-06 01:38:49 -0800263 dev_dbg_stamp(dev);
Mike Frysinger095b9d52008-02-06 01:38:51 -0800264 bfin_rtc_int_set_alarm(rtc);
265 break;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700266 case RTC_AIE_OFF:
Mike Frysinger5438de42008-02-06 01:38:49 -0800267 dev_dbg_stamp(dev);
Mike Frysinger605eb8b2008-08-05 13:01:18 -0700268 bfin_rtc_int_clear(~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
Mike Frysinger095b9d52008-02-06 01:38:51 -0800269 break;
270
271 default:
272 dev_dbg_stamp(dev);
273 ret = -ENOIOCTLCMD;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700274 }
275
Mike Frysinger095b9d52008-02-06 01:38:51 -0800276 return ret;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700277}
278
279static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm)
280{
281 struct bfin_rtc *rtc = dev_get_drvdata(dev);
282
Mike Frysinger5438de42008-02-06 01:38:49 -0800283 dev_dbg_stamp(dev);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700284
Mike Frysinger095b9d52008-02-06 01:38:51 -0800285 if (rtc->rtc_wrote_regs & 0x1)
286 bfin_rtc_sync_pending(dev);
287
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700288 rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700289
290 return 0;
291}
292
293static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm)
294{
295 struct bfin_rtc *rtc = dev_get_drvdata(dev);
296 int ret;
297 unsigned long now;
298
Mike Frysinger5438de42008-02-06 01:38:49 -0800299 dev_dbg_stamp(dev);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700300
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700301 ret = rtc_tm_to_time(tm, &now);
302 if (ret == 0) {
Mike Frysinger095b9d52008-02-06 01:38:51 -0800303 if (rtc->rtc_wrote_regs & 0x1)
304 bfin_rtc_sync_pending(dev);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700305 bfin_write_RTC_STAT(rtc_time_to_bfin(now));
Mike Frysinger095b9d52008-02-06 01:38:51 -0800306 rtc->rtc_wrote_regs = 0x1;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700307 }
308
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700309 return ret;
310}
311
312static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
313{
314 struct bfin_rtc *rtc = dev_get_drvdata(dev);
Mike Frysinger5438de42008-02-06 01:38:49 -0800315 dev_dbg_stamp(dev);
Mike Frysinger48c1a562008-02-06 01:38:50 -0800316 alrm->time = rtc->rtc_alarm;
Mike Frysinger095b9d52008-02-06 01:38:51 -0800317 bfin_rtc_sync_pending(dev);
Mike Frysinger68db3042008-02-06 01:38:49 -0800318 alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700319 return 0;
320}
321
322static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
323{
324 struct bfin_rtc *rtc = dev_get_drvdata(dev);
Mike Frysinger095b9d52008-02-06 01:38:51 -0800325 unsigned long rtc_alarm;
326
Mike Frysinger5438de42008-02-06 01:38:49 -0800327 dev_dbg_stamp(dev);
Mike Frysinger095b9d52008-02-06 01:38:51 -0800328
329 if (rtc_tm_to_time(&alrm->time, &rtc_alarm))
330 return -EINVAL;
331
Mike Frysinger68db3042008-02-06 01:38:49 -0800332 rtc->rtc_alarm = alrm->time;
Mike Frysinger095b9d52008-02-06 01:38:51 -0800333
334 bfin_rtc_sync_pending(dev);
335 bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
336 if (alrm->enabled)
337 bfin_rtc_int_set_alarm(rtc);
338
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700339 return 0;
340}
341
342static int bfin_rtc_proc(struct device *dev, struct seq_file *seq)
343{
Mike Frysinger64061162008-02-06 01:38:48 -0800344#define yesno(x) ((x) ? "yes" : "no")
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700345 u16 ictl = bfin_read_RTC_ICTL();
Mike Frysinger5438de42008-02-06 01:38:49 -0800346 dev_dbg_stamp(dev);
Mike Frysinger64061162008-02-06 01:38:48 -0800347 seq_printf(seq,
348 "alarm_IRQ\t: %s\n"
349 "wkalarm_IRQ\t: %s\n"
Mike Frysinger26cb8bb2008-08-05 13:01:21 -0700350 "seconds_IRQ\t: %s\n",
Mike Frysinger64061162008-02-06 01:38:48 -0800351 yesno(ictl & RTC_ISTAT_ALARM),
352 yesno(ictl & RTC_ISTAT_ALARM_DAY),
Mike Frysinger26cb8bb2008-08-05 13:01:21 -0700353 yesno(ictl & RTC_ISTAT_SEC));
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700354 return 0;
Mike Frysinger64061162008-02-06 01:38:48 -0800355#undef yesno
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700356}
357
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700358static struct rtc_class_ops bfin_rtc_ops = {
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700359 .ioctl = bfin_rtc_ioctl,
360 .read_time = bfin_rtc_read_time,
361 .set_time = bfin_rtc_set_time,
362 .read_alarm = bfin_rtc_read_alarm,
363 .set_alarm = bfin_rtc_set_alarm,
364 .proc = bfin_rtc_proc,
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700365};
366
367static int __devinit bfin_rtc_probe(struct platform_device *pdev)
368{
369 struct bfin_rtc *rtc;
Mike Frysingerfe2e1cf2008-08-20 14:09:01 -0700370 struct device *dev = &pdev->dev;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700371 int ret = 0;
Mike Frysinger99800602009-06-30 11:41:43 -0700372 unsigned long timeout = jiffies + HZ;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700373
Mike Frysingerfe2e1cf2008-08-20 14:09:01 -0700374 dev_dbg_stamp(dev);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700375
Mike Frysingerfe2e1cf2008-08-20 14:09:01 -0700376 /* Allocate memory for our RTC struct */
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700377 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
378 if (unlikely(!rtc))
379 return -ENOMEM;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700380 platform_set_drvdata(pdev, rtc);
Mike Frysinger8c9166f2008-08-20 14:09:02 -0700381 device_init_wakeup(dev, 1);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700382
Mike Frysinger99800602009-06-30 11:41:43 -0700383 /* Register our RTC with the RTC framework */
384 rtc->rtc_dev = rtc_device_register(pdev->name, dev, &bfin_rtc_ops,
385 THIS_MODULE);
386 if (unlikely(IS_ERR(rtc->rtc_dev))) {
387 ret = PTR_ERR(rtc->rtc_dev);
388 goto err;
389 }
390
Mike Frysingerfe2e1cf2008-08-20 14:09:01 -0700391 /* Grab the IRQ and init the hardware */
Michael Hennerich6bff5fb2009-09-22 16:46:25 -0700392 ret = request_irq(IRQ_RTC, bfin_rtc_interrupt, 0, pdev->name, dev);
Mike Frysingerfe2e1cf2008-08-20 14:09:01 -0700393 if (unlikely(ret))
Mike Frysinger99800602009-06-30 11:41:43 -0700394 goto err_reg;
Mike Frysingerd0fd9372008-08-20 14:09:03 -0700395 /* sometimes the bootloader touched things, but the write complete was not
396 * enabled, so let's just do a quick timeout here since the IRQ will not fire ...
397 */
Mike Frysingerd0fd9372008-08-20 14:09:03 -0700398 while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
399 if (time_after(jiffies, timeout))
400 break;
Mike Frysingerfe2e1cf2008-08-20 14:09:01 -0700401 bfin_rtc_reset(dev, RTC_ISTAT_WRITE_COMPLETE);
402 bfin_write_RTC_SWCNT(0);
403
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700404 return 0;
405
Mike Frysinger99800602009-06-30 11:41:43 -0700406err_reg:
407 rtc_device_unregister(rtc->rtc_dev);
408err:
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700409 kfree(rtc);
410 return ret;
411}
412
413static int __devexit bfin_rtc_remove(struct platform_device *pdev)
414{
415 struct bfin_rtc *rtc = platform_get_drvdata(pdev);
Mike Frysingerfe2e1cf2008-08-20 14:09:01 -0700416 struct device *dev = &pdev->dev;
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700417
Mike Frysingerfe2e1cf2008-08-20 14:09:01 -0700418 bfin_rtc_reset(dev, 0);
419 free_irq(IRQ_RTC, dev);
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700420 rtc_device_unregister(rtc->rtc_dev);
421 platform_set_drvdata(pdev, NULL);
422 kfree(rtc);
423
424 return 0;
425}
426
Sonic Zhang5aeb7762008-08-05 13:01:17 -0700427#ifdef CONFIG_PM
428static int bfin_rtc_suspend(struct platform_device *pdev, pm_message_t state)
429{
Mike Frysingerd7c7ef92010-10-27 15:33:04 -0700430 struct device *dev = &pdev->dev;
431
432 dev_dbg_stamp(dev);
433
434 if (device_may_wakeup(dev)) {
Mike Frysinger813006f2008-08-05 13:01:18 -0700435 enable_irq_wake(IRQ_RTC);
Mike Frysingerd7c7ef92010-10-27 15:33:04 -0700436 bfin_rtc_sync_pending(dev);
Mike Frysinger140fab12008-08-05 13:01:20 -0700437 } else
Mike Frysinger110b7e92010-09-09 16:37:27 -0700438 bfin_rtc_int_clear(0);
Mike Frysinger813006f2008-08-05 13:01:18 -0700439
Sonic Zhang5aeb7762008-08-05 13:01:17 -0700440 return 0;
441}
442
443static int bfin_rtc_resume(struct platform_device *pdev)
444{
Mike Frysingerd7c7ef92010-10-27 15:33:04 -0700445 struct device *dev = &pdev->dev;
446
447 dev_dbg_stamp(dev);
448
449 if (device_may_wakeup(dev))
Mike Frysinger813006f2008-08-05 13:01:18 -0700450 disable_irq_wake(IRQ_RTC);
Mike Frysingerb6de8602010-09-09 16:37:29 -0700451
452 /*
453 * Since only some of the RTC bits are maintained externally in the
454 * Vbat domain, we need to wait for the RTC MMRs to be synced into
455 * the core after waking up. This happens every RTC 1HZ. Once that
456 * has happened, we can go ahead and re-enable the important write
457 * complete interrupt event.
458 */
459 while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_SEC))
460 continue;
461 bfin_rtc_int_set(RTC_ISTAT_WRITE_COMPLETE);
Mike Frysinger813006f2008-08-05 13:01:18 -0700462
Sonic Zhang5aeb7762008-08-05 13:01:17 -0700463 return 0;
464}
Mike Frysinger813006f2008-08-05 13:01:18 -0700465#else
466# define bfin_rtc_suspend NULL
467# define bfin_rtc_resume NULL
Sonic Zhang5aeb7762008-08-05 13:01:17 -0700468#endif
469
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700470static struct platform_driver bfin_rtc_driver = {
471 .driver = {
472 .name = "rtc-bfin",
473 .owner = THIS_MODULE,
474 },
475 .probe = bfin_rtc_probe,
476 .remove = __devexit_p(bfin_rtc_remove),
Sonic Zhang5aeb7762008-08-05 13:01:17 -0700477 .suspend = bfin_rtc_suspend,
478 .resume = bfin_rtc_resume,
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700479};
480
481static int __init bfin_rtc_init(void)
482{
Wu, Bryan8cc75c92007-05-06 14:50:32 -0700483 return platform_driver_register(&bfin_rtc_driver);
484}
485
486static void __exit bfin_rtc_exit(void)
487{
488 platform_driver_unregister(&bfin_rtc_driver);
489}
490
491module_init(bfin_rtc_init);
492module_exit(bfin_rtc_exit);
493
494MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
495MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
496MODULE_LICENSE("GPL");
Kay Sieversad28a072008-04-10 21:29:25 -0700497MODULE_ALIAS("platform:rtc-bfin");