Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Zhenyu Wang | f8f235e | 2010-08-27 11:08:57 +0800 | [diff] [blame] | 37 | #include <linux/intel-gtt.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 40 | |
| 41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
| 42 | bool pipelined); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
| 44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
| 46 | int write); |
| 47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 48 | uint64_t offset, |
| 49 | uint64_t size); |
| 50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 52 | bool interruptible); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
| 54 | unsigned alignment); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 57 | struct drm_i915_gem_pwrite *args, |
| 58 | struct drm_file *file_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 60 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 61 | static int |
| 62 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
| 63 | gfp_t gfpmask); |
| 64 | |
| 65 | static void |
| 66 | i915_gem_object_put_pages(struct drm_gem_object *obj); |
| 67 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 68 | static LIST_HEAD(shrink_list); |
| 69 | static DEFINE_SPINLOCK(shrink_list_lock); |
| 70 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 71 | /* some bookkeeping */ |
| 72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 73 | size_t size) |
| 74 | { |
| 75 | dev_priv->mm.object_count++; |
| 76 | dev_priv->mm.object_memory += size; |
| 77 | } |
| 78 | |
| 79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 80 | size_t size) |
| 81 | { |
| 82 | dev_priv->mm.object_count--; |
| 83 | dev_priv->mm.object_memory -= size; |
| 84 | } |
| 85 | |
| 86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, |
| 87 | size_t size) |
| 88 | { |
| 89 | dev_priv->mm.gtt_count++; |
| 90 | dev_priv->mm.gtt_memory += size; |
| 91 | } |
| 92 | |
| 93 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, |
| 94 | size_t size) |
| 95 | { |
| 96 | dev_priv->mm.gtt_count--; |
| 97 | dev_priv->mm.gtt_memory -= size; |
| 98 | } |
| 99 | |
| 100 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, |
| 101 | size_t size) |
| 102 | { |
| 103 | dev_priv->mm.pin_count++; |
| 104 | dev_priv->mm.pin_memory += size; |
| 105 | } |
| 106 | |
| 107 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, |
| 108 | size_t size) |
| 109 | { |
| 110 | dev_priv->mm.pin_count--; |
| 111 | dev_priv->mm.pin_memory -= size; |
| 112 | } |
| 113 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 114 | int |
| 115 | i915_gem_check_is_wedged(struct drm_device *dev) |
| 116 | { |
| 117 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 118 | struct completion *x = &dev_priv->error_completion; |
| 119 | unsigned long flags; |
| 120 | int ret; |
| 121 | |
| 122 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 123 | return 0; |
| 124 | |
| 125 | ret = wait_for_completion_interruptible(x); |
| 126 | if (ret) |
| 127 | return ret; |
| 128 | |
| 129 | /* Success, we reset the GPU! */ |
| 130 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 131 | return 0; |
| 132 | |
| 133 | /* GPU is hung, bump the completion count to account for |
| 134 | * the token we just consumed so that we never hit zero and |
| 135 | * end up waiting upon a subsequent completion event that |
| 136 | * will never happen. |
| 137 | */ |
| 138 | spin_lock_irqsave(&x->wait.lock, flags); |
| 139 | x->done++; |
| 140 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 141 | return -EIO; |
| 142 | } |
| 143 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 144 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
| 145 | { |
| 146 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 147 | int ret; |
| 148 | |
| 149 | ret = i915_gem_check_is_wedged(dev); |
| 150 | if (ret) |
| 151 | return ret; |
| 152 | |
| 153 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 154 | if (ret) |
| 155 | return ret; |
| 156 | |
| 157 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 158 | mutex_unlock(&dev->struct_mutex); |
| 159 | return -EAGAIN; |
| 160 | } |
| 161 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 162 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 163 | return 0; |
| 164 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 165 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 166 | static inline bool |
| 167 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) |
| 168 | { |
| 169 | return obj_priv->gtt_space && |
| 170 | !obj_priv->active && |
| 171 | obj_priv->pin_count == 0; |
| 172 | } |
| 173 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 174 | int i915_gem_do_init(struct drm_device *dev, |
| 175 | unsigned long start, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 176 | unsigned long end) |
| 177 | { |
| 178 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 179 | |
| 180 | if (start >= end || |
| 181 | (start & (PAGE_SIZE - 1)) != 0 || |
| 182 | (end & (PAGE_SIZE - 1)) != 0) { |
| 183 | return -EINVAL; |
| 184 | } |
| 185 | |
| 186 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 187 | end - start); |
| 188 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 189 | dev_priv->mm.gtt_total = end - start; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 190 | |
| 191 | return 0; |
| 192 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 193 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 194 | int |
| 195 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 196 | struct drm_file *file_priv) |
| 197 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 198 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 199 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 200 | |
| 201 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 202 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 203 | mutex_unlock(&dev->struct_mutex); |
| 204 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 205 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 206 | } |
| 207 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 208 | int |
| 209 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 210 | struct drm_file *file_priv) |
| 211 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 212 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 213 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 214 | |
| 215 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 216 | return -ENODEV; |
| 217 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 218 | mutex_lock(&dev->struct_mutex); |
| 219 | args->aper_size = dev_priv->mm.gtt_total; |
| 220 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; |
| 221 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 226 | |
| 227 | /** |
| 228 | * Creates a new mm object and returns a handle to it. |
| 229 | */ |
| 230 | int |
| 231 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 232 | struct drm_file *file_priv) |
| 233 | { |
| 234 | struct drm_i915_gem_create *args = data; |
| 235 | struct drm_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 236 | int ret; |
| 237 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 238 | |
| 239 | args->size = roundup(args->size, PAGE_SIZE); |
| 240 | |
| 241 | /* Allocate the new object */ |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 242 | obj = i915_gem_alloc_object(dev, args->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 243 | if (obj == NULL) |
| 244 | return -ENOMEM; |
| 245 | |
| 246 | ret = drm_gem_handle_create(file_priv, obj, &handle); |
Dave Airlie | 29d08b3 | 2010-09-27 16:17:17 +1000 | [diff] [blame] | 247 | /* drop reference from allocate - handle holds it now */ |
| 248 | drm_gem_object_unreference_unlocked(obj); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 249 | if (ret) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 250 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 251 | } |
| 252 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 253 | args->handle = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 254 | return 0; |
| 255 | } |
| 256 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 257 | static inline int |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 258 | fast_shmem_read(struct page **pages, |
| 259 | loff_t page_base, int page_offset, |
| 260 | char __user *data, |
| 261 | int length) |
| 262 | { |
| 263 | char __iomem *vaddr; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 264 | int unwritten; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 265 | |
| 266 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 267 | if (vaddr == NULL) |
| 268 | return -ENOMEM; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 269 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 270 | kunmap_atomic(vaddr, KM_USER0); |
| 271 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 272 | if (unwritten) |
| 273 | return -EFAULT; |
| 274 | |
| 275 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 276 | } |
| 277 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 278 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
| 279 | { |
| 280 | drm_i915_private_t *dev_priv = obj->dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 281 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 282 | |
| 283 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 284 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 285 | } |
| 286 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 287 | static inline void |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 288 | slow_shmem_copy(struct page *dst_page, |
| 289 | int dst_offset, |
| 290 | struct page *src_page, |
| 291 | int src_offset, |
| 292 | int length) |
| 293 | { |
| 294 | char *dst_vaddr, *src_vaddr; |
| 295 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 296 | dst_vaddr = kmap(dst_page); |
| 297 | src_vaddr = kmap(src_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 298 | |
| 299 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 300 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 301 | kunmap(src_page); |
| 302 | kunmap(dst_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 303 | } |
| 304 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 305 | static inline void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 306 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 307 | int gpu_offset, |
| 308 | struct page *cpu_page, |
| 309 | int cpu_offset, |
| 310 | int length, |
| 311 | int is_read) |
| 312 | { |
| 313 | char *gpu_vaddr, *cpu_vaddr; |
| 314 | |
| 315 | /* Use the unswizzled path if this page isn't affected. */ |
| 316 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 317 | if (is_read) |
| 318 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 319 | gpu_page, gpu_offset, length); |
| 320 | else |
| 321 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 322 | cpu_page, cpu_offset, length); |
| 323 | } |
| 324 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 325 | gpu_vaddr = kmap(gpu_page); |
| 326 | cpu_vaddr = kmap(cpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 327 | |
| 328 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 329 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 330 | */ |
| 331 | while (length > 0) { |
| 332 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 333 | int this_length = min(cacheline_end - gpu_offset, length); |
| 334 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 335 | |
| 336 | if (is_read) { |
| 337 | memcpy(cpu_vaddr + cpu_offset, |
| 338 | gpu_vaddr + swizzled_gpu_offset, |
| 339 | this_length); |
| 340 | } else { |
| 341 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 342 | cpu_vaddr + cpu_offset, |
| 343 | this_length); |
| 344 | } |
| 345 | cpu_offset += this_length; |
| 346 | gpu_offset += this_length; |
| 347 | length -= this_length; |
| 348 | } |
| 349 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 350 | kunmap(cpu_page); |
| 351 | kunmap(gpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 352 | } |
| 353 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 354 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 355 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 356 | * from the backing pages of the object to the user's address space. On a |
| 357 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 358 | */ |
| 359 | static int |
| 360 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 361 | struct drm_i915_gem_pread *args, |
| 362 | struct drm_file *file_priv) |
| 363 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 364 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 365 | ssize_t remain; |
| 366 | loff_t offset, page_base; |
| 367 | char __user *user_data; |
| 368 | int page_offset, page_length; |
| 369 | int ret; |
| 370 | |
| 371 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 372 | remain = args->size; |
| 373 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 374 | ret = i915_mutex_lock_interruptible(dev); |
| 375 | if (ret) |
| 376 | return ret; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 377 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 378 | ret = i915_gem_object_get_pages(obj, 0); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 379 | if (ret != 0) |
| 380 | goto fail_unlock; |
| 381 | |
| 382 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 383 | args->size); |
| 384 | if (ret != 0) |
| 385 | goto fail_put_pages; |
| 386 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 387 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 388 | offset = args->offset; |
| 389 | |
| 390 | while (remain > 0) { |
| 391 | /* Operation in this page |
| 392 | * |
| 393 | * page_base = page offset within aperture |
| 394 | * page_offset = offset within page |
| 395 | * page_length = bytes to copy for this page |
| 396 | */ |
| 397 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 398 | page_offset = offset & (PAGE_SIZE-1); |
| 399 | page_length = remain; |
| 400 | if ((page_offset + remain) > PAGE_SIZE) |
| 401 | page_length = PAGE_SIZE - page_offset; |
| 402 | |
| 403 | ret = fast_shmem_read(obj_priv->pages, |
| 404 | page_base, page_offset, |
| 405 | user_data, page_length); |
| 406 | if (ret) |
| 407 | goto fail_put_pages; |
| 408 | |
| 409 | remain -= page_length; |
| 410 | user_data += page_length; |
| 411 | offset += page_length; |
| 412 | } |
| 413 | |
| 414 | fail_put_pages: |
| 415 | i915_gem_object_put_pages(obj); |
| 416 | fail_unlock: |
| 417 | mutex_unlock(&dev->struct_mutex); |
| 418 | |
| 419 | return ret; |
| 420 | } |
| 421 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 422 | static int |
| 423 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) |
| 424 | { |
| 425 | int ret; |
| 426 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 427 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 428 | |
| 429 | /* If we've insufficient memory to map in the pages, attempt |
| 430 | * to make some space by throwing out some old buffers. |
| 431 | */ |
| 432 | if (ret == -ENOMEM) { |
| 433 | struct drm_device *dev = obj->dev; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 434 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 435 | ret = i915_gem_evict_something(dev, obj->size, |
| 436 | i915_gem_get_gtt_alignment(obj)); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 437 | if (ret) |
| 438 | return ret; |
| 439 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 440 | ret = i915_gem_object_get_pages(obj, 0); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 441 | } |
| 442 | |
| 443 | return ret; |
| 444 | } |
| 445 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 446 | /** |
| 447 | * This is the fallback shmem pread path, which allocates temporary storage |
| 448 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 449 | * can copy out of the object's backing pages while holding the struct mutex |
| 450 | * and not take page faults. |
| 451 | */ |
| 452 | static int |
| 453 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 454 | struct drm_i915_gem_pread *args, |
| 455 | struct drm_file *file_priv) |
| 456 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 457 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 458 | struct mm_struct *mm = current->mm; |
| 459 | struct page **user_pages; |
| 460 | ssize_t remain; |
| 461 | loff_t offset, pinned_pages, i; |
| 462 | loff_t first_data_page, last_data_page, num_pages; |
| 463 | int shmem_page_index, shmem_page_offset; |
| 464 | int data_page_index, data_page_offset; |
| 465 | int page_length; |
| 466 | int ret; |
| 467 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 468 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 469 | |
| 470 | remain = args->size; |
| 471 | |
| 472 | /* Pin the user pages containing the data. We can't fault while |
| 473 | * holding the struct mutex, yet we want to hold it while |
| 474 | * dereferencing the user data. |
| 475 | */ |
| 476 | first_data_page = data_ptr / PAGE_SIZE; |
| 477 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 478 | num_pages = last_data_page - first_data_page + 1; |
| 479 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 480 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 481 | if (user_pages == NULL) |
| 482 | return -ENOMEM; |
| 483 | |
| 484 | down_read(&mm->mmap_sem); |
| 485 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 486 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 487 | up_read(&mm->mmap_sem); |
| 488 | if (pinned_pages < num_pages) { |
| 489 | ret = -EFAULT; |
| 490 | goto fail_put_user_pages; |
| 491 | } |
| 492 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 493 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 494 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 495 | ret = i915_mutex_lock_interruptible(dev); |
| 496 | if (ret) |
| 497 | goto fail_put_user_pages; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 498 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 499 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 500 | if (ret) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 501 | goto fail_unlock; |
| 502 | |
| 503 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 504 | args->size); |
| 505 | if (ret != 0) |
| 506 | goto fail_put_pages; |
| 507 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 508 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 509 | offset = args->offset; |
| 510 | |
| 511 | while (remain > 0) { |
| 512 | /* Operation in this page |
| 513 | * |
| 514 | * shmem_page_index = page number within shmem file |
| 515 | * shmem_page_offset = offset within page in shmem file |
| 516 | * data_page_index = page number in get_user_pages return |
| 517 | * data_page_offset = offset with data_page_index page. |
| 518 | * page_length = bytes to copy for this page |
| 519 | */ |
| 520 | shmem_page_index = offset / PAGE_SIZE; |
| 521 | shmem_page_offset = offset & ~PAGE_MASK; |
| 522 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 523 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 524 | |
| 525 | page_length = remain; |
| 526 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 527 | page_length = PAGE_SIZE - shmem_page_offset; |
| 528 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 529 | page_length = PAGE_SIZE - data_page_offset; |
| 530 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 531 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 532 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 533 | shmem_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 534 | user_pages[data_page_index], |
| 535 | data_page_offset, |
| 536 | page_length, |
| 537 | 1); |
| 538 | } else { |
| 539 | slow_shmem_copy(user_pages[data_page_index], |
| 540 | data_page_offset, |
| 541 | obj_priv->pages[shmem_page_index], |
| 542 | shmem_page_offset, |
| 543 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 544 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 545 | |
| 546 | remain -= page_length; |
| 547 | data_ptr += page_length; |
| 548 | offset += page_length; |
| 549 | } |
| 550 | |
| 551 | fail_put_pages: |
| 552 | i915_gem_object_put_pages(obj); |
| 553 | fail_unlock: |
| 554 | mutex_unlock(&dev->struct_mutex); |
| 555 | fail_put_user_pages: |
| 556 | for (i = 0; i < pinned_pages; i++) { |
| 557 | SetPageDirty(user_pages[i]); |
| 558 | page_cache_release(user_pages[i]); |
| 559 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 560 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 561 | |
| 562 | return ret; |
| 563 | } |
| 564 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 565 | /** |
| 566 | * Reads data from the object referenced by handle. |
| 567 | * |
| 568 | * On error, the contents of *data are undefined. |
| 569 | */ |
| 570 | int |
| 571 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 572 | struct drm_file *file_priv) |
| 573 | { |
| 574 | struct drm_i915_gem_pread *args = data; |
| 575 | struct drm_gem_object *obj; |
| 576 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 577 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 578 | |
| 579 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 580 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 581 | return -ENOENT; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 582 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 583 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 584 | /* Bounds check source. */ |
| 585 | if (args->offset > obj->size || args->size > obj->size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 586 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 587 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 588 | } |
| 589 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 590 | if (args->size == 0) |
| 591 | goto out; |
| 592 | |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 593 | if (!access_ok(VERIFY_WRITE, |
| 594 | (char __user *)(uintptr_t)args->data_ptr, |
| 595 | args->size)) { |
| 596 | ret = -EFAULT; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 597 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 598 | } |
| 599 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 600 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 601 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 602 | } else { |
| 603 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
| 604 | if (ret != 0) |
| 605 | ret = i915_gem_shmem_pread_slow(dev, obj, args, |
| 606 | file_priv); |
| 607 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 608 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 609 | out: |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 610 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 611 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 612 | } |
| 613 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 614 | /* This is the fast write path which cannot handle |
| 615 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 616 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 617 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 618 | static inline int |
| 619 | fast_user_write(struct io_mapping *mapping, |
| 620 | loff_t page_base, int page_offset, |
| 621 | char __user *user_data, |
| 622 | int length) |
| 623 | { |
| 624 | char *vaddr_atomic; |
| 625 | unsigned long unwritten; |
| 626 | |
Chris Wilson | fca3ec0 | 2010-08-04 14:34:24 +0100 | [diff] [blame] | 627 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 628 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 629 | user_data, length); |
Chris Wilson | fca3ec0 | 2010-08-04 14:34:24 +0100 | [diff] [blame] | 630 | io_mapping_unmap_atomic(vaddr_atomic, KM_USER0); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 631 | if (unwritten) |
| 632 | return -EFAULT; |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 633 | return 0; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 634 | } |
| 635 | |
| 636 | /* Here's the write path which can sleep for |
| 637 | * page faults |
| 638 | */ |
| 639 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 640 | static inline void |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 641 | slow_kernel_write(struct io_mapping *mapping, |
| 642 | loff_t gtt_base, int gtt_offset, |
| 643 | struct page *user_page, int user_offset, |
| 644 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 645 | { |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 646 | char __iomem *dst_vaddr; |
| 647 | char *src_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 648 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 649 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
| 650 | src_vaddr = kmap(user_page); |
| 651 | |
| 652 | memcpy_toio(dst_vaddr + gtt_offset, |
| 653 | src_vaddr + user_offset, |
| 654 | length); |
| 655 | |
| 656 | kunmap(user_page); |
| 657 | io_mapping_unmap(dst_vaddr); |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 658 | } |
| 659 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 660 | static inline int |
| 661 | fast_shmem_write(struct page **pages, |
| 662 | loff_t page_base, int page_offset, |
| 663 | char __user *data, |
| 664 | int length) |
| 665 | { |
| 666 | char __iomem *vaddr; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 667 | unsigned long unwritten; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 668 | |
| 669 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 670 | if (vaddr == NULL) |
| 671 | return -ENOMEM; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 672 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 673 | kunmap_atomic(vaddr, KM_USER0); |
| 674 | |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 675 | if (unwritten) |
| 676 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 677 | return 0; |
| 678 | } |
| 679 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 680 | /** |
| 681 | * This is the fast pwrite path, where we copy the data directly from the |
| 682 | * user into the GTT, uncached. |
| 683 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 684 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 685 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 686 | struct drm_i915_gem_pwrite *args, |
| 687 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 688 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 689 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 690 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 691 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 692 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 693 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 694 | int page_offset, page_length; |
| 695 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 696 | |
| 697 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 698 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 699 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 700 | ret = i915_mutex_lock_interruptible(dev); |
| 701 | if (ret) |
| 702 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 703 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 704 | ret = i915_gem_object_pin(obj, 0); |
| 705 | if (ret) { |
| 706 | mutex_unlock(&dev->struct_mutex); |
| 707 | return ret; |
| 708 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 709 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 710 | if (ret) |
| 711 | goto fail; |
| 712 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 713 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 714 | offset = obj_priv->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 715 | |
| 716 | while (remain > 0) { |
| 717 | /* Operation in this page |
| 718 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 719 | * page_base = page offset within aperture |
| 720 | * page_offset = offset within page |
| 721 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 722 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 723 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 724 | page_offset = offset & (PAGE_SIZE-1); |
| 725 | page_length = remain; |
| 726 | if ((page_offset + remain) > PAGE_SIZE) |
| 727 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 728 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 729 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, |
| 730 | page_offset, user_data, page_length); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 731 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 732 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 733 | * source page isn't available. Return the error and we'll |
| 734 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 735 | */ |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 736 | if (ret) |
| 737 | goto fail; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 738 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 739 | remain -= page_length; |
| 740 | user_data += page_length; |
| 741 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 742 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 743 | |
| 744 | fail: |
| 745 | i915_gem_object_unpin(obj); |
| 746 | mutex_unlock(&dev->struct_mutex); |
| 747 | |
| 748 | return ret; |
| 749 | } |
| 750 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 751 | /** |
| 752 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 753 | * the memory and maps it using kmap_atomic for copying. |
| 754 | * |
| 755 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 756 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 757 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 758 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 759 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 760 | struct drm_i915_gem_pwrite *args, |
| 761 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 762 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 763 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 764 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 765 | ssize_t remain; |
| 766 | loff_t gtt_page_base, offset; |
| 767 | loff_t first_data_page, last_data_page, num_pages; |
| 768 | loff_t pinned_pages, i; |
| 769 | struct page **user_pages; |
| 770 | struct mm_struct *mm = current->mm; |
| 771 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 772 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 773 | uint64_t data_ptr = args->data_ptr; |
| 774 | |
| 775 | remain = args->size; |
| 776 | |
| 777 | /* Pin the user pages containing the data. We can't fault while |
| 778 | * holding the struct mutex, and all of the pwrite implementations |
| 779 | * want to hold it while dereferencing the user data. |
| 780 | */ |
| 781 | first_data_page = data_ptr / PAGE_SIZE; |
| 782 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 783 | num_pages = last_data_page - first_data_page + 1; |
| 784 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 785 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 786 | if (user_pages == NULL) |
| 787 | return -ENOMEM; |
| 788 | |
| 789 | down_read(&mm->mmap_sem); |
| 790 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 791 | num_pages, 0, 0, user_pages, NULL); |
| 792 | up_read(&mm->mmap_sem); |
| 793 | if (pinned_pages < num_pages) { |
| 794 | ret = -EFAULT; |
| 795 | goto out_unpin_pages; |
| 796 | } |
| 797 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 798 | ret = i915_mutex_lock_interruptible(dev); |
| 799 | if (ret) |
| 800 | goto out_unpin_pages; |
| 801 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 802 | ret = i915_gem_object_pin(obj, 0); |
| 803 | if (ret) |
| 804 | goto out_unlock; |
| 805 | |
| 806 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 807 | if (ret) |
| 808 | goto out_unpin_object; |
| 809 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 810 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 811 | offset = obj_priv->gtt_offset + args->offset; |
| 812 | |
| 813 | while (remain > 0) { |
| 814 | /* Operation in this page |
| 815 | * |
| 816 | * gtt_page_base = page offset within aperture |
| 817 | * gtt_page_offset = offset within page in aperture |
| 818 | * data_page_index = page number in get_user_pages return |
| 819 | * data_page_offset = offset with data_page_index page. |
| 820 | * page_length = bytes to copy for this page |
| 821 | */ |
| 822 | gtt_page_base = offset & PAGE_MASK; |
| 823 | gtt_page_offset = offset & ~PAGE_MASK; |
| 824 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 825 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 826 | |
| 827 | page_length = remain; |
| 828 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 829 | page_length = PAGE_SIZE - gtt_page_offset; |
| 830 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 831 | page_length = PAGE_SIZE - data_page_offset; |
| 832 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 833 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 834 | gtt_page_base, gtt_page_offset, |
| 835 | user_pages[data_page_index], |
| 836 | data_page_offset, |
| 837 | page_length); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 838 | |
| 839 | remain -= page_length; |
| 840 | offset += page_length; |
| 841 | data_ptr += page_length; |
| 842 | } |
| 843 | |
| 844 | out_unpin_object: |
| 845 | i915_gem_object_unpin(obj); |
| 846 | out_unlock: |
| 847 | mutex_unlock(&dev->struct_mutex); |
| 848 | out_unpin_pages: |
| 849 | for (i = 0; i < pinned_pages; i++) |
| 850 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 851 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 852 | |
| 853 | return ret; |
| 854 | } |
| 855 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 856 | /** |
| 857 | * This is the fast shmem pwrite path, which attempts to directly |
| 858 | * copy_from_user into the kmapped pages backing the object. |
| 859 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 860 | static int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 861 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 862 | struct drm_i915_gem_pwrite *args, |
| 863 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 864 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 865 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 866 | ssize_t remain; |
| 867 | loff_t offset, page_base; |
| 868 | char __user *user_data; |
| 869 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 870 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 871 | |
| 872 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 873 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 874 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 875 | ret = i915_mutex_lock_interruptible(dev); |
| 876 | if (ret) |
| 877 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 878 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 879 | ret = i915_gem_object_get_pages(obj, 0); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 880 | if (ret != 0) |
| 881 | goto fail_unlock; |
| 882 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 883 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 884 | if (ret != 0) |
| 885 | goto fail_put_pages; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 886 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 887 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 888 | offset = args->offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 889 | obj_priv->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 890 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 891 | while (remain > 0) { |
| 892 | /* Operation in this page |
| 893 | * |
| 894 | * page_base = page offset within aperture |
| 895 | * page_offset = offset within page |
| 896 | * page_length = bytes to copy for this page |
| 897 | */ |
| 898 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 899 | page_offset = offset & (PAGE_SIZE-1); |
| 900 | page_length = remain; |
| 901 | if ((page_offset + remain) > PAGE_SIZE) |
| 902 | page_length = PAGE_SIZE - page_offset; |
| 903 | |
| 904 | ret = fast_shmem_write(obj_priv->pages, |
| 905 | page_base, page_offset, |
| 906 | user_data, page_length); |
| 907 | if (ret) |
| 908 | goto fail_put_pages; |
| 909 | |
| 910 | remain -= page_length; |
| 911 | user_data += page_length; |
| 912 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 913 | } |
| 914 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 915 | fail_put_pages: |
| 916 | i915_gem_object_put_pages(obj); |
| 917 | fail_unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 918 | mutex_unlock(&dev->struct_mutex); |
| 919 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 920 | return ret; |
| 921 | } |
| 922 | |
| 923 | /** |
| 924 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 925 | * the memory and maps it using kmap_atomic for copying. |
| 926 | * |
| 927 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 928 | * struct_mutex is held. |
| 929 | */ |
| 930 | static int |
| 931 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 932 | struct drm_i915_gem_pwrite *args, |
| 933 | struct drm_file *file_priv) |
| 934 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 935 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 936 | struct mm_struct *mm = current->mm; |
| 937 | struct page **user_pages; |
| 938 | ssize_t remain; |
| 939 | loff_t offset, pinned_pages, i; |
| 940 | loff_t first_data_page, last_data_page, num_pages; |
| 941 | int shmem_page_index, shmem_page_offset; |
| 942 | int data_page_index, data_page_offset; |
| 943 | int page_length; |
| 944 | int ret; |
| 945 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 946 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 947 | |
| 948 | remain = args->size; |
| 949 | |
| 950 | /* Pin the user pages containing the data. We can't fault while |
| 951 | * holding the struct mutex, and all of the pwrite implementations |
| 952 | * want to hold it while dereferencing the user data. |
| 953 | */ |
| 954 | first_data_page = data_ptr / PAGE_SIZE; |
| 955 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 956 | num_pages = last_data_page - first_data_page + 1; |
| 957 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 958 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 959 | if (user_pages == NULL) |
| 960 | return -ENOMEM; |
| 961 | |
| 962 | down_read(&mm->mmap_sem); |
| 963 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 964 | num_pages, 0, 0, user_pages, NULL); |
| 965 | up_read(&mm->mmap_sem); |
| 966 | if (pinned_pages < num_pages) { |
| 967 | ret = -EFAULT; |
| 968 | goto fail_put_user_pages; |
| 969 | } |
| 970 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 971 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 972 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 973 | ret = i915_mutex_lock_interruptible(dev); |
| 974 | if (ret) |
| 975 | goto fail_put_user_pages; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 976 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 977 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 978 | if (ret) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 979 | goto fail_unlock; |
| 980 | |
| 981 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 982 | if (ret != 0) |
| 983 | goto fail_put_pages; |
| 984 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 985 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 986 | offset = args->offset; |
| 987 | obj_priv->dirty = 1; |
| 988 | |
| 989 | while (remain > 0) { |
| 990 | /* Operation in this page |
| 991 | * |
| 992 | * shmem_page_index = page number within shmem file |
| 993 | * shmem_page_offset = offset within page in shmem file |
| 994 | * data_page_index = page number in get_user_pages return |
| 995 | * data_page_offset = offset with data_page_index page. |
| 996 | * page_length = bytes to copy for this page |
| 997 | */ |
| 998 | shmem_page_index = offset / PAGE_SIZE; |
| 999 | shmem_page_offset = offset & ~PAGE_MASK; |
| 1000 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 1001 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 1002 | |
| 1003 | page_length = remain; |
| 1004 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 1005 | page_length = PAGE_SIZE - shmem_page_offset; |
| 1006 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 1007 | page_length = PAGE_SIZE - data_page_offset; |
| 1008 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1009 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 1010 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1011 | shmem_page_offset, |
| 1012 | user_pages[data_page_index], |
| 1013 | data_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 1014 | page_length, |
| 1015 | 0); |
| 1016 | } else { |
| 1017 | slow_shmem_copy(obj_priv->pages[shmem_page_index], |
| 1018 | shmem_page_offset, |
| 1019 | user_pages[data_page_index], |
| 1020 | data_page_offset, |
| 1021 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1022 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1023 | |
| 1024 | remain -= page_length; |
| 1025 | data_ptr += page_length; |
| 1026 | offset += page_length; |
| 1027 | } |
| 1028 | |
| 1029 | fail_put_pages: |
| 1030 | i915_gem_object_put_pages(obj); |
| 1031 | fail_unlock: |
| 1032 | mutex_unlock(&dev->struct_mutex); |
| 1033 | fail_put_user_pages: |
| 1034 | for (i = 0; i < pinned_pages; i++) |
| 1035 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1036 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1037 | |
| 1038 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1039 | } |
| 1040 | |
| 1041 | /** |
| 1042 | * Writes data to the object referenced by handle. |
| 1043 | * |
| 1044 | * On error, the contents of the buffer that were to be modified are undefined. |
| 1045 | */ |
| 1046 | int |
| 1047 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1048 | struct drm_file *file_priv) |
| 1049 | { |
| 1050 | struct drm_i915_gem_pwrite *args = data; |
| 1051 | struct drm_gem_object *obj; |
| 1052 | struct drm_i915_gem_object *obj_priv; |
| 1053 | int ret = 0; |
| 1054 | |
| 1055 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1056 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1057 | return -ENOENT; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1058 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1059 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 1060 | /* Bounds check destination. */ |
| 1061 | if (args->offset > obj->size || args->size > obj->size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1062 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1063 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1064 | } |
| 1065 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1066 | if (args->size == 0) |
| 1067 | goto out; |
| 1068 | |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1069 | if (!access_ok(VERIFY_READ, |
| 1070 | (char __user *)(uintptr_t)args->data_ptr, |
| 1071 | args->size)) { |
| 1072 | ret = -EFAULT; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1073 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1074 | } |
| 1075 | |
| 1076 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1077 | * it would end up going through the fenced access, and we'll get |
| 1078 | * different detiling behavior between reading and writing. |
| 1079 | * pread/pwrite currently are reading and writing from the CPU |
| 1080 | * perspective, requiring manual detiling by the client. |
| 1081 | */ |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1082 | if (obj_priv->phys_obj) |
| 1083 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); |
| 1084 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1085 | obj_priv->gtt_space && |
Chris Wilson | 9b8c4a0 | 2010-05-27 14:21:01 +0100 | [diff] [blame] | 1086 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 1087 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
| 1088 | if (ret == -EFAULT) { |
| 1089 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, |
| 1090 | file_priv); |
| 1091 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1092 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
| 1093 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1094 | } else { |
| 1095 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); |
| 1096 | if (ret == -EFAULT) { |
| 1097 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, |
| 1098 | file_priv); |
| 1099 | } |
| 1100 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1101 | |
| 1102 | #if WATCH_PWRITE |
| 1103 | if (ret) |
| 1104 | DRM_INFO("pwrite failed %d\n", ret); |
| 1105 | #endif |
| 1106 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1107 | out: |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1108 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1109 | return ret; |
| 1110 | } |
| 1111 | |
| 1112 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1113 | * Called when user space prepares to use an object with the CPU, either |
| 1114 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1115 | */ |
| 1116 | int |
| 1117 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1118 | struct drm_file *file_priv) |
| 1119 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1120 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1121 | struct drm_i915_gem_set_domain *args = data; |
| 1122 | struct drm_gem_object *obj; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1123 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1124 | uint32_t read_domains = args->read_domains; |
| 1125 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1126 | int ret; |
| 1127 | |
| 1128 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1129 | return -ENODEV; |
| 1130 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1131 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1132 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1133 | return -EINVAL; |
| 1134 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1135 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1136 | return -EINVAL; |
| 1137 | |
| 1138 | /* Having something in the write domain implies it's in the read |
| 1139 | * domain, and only that read domain. Enforce that in the request. |
| 1140 | */ |
| 1141 | if (write_domain != 0 && read_domains != write_domain) |
| 1142 | return -EINVAL; |
| 1143 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1144 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1145 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1146 | return -ENOENT; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1147 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1148 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1149 | ret = i915_mutex_lock_interruptible(dev); |
| 1150 | if (ret) { |
| 1151 | drm_gem_object_unreference_unlocked(obj); |
| 1152 | return ret; |
| 1153 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1154 | |
| 1155 | intel_mark_busy(dev, obj); |
| 1156 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1157 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1158 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1159 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1160 | /* Update the LRU on the fence for the CPU access that's |
| 1161 | * about to occur. |
| 1162 | */ |
| 1163 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1164 | struct drm_i915_fence_reg *reg = |
| 1165 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1166 | list_move_tail(®->lru_list, |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1167 | &dev_priv->mm.fence_list); |
| 1168 | } |
| 1169 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1170 | /* Silently promote "you're not bound, there was nothing to do" |
| 1171 | * to success, since the client was just asking us to |
| 1172 | * make sure everything was done. |
| 1173 | */ |
| 1174 | if (ret == -EINVAL) |
| 1175 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1176 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1177 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1178 | } |
| 1179 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1180 | /* Maintain LRU order of "inactive" objects */ |
| 1181 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) |
| 1182 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 1183 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1184 | drm_gem_object_unreference(obj); |
| 1185 | mutex_unlock(&dev->struct_mutex); |
| 1186 | return ret; |
| 1187 | } |
| 1188 | |
| 1189 | /** |
| 1190 | * Called when user space has done writes to this buffer |
| 1191 | */ |
| 1192 | int |
| 1193 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1194 | struct drm_file *file_priv) |
| 1195 | { |
| 1196 | struct drm_i915_gem_sw_finish *args = data; |
| 1197 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1198 | int ret = 0; |
| 1199 | |
| 1200 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1201 | return -ENODEV; |
| 1202 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1203 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1204 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1205 | return -ENOENT; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1206 | |
| 1207 | ret = i915_mutex_lock_interruptible(dev); |
| 1208 | if (ret) { |
| 1209 | drm_gem_object_unreference_unlocked(obj); |
| 1210 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1211 | } |
| 1212 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1213 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 1214 | if (to_intel_bo(obj)->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1215 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1216 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1217 | drm_gem_object_unreference(obj); |
| 1218 | mutex_unlock(&dev->struct_mutex); |
| 1219 | return ret; |
| 1220 | } |
| 1221 | |
| 1222 | /** |
| 1223 | * Maps the contents of an object, returning the address it is mapped |
| 1224 | * into. |
| 1225 | * |
| 1226 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1227 | * imply a ref on the object itself. |
| 1228 | */ |
| 1229 | int |
| 1230 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1231 | struct drm_file *file_priv) |
| 1232 | { |
| 1233 | struct drm_i915_gem_mmap *args = data; |
| 1234 | struct drm_gem_object *obj; |
| 1235 | loff_t offset; |
| 1236 | unsigned long addr; |
| 1237 | |
| 1238 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1239 | return -ENODEV; |
| 1240 | |
| 1241 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1242 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1243 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1244 | |
| 1245 | offset = args->offset; |
| 1246 | |
| 1247 | down_write(¤t->mm->mmap_sem); |
| 1248 | addr = do_mmap(obj->filp, 0, args->size, |
| 1249 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1250 | args->offset); |
| 1251 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1252 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1253 | if (IS_ERR((void *)addr)) |
| 1254 | return addr; |
| 1255 | |
| 1256 | args->addr_ptr = (uint64_t) addr; |
| 1257 | |
| 1258 | return 0; |
| 1259 | } |
| 1260 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1261 | /** |
| 1262 | * i915_gem_fault - fault a page into the GTT |
| 1263 | * vma: VMA in question |
| 1264 | * vmf: fault info |
| 1265 | * |
| 1266 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1267 | * from userspace. The fault handler takes care of binding the object to |
| 1268 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1269 | * only if needed based on whether the old reg is still valid or the object |
| 1270 | * is tiled) and inserting a new PTE into the faulting process. |
| 1271 | * |
| 1272 | * Note that the faulting process may involve evicting existing objects |
| 1273 | * from the GTT and/or fence registers to make room. So performance may |
| 1274 | * suffer if the GTT working set is large or there are few fence registers |
| 1275 | * left. |
| 1276 | */ |
| 1277 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1278 | { |
| 1279 | struct drm_gem_object *obj = vma->vm_private_data; |
| 1280 | struct drm_device *dev = obj->dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1281 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1282 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1283 | pgoff_t page_offset; |
| 1284 | unsigned long pfn; |
| 1285 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1286 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1287 | |
| 1288 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1289 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1290 | PAGE_SHIFT; |
| 1291 | |
| 1292 | /* Now bind it into the GTT if needed */ |
| 1293 | mutex_lock(&dev->struct_mutex); |
| 1294 | if (!obj_priv->gtt_space) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1295 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1296 | if (ret) |
| 1297 | goto unlock; |
Kristian Høgsberg | 07f4f3e | 2009-05-27 14:37:28 -0400 | [diff] [blame] | 1298 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1299 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1300 | if (ret) |
| 1301 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1302 | } |
| 1303 | |
| 1304 | /* Need a new fence register? */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1305 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1306 | ret = i915_gem_object_get_fence_reg(obj, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1307 | if (ret) |
| 1308 | goto unlock; |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1309 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1310 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1311 | if (i915_gem_object_is_inactive(obj_priv)) |
| 1312 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 1313 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1314 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
| 1315 | page_offset; |
| 1316 | |
| 1317 | /* Finally, remap it using the new GTT offset */ |
| 1318 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1319 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1320 | mutex_unlock(&dev->struct_mutex); |
| 1321 | |
| 1322 | switch (ret) { |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1323 | case 0: |
| 1324 | case -ERESTARTSYS: |
| 1325 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1326 | case -ENOMEM: |
| 1327 | case -EAGAIN: |
| 1328 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1329 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1330 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1331 | } |
| 1332 | } |
| 1333 | |
| 1334 | /** |
| 1335 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1336 | * @obj: obj in question |
| 1337 | * |
| 1338 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1339 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1340 | * up the object based on the offset and sets up the various memory mapping |
| 1341 | * structures. |
| 1342 | * |
| 1343 | * This routine allocates and attaches a fake offset for @obj. |
| 1344 | */ |
| 1345 | static int |
| 1346 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) |
| 1347 | { |
| 1348 | struct drm_device *dev = obj->dev; |
| 1349 | struct drm_gem_mm *mm = dev->mm_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1350 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1351 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1352 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1353 | int ret = 0; |
| 1354 | |
| 1355 | /* Set the object up for mmap'ing */ |
| 1356 | list = &obj->map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1357 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1358 | if (!list->map) |
| 1359 | return -ENOMEM; |
| 1360 | |
| 1361 | map = list->map; |
| 1362 | map->type = _DRM_GEM; |
| 1363 | map->size = obj->size; |
| 1364 | map->handle = obj; |
| 1365 | |
| 1366 | /* Get a DRM GEM mmap offset allocated... */ |
| 1367 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
| 1368 | obj->size / PAGE_SIZE, 0, 0); |
| 1369 | if (!list->file_offset_node) { |
| 1370 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1371 | ret = -ENOSPC; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1372 | goto out_free_list; |
| 1373 | } |
| 1374 | |
| 1375 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
| 1376 | obj->size / PAGE_SIZE, 0); |
| 1377 | if (!list->file_offset_node) { |
| 1378 | ret = -ENOMEM; |
| 1379 | goto out_free_list; |
| 1380 | } |
| 1381 | |
| 1382 | list->hash.key = list->file_offset_node->start; |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1383 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
| 1384 | if (ret) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1385 | DRM_ERROR("failed to add to map hash\n"); |
| 1386 | goto out_free_mm; |
| 1387 | } |
| 1388 | |
| 1389 | /* By now we should be all set, any drm_mmap request on the offset |
| 1390 | * below will get to our mmap & fault handler */ |
| 1391 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; |
| 1392 | |
| 1393 | return 0; |
| 1394 | |
| 1395 | out_free_mm: |
| 1396 | drm_mm_put_block(list->file_offset_node); |
| 1397 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1398 | kfree(list->map); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1399 | |
| 1400 | return ret; |
| 1401 | } |
| 1402 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1403 | /** |
| 1404 | * i915_gem_release_mmap - remove physical page mappings |
| 1405 | * @obj: obj in question |
| 1406 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1407 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1408 | * relinquish ownership of the pages back to the system. |
| 1409 | * |
| 1410 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1411 | * object through the GTT and then lose the fence register due to |
| 1412 | * resource pressure. Similarly if the object has been moved out of the |
| 1413 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1414 | * mapping will then trigger a page fault on the next user access, allowing |
| 1415 | * fixup by i915_gem_fault(). |
| 1416 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1417 | void |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1418 | i915_gem_release_mmap(struct drm_gem_object *obj) |
| 1419 | { |
| 1420 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1421 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1422 | |
| 1423 | if (dev->dev_mapping) |
| 1424 | unmap_mapping_range(dev->dev_mapping, |
| 1425 | obj_priv->mmap_offset, obj->size, 1); |
| 1426 | } |
| 1427 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1428 | static void |
| 1429 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) |
| 1430 | { |
| 1431 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1432 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1433 | struct drm_gem_mm *mm = dev->mm_private; |
| 1434 | struct drm_map_list *list; |
| 1435 | |
| 1436 | list = &obj->map_list; |
| 1437 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
| 1438 | |
| 1439 | if (list->file_offset_node) { |
| 1440 | drm_mm_put_block(list->file_offset_node); |
| 1441 | list->file_offset_node = NULL; |
| 1442 | } |
| 1443 | |
| 1444 | if (list->map) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1445 | kfree(list->map); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1446 | list->map = NULL; |
| 1447 | } |
| 1448 | |
| 1449 | obj_priv->mmap_offset = 0; |
| 1450 | } |
| 1451 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1452 | /** |
| 1453 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1454 | * @obj: object to check |
| 1455 | * |
| 1456 | * Return the required GTT alignment for an object, taking into account |
| 1457 | * potential fence register mapping if needed. |
| 1458 | */ |
| 1459 | static uint32_t |
| 1460 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) |
| 1461 | { |
| 1462 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1463 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1464 | int start, i; |
| 1465 | |
| 1466 | /* |
| 1467 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1468 | * if a fence register is needed for the object. |
| 1469 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1470 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1471 | return 4096; |
| 1472 | |
| 1473 | /* |
| 1474 | * Previous chips need to be aligned to the size of the smallest |
| 1475 | * fence register that can contain the object. |
| 1476 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1477 | if (INTEL_INFO(dev)->gen == 3) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1478 | start = 1024*1024; |
| 1479 | else |
| 1480 | start = 512*1024; |
| 1481 | |
| 1482 | for (i = start; i < obj->size; i <<= 1) |
| 1483 | ; |
| 1484 | |
| 1485 | return i; |
| 1486 | } |
| 1487 | |
| 1488 | /** |
| 1489 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1490 | * @dev: DRM device |
| 1491 | * @data: GTT mapping ioctl data |
| 1492 | * @file_priv: GEM object info |
| 1493 | * |
| 1494 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1495 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1496 | * up so we can get faults in the handler above. |
| 1497 | * |
| 1498 | * The fault handler will take care of binding the object into the GTT |
| 1499 | * (since it may have been evicted to make room for something), allocating |
| 1500 | * a fence register, and mapping the appropriate aperture address into |
| 1501 | * userspace. |
| 1502 | */ |
| 1503 | int |
| 1504 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1505 | struct drm_file *file_priv) |
| 1506 | { |
| 1507 | struct drm_i915_gem_mmap_gtt *args = data; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1508 | struct drm_gem_object *obj; |
| 1509 | struct drm_i915_gem_object *obj_priv; |
| 1510 | int ret; |
| 1511 | |
| 1512 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1513 | return -ENODEV; |
| 1514 | |
| 1515 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1516 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1517 | return -ENOENT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1518 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1519 | ret = i915_mutex_lock_interruptible(dev); |
| 1520 | if (ret) { |
| 1521 | drm_gem_object_unreference_unlocked(obj); |
| 1522 | return ret; |
| 1523 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1524 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1525 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1526 | |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1527 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 1528 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
| 1529 | drm_gem_object_unreference(obj); |
| 1530 | mutex_unlock(&dev->struct_mutex); |
| 1531 | return -EINVAL; |
| 1532 | } |
| 1533 | |
| 1534 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1535 | if (!obj_priv->mmap_offset) { |
| 1536 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1537 | if (ret) { |
| 1538 | drm_gem_object_unreference(obj); |
| 1539 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1540 | return ret; |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1541 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1542 | } |
| 1543 | |
| 1544 | args->offset = obj_priv->mmap_offset; |
| 1545 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1546 | /* |
| 1547 | * Pull it into the GTT so that we have a page list (makes the |
| 1548 | * initial fault faster and any subsequent flushing possible). |
| 1549 | */ |
| 1550 | if (!obj_priv->agp_mem) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1551 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1552 | if (ret) { |
| 1553 | drm_gem_object_unreference(obj); |
| 1554 | mutex_unlock(&dev->struct_mutex); |
| 1555 | return ret; |
| 1556 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1557 | } |
| 1558 | |
| 1559 | drm_gem_object_unreference(obj); |
| 1560 | mutex_unlock(&dev->struct_mutex); |
| 1561 | |
| 1562 | return 0; |
| 1563 | } |
| 1564 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1565 | static void |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1566 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1567 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1568 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1569 | int page_count = obj->size / PAGE_SIZE; |
| 1570 | int i; |
| 1571 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1572 | BUG_ON(obj_priv->pages_refcount == 0); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1573 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1574 | |
| 1575 | if (--obj_priv->pages_refcount != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1576 | return; |
| 1577 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1578 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1579 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1580 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1581 | if (obj_priv->madv == I915_MADV_DONTNEED) |
Chris Wilson | 13a05fd | 2009-09-20 23:03:19 +0100 | [diff] [blame] | 1582 | obj_priv->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1583 | |
| 1584 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1585 | if (obj_priv->dirty) |
| 1586 | set_page_dirty(obj_priv->pages[i]); |
| 1587 | |
| 1588 | if (obj_priv->madv == I915_MADV_WILLNEED) |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1589 | mark_page_accessed(obj_priv->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1590 | |
| 1591 | page_cache_release(obj_priv->pages[i]); |
| 1592 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1593 | obj_priv->dirty = 0; |
| 1594 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1595 | drm_free_large(obj_priv->pages); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1596 | obj_priv->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1597 | } |
| 1598 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1599 | static uint32_t |
| 1600 | i915_gem_next_request_seqno(struct drm_device *dev, |
| 1601 | struct intel_ring_buffer *ring) |
| 1602 | { |
| 1603 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1604 | |
| 1605 | ring->outstanding_lazy_request = true; |
| 1606 | return dev_priv->next_seqno; |
| 1607 | } |
| 1608 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1609 | static void |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1610 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1611 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1612 | { |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1613 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1614 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1615 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1616 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1617 | BUG_ON(ring == NULL); |
| 1618 | obj_priv->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1619 | |
| 1620 | /* Add a reference if we're newly entering the active list. */ |
| 1621 | if (!obj_priv->active) { |
| 1622 | drm_gem_object_reference(obj); |
| 1623 | obj_priv->active = 1; |
| 1624 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1625 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1626 | /* Move from whatever list we were on to the tail of execution. */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1627 | list_move_tail(&obj_priv->list, &ring->active_list); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1628 | obj_priv->last_rendering_seqno = seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1629 | } |
| 1630 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1631 | static void |
| 1632 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) |
| 1633 | { |
| 1634 | struct drm_device *dev = obj->dev; |
| 1635 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1636 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1637 | |
| 1638 | BUG_ON(!obj_priv->active); |
| 1639 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); |
| 1640 | obj_priv->last_rendering_seqno = 0; |
| 1641 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1642 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1643 | /* Immediately discard the backing storage */ |
| 1644 | static void |
| 1645 | i915_gem_object_truncate(struct drm_gem_object *obj) |
| 1646 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1647 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1648 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1649 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1650 | /* Our goal here is to return as much of the memory as |
| 1651 | * is possible back to the system as we are called from OOM. |
| 1652 | * To do this we must instruct the shmfs to drop all of its |
| 1653 | * backing pages, *now*. Here we mirror the actions taken |
| 1654 | * when by shmem_delete_inode() to release the backing store. |
| 1655 | */ |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1656 | inode = obj->filp->f_path.dentry->d_inode; |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1657 | truncate_inode_pages(inode->i_mapping, 0); |
| 1658 | if (inode->i_op->truncate_range) |
| 1659 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1660 | |
| 1661 | obj_priv->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1662 | } |
| 1663 | |
| 1664 | static inline int |
| 1665 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) |
| 1666 | { |
| 1667 | return obj_priv->madv == I915_MADV_DONTNEED; |
| 1668 | } |
| 1669 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1670 | static void |
| 1671 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) |
| 1672 | { |
| 1673 | struct drm_device *dev = obj->dev; |
| 1674 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1675 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1676 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1677 | if (obj_priv->pin_count != 0) |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 1678 | list_move_tail(&obj_priv->list, &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1679 | else |
| 1680 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 1681 | |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 1682 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
| 1683 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1684 | obj_priv->last_rendering_seqno = 0; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1685 | obj_priv->ring = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1686 | if (obj_priv->active) { |
| 1687 | obj_priv->active = 0; |
| 1688 | drm_gem_object_unreference(obj); |
| 1689 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1690 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1691 | } |
| 1692 | |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 1693 | static void |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1694 | i915_gem_process_flushing_list(struct drm_device *dev, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1695 | uint32_t flush_domains, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1696 | struct intel_ring_buffer *ring) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1697 | { |
| 1698 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1699 | struct drm_i915_gem_object *obj_priv, *next; |
| 1700 | |
| 1701 | list_for_each_entry_safe(obj_priv, next, |
| 1702 | &dev_priv->mm.gpu_write_list, |
| 1703 | gpu_write_list) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 1704 | struct drm_gem_object *obj = &obj_priv->base; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1705 | |
Chris Wilson | 2b6efaa | 2010-09-14 17:04:02 +0100 | [diff] [blame] | 1706 | if (obj->write_domain & flush_domains && |
| 1707 | obj_priv->ring == ring) { |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1708 | uint32_t old_write_domain = obj->write_domain; |
| 1709 | |
| 1710 | obj->write_domain = 0; |
| 1711 | list_del_init(&obj_priv->gpu_write_list); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1712 | i915_gem_object_move_to_active(obj, ring); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1713 | |
| 1714 | /* update the fence lru list */ |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1715 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 1716 | struct drm_i915_fence_reg *reg = |
| 1717 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1718 | list_move_tail(®->lru_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1719 | &dev_priv->mm.fence_list); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1720 | } |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1721 | |
| 1722 | trace_i915_gem_object_change_domain(obj, |
| 1723 | obj->read_domains, |
| 1724 | old_write_domain); |
| 1725 | } |
| 1726 | } |
| 1727 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1728 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1729 | uint32_t |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1730 | i915_add_request(struct drm_device *dev, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1731 | struct drm_file *file, |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1732 | struct drm_i915_gem_request *request, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1733 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1734 | { |
| 1735 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1736 | struct drm_i915_file_private *file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1737 | uint32_t seqno; |
| 1738 | int was_empty; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1739 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1740 | if (file != NULL) |
| 1741 | file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1742 | |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1743 | if (request == NULL) { |
| 1744 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1745 | if (request == NULL) |
| 1746 | return 0; |
| 1747 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1748 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1749 | seqno = ring->add_request(dev, ring, 0); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1750 | ring->outstanding_lazy_request = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1751 | |
| 1752 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1753 | request->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1754 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1755 | was_empty = list_empty(&ring->request_list); |
| 1756 | list_add_tail(&request->list, &ring->request_list); |
| 1757 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1758 | if (file_priv) { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1759 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1760 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1761 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1762 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1763 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1764 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1765 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1766 | if (!dev_priv->mm.suspended) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1767 | mod_timer(&dev_priv->hangcheck_timer, |
| 1768 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1769 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1770 | queue_delayed_work(dev_priv->wq, |
| 1771 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1772 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1773 | return seqno; |
| 1774 | } |
| 1775 | |
| 1776 | /** |
| 1777 | * Command execution barrier |
| 1778 | * |
| 1779 | * Ensures that all commands in the ring are finished |
| 1780 | * before signalling the CPU |
| 1781 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1782 | static void |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1783 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1784 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1785 | uint32_t flush_domains = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1786 | |
| 1787 | /* The sampler always gets flushed on i965 (sigh) */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1788 | if (INTEL_INFO(dev)->gen >= 4) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1789 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1790 | |
| 1791 | ring->flush(dev, ring, |
| 1792 | I915_GEM_DOMAIN_COMMAND, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1793 | } |
| 1794 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1795 | static inline void |
| 1796 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1797 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1798 | struct drm_i915_file_private *file_priv = request->file_priv; |
| 1799 | |
| 1800 | if (!file_priv) |
| 1801 | return; |
| 1802 | |
| 1803 | spin_lock(&file_priv->mm.lock); |
| 1804 | list_del(&request->client_list); |
| 1805 | request->file_priv = NULL; |
| 1806 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1807 | } |
| 1808 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1809 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1810 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1811 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1812 | while (!list_empty(&ring->request_list)) { |
| 1813 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1814 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1815 | request = list_first_entry(&ring->request_list, |
| 1816 | struct drm_i915_gem_request, |
| 1817 | list); |
| 1818 | |
| 1819 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1820 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1821 | kfree(request); |
| 1822 | } |
| 1823 | |
| 1824 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1825 | struct drm_i915_gem_object *obj_priv; |
| 1826 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1827 | obj_priv = list_first_entry(&ring->active_list, |
| 1828 | struct drm_i915_gem_object, |
| 1829 | list); |
| 1830 | |
| 1831 | obj_priv->base.write_domain = 0; |
| 1832 | list_del_init(&obj_priv->gpu_write_list); |
| 1833 | i915_gem_object_move_to_inactive(&obj_priv->base); |
| 1834 | } |
| 1835 | } |
| 1836 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1837 | void i915_gem_reset(struct drm_device *dev) |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1838 | { |
| 1839 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1840 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1841 | int i; |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1842 | |
| 1843 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
| 1844 | if (HAS_BSD(dev)) |
| 1845 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
| 1846 | |
| 1847 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1848 | * to be lost on reset along with the data, so simply move the |
| 1849 | * lost bo to the inactive list. |
| 1850 | */ |
| 1851 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1852 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, |
| 1853 | struct drm_i915_gem_object, |
| 1854 | list); |
| 1855 | |
| 1856 | obj_priv->base.write_domain = 0; |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1857 | list_del_init(&obj_priv->gpu_write_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1858 | i915_gem_object_move_to_inactive(&obj_priv->base); |
| 1859 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1860 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1861 | /* Move everything out of the GPU domains to ensure we do any |
| 1862 | * necessary invalidation upon reuse. |
| 1863 | */ |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1864 | list_for_each_entry(obj_priv, |
| 1865 | &dev_priv->mm.inactive_list, |
| 1866 | list) |
| 1867 | { |
| 1868 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
| 1869 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1870 | |
| 1871 | /* The fence registers are invalidated so clear them out */ |
| 1872 | for (i = 0; i < 16; i++) { |
| 1873 | struct drm_i915_fence_reg *reg; |
| 1874 | |
| 1875 | reg = &dev_priv->fence_regs[i]; |
| 1876 | if (!reg->obj) |
| 1877 | continue; |
| 1878 | |
| 1879 | i915_gem_clear_fence_reg(reg->obj); |
| 1880 | } |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1881 | } |
| 1882 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1883 | /** |
| 1884 | * This function clears the request list as sequence numbers are passed. |
| 1885 | */ |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1886 | static void |
| 1887 | i915_gem_retire_requests_ring(struct drm_device *dev, |
| 1888 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1889 | { |
| 1890 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1891 | uint32_t seqno; |
| 1892 | |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1893 | if (!ring->status_page.page_addr || |
| 1894 | list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1895 | return; |
| 1896 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1897 | WARN_ON(i915_verify_lists(dev)); |
| 1898 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1899 | seqno = ring->get_seqno(dev, ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1900 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1901 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1902 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1903 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1904 | struct drm_i915_gem_request, |
| 1905 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1906 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1907 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1908 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1909 | |
| 1910 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1911 | |
| 1912 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1913 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1914 | kfree(request); |
| 1915 | } |
| 1916 | |
| 1917 | /* Move any buffers on the active list that are no longer referenced |
| 1918 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1919 | */ |
| 1920 | while (!list_empty(&ring->active_list)) { |
| 1921 | struct drm_gem_object *obj; |
| 1922 | struct drm_i915_gem_object *obj_priv; |
| 1923 | |
| 1924 | obj_priv = list_first_entry(&ring->active_list, |
| 1925 | struct drm_i915_gem_object, |
| 1926 | list); |
| 1927 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1928 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1929 | break; |
| 1930 | |
| 1931 | obj = &obj_priv->base; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1932 | if (obj->write_domain != 0) |
| 1933 | i915_gem_object_move_to_flushing(obj); |
| 1934 | else |
| 1935 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1936 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1937 | |
| 1938 | if (unlikely (dev_priv->trace_irq_seqno && |
| 1939 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1940 | ring->user_irq_put(dev, ring); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1941 | dev_priv->trace_irq_seqno = 0; |
| 1942 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1943 | |
| 1944 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1945 | } |
| 1946 | |
| 1947 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1948 | i915_gem_retire_requests(struct drm_device *dev) |
| 1949 | { |
| 1950 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1951 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1952 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
| 1953 | struct drm_i915_gem_object *obj_priv, *tmp; |
| 1954 | |
| 1955 | /* We must be careful that during unbind() we do not |
| 1956 | * accidentally infinitely recurse into retire requests. |
| 1957 | * Currently: |
| 1958 | * retire -> free -> unbind -> wait -> retire_ring |
| 1959 | */ |
| 1960 | list_for_each_entry_safe(obj_priv, tmp, |
| 1961 | &dev_priv->mm.deferred_free_list, |
| 1962 | list) |
| 1963 | i915_gem_free_object_tail(&obj_priv->base); |
| 1964 | } |
| 1965 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1966 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
| 1967 | if (HAS_BSD(dev)) |
| 1968 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
| 1969 | } |
| 1970 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1971 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1972 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1973 | { |
| 1974 | drm_i915_private_t *dev_priv; |
| 1975 | struct drm_device *dev; |
| 1976 | |
| 1977 | dev_priv = container_of(work, drm_i915_private_t, |
| 1978 | mm.retire_work.work); |
| 1979 | dev = dev_priv->dev; |
| 1980 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 1981 | /* Come back later if the device is busy... */ |
| 1982 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1983 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1984 | return; |
| 1985 | } |
| 1986 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1987 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1988 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 1989 | if (!dev_priv->mm.suspended && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1990 | (!list_empty(&dev_priv->render_ring.request_list) || |
| 1991 | (HAS_BSD(dev) && |
| 1992 | !list_empty(&dev_priv->bsd_ring.request_list)))) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1993 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1994 | mutex_unlock(&dev->struct_mutex); |
| 1995 | } |
| 1996 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1997 | int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1998 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1999 | bool interruptible, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2000 | { |
| 2001 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2002 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2003 | int ret = 0; |
| 2004 | |
| 2005 | BUG_ON(seqno == 0); |
| 2006 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2007 | if (atomic_read(&dev_priv->mm.wedged)) |
| 2008 | return -EAGAIN; |
| 2009 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2010 | if (ring->outstanding_lazy_request) { |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 2011 | seqno = i915_add_request(dev, NULL, NULL, ring); |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2012 | if (seqno == 0) |
| 2013 | return -ENOMEM; |
| 2014 | } |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2015 | BUG_ON(seqno == dev_priv->next_seqno); |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2016 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2017 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 2018 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2019 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 2020 | else |
| 2021 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2022 | if (!ier) { |
| 2023 | DRM_ERROR("something (likely vbetool) disabled " |
| 2024 | "interrupts, re-enabling\n"); |
| 2025 | i915_driver_irq_preinstall(dev); |
| 2026 | i915_driver_irq_postinstall(dev); |
| 2027 | } |
| 2028 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2029 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 2030 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2031 | ring->waiting_gem_seqno = seqno; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2032 | ring->user_irq_get(dev, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2033 | if (interruptible) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2034 | ret = wait_event_interruptible(ring->irq_queue, |
| 2035 | i915_seqno_passed( |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2036 | ring->get_seqno(dev, ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2037 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2038 | else |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2039 | wait_event(ring->irq_queue, |
| 2040 | i915_seqno_passed( |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2041 | ring->get_seqno(dev, ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2042 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2043 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2044 | ring->user_irq_put(dev, ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2045 | ring->waiting_gem_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2046 | |
| 2047 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2048 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2049 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2050 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2051 | |
| 2052 | if (ret && ret != -ERESTARTSYS) |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2053 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2054 | __func__, ret, seqno, ring->get_seqno(dev, ring), |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2055 | dev_priv->next_seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2056 | |
| 2057 | /* Directly dispatch request retiring. While we have the work queue |
| 2058 | * to handle this, the waiter on a request often wants an associated |
| 2059 | * buffer to have made it to the inactive list, and we would need |
| 2060 | * a separate wait queue to handle that. |
| 2061 | */ |
| 2062 | if (ret == 0) |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2063 | i915_gem_retire_requests_ring(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2064 | |
| 2065 | return ret; |
| 2066 | } |
| 2067 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2068 | /** |
| 2069 | * Waits for a sequence number to be signaled, and cleans up the |
| 2070 | * request and object lists appropriately for that event. |
| 2071 | */ |
| 2072 | static int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2073 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2074 | struct intel_ring_buffer *ring) |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2075 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2076 | return i915_do_wait_request(dev, seqno, 1, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2077 | } |
| 2078 | |
Chris Wilson | 20f0cd5 | 2010-09-23 11:00:38 +0100 | [diff] [blame] | 2079 | static void |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2080 | i915_gem_flush_ring(struct drm_device *dev, |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2081 | struct drm_file *file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2082 | struct intel_ring_buffer *ring, |
| 2083 | uint32_t invalidate_domains, |
| 2084 | uint32_t flush_domains) |
| 2085 | { |
| 2086 | ring->flush(dev, ring, invalidate_domains, flush_domains); |
| 2087 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
| 2088 | } |
| 2089 | |
| 2090 | static void |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2091 | i915_gem_flush(struct drm_device *dev, |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2092 | struct drm_file *file_priv, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2093 | uint32_t invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2094 | uint32_t flush_domains, |
| 2095 | uint32_t flush_rings) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2096 | { |
| 2097 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2098 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2099 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 2100 | drm_agp_chipset_flush(dev); |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2101 | |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2102 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
| 2103 | if (flush_rings & RING_RENDER) |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2104 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2105 | &dev_priv->render_ring, |
| 2106 | invalidate_domains, flush_domains); |
| 2107 | if (flush_rings & RING_BSD) |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2108 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2109 | &dev_priv->bsd_ring, |
| 2110 | invalidate_domains, flush_domains); |
| 2111 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2112 | } |
| 2113 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2114 | /** |
| 2115 | * Ensures that all rendering to the object has completed and the object is |
| 2116 | * safe to unbind from the GTT or access from the CPU. |
| 2117 | */ |
| 2118 | static int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2119 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 2120 | bool interruptible) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2121 | { |
| 2122 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2123 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2124 | int ret; |
| 2125 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2126 | /* This function only exists to support waiting for existing rendering, |
| 2127 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2128 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2129 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2130 | |
| 2131 | /* If there is rendering queued on the buffer being evicted, wait for |
| 2132 | * it. |
| 2133 | */ |
| 2134 | if (obj_priv->active) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2135 | ret = i915_do_wait_request(dev, |
| 2136 | obj_priv->last_rendering_seqno, |
| 2137 | interruptible, |
| 2138 | obj_priv->ring); |
| 2139 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2140 | return ret; |
| 2141 | } |
| 2142 | |
| 2143 | return 0; |
| 2144 | } |
| 2145 | |
| 2146 | /** |
| 2147 | * Unbinds an object from the GTT aperture. |
| 2148 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2149 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2150 | i915_gem_object_unbind(struct drm_gem_object *obj) |
| 2151 | { |
| 2152 | struct drm_device *dev = obj->dev; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2153 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2154 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2155 | int ret = 0; |
| 2156 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2157 | if (obj_priv->gtt_space == NULL) |
| 2158 | return 0; |
| 2159 | |
| 2160 | if (obj_priv->pin_count != 0) { |
| 2161 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2162 | return -EINVAL; |
| 2163 | } |
| 2164 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2165 | /* blow away mappings if mapped through GTT */ |
| 2166 | i915_gem_release_mmap(obj); |
| 2167 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2168 | /* Move the object to the CPU domain to ensure that |
| 2169 | * any possible CPU writes while it's not in the GTT |
| 2170 | * are flushed when we go to remap it. This will |
| 2171 | * also ensure that all pending GPU writes are finished |
| 2172 | * before we unbind. |
| 2173 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2174 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2175 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2176 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2177 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2178 | * should be safe and we need to cleanup or else we might |
| 2179 | * cause memory corruption through use-after-free. |
| 2180 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2181 | if (ret) { |
| 2182 | i915_gem_clflush_object(obj); |
| 2183 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2184 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2185 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2186 | /* release the fence reg _after_ flushing */ |
| 2187 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 2188 | i915_gem_clear_fence_reg(obj); |
| 2189 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2190 | drm_unbind_agp(obj_priv->agp_mem); |
| 2191 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2192 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2193 | i915_gem_object_put_pages(obj); |
Chris Wilson | a32808c | 2009-09-20 21:29:47 +0100 | [diff] [blame] | 2194 | BUG_ON(obj_priv->pages_refcount); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2195 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2196 | i915_gem_info_remove_gtt(dev_priv, obj->size); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 2197 | list_del_init(&obj_priv->list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2198 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2199 | drm_mm_put_block(obj_priv->gtt_space); |
| 2200 | obj_priv->gtt_space = NULL; |
| 2201 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2202 | if (i915_gem_object_is_purgeable(obj_priv)) |
| 2203 | i915_gem_object_truncate(obj); |
| 2204 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2205 | trace_i915_gem_object_unbind(obj); |
| 2206 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2207 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2208 | } |
| 2209 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2210 | static int i915_ring_idle(struct drm_device *dev, |
| 2211 | struct intel_ring_buffer *ring) |
| 2212 | { |
| 2213 | i915_gem_flush_ring(dev, NULL, ring, |
| 2214 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 2215 | return i915_wait_request(dev, |
| 2216 | i915_gem_next_request_seqno(dev, ring), |
| 2217 | ring); |
| 2218 | } |
| 2219 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2220 | int |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2221 | i915_gpu_idle(struct drm_device *dev) |
| 2222 | { |
| 2223 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2224 | bool lists_empty; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2225 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2226 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2227 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
| 2228 | list_empty(&dev_priv->render_ring.active_list) && |
| 2229 | (!HAS_BSD(dev) || |
| 2230 | list_empty(&dev_priv->bsd_ring.active_list))); |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2231 | if (lists_empty) |
| 2232 | return 0; |
| 2233 | |
| 2234 | /* Flush everything onto the inactive list. */ |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2235 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2236 | if (ret) |
| 2237 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2238 | |
| 2239 | if (HAS_BSD(dev)) { |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2240 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2241 | if (ret) |
| 2242 | return ret; |
| 2243 | } |
| 2244 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2245 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2246 | } |
| 2247 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 2248 | static int |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2249 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
| 2250 | gfp_t gfpmask) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2251 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2252 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2253 | int page_count, i; |
| 2254 | struct address_space *mapping; |
| 2255 | struct inode *inode; |
| 2256 | struct page *page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2257 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 2258 | BUG_ON(obj_priv->pages_refcount |
| 2259 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); |
| 2260 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2261 | if (obj_priv->pages_refcount++ != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2262 | return 0; |
| 2263 | |
| 2264 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2265 | * at this point until we release them. |
| 2266 | */ |
| 2267 | page_count = obj->size / PAGE_SIZE; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2268 | BUG_ON(obj_priv->pages != NULL); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 2269 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2270 | if (obj_priv->pages == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2271 | obj_priv->pages_refcount--; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2272 | return -ENOMEM; |
| 2273 | } |
| 2274 | |
| 2275 | inode = obj->filp->f_path.dentry->d_inode; |
| 2276 | mapping = inode->i_mapping; |
| 2277 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2278 | page = read_cache_page_gfp(mapping, i, |
Linus Torvalds | 985b823 | 2010-07-02 10:04:42 +1000 | [diff] [blame] | 2279 | GFP_HIGHUSER | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2280 | __GFP_COLD | |
Linus Torvalds | cd9f040 | 2010-07-18 09:44:37 -0700 | [diff] [blame] | 2281 | __GFP_RECLAIMABLE | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2282 | gfpmask); |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2283 | if (IS_ERR(page)) |
| 2284 | goto err_pages; |
| 2285 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2286 | obj_priv->pages[i] = page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2287 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2288 | |
| 2289 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 2290 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2291 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2292 | return 0; |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2293 | |
| 2294 | err_pages: |
| 2295 | while (i--) |
| 2296 | page_cache_release(obj_priv->pages[i]); |
| 2297 | |
| 2298 | drm_free_large(obj_priv->pages); |
| 2299 | obj_priv->pages = NULL; |
| 2300 | obj_priv->pages_refcount--; |
| 2301 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2302 | } |
| 2303 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2304 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2305 | { |
| 2306 | struct drm_gem_object *obj = reg->obj; |
| 2307 | struct drm_device *dev = obj->dev; |
| 2308 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2309 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2310 | int regnum = obj_priv->fence_reg; |
| 2311 | uint64_t val; |
| 2312 | |
| 2313 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2314 | 0xfffff000) << 32; |
| 2315 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2316 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << |
| 2317 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2318 | |
| 2319 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2320 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2321 | val |= I965_FENCE_REG_VALID; |
| 2322 | |
| 2323 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); |
| 2324 | } |
| 2325 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2326 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2327 | { |
| 2328 | struct drm_gem_object *obj = reg->obj; |
| 2329 | struct drm_device *dev = obj->dev; |
| 2330 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2331 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2332 | int regnum = obj_priv->fence_reg; |
| 2333 | uint64_t val; |
| 2334 | |
| 2335 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2336 | 0xfffff000) << 32; |
| 2337 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2338 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2339 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2340 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2341 | val |= I965_FENCE_REG_VALID; |
| 2342 | |
| 2343 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); |
| 2344 | } |
| 2345 | |
| 2346 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2347 | { |
| 2348 | struct drm_gem_object *obj = reg->obj; |
| 2349 | struct drm_device *dev = obj->dev; |
| 2350 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2351 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2352 | int regnum = obj_priv->fence_reg; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2353 | int tile_width; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2354 | uint32_t fence_reg, val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2355 | uint32_t pitch_val; |
| 2356 | |
| 2357 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2358 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Linus Torvalds | f06da26 | 2009-02-09 08:57:29 -0800 | [diff] [blame] | 2359 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2360 | __func__, obj_priv->gtt_offset, obj->size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2361 | return; |
| 2362 | } |
| 2363 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2364 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2365 | HAS_128_BYTE_Y_TILING(dev)) |
| 2366 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2367 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2368 | tile_width = 512; |
| 2369 | |
| 2370 | /* Note: pitch better be a power of two tile widths */ |
| 2371 | pitch_val = obj_priv->stride / tile_width; |
| 2372 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2373 | |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 2374 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2375 | HAS_128_BYTE_Y_TILING(dev)) |
| 2376 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2377 | else |
| 2378 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); |
| 2379 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2380 | val = obj_priv->gtt_offset; |
| 2381 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2382 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2383 | val |= I915_FENCE_SIZE_BITS(obj->size); |
| 2384 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2385 | val |= I830_FENCE_REG_VALID; |
| 2386 | |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2387 | if (regnum < 8) |
| 2388 | fence_reg = FENCE_REG_830_0 + (regnum * 4); |
| 2389 | else |
| 2390 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); |
| 2391 | I915_WRITE(fence_reg, val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2392 | } |
| 2393 | |
| 2394 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2395 | { |
| 2396 | struct drm_gem_object *obj = reg->obj; |
| 2397 | struct drm_device *dev = obj->dev; |
| 2398 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2399 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2400 | int regnum = obj_priv->fence_reg; |
| 2401 | uint32_t val; |
| 2402 | uint32_t pitch_val; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2403 | uint32_t fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2404 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2405 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2406 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2407 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2408 | __func__, obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2409 | return; |
| 2410 | } |
| 2411 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2412 | pitch_val = obj_priv->stride / 128; |
| 2413 | pitch_val = ffs(pitch_val) - 1; |
| 2414 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2415 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2416 | val = obj_priv->gtt_offset; |
| 2417 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2418 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2419 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
| 2420 | WARN_ON(fence_size_bits & ~0x00000f00); |
| 2421 | val |= fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2422 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2423 | val |= I830_FENCE_REG_VALID; |
| 2424 | |
| 2425 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2426 | } |
| 2427 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2428 | static int i915_find_fence_reg(struct drm_device *dev, |
| 2429 | bool interruptible) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2430 | { |
| 2431 | struct drm_i915_fence_reg *reg = NULL; |
| 2432 | struct drm_i915_gem_object *obj_priv = NULL; |
| 2433 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2434 | struct drm_gem_object *obj = NULL; |
| 2435 | int i, avail, ret; |
| 2436 | |
| 2437 | /* First try to find a free reg */ |
| 2438 | avail = 0; |
| 2439 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2440 | reg = &dev_priv->fence_regs[i]; |
| 2441 | if (!reg->obj) |
| 2442 | return i; |
| 2443 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2444 | obj_priv = to_intel_bo(reg->obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2445 | if (!obj_priv->pin_count) |
| 2446 | avail++; |
| 2447 | } |
| 2448 | |
| 2449 | if (avail == 0) |
| 2450 | return -ENOSPC; |
| 2451 | |
| 2452 | /* None available, try to steal one or wait for a user to finish */ |
| 2453 | i = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2454 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
| 2455 | lru_list) { |
| 2456 | obj = reg->obj; |
| 2457 | obj_priv = to_intel_bo(obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2458 | |
| 2459 | if (obj_priv->pin_count) |
| 2460 | continue; |
| 2461 | |
| 2462 | /* found one! */ |
| 2463 | i = obj_priv->fence_reg; |
| 2464 | break; |
| 2465 | } |
| 2466 | |
| 2467 | BUG_ON(i == I915_FENCE_REG_NONE); |
| 2468 | |
| 2469 | /* We only have a reference on obj from the active list. put_fence_reg |
| 2470 | * might drop that one, causing a use-after-free in it. So hold a |
| 2471 | * private reference to obj like the other callers of put_fence_reg |
| 2472 | * (set_tiling ioctl) do. */ |
| 2473 | drm_gem_object_reference(obj); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2474 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2475 | drm_gem_object_unreference(obj); |
| 2476 | if (ret != 0) |
| 2477 | return ret; |
| 2478 | |
| 2479 | return i; |
| 2480 | } |
| 2481 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2482 | /** |
| 2483 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2484 | * @obj: object to map through a fence reg |
| 2485 | * |
| 2486 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2487 | * to them without having to worry about swizzling if the object is tiled. |
| 2488 | * |
| 2489 | * This function walks the fence regs looking for a free one for @obj, |
| 2490 | * stealing one if it can't find any. |
| 2491 | * |
| 2492 | * It then sets up the reg based on the object's properties: address, pitch |
| 2493 | * and tiling format. |
| 2494 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2495 | int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2496 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
| 2497 | bool interruptible) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2498 | { |
| 2499 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2500 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2501 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2502 | struct drm_i915_fence_reg *reg = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2503 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2504 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2505 | /* Just update our place in the LRU if our fence is getting used. */ |
| 2506 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2507 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2508 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2509 | return 0; |
| 2510 | } |
| 2511 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2512 | switch (obj_priv->tiling_mode) { |
| 2513 | case I915_TILING_NONE: |
| 2514 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2515 | break; |
| 2516 | case I915_TILING_X: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2517 | if (!obj_priv->stride) |
| 2518 | return -EINVAL; |
| 2519 | WARN((obj_priv->stride & (512 - 1)), |
| 2520 | "object 0x%08x is X tiled but has non-512B pitch\n", |
| 2521 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2522 | break; |
| 2523 | case I915_TILING_Y: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2524 | if (!obj_priv->stride) |
| 2525 | return -EINVAL; |
| 2526 | WARN((obj_priv->stride & (128 - 1)), |
| 2527 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
| 2528 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2529 | break; |
| 2530 | } |
| 2531 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2532 | ret = i915_find_fence_reg(dev, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2533 | if (ret < 0) |
| 2534 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2535 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2536 | obj_priv->fence_reg = ret; |
| 2537 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2538 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2539 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2540 | reg->obj = obj; |
| 2541 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2542 | switch (INTEL_INFO(dev)->gen) { |
| 2543 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2544 | sandybridge_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2545 | break; |
| 2546 | case 5: |
| 2547 | case 4: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2548 | i965_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2549 | break; |
| 2550 | case 3: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2551 | i915_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2552 | break; |
| 2553 | case 2: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2554 | i830_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2555 | break; |
| 2556 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2557 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2558 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
| 2559 | obj_priv->tiling_mode); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2560 | |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2561 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2562 | } |
| 2563 | |
| 2564 | /** |
| 2565 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2566 | * @obj: object to clear |
| 2567 | * |
| 2568 | * Zeroes out the fence register itself and clears out the associated |
| 2569 | * data structures in dev_priv and obj_priv. |
| 2570 | */ |
| 2571 | static void |
| 2572 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) |
| 2573 | { |
| 2574 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2575 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2576 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2577 | struct drm_i915_fence_reg *reg = |
| 2578 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2579 | uint32_t fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2580 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2581 | switch (INTEL_INFO(dev)->gen) { |
| 2582 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2583 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
| 2584 | (obj_priv->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2585 | break; |
| 2586 | case 5: |
| 2587 | case 4: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2588 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2589 | break; |
| 2590 | case 3: |
Chris Wilson | 9b74f73 | 2010-09-22 19:10:44 +0100 | [diff] [blame] | 2591 | if (obj_priv->fence_reg >= 8) |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2592 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2593 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2594 | case 2: |
| 2595 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2596 | |
| 2597 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2598 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2599 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2600 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2601 | reg->obj = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2602 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2603 | list_del_init(®->lru_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2604 | } |
| 2605 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2606 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2607 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2608 | * to the buffer to finish, and then resets the fence register. |
| 2609 | * @obj: tiled object holding a fence register. |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2610 | * @bool: whether the wait upon the fence is interruptible |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2611 | * |
| 2612 | * Zeroes out the fence register itself and clears out the associated |
| 2613 | * data structures in dev_priv and obj_priv. |
| 2614 | */ |
| 2615 | int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2616 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
| 2617 | bool interruptible) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2618 | { |
| 2619 | struct drm_device *dev = obj->dev; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2620 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2621 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2622 | struct drm_i915_fence_reg *reg; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2623 | |
| 2624 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) |
| 2625 | return 0; |
| 2626 | |
Daniel Vetter | 10ae9bd | 2010-02-01 13:59:17 +0100 | [diff] [blame] | 2627 | /* If we've changed tiling, GTT-mappings of the object |
| 2628 | * need to re-fault to ensure that the correct fence register |
| 2629 | * setup is in place. |
| 2630 | */ |
| 2631 | i915_gem_release_mmap(obj); |
| 2632 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2633 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2634 | * therefore we must wait for any outstanding access to complete |
| 2635 | * before clearing the fence. |
| 2636 | */ |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2637 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2638 | if (reg->gpu) { |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2639 | int ret; |
| 2640 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2641 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2642 | if (ret) |
| 2643 | return ret; |
| 2644 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2645 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2646 | if (ret) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2647 | return ret; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2648 | |
| 2649 | reg->gpu = false; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2650 | } |
| 2651 | |
Daniel Vetter | 4a72661 | 2010-02-01 13:59:16 +0100 | [diff] [blame] | 2652 | i915_gem_object_flush_gtt_write_domain(obj); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2653 | i915_gem_clear_fence_reg(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2654 | |
| 2655 | return 0; |
| 2656 | } |
| 2657 | |
| 2658 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2659 | * Finds free space in the GTT aperture and binds the object there. |
| 2660 | */ |
| 2661 | static int |
| 2662 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) |
| 2663 | { |
| 2664 | struct drm_device *dev = obj->dev; |
| 2665 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2666 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2667 | struct drm_mm_node *free_space; |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2668 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2669 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2670 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 2671 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2672 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2673 | return -EINVAL; |
| 2674 | } |
| 2675 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2676 | if (alignment == 0) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2677 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2678 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2679 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2680 | return -EINVAL; |
| 2681 | } |
| 2682 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2683 | /* If the object is bigger than the entire aperture, reject it early |
| 2684 | * before evicting everything in a vain attempt to find space. |
| 2685 | */ |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2686 | if (obj->size > dev_priv->mm.gtt_total) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2687 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2688 | return -E2BIG; |
| 2689 | } |
| 2690 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2691 | search_free: |
| 2692 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
| 2693 | obj->size, alignment, 0); |
| 2694 | if (free_space != NULL) { |
| 2695 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, |
| 2696 | alignment); |
Daniel Vetter | db3307a | 2010-07-02 15:02:12 +0100 | [diff] [blame] | 2697 | if (obj_priv->gtt_space != NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2698 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2699 | } |
| 2700 | if (obj_priv->gtt_space == NULL) { |
| 2701 | /* If the gtt is empty and we're still having trouble |
| 2702 | * fitting our object in, we're out of memory. |
| 2703 | */ |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2704 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2705 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2706 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2707 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2708 | goto search_free; |
| 2709 | } |
| 2710 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2711 | ret = i915_gem_object_get_pages(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2712 | if (ret) { |
| 2713 | drm_mm_put_block(obj_priv->gtt_space); |
| 2714 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2715 | |
| 2716 | if (ret == -ENOMEM) { |
| 2717 | /* first try to clear up some space from the GTT */ |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2718 | ret = i915_gem_evict_something(dev, obj->size, |
| 2719 | alignment); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2720 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2721 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2722 | if (gfpmask) { |
| 2723 | gfpmask = 0; |
| 2724 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2725 | } |
| 2726 | |
| 2727 | return ret; |
| 2728 | } |
| 2729 | |
| 2730 | goto search_free; |
| 2731 | } |
| 2732 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2733 | return ret; |
| 2734 | } |
| 2735 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2736 | /* Create an AGP memory structure pointing at our pages, and bind it |
| 2737 | * into the GTT. |
| 2738 | */ |
| 2739 | obj_priv->agp_mem = drm_agp_bind_pages(dev, |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2740 | obj_priv->pages, |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2741 | obj->size >> PAGE_SHIFT, |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 2742 | obj_priv->gtt_offset, |
| 2743 | obj_priv->agp_type); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2744 | if (obj_priv->agp_mem == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2745 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2746 | drm_mm_put_block(obj_priv->gtt_space); |
| 2747 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2748 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2749 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2750 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2751 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2752 | |
| 2753 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2754 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2755 | |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2756 | /* keep track of bounds object by adding it to the inactive list */ |
| 2757 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2758 | i915_gem_info_add_gtt(dev_priv, obj->size); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2759 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2760 | /* Assert that the object is not currently in any GPU domain. As it |
| 2761 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2762 | * a GPU cache |
| 2763 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 2764 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
| 2765 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2766 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2767 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
| 2768 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2769 | return 0; |
| 2770 | } |
| 2771 | |
| 2772 | void |
| 2773 | i915_gem_clflush_object(struct drm_gem_object *obj) |
| 2774 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2775 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2776 | |
| 2777 | /* If we don't have a page list set up, then we're not pinned |
| 2778 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2779 | * again at bind time. |
| 2780 | */ |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2781 | if (obj_priv->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2782 | return; |
| 2783 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2784 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2785 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2786 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2787 | } |
| 2788 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2789 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2790 | static int |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2791 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
| 2792 | bool pipelined) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2793 | { |
| 2794 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2795 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2796 | |
| 2797 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2798 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2799 | |
| 2800 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2801 | old_write_domain = obj->write_domain; |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2802 | i915_gem_flush_ring(dev, NULL, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2803 | to_intel_bo(obj)->ring, |
| 2804 | 0, obj->write_domain); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2805 | BUG_ON(obj->write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2806 | |
| 2807 | trace_i915_gem_object_change_domain(obj, |
| 2808 | obj->read_domains, |
| 2809 | old_write_domain); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2810 | |
| 2811 | if (pipelined) |
| 2812 | return 0; |
| 2813 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2814 | return i915_gem_object_wait_rendering(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2815 | } |
| 2816 | |
| 2817 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2818 | static void |
| 2819 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) |
| 2820 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2821 | uint32_t old_write_domain; |
| 2822 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2823 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
| 2824 | return; |
| 2825 | |
| 2826 | /* No actual flushing is required for the GTT write domain. Writes |
| 2827 | * to it immediately go to main memory as far as we know, so there's |
| 2828 | * no chipset flush. It also doesn't land in render cache. |
| 2829 | */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2830 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2831 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2832 | |
| 2833 | trace_i915_gem_object_change_domain(obj, |
| 2834 | obj->read_domains, |
| 2835 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2836 | } |
| 2837 | |
| 2838 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2839 | static void |
| 2840 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) |
| 2841 | { |
| 2842 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2843 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2844 | |
| 2845 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) |
| 2846 | return; |
| 2847 | |
| 2848 | i915_gem_clflush_object(obj); |
| 2849 | drm_agp_chipset_flush(dev); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2850 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2851 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2852 | |
| 2853 | trace_i915_gem_object_change_domain(obj, |
| 2854 | obj->read_domains, |
| 2855 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2856 | } |
| 2857 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2858 | /** |
| 2859 | * Moves a single object to the GTT read, and possibly write domain. |
| 2860 | * |
| 2861 | * This function returns when the move is complete, including waiting on |
| 2862 | * flushes to occur. |
| 2863 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2864 | int |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2865 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
| 2866 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2867 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2868 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2869 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2870 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2871 | /* Not valid to be called on unbound objects. */ |
| 2872 | if (obj_priv->gtt_space == NULL) |
| 2873 | return -EINVAL; |
| 2874 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2875 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2876 | if (ret != 0) |
| 2877 | return ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2878 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2879 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2880 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2881 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2882 | ret = i915_gem_object_wait_rendering(obj, true); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2883 | if (ret) |
| 2884 | return ret; |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2885 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2886 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2887 | old_write_domain = obj->write_domain; |
| 2888 | old_read_domains = obj->read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2889 | |
| 2890 | /* It should now be out of any other write domains, and we can update |
| 2891 | * the domain values for our changes. |
| 2892 | */ |
| 2893 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2894 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2895 | if (write) { |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2896 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2897 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2898 | obj_priv->dirty = 1; |
| 2899 | } |
| 2900 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2901 | trace_i915_gem_object_change_domain(obj, |
| 2902 | old_read_domains, |
| 2903 | old_write_domain); |
| 2904 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2905 | return 0; |
| 2906 | } |
| 2907 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2908 | /* |
| 2909 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 2910 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 2911 | */ |
| 2912 | int |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2913 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
| 2914 | bool pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2915 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2916 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2917 | uint32_t old_read_domains; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2918 | int ret; |
| 2919 | |
| 2920 | /* Not valid to be called on unbound objects. */ |
| 2921 | if (obj_priv->gtt_space == NULL) |
| 2922 | return -EINVAL; |
| 2923 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 2924 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2925 | if (ret) |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2926 | return ret; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2927 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 2928 | /* Currently, we are always called from an non-interruptible context. */ |
| 2929 | if (!pipelined) { |
| 2930 | ret = i915_gem_object_wait_rendering(obj, false); |
| 2931 | if (ret) |
| 2932 | return ret; |
| 2933 | } |
| 2934 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2935 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2936 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2937 | old_read_domains = obj->read_domains; |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2938 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2939 | |
| 2940 | trace_i915_gem_object_change_domain(obj, |
| 2941 | old_read_domains, |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2942 | obj->write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2943 | |
| 2944 | return 0; |
| 2945 | } |
| 2946 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2947 | /** |
| 2948 | * Moves a single object to the CPU read, and possibly write domain. |
| 2949 | * |
| 2950 | * This function returns when the move is complete, including waiting on |
| 2951 | * flushes to occur. |
| 2952 | */ |
| 2953 | static int |
| 2954 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) |
| 2955 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2956 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2957 | int ret; |
| 2958 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2959 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2960 | if (ret != 0) |
| 2961 | return ret; |
| 2962 | |
| 2963 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2964 | |
| 2965 | /* If we have a partially-valid cache of the object in the CPU, |
| 2966 | * finish invalidating it and free the per-page flags. |
| 2967 | */ |
| 2968 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 2969 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2970 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2971 | ret = i915_gem_object_wait_rendering(obj, true); |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2972 | if (ret) |
| 2973 | return ret; |
| 2974 | } |
| 2975 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2976 | old_write_domain = obj->write_domain; |
| 2977 | old_read_domains = obj->read_domains; |
| 2978 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2979 | /* Flush the CPU cache if it's still invalid. */ |
| 2980 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 2981 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2982 | |
| 2983 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 2984 | } |
| 2985 | |
| 2986 | /* It should now be out of any other write domains, and we can update |
| 2987 | * the domain values for our changes. |
| 2988 | */ |
| 2989 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 2990 | |
| 2991 | /* If we're writing through the CPU, then the GPU read domains will |
| 2992 | * need to be invalidated at next use. |
| 2993 | */ |
| 2994 | if (write) { |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2995 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2996 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2997 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2998 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2999 | trace_i915_gem_object_change_domain(obj, |
| 3000 | old_read_domains, |
| 3001 | old_write_domain); |
| 3002 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3003 | return 0; |
| 3004 | } |
| 3005 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3006 | /* |
| 3007 | * Set the next domain for the specified object. This |
| 3008 | * may not actually perform the necessary flushing/invaliding though, |
| 3009 | * as that may want to be batched with other set_domain operations |
| 3010 | * |
| 3011 | * This is (we hope) the only really tricky part of gem. The goal |
| 3012 | * is fairly simple -- track which caches hold bits of the object |
| 3013 | * and make sure they remain coherent. A few concrete examples may |
| 3014 | * help to explain how it works. For shorthand, we use the notation |
| 3015 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 3016 | * a pair of read and write domain masks. |
| 3017 | * |
| 3018 | * Case 1: the batch buffer |
| 3019 | * |
| 3020 | * 1. Allocated |
| 3021 | * 2. Written by CPU |
| 3022 | * 3. Mapped to GTT |
| 3023 | * 4. Read by GPU |
| 3024 | * 5. Unmapped from GTT |
| 3025 | * 6. Freed |
| 3026 | * |
| 3027 | * Let's take these a step at a time |
| 3028 | * |
| 3029 | * 1. Allocated |
| 3030 | * Pages allocated from the kernel may still have |
| 3031 | * cache contents, so we set them to (CPU, CPU) always. |
| 3032 | * 2. Written by CPU (using pwrite) |
| 3033 | * The pwrite function calls set_domain (CPU, CPU) and |
| 3034 | * this function does nothing (as nothing changes) |
| 3035 | * 3. Mapped by GTT |
| 3036 | * This function asserts that the object is not |
| 3037 | * currently in any GPU-based read or write domains |
| 3038 | * 4. Read by GPU |
| 3039 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 3040 | * As write_domain is zero, this function adds in the |
| 3041 | * current read domains (CPU+COMMAND, 0). |
| 3042 | * flush_domains is set to CPU. |
| 3043 | * invalidate_domains is set to COMMAND |
| 3044 | * clflush is run to get data out of the CPU caches |
| 3045 | * then i915_dev_set_domain calls i915_gem_flush to |
| 3046 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 3047 | * 5. Unmapped from GTT |
| 3048 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 3049 | * flush_domains and invalidate_domains end up both zero |
| 3050 | * so no flushing/invalidating happens |
| 3051 | * 6. Freed |
| 3052 | * yay, done |
| 3053 | * |
| 3054 | * Case 2: The shared render buffer |
| 3055 | * |
| 3056 | * 1. Allocated |
| 3057 | * 2. Mapped to GTT |
| 3058 | * 3. Read/written by GPU |
| 3059 | * 4. set_domain to (CPU,CPU) |
| 3060 | * 5. Read/written by CPU |
| 3061 | * 6. Read/written by GPU |
| 3062 | * |
| 3063 | * 1. Allocated |
| 3064 | * Same as last example, (CPU, CPU) |
| 3065 | * 2. Mapped to GTT |
| 3066 | * Nothing changes (assertions find that it is not in the GPU) |
| 3067 | * 3. Read/written by GPU |
| 3068 | * execbuffer calls set_domain (RENDER, RENDER) |
| 3069 | * flush_domains gets CPU |
| 3070 | * invalidate_domains gets GPU |
| 3071 | * clflush (obj) |
| 3072 | * MI_FLUSH and drm_agp_chipset_flush |
| 3073 | * 4. set_domain (CPU, CPU) |
| 3074 | * flush_domains gets GPU |
| 3075 | * invalidate_domains gets CPU |
| 3076 | * wait_rendering (obj) to make sure all drawing is complete. |
| 3077 | * This will include an MI_FLUSH to get the data from GPU |
| 3078 | * to memory |
| 3079 | * clflush (obj) to invalidate the CPU cache |
| 3080 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 3081 | * 5. Read/written by CPU |
| 3082 | * cache lines are loaded and dirtied |
| 3083 | * 6. Read written by GPU |
| 3084 | * Same as last GPU access |
| 3085 | * |
| 3086 | * Case 3: The constant buffer |
| 3087 | * |
| 3088 | * 1. Allocated |
| 3089 | * 2. Written by CPU |
| 3090 | * 3. Read by GPU |
| 3091 | * 4. Updated (written) by CPU again |
| 3092 | * 5. Read by GPU |
| 3093 | * |
| 3094 | * 1. Allocated |
| 3095 | * (CPU, CPU) |
| 3096 | * 2. Written by CPU |
| 3097 | * (CPU, CPU) |
| 3098 | * 3. Read by GPU |
| 3099 | * (CPU+RENDER, 0) |
| 3100 | * flush_domains = CPU |
| 3101 | * invalidate_domains = RENDER |
| 3102 | * clflush (obj) |
| 3103 | * MI_FLUSH |
| 3104 | * drm_agp_chipset_flush |
| 3105 | * 4. Updated (written) by CPU again |
| 3106 | * (CPU, CPU) |
| 3107 | * flush_domains = 0 (no previous write domain) |
| 3108 | * invalidate_domains = 0 (no new read domains) |
| 3109 | * 5. Read by GPU |
| 3110 | * (CPU+RENDER, 0) |
| 3111 | * flush_domains = CPU |
| 3112 | * invalidate_domains = RENDER |
| 3113 | * clflush (obj) |
| 3114 | * MI_FLUSH |
| 3115 | * drm_agp_chipset_flush |
| 3116 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 3117 | static void |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3118 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3119 | { |
| 3120 | struct drm_device *dev = obj->dev; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3121 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3122 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3123 | uint32_t invalidate_domains = 0; |
| 3124 | uint32_t flush_domains = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3125 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3126 | |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3127 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
| 3128 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3129 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3130 | intel_mark_busy(dev, obj); |
| 3131 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3132 | /* |
| 3133 | * If the object isn't moving to a new write domain, |
| 3134 | * let the object stay in multiple read domains |
| 3135 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3136 | if (obj->pending_write_domain == 0) |
| 3137 | obj->pending_read_domains |= obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3138 | else |
| 3139 | obj_priv->dirty = 1; |
| 3140 | |
| 3141 | /* |
| 3142 | * Flush the current write domain if |
| 3143 | * the new read domains don't match. Invalidate |
| 3144 | * any read domains which differ from the old |
| 3145 | * write domain |
| 3146 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3147 | if (obj->write_domain && |
| 3148 | obj->write_domain != obj->pending_read_domains) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3149 | flush_domains |= obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3150 | invalidate_domains |= |
| 3151 | obj->pending_read_domains & ~obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3152 | } |
| 3153 | /* |
| 3154 | * Invalidate any read caches which may have |
| 3155 | * stale data. That is, any new read domains. |
| 3156 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3157 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 3158 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3159 | i915_gem_clflush_object(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3160 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3161 | old_read_domains = obj->read_domains; |
| 3162 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3163 | /* The actual obj->write_domain will be updated with |
| 3164 | * pending_write_domain after we emit the accumulated flush for all |
| 3165 | * of our domain changes in execbuffers (which clears objects' |
| 3166 | * write_domains). So if we have a current write domain that we |
| 3167 | * aren't changing, set pending_write_domain to that. |
| 3168 | */ |
| 3169 | if (flush_domains == 0 && obj->pending_write_domain == 0) |
| 3170 | obj->pending_write_domain = obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3171 | obj->read_domains = obj->pending_read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3172 | |
| 3173 | dev->invalidate_domains |= invalidate_domains; |
| 3174 | dev->flush_domains |= flush_domains; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3175 | if (obj_priv->ring) |
| 3176 | dev_priv->mm.flush_rings |= obj_priv->ring->id; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3177 | |
| 3178 | trace_i915_gem_object_change_domain(obj, |
| 3179 | old_read_domains, |
| 3180 | obj->write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3181 | } |
| 3182 | |
| 3183 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3184 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3185 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3186 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3187 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3188 | */ |
| 3189 | static void |
| 3190 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) |
| 3191 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3192 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3193 | |
| 3194 | if (!obj_priv->page_cpu_valid) |
| 3195 | return; |
| 3196 | |
| 3197 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3198 | */ |
| 3199 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3200 | int i; |
| 3201 | |
| 3202 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { |
| 3203 | if (obj_priv->page_cpu_valid[i]) |
| 3204 | continue; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3205 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3206 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3207 | } |
| 3208 | |
| 3209 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3210 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3211 | */ |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3212 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3213 | obj_priv->page_cpu_valid = NULL; |
| 3214 | } |
| 3215 | |
| 3216 | /** |
| 3217 | * Set the CPU read domain on a range of the object. |
| 3218 | * |
| 3219 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3220 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3221 | * pages have been flushed, and will be respected by |
| 3222 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3223 | * of the whole object. |
| 3224 | * |
| 3225 | * This function returns when the move is complete, including waiting on |
| 3226 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3227 | */ |
| 3228 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3229 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 3230 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3231 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3232 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3233 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3234 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3235 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3236 | if (offset == 0 && size == obj->size) |
| 3237 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3238 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3239 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3240 | if (ret != 0) |
| 3241 | return ret; |
| 3242 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3243 | |
| 3244 | /* If we're already fully in the CPU read domain, we're done. */ |
| 3245 | if (obj_priv->page_cpu_valid == NULL && |
| 3246 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3247 | return 0; |
| 3248 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3249 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3250 | * newly adding I915_GEM_DOMAIN_CPU |
| 3251 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3252 | if (obj_priv->page_cpu_valid == NULL) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3253 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
| 3254 | GFP_KERNEL); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3255 | if (obj_priv->page_cpu_valid == NULL) |
| 3256 | return -ENOMEM; |
| 3257 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3258 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3259 | |
| 3260 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3261 | * perspective. |
| 3262 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3263 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3264 | i++) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3265 | if (obj_priv->page_cpu_valid[i]) |
| 3266 | continue; |
| 3267 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3268 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3269 | |
| 3270 | obj_priv->page_cpu_valid[i] = 1; |
| 3271 | } |
| 3272 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3273 | /* It should now be out of any other write domains, and we can update |
| 3274 | * the domain values for our changes. |
| 3275 | */ |
| 3276 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3277 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3278 | old_read_domains = obj->read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3279 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3280 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3281 | trace_i915_gem_object_change_domain(obj, |
| 3282 | old_read_domains, |
| 3283 | obj->write_domain); |
| 3284 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3285 | return 0; |
| 3286 | } |
| 3287 | |
| 3288 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3289 | * Pin an object to the GTT and evaluate the relocations landing in it. |
| 3290 | */ |
| 3291 | static int |
| 3292 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, |
| 3293 | struct drm_file *file_priv, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3294 | struct drm_i915_gem_exec_object2 *entry) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3295 | { |
| 3296 | struct drm_device *dev = obj->dev; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3297 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3298 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3299 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3300 | int i, ret; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3301 | void __iomem *reloc_page; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3302 | bool need_fence; |
| 3303 | |
| 3304 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3305 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 3306 | |
| 3307 | /* Check fence reg constraints and rebind if necessary */ |
Chris Wilson | 808b24d6 | 2010-05-27 13:18:15 +0100 | [diff] [blame] | 3308 | if (need_fence && |
| 3309 | !i915_gem_object_fence_offset_ok(obj, |
| 3310 | obj_priv->tiling_mode)) { |
| 3311 | ret = i915_gem_object_unbind(obj); |
| 3312 | if (ret) |
| 3313 | return ret; |
| 3314 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3315 | |
| 3316 | /* Choose the GTT offset for our buffer and put it there. */ |
| 3317 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); |
| 3318 | if (ret) |
| 3319 | return ret; |
| 3320 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3321 | /* |
| 3322 | * Pre-965 chips need a fence register set up in order to |
| 3323 | * properly handle blits to/from tiled surfaces. |
| 3324 | */ |
| 3325 | if (need_fence) { |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 3326 | ret = i915_gem_object_get_fence_reg(obj, true); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3327 | if (ret != 0) { |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3328 | i915_gem_object_unpin(obj); |
| 3329 | return ret; |
| 3330 | } |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 3331 | |
| 3332 | dev_priv->fence_regs[obj_priv->fence_reg].gpu = true; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3333 | } |
| 3334 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3335 | entry->offset = obj_priv->gtt_offset; |
| 3336 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3337 | /* Apply the relocations, using the GTT aperture to avoid cache |
| 3338 | * flushing requirements. |
| 3339 | */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3340 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3341 | for (i = 0; i < entry->relocation_count; i++) { |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3342 | struct drm_i915_gem_relocation_entry reloc; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3343 | struct drm_gem_object *target_obj; |
| 3344 | struct drm_i915_gem_object *target_obj_priv; |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3345 | uint32_t reloc_val, reloc_offset; |
| 3346 | uint32_t __iomem *reloc_entry; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3347 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3348 | ret = __copy_from_user_inatomic(&reloc, |
| 3349 | user_relocs+i, |
| 3350 | sizeof(reloc)); |
| 3351 | if (ret) { |
| 3352 | i915_gem_object_unpin(obj); |
| 3353 | return -EFAULT; |
| 3354 | } |
| 3355 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3356 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3357 | reloc.target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3358 | if (target_obj == NULL) { |
| 3359 | i915_gem_object_unpin(obj); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3360 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3361 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3362 | target_obj_priv = to_intel_bo(target_obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3363 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3364 | #if WATCH_RELOC |
| 3365 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3366 | "read %08x write %08x gtt %08x " |
| 3367 | "presumed %08x delta %08x\n", |
| 3368 | __func__, |
| 3369 | obj, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3370 | (int) reloc.offset, |
| 3371 | (int) reloc.target_handle, |
| 3372 | (int) reloc.read_domains, |
| 3373 | (int) reloc.write_domain, |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3374 | (int) target_obj_priv->gtt_offset, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3375 | (int) reloc.presumed_offset, |
| 3376 | reloc.delta); |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3377 | #endif |
| 3378 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3379 | /* The target buffer should have appeared before us in the |
| 3380 | * exec_object list, so it should have a GTT space bound by now. |
| 3381 | */ |
| 3382 | if (target_obj_priv->gtt_space == NULL) { |
| 3383 | DRM_ERROR("No GTT space found for object %d\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3384 | reloc.target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3385 | drm_gem_object_unreference(target_obj); |
| 3386 | i915_gem_object_unpin(obj); |
| 3387 | return -EINVAL; |
| 3388 | } |
| 3389 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3390 | /* Validate that the target is in a valid r/w GPU domain */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3391 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3392 | DRM_ERROR("reloc with multiple write domains: " |
| 3393 | "obj %p target %d offset %d " |
| 3394 | "read %08x write %08x", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3395 | obj, reloc.target_handle, |
| 3396 | (int) reloc.offset, |
| 3397 | reloc.read_domains, |
| 3398 | reloc.write_domain); |
Julia Lawall | 929f49b | 2010-10-02 15:59:17 +0200 | [diff] [blame] | 3399 | drm_gem_object_unreference(target_obj); |
| 3400 | i915_gem_object_unpin(obj); |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3401 | return -EINVAL; |
| 3402 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3403 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
| 3404 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3405 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3406 | "obj %p target %d offset %d " |
| 3407 | "read %08x write %08x", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3408 | obj, reloc.target_handle, |
| 3409 | (int) reloc.offset, |
| 3410 | reloc.read_domains, |
| 3411 | reloc.write_domain); |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3412 | drm_gem_object_unreference(target_obj); |
| 3413 | i915_gem_object_unpin(obj); |
| 3414 | return -EINVAL; |
| 3415 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3416 | if (reloc.write_domain && target_obj->pending_write_domain && |
| 3417 | reloc.write_domain != target_obj->pending_write_domain) { |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3418 | DRM_ERROR("Write domain conflict: " |
| 3419 | "obj %p target %d offset %d " |
| 3420 | "new %08x old %08x\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3421 | obj, reloc.target_handle, |
| 3422 | (int) reloc.offset, |
| 3423 | reloc.write_domain, |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3424 | target_obj->pending_write_domain); |
| 3425 | drm_gem_object_unreference(target_obj); |
| 3426 | i915_gem_object_unpin(obj); |
| 3427 | return -EINVAL; |
| 3428 | } |
| 3429 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3430 | target_obj->pending_read_domains |= reloc.read_domains; |
| 3431 | target_obj->pending_write_domain |= reloc.write_domain; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3432 | |
| 3433 | /* If the relocation already has the right value in it, no |
| 3434 | * more work needs to be done. |
| 3435 | */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3436 | if (target_obj_priv->gtt_offset == reloc.presumed_offset) { |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3437 | drm_gem_object_unreference(target_obj); |
| 3438 | continue; |
| 3439 | } |
| 3440 | |
| 3441 | /* Check that the relocation address is valid... */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3442 | if (reloc.offset > obj->size - 4) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3443 | DRM_ERROR("Relocation beyond object bounds: " |
| 3444 | "obj %p target %d offset %d size %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3445 | obj, reloc.target_handle, |
| 3446 | (int) reloc.offset, (int) obj->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3447 | drm_gem_object_unreference(target_obj); |
| 3448 | i915_gem_object_unpin(obj); |
| 3449 | return -EINVAL; |
| 3450 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3451 | if (reloc.offset & 3) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3452 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3453 | "obj %p target %d offset %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3454 | obj, reloc.target_handle, |
| 3455 | (int) reloc.offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3456 | drm_gem_object_unreference(target_obj); |
| 3457 | i915_gem_object_unpin(obj); |
| 3458 | return -EINVAL; |
| 3459 | } |
| 3460 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3461 | /* and points to somewhere within the target object. */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3462 | if (reloc.delta >= target_obj->size) { |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3463 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3464 | "obj %p target %d delta %d size %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3465 | obj, reloc.target_handle, |
| 3466 | (int) reloc.delta, (int) target_obj->size); |
Chris Wilson | 491152b | 2009-02-11 14:26:32 +0000 | [diff] [blame] | 3467 | drm_gem_object_unreference(target_obj); |
| 3468 | i915_gem_object_unpin(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3469 | return -EINVAL; |
| 3470 | } |
| 3471 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3472 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 3473 | if (ret != 0) { |
| 3474 | drm_gem_object_unreference(target_obj); |
| 3475 | i915_gem_object_unpin(obj); |
Chris Wilson | 1cdf7fe | 2010-10-02 15:12:41 +0100 | [diff] [blame] | 3476 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3477 | } |
| 3478 | |
| 3479 | /* Map the page containing the relocation we're going to |
| 3480 | * perform. |
| 3481 | */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3482 | reloc_offset = obj_priv->gtt_offset + reloc.offset; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3483 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 3484 | (reloc_offset & |
Chris Wilson | fca3ec0 | 2010-08-04 14:34:24 +0100 | [diff] [blame] | 3485 | ~(PAGE_SIZE - 1)), |
| 3486 | KM_USER0); |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3487 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3488 | (reloc_offset & (PAGE_SIZE - 1))); |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3489 | reloc_val = target_obj_priv->gtt_offset + reloc.delta; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3490 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3491 | writel(reloc_val, reloc_entry); |
Chris Wilson | fca3ec0 | 2010-08-04 14:34:24 +0100 | [diff] [blame] | 3492 | io_mapping_unmap_atomic(reloc_page, KM_USER0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3493 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3494 | drm_gem_object_unreference(target_obj); |
| 3495 | } |
| 3496 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3497 | return 0; |
| 3498 | } |
| 3499 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3500 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3501 | * emitted over 20 msec ago. |
| 3502 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3503 | * Note that if we were to use the current jiffies each time around the loop, |
| 3504 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3505 | * render a frame was over 20ms. |
| 3506 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3507 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3508 | * relatively low latency when blocking on a particular request to finish. |
| 3509 | */ |
| 3510 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3511 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3512 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3513 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3514 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3515 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3516 | struct drm_i915_gem_request *request; |
| 3517 | struct intel_ring_buffer *ring = NULL; |
| 3518 | u32 seqno = 0; |
| 3519 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3520 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3521 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3522 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3523 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3524 | break; |
| 3525 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3526 | ring = request->ring; |
| 3527 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3528 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3529 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3530 | |
| 3531 | if (seqno == 0) |
| 3532 | return 0; |
| 3533 | |
| 3534 | ret = 0; |
| 3535 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { |
| 3536 | /* And wait for the seqno passing without holding any locks and |
| 3537 | * causing extra latency for others. This is safe as the irq |
| 3538 | * generation is designed to be run atomically and so is |
| 3539 | * lockless. |
| 3540 | */ |
| 3541 | ring->user_irq_get(dev, ring); |
| 3542 | ret = wait_event_interruptible(ring->irq_queue, |
| 3543 | i915_seqno_passed(ring->get_seqno(dev, ring), seqno) |
| 3544 | || atomic_read(&dev_priv->mm.wedged)); |
| 3545 | ring->user_irq_put(dev, ring); |
| 3546 | |
| 3547 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3548 | ret = -EIO; |
| 3549 | } |
| 3550 | |
| 3551 | if (ret == 0) |
| 3552 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3553 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3554 | return ret; |
| 3555 | } |
| 3556 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3557 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3558 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
| 3559 | uint64_t exec_offset) |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3560 | { |
| 3561 | uint32_t exec_start, exec_len; |
| 3562 | |
| 3563 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3564 | exec_len = (uint32_t) exec->batch_len; |
| 3565 | |
| 3566 | if ((exec_start | exec_len) & 0x7) |
| 3567 | return -EINVAL; |
| 3568 | |
| 3569 | if (!exec_start) |
| 3570 | return -EINVAL; |
| 3571 | |
| 3572 | return 0; |
| 3573 | } |
| 3574 | |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3575 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3576 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
| 3577 | int count) |
| 3578 | { |
| 3579 | int i; |
| 3580 | |
| 3581 | for (i = 0; i < count; i++) { |
| 3582 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; |
| 3583 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); |
| 3584 | |
| 3585 | if (!access_ok(VERIFY_READ, ptr, length)) |
| 3586 | return -EFAULT; |
| 3587 | |
| 3588 | if (fault_in_pages_readable(ptr, length)) |
| 3589 | return -EFAULT; |
| 3590 | } |
| 3591 | |
| 3592 | return 0; |
| 3593 | } |
| 3594 | |
| 3595 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3596 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
| 3597 | struct drm_file *file_priv, |
| 3598 | struct drm_i915_gem_execbuffer2 *args, |
| 3599 | struct drm_i915_gem_exec_object2 *exec_list) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3600 | { |
| 3601 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3602 | struct drm_gem_object **object_list = NULL; |
| 3603 | struct drm_gem_object *batch_obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3604 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3605 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3606 | struct drm_i915_gem_request *request = NULL; |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3607 | int ret, i, pinned = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3608 | uint64_t exec_offset; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3609 | int pin_tries, flips; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3610 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3611 | struct intel_ring_buffer *ring = NULL; |
| 3612 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3613 | ret = i915_gem_check_is_wedged(dev); |
| 3614 | if (ret) |
| 3615 | return ret; |
| 3616 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3617 | ret = validate_exec_list(exec_list, args->buffer_count); |
| 3618 | if (ret) |
| 3619 | return ret; |
| 3620 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3621 | #if WATCH_EXEC |
| 3622 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3623 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3624 | #endif |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3625 | if (args->flags & I915_EXEC_BSD) { |
| 3626 | if (!HAS_BSD(dev)) { |
| 3627 | DRM_ERROR("execbuf with wrong flag\n"); |
| 3628 | return -EINVAL; |
| 3629 | } |
| 3630 | ring = &dev_priv->bsd_ring; |
| 3631 | } else { |
| 3632 | ring = &dev_priv->render_ring; |
| 3633 | } |
| 3634 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3635 | if (args->buffer_count < 1) { |
| 3636 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3637 | return -EINVAL; |
| 3638 | } |
Eric Anholt | c8e0f93 | 2009-11-22 03:49:37 +0100 | [diff] [blame] | 3639 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3640 | if (object_list == NULL) { |
| 3641 | DRM_ERROR("Failed to allocate object list for %d buffers\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3642 | args->buffer_count); |
| 3643 | ret = -ENOMEM; |
| 3644 | goto pre_mutex_err; |
| 3645 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3646 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3647 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3648 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3649 | GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3650 | if (cliprects == NULL) { |
| 3651 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3652 | goto pre_mutex_err; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3653 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3654 | |
| 3655 | ret = copy_from_user(cliprects, |
| 3656 | (struct drm_clip_rect __user *) |
| 3657 | (uintptr_t) args->cliprects_ptr, |
| 3658 | sizeof(*cliprects) * args->num_cliprects); |
| 3659 | if (ret != 0) { |
| 3660 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 3661 | args->num_cliprects, ret); |
Dan Carpenter | c877cdc | 2010-06-23 19:03:01 +0200 | [diff] [blame] | 3662 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3663 | goto pre_mutex_err; |
| 3664 | } |
| 3665 | } |
| 3666 | |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3667 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 3668 | if (request == NULL) { |
| 3669 | ret = -ENOMEM; |
| 3670 | goto pre_mutex_err; |
| 3671 | } |
| 3672 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3673 | ret = i915_mutex_lock_interruptible(dev); |
| 3674 | if (ret) |
| 3675 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3676 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3677 | if (dev_priv->mm.suspended) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3678 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3679 | ret = -EBUSY; |
| 3680 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3681 | } |
| 3682 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3683 | /* Look up object handles */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3684 | for (i = 0; i < args->buffer_count; i++) { |
| 3685 | object_list[i] = drm_gem_object_lookup(dev, file_priv, |
| 3686 | exec_list[i].handle); |
| 3687 | if (object_list[i] == NULL) { |
| 3688 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 3689 | exec_list[i].handle, i); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3690 | /* prevent error path from reading uninitialized data */ |
| 3691 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3692 | ret = -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3693 | goto err; |
| 3694 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3695 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3696 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3697 | if (obj_priv->in_execbuffer) { |
| 3698 | DRM_ERROR("Object %p appears more than once in object list\n", |
| 3699 | object_list[i]); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3700 | /* prevent error path from reading uninitialized data */ |
| 3701 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3702 | ret = -EINVAL; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3703 | goto err; |
| 3704 | } |
| 3705 | obj_priv->in_execbuffer = true; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3706 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3707 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3708 | /* Pin and relocate */ |
| 3709 | for (pin_tries = 0; ; pin_tries++) { |
| 3710 | ret = 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3711 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3712 | for (i = 0; i < args->buffer_count; i++) { |
| 3713 | object_list[i]->pending_read_domains = 0; |
| 3714 | object_list[i]->pending_write_domain = 0; |
| 3715 | ret = i915_gem_object_pin_and_relocate(object_list[i], |
| 3716 | file_priv, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame^] | 3717 | &exec_list[i]); |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3718 | if (ret) |
| 3719 | break; |
| 3720 | pinned = i + 1; |
| 3721 | } |
| 3722 | /* success */ |
| 3723 | if (ret == 0) |
| 3724 | break; |
| 3725 | |
| 3726 | /* error other than GTT full, or we've already tried again */ |
Chris Wilson | 2939e1f | 2009-06-06 09:46:03 +0100 | [diff] [blame] | 3727 | if (ret != -ENOSPC || pin_tries >= 1) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3728 | if (ret != -ERESTARTSYS) { |
| 3729 | unsigned long long total_size = 0; |
Chris Wilson | 3d1cc47 | 2010-05-27 13:18:19 +0100 | [diff] [blame] | 3730 | int num_fences = 0; |
| 3731 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 43b27f4 | 2010-07-02 08:57:15 +0100 | [diff] [blame] | 3732 | obj_priv = to_intel_bo(object_list[i]); |
Chris Wilson | 3d1cc47 | 2010-05-27 13:18:19 +0100 | [diff] [blame] | 3733 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3734 | total_size += object_list[i]->size; |
Chris Wilson | 3d1cc47 | 2010-05-27 13:18:19 +0100 | [diff] [blame] | 3735 | num_fences += |
| 3736 | exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3737 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 3738 | } |
| 3739 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n", |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3740 | pinned+1, args->buffer_count, |
Chris Wilson | 3d1cc47 | 2010-05-27 13:18:19 +0100 | [diff] [blame] | 3741 | total_size, num_fences, |
| 3742 | ret); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3743 | DRM_ERROR("%u objects [%u pinned, %u GTT], " |
| 3744 | "%zu object bytes [%zu pinned], " |
| 3745 | "%zu /%zu gtt bytes\n", |
| 3746 | dev_priv->mm.object_count, |
| 3747 | dev_priv->mm.pin_count, |
| 3748 | dev_priv->mm.gtt_count, |
| 3749 | dev_priv->mm.object_memory, |
| 3750 | dev_priv->mm.pin_memory, |
| 3751 | dev_priv->mm.gtt_memory, |
| 3752 | dev_priv->mm.gtt_total); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3753 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3754 | goto err; |
| 3755 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3756 | |
| 3757 | /* unpin all of our buffers */ |
| 3758 | for (i = 0; i < pinned; i++) |
| 3759 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | b117763 | 2008-12-10 10:09:41 -0800 | [diff] [blame] | 3760 | pinned = 0; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3761 | |
| 3762 | /* evict everyone we can from the aperture */ |
| 3763 | ret = i915_gem_evict_everything(dev); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3764 | if (ret && ret != -ENOSPC) |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3765 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3766 | } |
| 3767 | |
| 3768 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 3769 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 3770 | if (batch_obj->pending_write_domain) { |
| 3771 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 3772 | ret = -EINVAL; |
| 3773 | goto err; |
| 3774 | } |
| 3775 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3776 | |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3777 | /* Sanity check the batch buffer, prior to moving objects */ |
| 3778 | exec_offset = exec_list[args->buffer_count - 1].offset; |
| 3779 | ret = i915_gem_check_execbuffer (args, exec_offset); |
| 3780 | if (ret != 0) { |
| 3781 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 3782 | goto err; |
| 3783 | } |
| 3784 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3785 | /* Zero the global flush/invalidate flags. These |
| 3786 | * will be modified as new domains are computed |
| 3787 | * for each object |
| 3788 | */ |
| 3789 | dev->invalidate_domains = 0; |
| 3790 | dev->flush_domains = 0; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3791 | dev_priv->mm.flush_rings = 0; |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3792 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3793 | for (i = 0; i < args->buffer_count; i++) { |
| 3794 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3795 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3796 | /* Compute new gpu domains and update invalidate/flush */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3797 | i915_gem_object_set_to_gpu_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3798 | } |
| 3799 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3800 | if (dev->invalidate_domains | dev->flush_domains) { |
| 3801 | #if WATCH_EXEC |
| 3802 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3803 | __func__, |
| 3804 | dev->invalidate_domains, |
| 3805 | dev->flush_domains); |
| 3806 | #endif |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 3807 | i915_gem_flush(dev, file_priv, |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3808 | dev->invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3809 | dev->flush_domains, |
| 3810 | dev_priv->mm.flush_rings); |
Daniel Vetter | a691043 | 2010-02-02 17:08:37 +0100 | [diff] [blame] | 3811 | } |
| 3812 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3813 | for (i = 0; i < args->buffer_count; i++) { |
| 3814 | struct drm_gem_object *obj = object_list[i]; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3815 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3816 | uint32_t old_write_domain = obj->write_domain; |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3817 | |
| 3818 | obj->write_domain = obj->pending_write_domain; |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 3819 | if (obj->write_domain) |
| 3820 | list_move_tail(&obj_priv->gpu_write_list, |
| 3821 | &dev_priv->mm.gpu_write_list); |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 3822 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3823 | trace_i915_gem_object_change_domain(obj, |
| 3824 | obj->read_domains, |
| 3825 | old_write_domain); |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3826 | } |
| 3827 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3828 | #if WATCH_COHERENCY |
| 3829 | for (i = 0; i < args->buffer_count; i++) { |
| 3830 | i915_gem_object_check_coherency(object_list[i], |
| 3831 | exec_list[i].handle); |
| 3832 | } |
| 3833 | #endif |
| 3834 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3835 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 3836 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3837 | args->batch_len, |
| 3838 | __func__, |
| 3839 | ~0); |
| 3840 | #endif |
| 3841 | |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 3842 | /* Check for any pending flips. As we only maintain a flip queue depth |
| 3843 | * of 1, we can simply insert a WAIT for the next display flip prior |
| 3844 | * to executing the batch and avoid stalling the CPU. |
| 3845 | */ |
| 3846 | flips = 0; |
| 3847 | for (i = 0; i < args->buffer_count; i++) { |
| 3848 | if (object_list[i]->write_domain) |
| 3849 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); |
| 3850 | } |
| 3851 | if (flips) { |
| 3852 | int plane, flip_mask; |
| 3853 | |
| 3854 | for (plane = 0; flips >> plane; plane++) { |
| 3855 | if (((flips >> plane) & 1) == 0) |
| 3856 | continue; |
| 3857 | |
| 3858 | if (plane) |
| 3859 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 3860 | else |
| 3861 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 3862 | |
| 3863 | intel_ring_begin(dev, ring, 2); |
| 3864 | intel_ring_emit(dev, ring, |
| 3865 | MI_WAIT_FOR_EVENT | flip_mask); |
| 3866 | intel_ring_emit(dev, ring, MI_NOOP); |
| 3867 | intel_ring_advance(dev, ring); |
| 3868 | } |
| 3869 | } |
| 3870 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3871 | /* Exec the batchbuffer */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3872 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 3873 | cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3874 | if (ret) { |
| 3875 | DRM_ERROR("dispatch failed %d\n", ret); |
| 3876 | goto err; |
| 3877 | } |
| 3878 | |
| 3879 | /* |
| 3880 | * Ensure that the commands in the batch buffer are |
| 3881 | * finished before the interrupt fires |
| 3882 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 3883 | i915_retire_commands(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3884 | |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 3885 | for (i = 0; i < args->buffer_count; i++) { |
| 3886 | struct drm_gem_object *obj = object_list[i]; |
| 3887 | obj_priv = to_intel_bo(obj); |
| 3888 | |
| 3889 | i915_gem_object_move_to_active(obj, ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 3890 | } |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 3891 | |
Chris Wilson | 5c12a07e | 2010-09-22 11:22:30 +0100 | [diff] [blame] | 3892 | i915_add_request(dev, file_priv, request, ring); |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3893 | request = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3894 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3895 | err: |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3896 | for (i = 0; i < pinned; i++) |
| 3897 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3898 | |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3899 | for (i = 0; i < args->buffer_count; i++) { |
| 3900 | if (object_list[i]) { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3901 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3902 | obj_priv->in_execbuffer = false; |
| 3903 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3904 | drm_gem_object_unreference(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3905 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3906 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3907 | mutex_unlock(&dev->struct_mutex); |
| 3908 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3909 | pre_mutex_err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3910 | drm_free_large(object_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3911 | kfree(cliprects); |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3912 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3913 | |
| 3914 | return ret; |
| 3915 | } |
| 3916 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3917 | /* |
| 3918 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 3919 | * list array and passes it to the real function. |
| 3920 | */ |
| 3921 | int |
| 3922 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 3923 | struct drm_file *file_priv) |
| 3924 | { |
| 3925 | struct drm_i915_gem_execbuffer *args = data; |
| 3926 | struct drm_i915_gem_execbuffer2 exec2; |
| 3927 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 3928 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 3929 | int ret, i; |
| 3930 | |
| 3931 | #if WATCH_EXEC |
| 3932 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3933 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3934 | #endif |
| 3935 | |
| 3936 | if (args->buffer_count < 1) { |
| 3937 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3938 | return -EINVAL; |
| 3939 | } |
| 3940 | |
| 3941 | /* Copy in the exec list from userland */ |
| 3942 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 3943 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 3944 | if (exec_list == NULL || exec2_list == NULL) { |
| 3945 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 3946 | args->buffer_count); |
| 3947 | drm_free_large(exec_list); |
| 3948 | drm_free_large(exec2_list); |
| 3949 | return -ENOMEM; |
| 3950 | } |
| 3951 | ret = copy_from_user(exec_list, |
| 3952 | (struct drm_i915_relocation_entry __user *) |
| 3953 | (uintptr_t) args->buffers_ptr, |
| 3954 | sizeof(*exec_list) * args->buffer_count); |
| 3955 | if (ret != 0) { |
| 3956 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 3957 | args->buffer_count, ret); |
| 3958 | drm_free_large(exec_list); |
| 3959 | drm_free_large(exec2_list); |
| 3960 | return -EFAULT; |
| 3961 | } |
| 3962 | |
| 3963 | for (i = 0; i < args->buffer_count; i++) { |
| 3964 | exec2_list[i].handle = exec_list[i].handle; |
| 3965 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 3966 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 3967 | exec2_list[i].alignment = exec_list[i].alignment; |
| 3968 | exec2_list[i].offset = exec_list[i].offset; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3969 | if (INTEL_INFO(dev)->gen < 4) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3970 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 3971 | else |
| 3972 | exec2_list[i].flags = 0; |
| 3973 | } |
| 3974 | |
| 3975 | exec2.buffers_ptr = args->buffers_ptr; |
| 3976 | exec2.buffer_count = args->buffer_count; |
| 3977 | exec2.batch_start_offset = args->batch_start_offset; |
| 3978 | exec2.batch_len = args->batch_len; |
| 3979 | exec2.DR1 = args->DR1; |
| 3980 | exec2.DR4 = args->DR4; |
| 3981 | exec2.num_cliprects = args->num_cliprects; |
| 3982 | exec2.cliprects_ptr = args->cliprects_ptr; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3983 | exec2.flags = I915_EXEC_RENDER; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3984 | |
| 3985 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); |
| 3986 | if (!ret) { |
| 3987 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 3988 | for (i = 0; i < args->buffer_count; i++) |
| 3989 | exec_list[i].offset = exec2_list[i].offset; |
| 3990 | /* ... and back out to userspace */ |
| 3991 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 3992 | (uintptr_t) args->buffers_ptr, |
| 3993 | exec_list, |
| 3994 | sizeof(*exec_list) * args->buffer_count); |
| 3995 | if (ret) { |
| 3996 | ret = -EFAULT; |
| 3997 | DRM_ERROR("failed to copy %d exec entries " |
| 3998 | "back to user (%d)\n", |
| 3999 | args->buffer_count, ret); |
| 4000 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4001 | } |
| 4002 | |
| 4003 | drm_free_large(exec_list); |
| 4004 | drm_free_large(exec2_list); |
| 4005 | return ret; |
| 4006 | } |
| 4007 | |
| 4008 | int |
| 4009 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 4010 | struct drm_file *file_priv) |
| 4011 | { |
| 4012 | struct drm_i915_gem_execbuffer2 *args = data; |
| 4013 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 4014 | int ret; |
| 4015 | |
| 4016 | #if WATCH_EXEC |
| 4017 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 4018 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 4019 | #endif |
| 4020 | |
| 4021 | if (args->buffer_count < 1) { |
| 4022 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); |
| 4023 | return -EINVAL; |
| 4024 | } |
| 4025 | |
| 4026 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4027 | if (exec2_list == NULL) { |
| 4028 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4029 | args->buffer_count); |
| 4030 | return -ENOMEM; |
| 4031 | } |
| 4032 | ret = copy_from_user(exec2_list, |
| 4033 | (struct drm_i915_relocation_entry __user *) |
| 4034 | (uintptr_t) args->buffers_ptr, |
| 4035 | sizeof(*exec2_list) * args->buffer_count); |
| 4036 | if (ret != 0) { |
| 4037 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4038 | args->buffer_count, ret); |
| 4039 | drm_free_large(exec2_list); |
| 4040 | return -EFAULT; |
| 4041 | } |
| 4042 | |
| 4043 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); |
| 4044 | if (!ret) { |
| 4045 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4046 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4047 | (uintptr_t) args->buffers_ptr, |
| 4048 | exec2_list, |
| 4049 | sizeof(*exec2_list) * args->buffer_count); |
| 4050 | if (ret) { |
| 4051 | ret = -EFAULT; |
| 4052 | DRM_ERROR("failed to copy %d exec entries " |
| 4053 | "back to user (%d)\n", |
| 4054 | args->buffer_count, ret); |
| 4055 | } |
| 4056 | } |
| 4057 | |
| 4058 | drm_free_large(exec2_list); |
| 4059 | return ret; |
| 4060 | } |
| 4061 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4062 | int |
| 4063 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) |
| 4064 | { |
| 4065 | struct drm_device *dev = obj->dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4066 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4067 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4068 | int ret; |
| 4069 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 4070 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4071 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4072 | |
| 4073 | if (obj_priv->gtt_space != NULL) { |
| 4074 | if (alignment == 0) |
| 4075 | alignment = i915_gem_get_gtt_alignment(obj); |
| 4076 | if (obj_priv->gtt_offset & (alignment - 1)) { |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 4077 | WARN(obj_priv->pin_count, |
| 4078 | "bo is already pinned with incorrect alignment:" |
| 4079 | " offset=%x, req.alignment=%x\n", |
| 4080 | obj_priv->gtt_offset, alignment); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4081 | ret = i915_gem_object_unbind(obj); |
| 4082 | if (ret) |
| 4083 | return ret; |
| 4084 | } |
| 4085 | } |
| 4086 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4087 | if (obj_priv->gtt_space == NULL) { |
| 4088 | ret = i915_gem_object_bind_to_gtt(obj, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 4089 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4090 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4091 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4092 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4093 | obj_priv->pin_count++; |
| 4094 | |
| 4095 | /* If the object is not active and not pending a flush, |
| 4096 | * remove it from the inactive list |
| 4097 | */ |
| 4098 | if (obj_priv->pin_count == 1) { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4099 | i915_gem_info_add_pin(dev_priv, obj->size); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4100 | if (!obj_priv->active) |
| 4101 | list_move_tail(&obj_priv->list, |
| 4102 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4103 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4104 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4105 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4106 | return 0; |
| 4107 | } |
| 4108 | |
| 4109 | void |
| 4110 | i915_gem_object_unpin(struct drm_gem_object *obj) |
| 4111 | { |
| 4112 | struct drm_device *dev = obj->dev; |
| 4113 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4114 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4115 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4116 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4117 | obj_priv->pin_count--; |
| 4118 | BUG_ON(obj_priv->pin_count < 0); |
| 4119 | BUG_ON(obj_priv->gtt_space == NULL); |
| 4120 | |
| 4121 | /* If the object is no longer pinned, and is |
| 4122 | * neither active nor being flushed, then stick it on |
| 4123 | * the inactive list |
| 4124 | */ |
| 4125 | if (obj_priv->pin_count == 0) { |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4126 | if (!obj_priv->active) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4127 | list_move_tail(&obj_priv->list, |
| 4128 | &dev_priv->mm.inactive_list); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4129 | i915_gem_info_remove_pin(dev_priv, obj->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4130 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4131 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4132 | } |
| 4133 | |
| 4134 | int |
| 4135 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 4136 | struct drm_file *file_priv) |
| 4137 | { |
| 4138 | struct drm_i915_gem_pin *args = data; |
| 4139 | struct drm_gem_object *obj; |
| 4140 | struct drm_i915_gem_object *obj_priv; |
| 4141 | int ret; |
| 4142 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4143 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4144 | if (obj == NULL) { |
| 4145 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", |
| 4146 | args->handle); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4147 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4148 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4149 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4150 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4151 | ret = i915_mutex_lock_interruptible(dev); |
| 4152 | if (ret) { |
| 4153 | drm_gem_object_unreference_unlocked(obj); |
| 4154 | return ret; |
| 4155 | } |
| 4156 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4157 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 4158 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4159 | drm_gem_object_unreference(obj); |
| 4160 | mutex_unlock(&dev->struct_mutex); |
| 4161 | return -EINVAL; |
| 4162 | } |
| 4163 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4164 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
| 4165 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 4166 | args->handle); |
Chris Wilson | 96dec61 | 2009-02-08 19:08:04 +0000 | [diff] [blame] | 4167 | drm_gem_object_unreference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4168 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4169 | return -EINVAL; |
| 4170 | } |
| 4171 | |
| 4172 | obj_priv->user_pin_count++; |
| 4173 | obj_priv->pin_filp = file_priv; |
| 4174 | if (obj_priv->user_pin_count == 1) { |
| 4175 | ret = i915_gem_object_pin(obj, args->alignment); |
| 4176 | if (ret != 0) { |
| 4177 | drm_gem_object_unreference(obj); |
| 4178 | mutex_unlock(&dev->struct_mutex); |
| 4179 | return ret; |
| 4180 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4181 | } |
| 4182 | |
| 4183 | /* XXX - flush the CPU caches for pinned objects |
| 4184 | * as the X server doesn't manage domains yet |
| 4185 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4186 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4187 | args->offset = obj_priv->gtt_offset; |
| 4188 | drm_gem_object_unreference(obj); |
| 4189 | mutex_unlock(&dev->struct_mutex); |
| 4190 | |
| 4191 | return 0; |
| 4192 | } |
| 4193 | |
| 4194 | int |
| 4195 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 4196 | struct drm_file *file_priv) |
| 4197 | { |
| 4198 | struct drm_i915_gem_pin *args = data; |
| 4199 | struct drm_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4200 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4201 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4202 | |
| 4203 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4204 | if (obj == NULL) { |
| 4205 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", |
| 4206 | args->handle); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4207 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4208 | } |
| 4209 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4210 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4211 | |
| 4212 | ret = i915_mutex_lock_interruptible(dev); |
| 4213 | if (ret) { |
| 4214 | drm_gem_object_unreference_unlocked(obj); |
| 4215 | return ret; |
| 4216 | } |
| 4217 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4218 | if (obj_priv->pin_filp != file_priv) { |
| 4219 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4220 | args->handle); |
| 4221 | drm_gem_object_unreference(obj); |
| 4222 | mutex_unlock(&dev->struct_mutex); |
| 4223 | return -EINVAL; |
| 4224 | } |
| 4225 | obj_priv->user_pin_count--; |
| 4226 | if (obj_priv->user_pin_count == 0) { |
| 4227 | obj_priv->pin_filp = NULL; |
| 4228 | i915_gem_object_unpin(obj); |
| 4229 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4230 | |
| 4231 | drm_gem_object_unreference(obj); |
| 4232 | mutex_unlock(&dev->struct_mutex); |
| 4233 | return 0; |
| 4234 | } |
| 4235 | |
| 4236 | int |
| 4237 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4238 | struct drm_file *file_priv) |
| 4239 | { |
| 4240 | struct drm_i915_gem_busy *args = data; |
| 4241 | struct drm_gem_object *obj; |
| 4242 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4243 | int ret; |
| 4244 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4245 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4246 | if (obj == NULL) { |
| 4247 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", |
| 4248 | args->handle); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4249 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4250 | } |
| 4251 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4252 | ret = i915_mutex_lock_interruptible(dev); |
| 4253 | if (ret) { |
| 4254 | drm_gem_object_unreference_unlocked(obj); |
| 4255 | return ret; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4256 | } |
| 4257 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4258 | /* Count all active objects as busy, even if they are currently not used |
| 4259 | * by the gpu. Users of this interface expect objects to eventually |
| 4260 | * become non-busy without any further actions, therefore emit any |
| 4261 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4262 | */ |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4263 | obj_priv = to_intel_bo(obj); |
| 4264 | args->busy = obj_priv->active; |
| 4265 | if (args->busy) { |
| 4266 | /* Unconditionally flush objects, even when the gpu still uses this |
| 4267 | * object. Userspace calling this function indicates that it wants to |
| 4268 | * use this buffer rather sooner than later, so issuing the required |
| 4269 | * flush earlier is beneficial. |
| 4270 | */ |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 4271 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
| 4272 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 4273 | obj_priv->ring, |
| 4274 | 0, obj->write_domain); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4275 | |
| 4276 | /* Update the active list for the hardware's current position. |
| 4277 | * Otherwise this only updates on a delayed timer or when irqs |
| 4278 | * are actually unmasked, and our working set ends up being |
| 4279 | * larger than required. |
| 4280 | */ |
| 4281 | i915_gem_retire_requests_ring(dev, obj_priv->ring); |
| 4282 | |
| 4283 | args->busy = obj_priv->active; |
| 4284 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4285 | |
| 4286 | drm_gem_object_unreference(obj); |
| 4287 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4288 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4289 | } |
| 4290 | |
| 4291 | int |
| 4292 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4293 | struct drm_file *file_priv) |
| 4294 | { |
| 4295 | return i915_gem_ring_throttle(dev, file_priv); |
| 4296 | } |
| 4297 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4298 | int |
| 4299 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4300 | struct drm_file *file_priv) |
| 4301 | { |
| 4302 | struct drm_i915_gem_madvise *args = data; |
| 4303 | struct drm_gem_object *obj; |
| 4304 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4305 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4306 | |
| 4307 | switch (args->madv) { |
| 4308 | case I915_MADV_DONTNEED: |
| 4309 | case I915_MADV_WILLNEED: |
| 4310 | break; |
| 4311 | default: |
| 4312 | return -EINVAL; |
| 4313 | } |
| 4314 | |
| 4315 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4316 | if (obj == NULL) { |
| 4317 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", |
| 4318 | args->handle); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 4319 | return -ENOENT; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4320 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4321 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4322 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4323 | ret = i915_mutex_lock_interruptible(dev); |
| 4324 | if (ret) { |
| 4325 | drm_gem_object_unreference_unlocked(obj); |
| 4326 | return ret; |
| 4327 | } |
| 4328 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4329 | if (obj_priv->pin_count) { |
| 4330 | drm_gem_object_unreference(obj); |
| 4331 | mutex_unlock(&dev->struct_mutex); |
| 4332 | |
| 4333 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); |
| 4334 | return -EINVAL; |
| 4335 | } |
| 4336 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4337 | if (obj_priv->madv != __I915_MADV_PURGED) |
| 4338 | obj_priv->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4339 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4340 | /* if the object is no longer bound, discard its backing storage */ |
| 4341 | if (i915_gem_object_is_purgeable(obj_priv) && |
| 4342 | obj_priv->gtt_space == NULL) |
| 4343 | i915_gem_object_truncate(obj); |
| 4344 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4345 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
| 4346 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4347 | drm_gem_object_unreference(obj); |
| 4348 | mutex_unlock(&dev->struct_mutex); |
| 4349 | |
| 4350 | return 0; |
| 4351 | } |
| 4352 | |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4353 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
| 4354 | size_t size) |
| 4355 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4356 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4357 | struct drm_i915_gem_object *obj; |
| 4358 | |
| 4359 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 4360 | if (obj == NULL) |
| 4361 | return NULL; |
| 4362 | |
| 4363 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 4364 | kfree(obj); |
| 4365 | return NULL; |
| 4366 | } |
| 4367 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4368 | i915_gem_info_add_obj(dev_priv, size); |
| 4369 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4370 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4371 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4372 | |
| 4373 | obj->agp_type = AGP_USER_MEMORY; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 4374 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4375 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4376 | INIT_LIST_HEAD(&obj->list); |
| 4377 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4378 | obj->madv = I915_MADV_WILLNEED; |
| 4379 | |
| 4380 | trace_i915_gem_object_create(&obj->base); |
| 4381 | |
| 4382 | return &obj->base; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4383 | } |
| 4384 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4385 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4386 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4387 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4388 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4389 | return 0; |
| 4390 | } |
| 4391 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4392 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
| 4393 | { |
| 4394 | struct drm_device *dev = obj->dev; |
| 4395 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4396 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 4397 | int ret; |
| 4398 | |
| 4399 | ret = i915_gem_object_unbind(obj); |
| 4400 | if (ret == -ERESTARTSYS) { |
| 4401 | list_move(&obj_priv->list, |
| 4402 | &dev_priv->mm.deferred_free_list); |
| 4403 | return; |
| 4404 | } |
| 4405 | |
| 4406 | if (obj_priv->mmap_offset) |
| 4407 | i915_gem_free_mmap_offset(obj); |
| 4408 | |
| 4409 | drm_gem_object_release(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4410 | i915_gem_info_remove_obj(dev_priv, obj->size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4411 | |
| 4412 | kfree(obj_priv->page_cpu_valid); |
| 4413 | kfree(obj_priv->bit_17); |
| 4414 | kfree(obj_priv); |
| 4415 | } |
| 4416 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4417 | void i915_gem_free_object(struct drm_gem_object *obj) |
| 4418 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4419 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4420 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4421 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4422 | trace_i915_gem_object_destroy(obj); |
| 4423 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4424 | while (obj_priv->pin_count > 0) |
| 4425 | i915_gem_object_unpin(obj); |
| 4426 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4427 | if (obj_priv->phys_obj) |
| 4428 | i915_gem_detach_phys_object(dev, obj); |
| 4429 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4430 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4431 | } |
| 4432 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4433 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4434 | i915_gem_idle(struct drm_device *dev) |
| 4435 | { |
| 4436 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4437 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4438 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4439 | mutex_lock(&dev->struct_mutex); |
| 4440 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4441 | if (dev_priv->mm.suspended || |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4442 | (dev_priv->render_ring.gem_object == NULL) || |
| 4443 | (HAS_BSD(dev) && |
| 4444 | dev_priv->bsd_ring.gem_object == NULL)) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4445 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4446 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4447 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4448 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4449 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4450 | if (ret) { |
| 4451 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4452 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4453 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4454 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4455 | /* Under UMS, be paranoid and evict. */ |
| 4456 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 4457 | ret = i915_gem_evict_inactive(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4458 | if (ret) { |
| 4459 | mutex_unlock(&dev->struct_mutex); |
| 4460 | return ret; |
| 4461 | } |
| 4462 | } |
| 4463 | |
| 4464 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4465 | * We need to replace this with a semaphore, or something. |
| 4466 | * And not confound mm.suspended! |
| 4467 | */ |
| 4468 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 4469 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4470 | |
| 4471 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4472 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4473 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4474 | mutex_unlock(&dev->struct_mutex); |
| 4475 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4476 | /* Cancel the retire work handler, which should be idle now. */ |
| 4477 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4478 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4479 | return 0; |
| 4480 | } |
| 4481 | |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4482 | /* |
| 4483 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 4484 | * over cache flushing. |
| 4485 | */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4486 | static int |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4487 | i915_gem_init_pipe_control(struct drm_device *dev) |
| 4488 | { |
| 4489 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4490 | struct drm_gem_object *obj; |
| 4491 | struct drm_i915_gem_object *obj_priv; |
| 4492 | int ret; |
| 4493 | |
Eric Anholt | 34dc4d4 | 2010-05-07 14:30:03 -0700 | [diff] [blame] | 4494 | obj = i915_gem_alloc_object(dev, 4096); |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4495 | if (obj == NULL) { |
| 4496 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 4497 | ret = -ENOMEM; |
| 4498 | goto err; |
| 4499 | } |
| 4500 | obj_priv = to_intel_bo(obj); |
| 4501 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
| 4502 | |
| 4503 | ret = i915_gem_object_pin(obj, 4096); |
| 4504 | if (ret) |
| 4505 | goto err_unref; |
| 4506 | |
| 4507 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; |
| 4508 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); |
| 4509 | if (dev_priv->seqno_page == NULL) |
| 4510 | goto err_unpin; |
| 4511 | |
| 4512 | dev_priv->seqno_obj = obj; |
| 4513 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); |
| 4514 | |
| 4515 | return 0; |
| 4516 | |
| 4517 | err_unpin: |
| 4518 | i915_gem_object_unpin(obj); |
| 4519 | err_unref: |
| 4520 | drm_gem_object_unreference(obj); |
| 4521 | err: |
| 4522 | return ret; |
| 4523 | } |
| 4524 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4525 | |
| 4526 | static void |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4527 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
| 4528 | { |
| 4529 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4530 | struct drm_gem_object *obj; |
| 4531 | struct drm_i915_gem_object *obj_priv; |
| 4532 | |
| 4533 | obj = dev_priv->seqno_obj; |
| 4534 | obj_priv = to_intel_bo(obj); |
| 4535 | kunmap(obj_priv->pages[0]); |
| 4536 | i915_gem_object_unpin(obj); |
| 4537 | drm_gem_object_unreference(obj); |
| 4538 | dev_priv->seqno_obj = NULL; |
| 4539 | |
| 4540 | dev_priv->seqno_page = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4541 | } |
| 4542 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4543 | int |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4544 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4545 | { |
| 4546 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4547 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4548 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4549 | if (HAS_PIPE_CONTROL(dev)) { |
| 4550 | ret = i915_gem_init_pipe_control(dev); |
| 4551 | if (ret) |
| 4552 | return ret; |
| 4553 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4554 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4555 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4556 | if (ret) |
| 4557 | goto cleanup_pipe_control; |
| 4558 | |
| 4559 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4560 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4561 | if (ret) |
| 4562 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4563 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4564 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 4565 | dev_priv->next_seqno = 1; |
| 4566 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4567 | return 0; |
| 4568 | |
| 4569 | cleanup_render_ring: |
| 4570 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); |
| 4571 | cleanup_pipe_control: |
| 4572 | if (HAS_PIPE_CONTROL(dev)) |
| 4573 | i915_gem_cleanup_pipe_control(dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4574 | return ret; |
| 4575 | } |
| 4576 | |
| 4577 | void |
| 4578 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4579 | { |
| 4580 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4581 | |
| 4582 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4583 | if (HAS_BSD(dev)) |
| 4584 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4585 | if (HAS_PIPE_CONTROL(dev)) |
| 4586 | i915_gem_cleanup_pipe_control(dev); |
| 4587 | } |
| 4588 | |
| 4589 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4590 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4591 | struct drm_file *file_priv) |
| 4592 | { |
| 4593 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4594 | int ret; |
| 4595 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4596 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4597 | return 0; |
| 4598 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4599 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4600 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4601 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4602 | } |
| 4603 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4604 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4605 | dev_priv->mm.suspended = 0; |
| 4606 | |
| 4607 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4608 | if (ret != 0) { |
| 4609 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4610 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4611 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4612 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4613 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4614 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4615 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4616 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4617 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4618 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4619 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4620 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4621 | ret = drm_irq_install(dev); |
| 4622 | if (ret) |
| 4623 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4624 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4625 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4626 | |
| 4627 | cleanup_ringbuffer: |
| 4628 | mutex_lock(&dev->struct_mutex); |
| 4629 | i915_gem_cleanup_ringbuffer(dev); |
| 4630 | dev_priv->mm.suspended = 1; |
| 4631 | mutex_unlock(&dev->struct_mutex); |
| 4632 | |
| 4633 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4634 | } |
| 4635 | |
| 4636 | int |
| 4637 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4638 | struct drm_file *file_priv) |
| 4639 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4640 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4641 | return 0; |
| 4642 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4643 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4644 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4645 | } |
| 4646 | |
| 4647 | void |
| 4648 | i915_gem_lastclose(struct drm_device *dev) |
| 4649 | { |
| 4650 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4651 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4652 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4653 | return; |
| 4654 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4655 | ret = i915_gem_idle(dev); |
| 4656 | if (ret) |
| 4657 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4658 | } |
| 4659 | |
| 4660 | void |
| 4661 | i915_gem_load(struct drm_device *dev) |
| 4662 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4663 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4664 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4665 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4666 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 4667 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4668 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4669 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4670 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4671 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4672 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
| 4673 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4674 | if (HAS_BSD(dev)) { |
| 4675 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); |
| 4676 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); |
| 4677 | } |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4678 | for (i = 0; i < 16; i++) |
| 4679 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4680 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4681 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4682 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4683 | spin_lock(&shrink_list_lock); |
| 4684 | list_add(&dev_priv->mm.shrink_list, &shrink_list); |
| 4685 | spin_unlock(&shrink_list_lock); |
| 4686 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4687 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4688 | if (IS_GEN3(dev)) { |
| 4689 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 4690 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 4691 | /* arb state is a masked write, so set bit + bit in mask */ |
| 4692 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 4693 | I915_WRITE(MI_ARB_STATE, tmp); |
| 4694 | } |
| 4695 | } |
| 4696 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4697 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4698 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4699 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4700 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4701 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4702 | dev_priv->num_fence_regs = 16; |
| 4703 | else |
| 4704 | dev_priv->num_fence_regs = 8; |
| 4705 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4706 | /* Initialize fence registers to zero */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4707 | switch (INTEL_INFO(dev)->gen) { |
| 4708 | case 6: |
| 4709 | for (i = 0; i < 16; i++) |
| 4710 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); |
| 4711 | break; |
| 4712 | case 5: |
| 4713 | case 4: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4714 | for (i = 0; i < 16; i++) |
| 4715 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4716 | break; |
| 4717 | case 3: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4718 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4719 | for (i = 0; i < 8; i++) |
| 4720 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4721 | case 2: |
| 4722 | for (i = 0; i < 8; i++) |
| 4723 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4724 | break; |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4725 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4726 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4727 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4728 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4729 | |
| 4730 | /* |
| 4731 | * Create a physically contiguous memory object for this object |
| 4732 | * e.g. for cursor + overlay regs |
| 4733 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4734 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4735 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4736 | { |
| 4737 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4738 | struct drm_i915_gem_phys_object *phys_obj; |
| 4739 | int ret; |
| 4740 | |
| 4741 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4742 | return 0; |
| 4743 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4744 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4745 | if (!phys_obj) |
| 4746 | return -ENOMEM; |
| 4747 | |
| 4748 | phys_obj->id = id; |
| 4749 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4750 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4751 | if (!phys_obj->handle) { |
| 4752 | ret = -ENOMEM; |
| 4753 | goto kfree_obj; |
| 4754 | } |
| 4755 | #ifdef CONFIG_X86 |
| 4756 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4757 | #endif |
| 4758 | |
| 4759 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4760 | |
| 4761 | return 0; |
| 4762 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4763 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4764 | return ret; |
| 4765 | } |
| 4766 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4767 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4768 | { |
| 4769 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4770 | struct drm_i915_gem_phys_object *phys_obj; |
| 4771 | |
| 4772 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4773 | return; |
| 4774 | |
| 4775 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4776 | if (phys_obj->cur_obj) { |
| 4777 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4778 | } |
| 4779 | |
| 4780 | #ifdef CONFIG_X86 |
| 4781 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4782 | #endif |
| 4783 | drm_pci_free(dev, phys_obj->handle); |
| 4784 | kfree(phys_obj); |
| 4785 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4786 | } |
| 4787 | |
| 4788 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4789 | { |
| 4790 | int i; |
| 4791 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4792 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4793 | i915_gem_free_phys_object(dev, i); |
| 4794 | } |
| 4795 | |
| 4796 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 4797 | struct drm_gem_object *obj) |
| 4798 | { |
| 4799 | struct drm_i915_gem_object *obj_priv; |
| 4800 | int i; |
| 4801 | int ret; |
| 4802 | int page_count; |
| 4803 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4804 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4805 | if (!obj_priv->phys_obj) |
| 4806 | return; |
| 4807 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4808 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4809 | if (ret) |
| 4810 | goto out; |
| 4811 | |
| 4812 | page_count = obj->size / PAGE_SIZE; |
| 4813 | |
| 4814 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4815 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4816 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4817 | |
| 4818 | memcpy(dst, src, PAGE_SIZE); |
| 4819 | kunmap_atomic(dst, KM_USER0); |
| 4820 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4821 | drm_clflush_pages(obj_priv->pages, page_count); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4822 | drm_agp_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4823 | |
| 4824 | i915_gem_object_put_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4825 | out: |
| 4826 | obj_priv->phys_obj->cur_obj = NULL; |
| 4827 | obj_priv->phys_obj = NULL; |
| 4828 | } |
| 4829 | |
| 4830 | int |
| 4831 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4832 | struct drm_gem_object *obj, |
| 4833 | int id, |
| 4834 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4835 | { |
| 4836 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4837 | struct drm_i915_gem_object *obj_priv; |
| 4838 | int ret = 0; |
| 4839 | int page_count; |
| 4840 | int i; |
| 4841 | |
| 4842 | if (id > I915_MAX_PHYS_OBJECT) |
| 4843 | return -EINVAL; |
| 4844 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4845 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4846 | |
| 4847 | if (obj_priv->phys_obj) { |
| 4848 | if (obj_priv->phys_obj->id == id) |
| 4849 | return 0; |
| 4850 | i915_gem_detach_phys_object(dev, obj); |
| 4851 | } |
| 4852 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4853 | /* create a new object */ |
| 4854 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4855 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4856 | obj->size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4857 | if (ret) { |
Linus Torvalds | aeb565d | 2009-01-26 10:01:53 -0800 | [diff] [blame] | 4858 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4859 | goto out; |
| 4860 | } |
| 4861 | } |
| 4862 | |
| 4863 | /* bind to the object */ |
| 4864 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4865 | obj_priv->phys_obj->cur_obj = obj; |
| 4866 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4867 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4868 | if (ret) { |
| 4869 | DRM_ERROR("failed to get page list\n"); |
| 4870 | goto out; |
| 4871 | } |
| 4872 | |
| 4873 | page_count = obj->size / PAGE_SIZE; |
| 4874 | |
| 4875 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4876 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4877 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4878 | |
| 4879 | memcpy(dst, src, PAGE_SIZE); |
| 4880 | kunmap_atomic(src, KM_USER0); |
| 4881 | } |
| 4882 | |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4883 | i915_gem_object_put_pages(obj); |
| 4884 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4885 | return 0; |
| 4886 | out: |
| 4887 | return ret; |
| 4888 | } |
| 4889 | |
| 4890 | static int |
| 4891 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 4892 | struct drm_i915_gem_pwrite *args, |
| 4893 | struct drm_file *file_priv) |
| 4894 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4895 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4896 | void *obj_addr; |
| 4897 | int ret; |
| 4898 | char __user *user_data; |
| 4899 | |
| 4900 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 4901 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; |
| 4902 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4903 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4904 | ret = copy_from_user(obj_addr, user_data, args->size); |
| 4905 | if (ret) |
| 4906 | return -EFAULT; |
| 4907 | |
| 4908 | drm_agp_chipset_flush(dev); |
| 4909 | return 0; |
| 4910 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4911 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4912 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4913 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4914 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4915 | |
| 4916 | /* Clean up our request list when the client is going away, so that |
| 4917 | * later retire_requests won't dereference our soon-to-be-gone |
| 4918 | * file_priv. |
| 4919 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4920 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4921 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4922 | struct drm_i915_gem_request *request; |
| 4923 | |
| 4924 | request = list_first_entry(&file_priv->mm.request_list, |
| 4925 | struct drm_i915_gem_request, |
| 4926 | client_list); |
| 4927 | list_del(&request->client_list); |
| 4928 | request->file_priv = NULL; |
| 4929 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4930 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4931 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4932 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4933 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4934 | i915_gpu_is_active(struct drm_device *dev) |
| 4935 | { |
| 4936 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4937 | int lists_empty; |
| 4938 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4939 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4940 | list_empty(&dev_priv->render_ring.active_list); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4941 | if (HAS_BSD(dev)) |
| 4942 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4943 | |
| 4944 | return !lists_empty; |
| 4945 | } |
| 4946 | |
| 4947 | static int |
Dave Chinner | 7f8275d | 2010-07-19 14:56:17 +1000 | [diff] [blame] | 4948 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4949 | { |
| 4950 | drm_i915_private_t *dev_priv, *next_dev; |
| 4951 | struct drm_i915_gem_object *obj_priv, *next_obj; |
| 4952 | int cnt = 0; |
| 4953 | int would_deadlock = 1; |
| 4954 | |
| 4955 | /* "fast-path" to count number of available objects */ |
| 4956 | if (nr_to_scan == 0) { |
| 4957 | spin_lock(&shrink_list_lock); |
| 4958 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 4959 | struct drm_device *dev = dev_priv->dev; |
| 4960 | |
| 4961 | if (mutex_trylock(&dev->struct_mutex)) { |
| 4962 | list_for_each_entry(obj_priv, |
| 4963 | &dev_priv->mm.inactive_list, |
| 4964 | list) |
| 4965 | cnt++; |
| 4966 | mutex_unlock(&dev->struct_mutex); |
| 4967 | } |
| 4968 | } |
| 4969 | spin_unlock(&shrink_list_lock); |
| 4970 | |
| 4971 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 4972 | } |
| 4973 | |
| 4974 | spin_lock(&shrink_list_lock); |
| 4975 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4976 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4977 | /* first scan for clean buffers */ |
| 4978 | list_for_each_entry_safe(dev_priv, next_dev, |
| 4979 | &shrink_list, mm.shrink_list) { |
| 4980 | struct drm_device *dev = dev_priv->dev; |
| 4981 | |
| 4982 | if (! mutex_trylock(&dev->struct_mutex)) |
| 4983 | continue; |
| 4984 | |
| 4985 | spin_unlock(&shrink_list_lock); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 4986 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4987 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4988 | list_for_each_entry_safe(obj_priv, next_obj, |
| 4989 | &dev_priv->mm.inactive_list, |
| 4990 | list) { |
| 4991 | if (i915_gem_object_is_purgeable(obj_priv)) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 4992 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4993 | if (--nr_to_scan <= 0) |
| 4994 | break; |
| 4995 | } |
| 4996 | } |
| 4997 | |
| 4998 | spin_lock(&shrink_list_lock); |
| 4999 | mutex_unlock(&dev->struct_mutex); |
| 5000 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 5001 | would_deadlock = 0; |
| 5002 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5003 | if (nr_to_scan <= 0) |
| 5004 | break; |
| 5005 | } |
| 5006 | |
| 5007 | /* second pass, evict/count anything still on the inactive list */ |
| 5008 | list_for_each_entry_safe(dev_priv, next_dev, |
| 5009 | &shrink_list, mm.shrink_list) { |
| 5010 | struct drm_device *dev = dev_priv->dev; |
| 5011 | |
| 5012 | if (! mutex_trylock(&dev->struct_mutex)) |
| 5013 | continue; |
| 5014 | |
| 5015 | spin_unlock(&shrink_list_lock); |
| 5016 | |
| 5017 | list_for_each_entry_safe(obj_priv, next_obj, |
| 5018 | &dev_priv->mm.inactive_list, |
| 5019 | list) { |
| 5020 | if (nr_to_scan > 0) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 5021 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5022 | nr_to_scan--; |
| 5023 | } else |
| 5024 | cnt++; |
| 5025 | } |
| 5026 | |
| 5027 | spin_lock(&shrink_list_lock); |
| 5028 | mutex_unlock(&dev->struct_mutex); |
| 5029 | |
| 5030 | would_deadlock = 0; |
| 5031 | } |
| 5032 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5033 | if (nr_to_scan) { |
| 5034 | int active = 0; |
| 5035 | |
| 5036 | /* |
| 5037 | * We are desperate for pages, so as a last resort, wait |
| 5038 | * for the GPU to finish and discard whatever we can. |
| 5039 | * This has a dramatic impact to reduce the number of |
| 5040 | * OOM-killer events whilst running the GPU aggressively. |
| 5041 | */ |
| 5042 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 5043 | struct drm_device *dev = dev_priv->dev; |
| 5044 | |
| 5045 | if (!mutex_trylock(&dev->struct_mutex)) |
| 5046 | continue; |
| 5047 | |
| 5048 | spin_unlock(&shrink_list_lock); |
| 5049 | |
| 5050 | if (i915_gpu_is_active(dev)) { |
| 5051 | i915_gpu_idle(dev); |
| 5052 | active++; |
| 5053 | } |
| 5054 | |
| 5055 | spin_lock(&shrink_list_lock); |
| 5056 | mutex_unlock(&dev->struct_mutex); |
| 5057 | } |
| 5058 | |
| 5059 | if (active) |
| 5060 | goto rescan; |
| 5061 | } |
| 5062 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5063 | spin_unlock(&shrink_list_lock); |
| 5064 | |
| 5065 | if (would_deadlock) |
| 5066 | return -1; |
| 5067 | else if (cnt > 0) |
| 5068 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 5069 | else |
| 5070 | return 0; |
| 5071 | } |
| 5072 | |
| 5073 | static struct shrinker shrinker = { |
| 5074 | .shrink = i915_gem_shrink, |
| 5075 | .seeks = DEFAULT_SEEKS, |
| 5076 | }; |
| 5077 | |
| 5078 | __init void |
| 5079 | i915_gem_shrinker_init(void) |
| 5080 | { |
| 5081 | register_shrinker(&shrinker); |
| 5082 | } |
| 5083 | |
| 5084 | __exit void |
| 5085 | i915_gem_shrinker_exit(void) |
| 5086 | { |
| 5087 | unregister_shrinker(&shrinker); |
| 5088 | } |