blob: f028aef9a861f284f280abf52f00fa106bdcad26 [file] [log] [blame]
Russell Kingd111e8f2006-09-27 15:27:33 +01001/*
2 * linux/arch/arm/mm/mmu.c
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
Russell Kingae8f1542006-09-27 15:38:34 +010010#include <linux/module.h>
Russell Kingd111e8f2006-09-27 15:27:33 +010011#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/bootmem.h>
15#include <linux/mman.h>
16#include <linux/nodemask.h>
17
18#include <asm/mach-types.h>
19#include <asm/setup.h>
20#include <asm/sizes.h>
21#include <asm/tlb.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25
26#include "mm.h"
27
28DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
29
Russell King6ae5a6e2006-09-30 10:50:05 +010030extern void _stext, _etext, __data_start, _end;
Russell Kingd111e8f2006-09-27 15:27:33 +010031extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
32
33/*
34 * empty_zero_page is a special page that is used for
35 * zero-initialized data and COW.
36 */
37struct page *empty_zero_page;
38
39/*
40 * The pmd table for the upper-most set of pages.
41 */
42pmd_t *top_pmd;
43
Russell Kingae8f1542006-09-27 15:38:34 +010044#define CPOLICY_UNCACHED 0
45#define CPOLICY_BUFFERED 1
46#define CPOLICY_WRITETHROUGH 2
47#define CPOLICY_WRITEBACK 3
48#define CPOLICY_WRITEALLOC 4
49
50static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
51static unsigned int ecc_mask __initdata = 0;
52pgprot_t pgprot_kernel;
53
54EXPORT_SYMBOL(pgprot_kernel);
55
56struct cachepolicy {
57 const char policy[16];
58 unsigned int cr_mask;
59 unsigned int pmd;
60 unsigned int pte;
61};
62
63static struct cachepolicy cache_policies[] __initdata = {
64 {
65 .policy = "uncached",
66 .cr_mask = CR_W|CR_C,
67 .pmd = PMD_SECT_UNCACHED,
68 .pte = 0,
69 }, {
70 .policy = "buffered",
71 .cr_mask = CR_C,
72 .pmd = PMD_SECT_BUFFERED,
73 .pte = PTE_BUFFERABLE,
74 }, {
75 .policy = "writethrough",
76 .cr_mask = 0,
77 .pmd = PMD_SECT_WT,
78 .pte = PTE_CACHEABLE,
79 }, {
80 .policy = "writeback",
81 .cr_mask = 0,
82 .pmd = PMD_SECT_WB,
83 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
84 }, {
85 .policy = "writealloc",
86 .cr_mask = 0,
87 .pmd = PMD_SECT_WBWA,
88 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
89 }
90};
91
92/*
93 * These are useful for identifing cache coherency
94 * problems by allowing the cache or the cache and
95 * writebuffer to be turned off. (Note: the write
96 * buffer should not be on and the cache off).
97 */
98static void __init early_cachepolicy(char **p)
99{
100 int i;
101
102 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
103 int len = strlen(cache_policies[i].policy);
104
105 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
106 cachepolicy = i;
107 cr_alignment &= ~cache_policies[i].cr_mask;
108 cr_no_alignment &= ~cache_policies[i].cr_mask;
109 *p += len;
110 break;
111 }
112 }
113 if (i == ARRAY_SIZE(cache_policies))
114 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
115 flush_cache_all();
116 set_cr(cr_alignment);
117}
118__early_param("cachepolicy=", early_cachepolicy);
119
120static void __init early_nocache(char **__unused)
121{
122 char *p = "buffered";
123 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
124 early_cachepolicy(&p);
125}
126__early_param("nocache", early_nocache);
127
128static void __init early_nowrite(char **__unused)
129{
130 char *p = "uncached";
131 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
132 early_cachepolicy(&p);
133}
134__early_param("nowb", early_nowrite);
135
136static void __init early_ecc(char **p)
137{
138 if (memcmp(*p, "on", 2) == 0) {
139 ecc_mask = PMD_PROTECTION;
140 *p += 2;
141 } else if (memcmp(*p, "off", 3) == 0) {
142 ecc_mask = 0;
143 *p += 3;
144 }
145}
146__early_param("ecc=", early_ecc);
147
148static int __init noalign_setup(char *__unused)
149{
150 cr_alignment &= ~CR_A;
151 cr_no_alignment &= ~CR_A;
152 set_cr(cr_alignment);
153 return 1;
154}
155__setup("noalign", noalign_setup);
156
157struct mem_types {
158 unsigned int prot_pte;
159 unsigned int prot_l1;
160 unsigned int prot_sect;
161 unsigned int domain;
162};
163
164static struct mem_types mem_types[] __initdata = {
165 [MT_DEVICE] = {
166 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
167 L_PTE_WRITE,
168 .prot_l1 = PMD_TYPE_TABLE,
169 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
170 PMD_SECT_AP_WRITE,
171 .domain = DOMAIN_IO,
172 },
173 [MT_CACHECLEAN] = {
174 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
175 .domain = DOMAIN_KERNEL,
176 },
177 [MT_MINICLEAN] = {
178 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
179 .domain = DOMAIN_KERNEL,
180 },
181 [MT_LOW_VECTORS] = {
182 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
183 L_PTE_EXEC,
184 .prot_l1 = PMD_TYPE_TABLE,
185 .domain = DOMAIN_USER,
186 },
187 [MT_HIGH_VECTORS] = {
188 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
189 L_PTE_USER | L_PTE_EXEC,
190 .prot_l1 = PMD_TYPE_TABLE,
191 .domain = DOMAIN_USER,
192 },
193 [MT_MEMORY] = {
194 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
195 .domain = DOMAIN_KERNEL,
196 },
197 [MT_ROM] = {
198 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
199 .domain = DOMAIN_KERNEL,
200 },
201 [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
202 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
203 L_PTE_WRITE,
204 .prot_l1 = PMD_TYPE_TABLE,
205 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
206 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
207 PMD_SECT_TEX(1),
208 .domain = DOMAIN_IO,
209 },
210 [MT_NONSHARED_DEVICE] = {
211 .prot_l1 = PMD_TYPE_TABLE,
212 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV |
213 PMD_SECT_AP_WRITE,
214 .domain = DOMAIN_IO,
215 }
216};
217
218/*
219 * Adjust the PMD section entries according to the CPU in use.
220 */
221static void __init build_mem_type_table(void)
222{
223 struct cachepolicy *cp;
224 unsigned int cr = get_cr();
225 unsigned int user_pgprot, kern_pgprot;
226 int cpu_arch = cpu_architecture();
227 int i;
228
229#if defined(CONFIG_CPU_DCACHE_DISABLE)
230 if (cachepolicy > CPOLICY_BUFFERED)
231 cachepolicy = CPOLICY_BUFFERED;
232#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
233 if (cachepolicy > CPOLICY_WRITETHROUGH)
234 cachepolicy = CPOLICY_WRITETHROUGH;
235#endif
236 if (cpu_arch < CPU_ARCH_ARMv5) {
237 if (cachepolicy >= CPOLICY_WRITEALLOC)
238 cachepolicy = CPOLICY_WRITEBACK;
239 ecc_mask = 0;
240 }
241
242 /*
243 * Xscale must not have PMD bit 4 set for section mappings.
244 */
245 if (cpu_is_xscale())
246 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
247 mem_types[i].prot_sect &= ~PMD_BIT4;
248
249 /*
250 * ARMv5 and lower, excluding Xscale, bit 4 must be set for
251 * page tables.
252 */
253 if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale())
254 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
255 if (mem_types[i].prot_l1)
256 mem_types[i].prot_l1 |= PMD_BIT4;
257
258 cp = &cache_policies[cachepolicy];
259 kern_pgprot = user_pgprot = cp->pte;
260
261 /*
262 * Enable CPU-specific coherency if supported.
263 * (Only available on XSC3 at the moment.)
264 */
265 if (arch_is_coherent()) {
266 if (cpu_is_xsc3()) {
267 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
Lennert Buytenhek0e5fdca2006-12-02 00:03:47 +0100268 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
Russell Kingae8f1542006-09-27 15:38:34 +0100269 }
270 }
271
272 /*
273 * ARMv6 and above have extended page tables.
274 */
275 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
276 /*
277 * bit 4 becomes XN which we must clear for the
278 * kernel memory mapping.
279 */
280 mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN;
281 mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN;
282
283 /*
284 * Mark cache clean areas and XIP ROM read only
285 * from SVC mode and no access from userspace.
286 */
287 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
288 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
289 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
290
291 /*
292 * Mark the device area as "shared device"
293 */
294 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
295 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
296
Russell Kingae8f1542006-09-27 15:38:34 +0100297#ifdef CONFIG_SMP
298 /*
299 * Mark memory with the "shared" attribute for SMP systems
300 */
301 user_pgprot |= L_PTE_SHARED;
302 kern_pgprot |= L_PTE_SHARED;
303 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
304#endif
305 }
306
307 for (i = 0; i < 16; i++) {
308 unsigned long v = pgprot_val(protection_map[i]);
309 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
310 protection_map[i] = __pgprot(v);
311 }
312
313 mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
314 mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
315
316 if (cpu_arch >= CPU_ARCH_ARMv5) {
317#ifndef CONFIG_SMP
318 /*
319 * Only use write-through for non-SMP systems
320 */
321 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
322 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
323#endif
324 } else {
325 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
326 }
327
328 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
329 L_PTE_DIRTY | L_PTE_WRITE |
330 L_PTE_EXEC | kern_pgprot);
331
332 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
333 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
334 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
335 mem_types[MT_ROM].prot_sect |= cp->pmd;
336
337 switch (cp->pmd) {
338 case PMD_SECT_WT:
339 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
340 break;
341 case PMD_SECT_WB:
342 case PMD_SECT_WBWA:
343 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
344 break;
345 }
346 printk("Memory policy: ECC %sabled, Data cache %s\n",
347 ecc_mask ? "en" : "dis", cp->policy);
348}
349
350#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
351
352/*
353 * Create a SECTION PGD between VIRT and PHYS in domain
354 * DOMAIN with protection PROT. This operates on half-
355 * pgdir entry increments.
356 */
357static inline void
358alloc_init_section(unsigned long virt, unsigned long phys, int prot)
359{
360 pmd_t *pmdp = pmd_off_k(virt);
361
362 if (virt & (1 << 20))
363 pmdp++;
364
365 *pmdp = __pmd(phys | prot);
366 flush_pmd_entry(pmdp);
367}
368
369/*
370 * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT
371 */
372static inline void
373alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
374{
375 int i;
376
377 for (i = 0; i < 16; i += 1) {
378 alloc_init_section(virt, phys, prot | PMD_SECT_SUPER);
379
380 virt += (PGDIR_SIZE / 2);
381 }
382}
383
384/*
385 * Add a PAGE mapping between VIRT and PHYS in domain
386 * DOMAIN with protection PROT. Note that due to the
387 * way we map the PTEs, we must allocate two PTE_SIZE'd
388 * blocks - one for the Linux pte table, and one for
389 * the hardware pte table.
390 */
391static inline void
392alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
393{
394 pmd_t *pmdp = pmd_off_k(virt);
395 pte_t *ptep;
396
397 if (pmd_none(*pmdp)) {
398 ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
399 sizeof(pte_t));
400
401 __pmd_populate(pmdp, __pa(ptep) | prot_l1);
402 }
403 ptep = pte_offset_kernel(pmdp, virt);
404
Russell Kingad1ae2f2006-12-13 14:34:43 +0000405 set_pte_ext(ptep, pfn_pte(phys >> PAGE_SHIFT, prot), 0);
Russell Kingae8f1542006-09-27 15:38:34 +0100406}
407
408/*
409 * Create the page directory entries and any necessary
410 * page tables for the mapping specified by `md'. We
411 * are able to cope here with varying sizes and address
412 * offsets, and we take full advantage of sections and
413 * supersections.
414 */
415void __init create_mapping(struct map_desc *md)
416{
417 unsigned long virt, length;
418 int prot_sect, prot_l1, domain;
419 pgprot_t prot_pte;
420 unsigned long off = (u32)__pfn_to_phys(md->pfn);
421
422 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
423 printk(KERN_WARNING "BUG: not creating mapping for "
424 "0x%08llx at 0x%08lx in user region\n",
425 __pfn_to_phys((u64)md->pfn), md->virtual);
426 return;
427 }
428
429 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
430 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
431 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
432 "overlaps vmalloc space\n",
433 __pfn_to_phys((u64)md->pfn), md->virtual);
434 }
435
436 domain = mem_types[md->type].domain;
437 prot_pte = __pgprot(mem_types[md->type].prot_pte);
438 prot_l1 = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
439 prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain);
440
441 /*
442 * Catch 36-bit addresses
443 */
444 if(md->pfn >= 0x100000) {
445 if(domain) {
446 printk(KERN_ERR "MM: invalid domain in supersection "
447 "mapping for 0x%08llx at 0x%08lx\n",
448 __pfn_to_phys((u64)md->pfn), md->virtual);
449 return;
450 }
451 if((md->virtual | md->length | __pfn_to_phys(md->pfn))
452 & ~SUPERSECTION_MASK) {
453 printk(KERN_ERR "MM: cannot create mapping for "
454 "0x%08llx at 0x%08lx invalid alignment\n",
455 __pfn_to_phys((u64)md->pfn), md->virtual);
456 return;
457 }
458
459 /*
460 * Shift bits [35:32] of address into bits [23:20] of PMD
461 * (See ARMv6 spec).
462 */
463 off |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
464 }
465
466 virt = md->virtual;
467 off -= virt;
468 length = md->length;
469
470 if (mem_types[md->type].prot_l1 == 0 &&
471 (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
472 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
473 "be mapped using pages, ignoring.\n",
474 __pfn_to_phys(md->pfn), md->virtual);
475 return;
476 }
477
478 while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
479 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
480
481 virt += PAGE_SIZE;
482 length -= PAGE_SIZE;
483 }
484
485 /* N.B. ARMv6 supersections are only defined to work with domain 0.
486 * Since domain assignments can in fact be arbitrary, the
487 * 'domain == 0' check below is required to insure that ARMv6
488 * supersections are only allocated for domain 0 regardless
489 * of the actual domain assignments in use.
490 */
491 if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())
492 && domain == 0) {
493 /*
494 * Align to supersection boundary if !high pages.
495 * High pages have already been checked for proper
496 * alignment above and they will fail the SUPSERSECTION_MASK
497 * check because of the way the address is encoded into
498 * offset.
499 */
500 if (md->pfn <= 0x100000) {
501 while ((virt & ~SUPERSECTION_MASK ||
502 (virt + off) & ~SUPERSECTION_MASK) &&
503 length >= (PGDIR_SIZE / 2)) {
504 alloc_init_section(virt, virt + off, prot_sect);
505
506 virt += (PGDIR_SIZE / 2);
507 length -= (PGDIR_SIZE / 2);
508 }
509 }
510
511 while (length >= SUPERSECTION_SIZE) {
512 alloc_init_supersection(virt, virt + off, prot_sect);
513
514 virt += SUPERSECTION_SIZE;
515 length -= SUPERSECTION_SIZE;
516 }
517 }
518
519 /*
520 * A section mapping covers half a "pgdir" entry.
521 */
522 while (length >= (PGDIR_SIZE / 2)) {
523 alloc_init_section(virt, virt + off, prot_sect);
524
525 virt += (PGDIR_SIZE / 2);
526 length -= (PGDIR_SIZE / 2);
527 }
528
529 while (length >= PAGE_SIZE) {
530 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
531
532 virt += PAGE_SIZE;
533 length -= PAGE_SIZE;
534 }
535}
536
537/*
538 * Create the architecture specific mappings
539 */
540void __init iotable_init(struct map_desc *io_desc, int nr)
541{
542 int i;
543
544 for (i = 0; i < nr; i++)
545 create_mapping(io_desc + i);
546}
547
Russell Kingd111e8f2006-09-27 15:27:33 +0100548static inline void prepare_page_table(struct meminfo *mi)
549{
550 unsigned long addr;
551
552 /*
553 * Clear out all the mappings below the kernel image.
554 */
555 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE)
556 pmd_clear(pmd_off_k(addr));
557
558#ifdef CONFIG_XIP_KERNEL
559 /* The XIP kernel is mapped in the module area -- skip over it */
560 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
561#endif
562 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
563 pmd_clear(pmd_off_k(addr));
564
565 /*
566 * Clear out all the kernel space mappings, except for the first
567 * memory bank, up to the end of the vmalloc region.
568 */
569 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
570 addr < VMALLOC_END; addr += PGDIR_SIZE)
571 pmd_clear(pmd_off_k(addr));
572}
573
574/*
575 * Reserve the various regions of node 0
576 */
577void __init reserve_node_zero(pg_data_t *pgdat)
578{
579 unsigned long res_size = 0;
580
581 /*
582 * Register the kernel text and data with bootmem.
583 * Note that this can only be in node 0.
584 */
585#ifdef CONFIG_XIP_KERNEL
586 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start);
587#else
588 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext);
589#endif
590
591 /*
592 * Reserve the page tables. These are already in use,
593 * and can only be in node 0.
594 */
595 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
596 PTRS_PER_PGD * sizeof(pgd_t));
597
598 /*
599 * Hmm... This should go elsewhere, but we really really need to
600 * stop things allocating the low memory; ideally we need a better
601 * implementation of GFP_DMA which does not assume that DMA-able
602 * memory starts at zero.
603 */
604 if (machine_is_integrator() || machine_is_cintegrator())
605 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
606
607 /*
608 * These should likewise go elsewhere. They pre-reserve the
609 * screen memory region at the start of main system memory.
610 */
611 if (machine_is_edb7211())
612 res_size = 0x00020000;
613 if (machine_is_p720t())
614 res_size = 0x00014000;
615
Ben Dooksbbf6f282006-12-07 20:47:58 +0100616 /* H1940 and RX3715 need to reserve this for suspend */
617
618 if (machine_is_h1940() || machine_is_rx3715()) {
Ben Dooks90733412006-12-06 01:50:24 +0100619 reserve_bootmem_node(pgdat, 0x30003000, 0x1000);
620 reserve_bootmem_node(pgdat, 0x30081000, 0x1000);
621 }
622
Russell Kingd111e8f2006-09-27 15:27:33 +0100623#ifdef CONFIG_SA1111
624 /*
625 * Because of the SA1111 DMA bug, we want to preserve our
626 * precious DMA-able memory...
627 */
628 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
629#endif
630 if (res_size)
631 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size);
632}
633
634/*
635 * Set up device the mappings. Since we clear out the page tables for all
636 * mappings above VMALLOC_END, we will remove any debug device mappings.
637 * This means you have to be careful how you debug this function, or any
638 * called function. This means you can't use any function or debugging
639 * method which may touch any device, otherwise the kernel _will_ crash.
640 */
641static void __init devicemaps_init(struct machine_desc *mdesc)
642{
643 struct map_desc map;
644 unsigned long addr;
645 void *vectors;
646
647 /*
648 * Allocate the vector page early.
649 */
650 vectors = alloc_bootmem_low_pages(PAGE_SIZE);
651 BUG_ON(!vectors);
652
653 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
654 pmd_clear(pmd_off_k(addr));
655
656 /*
657 * Map the kernel if it is XIP.
658 * It is always first in the modulearea.
659 */
660#ifdef CONFIG_XIP_KERNEL
661 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
662 map.virtual = MODULE_START;
663 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
664 map.type = MT_ROM;
665 create_mapping(&map);
666#endif
667
668 /*
669 * Map the cache flushing regions.
670 */
671#ifdef FLUSH_BASE
672 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
673 map.virtual = FLUSH_BASE;
674 map.length = SZ_1M;
675 map.type = MT_CACHECLEAN;
676 create_mapping(&map);
677#endif
678#ifdef FLUSH_BASE_MINICACHE
679 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
680 map.virtual = FLUSH_BASE_MINICACHE;
681 map.length = SZ_1M;
682 map.type = MT_MINICLEAN;
683 create_mapping(&map);
684#endif
685
686 /*
687 * Create a mapping for the machine vectors at the high-vectors
688 * location (0xffff0000). If we aren't using high-vectors, also
689 * create a mapping at the low-vectors virtual address.
690 */
691 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
692 map.virtual = 0xffff0000;
693 map.length = PAGE_SIZE;
694 map.type = MT_HIGH_VECTORS;
695 create_mapping(&map);
696
697 if (!vectors_high()) {
698 map.virtual = 0;
699 map.type = MT_LOW_VECTORS;
700 create_mapping(&map);
701 }
702
703 /*
704 * Ask the machine support to map in the statically mapped devices.
705 */
706 if (mdesc->map_io)
707 mdesc->map_io();
708
709 /*
710 * Finally flush the caches and tlb to ensure that we're in a
711 * consistent state wrt the writebuffer. This also ensures that
712 * any write-allocated cache lines in the vector page are written
713 * back. After this point, we can start to touch devices again.
714 */
715 local_flush_tlb_all();
716 flush_cache_all();
717}
718
719/*
720 * paging_init() sets up the page tables, initialises the zone memory
721 * maps, and sets up the zero page, bad page and bad page tables.
722 */
723void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
724{
725 void *zero_page;
726
727 build_mem_type_table();
728 prepare_page_table(mi);
729 bootmem_init(mi);
730 devicemaps_init(mdesc);
731
732 top_pmd = pmd_off_k(0xffff0000);
733
734 /*
735 * allocate the zero page. Note that we count on this going ok.
736 */
737 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
738 memzero(zero_page, PAGE_SIZE);
739 empty_zero_page = virt_to_page(zero_page);
740 flush_dcache_page(empty_zero_page);
741}
Russell Kingae8f1542006-09-27 15:38:34 +0100742
743/*
744 * In order to soft-boot, we need to insert a 1:1 mapping in place of
745 * the user-mode pages. This will then ensure that we have predictable
746 * results when turning the mmu off
747 */
748void setup_mm_for_reboot(char mode)
749{
750 unsigned long base_pmdval;
751 pgd_t *pgd;
752 int i;
753
754 if (current->mm && current->mm->pgd)
755 pgd = current->mm->pgd;
756 else
757 pgd = init_mm.pgd;
758
759 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
760 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
761 base_pmdval |= PMD_BIT4;
762
763 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
764 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
765 pmd_t *pmd;
766
767 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
768 pmd[0] = __pmd(pmdval);
769 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
770 flush_pmd_entry(pmd);
771 }
772}