blob: db7f88a1bdee46eef8ee38d4cd4b4a72cd851323 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
Russell King68b65f72010-12-22 17:24:39 +00008 * Copyright (C) 2010 ST-Ericsson SA
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070024 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
32#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33#define SUPPORT_SYSRQ
34#endif
35
36#include <linux/module.h>
37#include <linux/ioport.h>
38#include <linux/init.h>
39#include <linux/console.h>
40#include <linux/sysrq.h>
41#include <linux/device.h>
42#include <linux/tty.h>
43#include <linux/tty_flip.h>
44#include <linux/serial_core.h>
45#include <linux/serial.h>
Russell Kinga62c80e2006-01-07 13:52:45 +000046#include <linux/amba/bus.h>
47#include <linux/amba/serial.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000048#include <linux/clk.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090049#include <linux/slab.h>
Russell King68b65f72010-12-22 17:24:39 +000050#include <linux/dmaengine.h>
51#include <linux/dma-mapping.h>
52#include <linux/scatterlist.h>
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +020053#include <linux/delay.h>
Viresh Kumar258aea72012-02-01 16:12:19 +053054#include <linux/types.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
56#include <asm/io.h>
Russell Kingc6b8fda2005-10-28 14:05:16 +010057#include <asm/sizes.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
59#define UART_NR 14
60
61#define SERIAL_AMBA_MAJOR 204
62#define SERIAL_AMBA_MINOR 64
63#define SERIAL_AMBA_NR UART_NR
64
65#define AMBA_ISR_PASS_LIMIT 256
66
Russell Kingb63d4f02005-11-19 11:10:35 +000067#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
68#define UART_DUMMY_DR_RX (1 << 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +020070
71#define UART_WA_SAVE_NR 14
72
73static void pl011_lockup_wa(unsigned long data);
74static const u32 uart_wa_reg[UART_WA_SAVE_NR] = {
75 ST_UART011_DMAWM,
76 ST_UART011_TIMEOUT,
77 ST_UART011_LCRH_RX,
78 UART011_IBRD,
79 UART011_FBRD,
80 ST_UART011_LCRH_TX,
81 UART011_IFLS,
82 ST_UART011_XFCR,
83 ST_UART011_XON1,
84 ST_UART011_XON2,
85 ST_UART011_XOFF1,
86 ST_UART011_XOFF2,
87 UART011_CR,
88 UART011_IMSC
89};
90
91static u32 uart_wa_regdata[UART_WA_SAVE_NR];
92static DECLARE_TASKLET(pl011_lockup_tlet, pl011_lockup_wa, 0);
93
Alessandro Rubini5926a292009-06-04 17:43:04 +010094/* There is by now at least one vendor with differing details, so handle it */
95struct vendor_data {
96 unsigned int ifls;
97 unsigned int fifosize;
Linus Walleijec489aa2010-06-02 08:13:52 +010098 unsigned int lcrh_tx;
99 unsigned int lcrh_rx;
Linus Walleijac3e3fb2010-06-02 20:40:22 +0100100 bool oversampling;
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +0200101 bool interrupt_may_hang; /* vendor-specific */
Russell King38d62432010-12-22 17:59:16 +0000102 bool dma_threshold;
Alessandro Rubini5926a292009-06-04 17:43:04 +0100103};
104
105static struct vendor_data vendor_arm = {
106 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
107 .fifosize = 16,
Linus Walleijec489aa2010-06-02 08:13:52 +0100108 .lcrh_tx = UART011_LCRH,
109 .lcrh_rx = UART011_LCRH,
Linus Walleijac3e3fb2010-06-02 20:40:22 +0100110 .oversampling = false,
Russell King38d62432010-12-22 17:59:16 +0000111 .dma_threshold = false,
Alessandro Rubini5926a292009-06-04 17:43:04 +0100112};
113
114static struct vendor_data vendor_st = {
115 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
116 .fifosize = 64,
Linus Walleijec489aa2010-06-02 08:13:52 +0100117 .lcrh_tx = ST_UART011_LCRH_TX,
118 .lcrh_rx = ST_UART011_LCRH_RX,
Linus Walleijac3e3fb2010-06-02 20:40:22 +0100119 .oversampling = true,
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +0200120 .interrupt_may_hang = true,
Russell King38d62432010-12-22 17:59:16 +0000121 .dma_threshold = true,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122};
123
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +0200124static struct uart_amba_port *amba_ports[UART_NR];
125
Russell King68b65f72010-12-22 17:24:39 +0000126/* Deals with DMA transactions */
Linus Walleijead76f32011-02-24 13:21:08 +0100127
128struct pl011_sgbuf {
129 struct scatterlist sg;
130 char *buf;
131};
132
133struct pl011_dmarx_data {
134 struct dma_chan *chan;
135 struct completion complete;
136 bool use_buf_b;
137 struct pl011_sgbuf sgbuf_a;
138 struct pl011_sgbuf sgbuf_b;
139 dma_cookie_t cookie;
140 bool running;
141};
142
Russell King68b65f72010-12-22 17:24:39 +0000143struct pl011_dmatx_data {
144 struct dma_chan *chan;
145 struct scatterlist sg;
146 char *buf;
147 bool queued;
148};
149
Russell Kingc19f12b2010-12-22 17:48:26 +0000150/*
151 * We wrap our port structure around the generic uart_port.
152 */
153struct uart_amba_port {
154 struct uart_port port;
155 struct clk *clk;
156 const struct vendor_data *vendor;
Russell King68b65f72010-12-22 17:24:39 +0000157 unsigned int dmacr; /* dma control reg */
Russell Kingc19f12b2010-12-22 17:48:26 +0000158 unsigned int im; /* interrupt mask */
159 unsigned int old_status;
Russell Kingffca2b12010-12-22 17:13:05 +0000160 unsigned int fifosize; /* vendor-specific */
Russell Kingc19f12b2010-12-22 17:48:26 +0000161 unsigned int lcrh_tx; /* vendor-specific */
162 unsigned int lcrh_rx; /* vendor-specific */
163 bool autorts;
164 char type[12];
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +0200165 bool interrupt_may_hang; /* vendor-specific */
Russell King68b65f72010-12-22 17:24:39 +0000166#ifdef CONFIG_DMA_ENGINE
167 /* DMA stuff */
Linus Walleijead76f32011-02-24 13:21:08 +0100168 bool using_tx_dma;
169 bool using_rx_dma;
170 struct pl011_dmarx_data dmarx;
Russell King68b65f72010-12-22 17:24:39 +0000171 struct pl011_dmatx_data dmatx;
172#endif
Russell Kingc19f12b2010-12-22 17:48:26 +0000173};
174
Russell King68b65f72010-12-22 17:24:39 +0000175/*
Linus Walleij29772c42011-02-24 13:21:36 +0100176 * Reads up to 256 characters from the FIFO or until it's empty and
177 * inserts them into the TTY layer. Returns the number of characters
178 * read from the FIFO.
179 */
180static int pl011_fifo_to_tty(struct uart_amba_port *uap)
181{
182 u16 status, ch;
183 unsigned int flag, max_count = 256;
184 int fifotaken = 0;
185
186 while (max_count--) {
187 status = readw(uap->port.membase + UART01x_FR);
188 if (status & UART01x_FR_RXFE)
189 break;
190
191 /* Take chars from the FIFO and update status */
192 ch = readw(uap->port.membase + UART01x_DR) |
193 UART_DUMMY_DR_RX;
194 flag = TTY_NORMAL;
195 uap->port.icount.rx++;
196 fifotaken++;
197
198 if (unlikely(ch & UART_DR_ERROR)) {
199 if (ch & UART011_DR_BE) {
200 ch &= ~(UART011_DR_FE | UART011_DR_PE);
201 uap->port.icount.brk++;
202 if (uart_handle_break(&uap->port))
203 continue;
204 } else if (ch & UART011_DR_PE)
205 uap->port.icount.parity++;
206 else if (ch & UART011_DR_FE)
207 uap->port.icount.frame++;
208 if (ch & UART011_DR_OE)
209 uap->port.icount.overrun++;
210
211 ch &= uap->port.read_status_mask;
212
213 if (ch & UART011_DR_BE)
214 flag = TTY_BREAK;
215 else if (ch & UART011_DR_PE)
216 flag = TTY_PARITY;
217 else if (ch & UART011_DR_FE)
218 flag = TTY_FRAME;
219 }
220
221 if (uart_handle_sysrq_char(&uap->port, ch & 255))
222 continue;
223
224 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
225 }
226
227 return fifotaken;
228}
229
230
231/*
Russell King68b65f72010-12-22 17:24:39 +0000232 * All the DMA operation mode stuff goes inside this ifdef.
233 * This assumes that you have a generic DMA device interface,
234 * no custom DMA interfaces are supported.
235 */
236#ifdef CONFIG_DMA_ENGINE
237
238#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
239
Linus Walleijead76f32011-02-24 13:21:08 +0100240static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
241 enum dma_data_direction dir)
242{
243 sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
244 if (!sg->buf)
245 return -ENOMEM;
246
247 sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE);
248
249 if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) {
250 kfree(sg->buf);
251 return -EINVAL;
252 }
253 return 0;
254}
255
256static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
257 enum dma_data_direction dir)
258{
259 if (sg->buf) {
260 dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir);
261 kfree(sg->buf);
262 }
263}
264
Russell King68b65f72010-12-22 17:24:39 +0000265static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
266{
267 /* DMA is the sole user of the platform data right now */
268 struct amba_pl011_data *plat = uap->port.dev->platform_data;
269 struct dma_slave_config tx_conf = {
270 .dst_addr = uap->port.mapbase + UART01x_DR,
271 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
Vinod Koula485df42011-10-14 10:47:38 +0530272 .direction = DMA_MEM_TO_DEV,
Russell King68b65f72010-12-22 17:24:39 +0000273 .dst_maxburst = uap->fifosize >> 1,
Viresh Kumar258aea72012-02-01 16:12:19 +0530274 .device_fc = false,
Russell King68b65f72010-12-22 17:24:39 +0000275 };
276 struct dma_chan *chan;
277 dma_cap_mask_t mask;
278
279 /* We need platform data */
280 if (!plat || !plat->dma_filter) {
281 dev_info(uap->port.dev, "no DMA platform data\n");
282 return;
283 }
284
Linus Walleijead76f32011-02-24 13:21:08 +0100285 /* Try to acquire a generic DMA engine slave TX channel */
Russell King68b65f72010-12-22 17:24:39 +0000286 dma_cap_zero(mask);
287 dma_cap_set(DMA_SLAVE, mask);
288
289 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
290 if (!chan) {
291 dev_err(uap->port.dev, "no TX DMA channel!\n");
292 return;
293 }
294
295 dmaengine_slave_config(chan, &tx_conf);
296 uap->dmatx.chan = chan;
297
298 dev_info(uap->port.dev, "DMA channel TX %s\n",
299 dma_chan_name(uap->dmatx.chan));
Linus Walleijead76f32011-02-24 13:21:08 +0100300
301 /* Optionally make use of an RX channel as well */
302 if (plat->dma_rx_param) {
303 struct dma_slave_config rx_conf = {
304 .src_addr = uap->port.mapbase + UART01x_DR,
305 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
Vinod Koula485df42011-10-14 10:47:38 +0530306 .direction = DMA_DEV_TO_MEM,
Linus Walleijead76f32011-02-24 13:21:08 +0100307 .src_maxburst = uap->fifosize >> 1,
Viresh Kumar258aea72012-02-01 16:12:19 +0530308 .device_fc = false,
Linus Walleijead76f32011-02-24 13:21:08 +0100309 };
310
311 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
312 if (!chan) {
313 dev_err(uap->port.dev, "no RX DMA channel!\n");
314 return;
315 }
316
317 dmaengine_slave_config(chan, &rx_conf);
318 uap->dmarx.chan = chan;
319
320 dev_info(uap->port.dev, "DMA channel RX %s\n",
321 dma_chan_name(uap->dmarx.chan));
322 }
Russell King68b65f72010-12-22 17:24:39 +0000323}
324
325#ifndef MODULE
326/*
327 * Stack up the UARTs and let the above initcall be done at device
328 * initcall time, because the serial driver is called as an arch
329 * initcall, and at this time the DMA subsystem is not yet registered.
330 * At this point the driver will switch over to using DMA where desired.
331 */
332struct dma_uap {
333 struct list_head node;
334 struct uart_amba_port *uap;
335};
336
337static LIST_HEAD(pl011_dma_uarts);
338
339static int __init pl011_dma_initcall(void)
340{
341 struct list_head *node, *tmp;
342
343 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
344 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
345 pl011_dma_probe_initcall(dmau->uap);
346 list_del(node);
347 kfree(dmau);
348 }
349 return 0;
350}
351
352device_initcall(pl011_dma_initcall);
353
354static void pl011_dma_probe(struct uart_amba_port *uap)
355{
356 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
357 if (dmau) {
358 dmau->uap = uap;
359 list_add_tail(&dmau->node, &pl011_dma_uarts);
360 }
361}
362#else
363static void pl011_dma_probe(struct uart_amba_port *uap)
364{
365 pl011_dma_probe_initcall(uap);
366}
367#endif
368
369static void pl011_dma_remove(struct uart_amba_port *uap)
370{
371 /* TODO: remove the initcall if it has not yet executed */
372 if (uap->dmatx.chan)
373 dma_release_channel(uap->dmatx.chan);
Linus Walleijead76f32011-02-24 13:21:08 +0100374 if (uap->dmarx.chan)
375 dma_release_channel(uap->dmarx.chan);
Russell King68b65f72010-12-22 17:24:39 +0000376}
377
Russell King68b65f72010-12-22 17:24:39 +0000378/* Forward declare this for the refill routine */
379static int pl011_dma_tx_refill(struct uart_amba_port *uap);
380
381/*
382 * The current DMA TX buffer has been sent.
383 * Try to queue up another DMA buffer.
384 */
385static void pl011_dma_tx_callback(void *data)
386{
387 struct uart_amba_port *uap = data;
388 struct pl011_dmatx_data *dmatx = &uap->dmatx;
389 unsigned long flags;
390 u16 dmacr;
391
392 spin_lock_irqsave(&uap->port.lock, flags);
393 if (uap->dmatx.queued)
394 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
395 DMA_TO_DEVICE);
396
397 dmacr = uap->dmacr;
398 uap->dmacr = dmacr & ~UART011_TXDMAE;
399 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
400
401 /*
402 * If TX DMA was disabled, it means that we've stopped the DMA for
403 * some reason (eg, XOFF received, or we want to send an X-char.)
404 *
405 * Note: we need to be careful here of a potential race between DMA
406 * and the rest of the driver - if the driver disables TX DMA while
407 * a TX buffer completing, we must update the tx queued status to
408 * get further refills (hence we check dmacr).
409 */
410 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
411 uart_circ_empty(&uap->port.state->xmit)) {
412 uap->dmatx.queued = false;
413 spin_unlock_irqrestore(&uap->port.lock, flags);
414 return;
415 }
416
417 if (pl011_dma_tx_refill(uap) <= 0) {
418 /*
419 * We didn't queue a DMA buffer for some reason, but we
420 * have data pending to be sent. Re-enable the TX IRQ.
421 */
422 uap->im |= UART011_TXIM;
423 writew(uap->im, uap->port.membase + UART011_IMSC);
424 }
425 spin_unlock_irqrestore(&uap->port.lock, flags);
426}
427
428/*
429 * Try to refill the TX DMA buffer.
430 * Locking: called with port lock held and IRQs disabled.
431 * Returns:
432 * 1 if we queued up a TX DMA buffer.
433 * 0 if we didn't want to handle this by DMA
434 * <0 on error
435 */
436static int pl011_dma_tx_refill(struct uart_amba_port *uap)
437{
438 struct pl011_dmatx_data *dmatx = &uap->dmatx;
439 struct dma_chan *chan = dmatx->chan;
440 struct dma_device *dma_dev = chan->device;
441 struct dma_async_tx_descriptor *desc;
442 struct circ_buf *xmit = &uap->port.state->xmit;
443 unsigned int count;
444
445 /*
446 * Try to avoid the overhead involved in using DMA if the
447 * transaction fits in the first half of the FIFO, by using
448 * the standard interrupt handling. This ensures that we
449 * issue a uart_write_wakeup() at the appropriate time.
450 */
451 count = uart_circ_chars_pending(xmit);
452 if (count < (uap->fifosize >> 1)) {
453 uap->dmatx.queued = false;
454 return 0;
455 }
456
457 /*
458 * Bodge: don't send the last character by DMA, as this
459 * will prevent XON from notifying us to restart DMA.
460 */
461 count -= 1;
462
463 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
464 if (count > PL011_DMA_BUFFER_SIZE)
465 count = PL011_DMA_BUFFER_SIZE;
466
467 if (xmit->tail < xmit->head)
468 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
469 else {
470 size_t first = UART_XMIT_SIZE - xmit->tail;
471 size_t second = xmit->head;
472
473 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
474 if (second)
475 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
476 }
477
478 dmatx->sg.length = count;
479
480 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
481 uap->dmatx.queued = false;
482 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
483 return -EBUSY;
484 }
485
Vinod Koula485df42011-10-14 10:47:38 +0530486 desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
Russell King68b65f72010-12-22 17:24:39 +0000487 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
488 if (!desc) {
489 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
490 uap->dmatx.queued = false;
491 /*
492 * If DMA cannot be used right now, we complete this
493 * transaction via IRQ and let the TTY layer retry.
494 */
495 dev_dbg(uap->port.dev, "TX DMA busy\n");
496 return -EBUSY;
497 }
498
499 /* Some data to go along to the callback */
500 desc->callback = pl011_dma_tx_callback;
501 desc->callback_param = uap;
502
503 /* All errors should happen at prepare time */
504 dmaengine_submit(desc);
505
506 /* Fire the DMA transaction */
507 dma_dev->device_issue_pending(chan);
508
509 uap->dmacr |= UART011_TXDMAE;
510 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
511 uap->dmatx.queued = true;
512
513 /*
514 * Now we know that DMA will fire, so advance the ring buffer
515 * with the stuff we just dispatched.
516 */
517 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
518 uap->port.icount.tx += count;
519
520 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
521 uart_write_wakeup(&uap->port);
522
523 return 1;
524}
525
526/*
527 * We received a transmit interrupt without a pending X-char but with
528 * pending characters.
529 * Locking: called with port lock held and IRQs disabled.
530 * Returns:
531 * false if we want to use PIO to transmit
532 * true if we queued a DMA buffer
533 */
534static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
535{
Linus Walleijead76f32011-02-24 13:21:08 +0100536 if (!uap->using_tx_dma)
Russell King68b65f72010-12-22 17:24:39 +0000537 return false;
538
539 /*
540 * If we already have a TX buffer queued, but received a
541 * TX interrupt, it will be because we've just sent an X-char.
542 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
543 */
544 if (uap->dmatx.queued) {
545 uap->dmacr |= UART011_TXDMAE;
546 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
547 uap->im &= ~UART011_TXIM;
548 writew(uap->im, uap->port.membase + UART011_IMSC);
549 return true;
550 }
551
552 /*
553 * We don't have a TX buffer queued, so try to queue one.
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300554 * If we successfully queued a buffer, mask the TX IRQ.
Russell King68b65f72010-12-22 17:24:39 +0000555 */
556 if (pl011_dma_tx_refill(uap) > 0) {
557 uap->im &= ~UART011_TXIM;
558 writew(uap->im, uap->port.membase + UART011_IMSC);
559 return true;
560 }
561 return false;
562}
563
564/*
565 * Stop the DMA transmit (eg, due to received XOFF).
566 * Locking: called with port lock held and IRQs disabled.
567 */
568static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
569{
570 if (uap->dmatx.queued) {
571 uap->dmacr &= ~UART011_TXDMAE;
572 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
573 }
574}
575
576/*
577 * Try to start a DMA transmit, or in the case of an XON/OFF
578 * character queued for send, try to get that character out ASAP.
579 * Locking: called with port lock held and IRQs disabled.
580 * Returns:
581 * false if we want the TX IRQ to be enabled
582 * true if we have a buffer queued
583 */
584static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
585{
586 u16 dmacr;
587
Linus Walleijead76f32011-02-24 13:21:08 +0100588 if (!uap->using_tx_dma)
Russell King68b65f72010-12-22 17:24:39 +0000589 return false;
590
591 if (!uap->port.x_char) {
592 /* no X-char, try to push chars out in DMA mode */
593 bool ret = true;
594
595 if (!uap->dmatx.queued) {
596 if (pl011_dma_tx_refill(uap) > 0) {
597 uap->im &= ~UART011_TXIM;
598 ret = true;
599 } else {
600 uap->im |= UART011_TXIM;
601 ret = false;
602 }
603 writew(uap->im, uap->port.membase + UART011_IMSC);
604 } else if (!(uap->dmacr & UART011_TXDMAE)) {
605 uap->dmacr |= UART011_TXDMAE;
606 writew(uap->dmacr,
607 uap->port.membase + UART011_DMACR);
608 }
609 return ret;
610 }
611
612 /*
613 * We have an X-char to send. Disable DMA to prevent it loading
614 * the TX fifo, and then see if we can stuff it into the FIFO.
615 */
616 dmacr = uap->dmacr;
617 uap->dmacr &= ~UART011_TXDMAE;
618 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
619
620 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
621 /*
622 * No space in the FIFO, so enable the transmit interrupt
623 * so we know when there is space. Note that once we've
624 * loaded the character, we should just re-enable DMA.
625 */
626 return false;
627 }
628
629 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
630 uap->port.icount.tx++;
631 uap->port.x_char = 0;
632
633 /* Success - restore the DMA state */
634 uap->dmacr = dmacr;
635 writew(dmacr, uap->port.membase + UART011_DMACR);
636
637 return true;
638}
639
640/*
641 * Flush the transmit buffer.
642 * Locking: called with port lock held and IRQs disabled.
643 */
644static void pl011_dma_flush_buffer(struct uart_port *port)
645{
646 struct uart_amba_port *uap = (struct uart_amba_port *)port;
647
Linus Walleijead76f32011-02-24 13:21:08 +0100648 if (!uap->using_tx_dma)
Russell King68b65f72010-12-22 17:24:39 +0000649 return;
650
651 /* Avoid deadlock with the DMA engine callback */
652 spin_unlock(&uap->port.lock);
653 dmaengine_terminate_all(uap->dmatx.chan);
654 spin_lock(&uap->port.lock);
655 if (uap->dmatx.queued) {
656 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
657 DMA_TO_DEVICE);
658 uap->dmatx.queued = false;
659 uap->dmacr &= ~UART011_TXDMAE;
660 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
661 }
662}
663
Linus Walleijead76f32011-02-24 13:21:08 +0100664static void pl011_dma_rx_callback(void *data);
665
666static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
667{
668 struct dma_chan *rxchan = uap->dmarx.chan;
669 struct dma_device *dma_dev;
670 struct pl011_dmarx_data *dmarx = &uap->dmarx;
671 struct dma_async_tx_descriptor *desc;
672 struct pl011_sgbuf *sgbuf;
673
674 if (!rxchan)
675 return -EIO;
676
677 /* Start the RX DMA job */
678 sgbuf = uap->dmarx.use_buf_b ?
679 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
680 dma_dev = rxchan->device;
681 desc = rxchan->device->device_prep_slave_sg(rxchan, &sgbuf->sg, 1,
Vinod Koula485df42011-10-14 10:47:38 +0530682 DMA_DEV_TO_MEM,
Linus Walleijead76f32011-02-24 13:21:08 +0100683 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
684 /*
685 * If the DMA engine is busy and cannot prepare a
686 * channel, no big deal, the driver will fall back
687 * to interrupt mode as a result of this error code.
688 */
689 if (!desc) {
690 uap->dmarx.running = false;
691 dmaengine_terminate_all(rxchan);
692 return -EBUSY;
693 }
694
695 /* Some data to go along to the callback */
696 desc->callback = pl011_dma_rx_callback;
697 desc->callback_param = uap;
698 dmarx->cookie = dmaengine_submit(desc);
699 dma_async_issue_pending(rxchan);
700
701 uap->dmacr |= UART011_RXDMAE;
702 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
703 uap->dmarx.running = true;
704
705 uap->im &= ~UART011_RXIM;
706 writew(uap->im, uap->port.membase + UART011_IMSC);
707
708 return 0;
709}
710
711/*
712 * This is called when either the DMA job is complete, or
713 * the FIFO timeout interrupt occurred. This must be called
714 * with the port spinlock uap->port.lock held.
715 */
716static void pl011_dma_rx_chars(struct uart_amba_port *uap,
717 u32 pending, bool use_buf_b,
718 bool readfifo)
719{
720 struct tty_struct *tty = uap->port.state->port.tty;
721 struct pl011_sgbuf *sgbuf = use_buf_b ?
722 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
723 struct device *dev = uap->dmarx.chan->device->dev;
Linus Walleijead76f32011-02-24 13:21:08 +0100724 int dma_count = 0;
725 u32 fifotaken = 0; /* only used for vdbg() */
726
727 /* Pick everything from the DMA first */
728 if (pending) {
729 /* Sync in buffer */
730 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
731
732 /*
733 * First take all chars in the DMA pipe, then look in the FIFO.
734 * Note that tty_insert_flip_buf() tries to take as many chars
735 * as it can.
736 */
737 dma_count = tty_insert_flip_string(uap->port.state->port.tty,
738 sgbuf->buf, pending);
739
740 /* Return buffer to device */
741 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
742
743 uap->port.icount.rx += dma_count;
744 if (dma_count < pending)
745 dev_warn(uap->port.dev,
746 "couldn't insert all characters (TTY is full?)\n");
747 }
748
749 /*
750 * Only continue with trying to read the FIFO if all DMA chars have
751 * been taken first.
752 */
753 if (dma_count == pending && readfifo) {
754 /* Clear any error flags */
755 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
756 uap->port.membase + UART011_ICR);
757
758 /*
759 * If we read all the DMA'd characters, and we had an
Linus Walleij29772c42011-02-24 13:21:36 +0100760 * incomplete buffer, that could be due to an rx error, or
761 * maybe we just timed out. Read any pending chars and check
762 * the error status.
763 *
764 * Error conditions will only occur in the FIFO, these will
765 * trigger an immediate interrupt and stop the DMA job, so we
766 * will always find the error in the FIFO, never in the DMA
767 * buffer.
Linus Walleijead76f32011-02-24 13:21:08 +0100768 */
Linus Walleij29772c42011-02-24 13:21:36 +0100769 fifotaken = pl011_fifo_to_tty(uap);
Linus Walleijead76f32011-02-24 13:21:08 +0100770 }
771
772 spin_unlock(&uap->port.lock);
773 dev_vdbg(uap->port.dev,
774 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
775 dma_count, fifotaken);
776 tty_flip_buffer_push(tty);
777 spin_lock(&uap->port.lock);
778}
779
780static void pl011_dma_rx_irq(struct uart_amba_port *uap)
781{
782 struct pl011_dmarx_data *dmarx = &uap->dmarx;
783 struct dma_chan *rxchan = dmarx->chan;
784 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
785 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
786 size_t pending;
787 struct dma_tx_state state;
788 enum dma_status dmastat;
789
790 /*
791 * Pause the transfer so we can trust the current counter,
792 * do this before we pause the PL011 block, else we may
793 * overflow the FIFO.
794 */
795 if (dmaengine_pause(rxchan))
796 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
797 dmastat = rxchan->device->device_tx_status(rxchan,
798 dmarx->cookie, &state);
799 if (dmastat != DMA_PAUSED)
800 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
801
802 /* Disable RX DMA - incoming data will wait in the FIFO */
803 uap->dmacr &= ~UART011_RXDMAE;
804 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
805 uap->dmarx.running = false;
806
807 pending = sgbuf->sg.length - state.residue;
808 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
809 /* Then we terminate the transfer - we now know our residue */
810 dmaengine_terminate_all(rxchan);
811
812 /*
813 * This will take the chars we have so far and insert
814 * into the framework.
815 */
816 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
817
818 /* Switch buffer & re-trigger DMA job */
819 dmarx->use_buf_b = !dmarx->use_buf_b;
820 if (pl011_dma_rx_trigger_dma(uap)) {
821 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
822 "fall back to interrupt mode\n");
823 uap->im |= UART011_RXIM;
824 writew(uap->im, uap->port.membase + UART011_IMSC);
825 }
826}
827
828static void pl011_dma_rx_callback(void *data)
829{
830 struct uart_amba_port *uap = data;
831 struct pl011_dmarx_data *dmarx = &uap->dmarx;
832 bool lastbuf = dmarx->use_buf_b;
833 int ret;
834
835 /*
836 * This completion interrupt occurs typically when the
837 * RX buffer is totally stuffed but no timeout has yet
838 * occurred. When that happens, we just want the RX
839 * routine to flush out the secondary DMA buffer while
840 * we immediately trigger the next DMA job.
841 */
842 spin_lock_irq(&uap->port.lock);
843 uap->dmarx.running = false;
844 dmarx->use_buf_b = !lastbuf;
845 ret = pl011_dma_rx_trigger_dma(uap);
846
847 pl011_dma_rx_chars(uap, PL011_DMA_BUFFER_SIZE, lastbuf, false);
848 spin_unlock_irq(&uap->port.lock);
849 /*
850 * Do this check after we picked the DMA chars so we don't
851 * get some IRQ immediately from RX.
852 */
853 if (ret) {
854 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
855 "fall back to interrupt mode\n");
856 uap->im |= UART011_RXIM;
857 writew(uap->im, uap->port.membase + UART011_IMSC);
858 }
859}
860
861/*
862 * Stop accepting received characters, when we're shutting down or
863 * suspending this port.
864 * Locking: called with port lock held and IRQs disabled.
865 */
866static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
867{
868 /* FIXME. Just disable the DMA enable */
869 uap->dmacr &= ~UART011_RXDMAE;
870 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
871}
Russell King68b65f72010-12-22 17:24:39 +0000872
873static void pl011_dma_startup(struct uart_amba_port *uap)
874{
Linus Walleijead76f32011-02-24 13:21:08 +0100875 int ret;
876
Russell King68b65f72010-12-22 17:24:39 +0000877 if (!uap->dmatx.chan)
878 return;
879
880 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
881 if (!uap->dmatx.buf) {
882 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
883 uap->port.fifosize = uap->fifosize;
884 return;
885 }
886
887 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
888
889 /* The DMA buffer is now the FIFO the TTY subsystem can use */
890 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
Linus Walleijead76f32011-02-24 13:21:08 +0100891 uap->using_tx_dma = true;
Russell King68b65f72010-12-22 17:24:39 +0000892
Linus Walleijead76f32011-02-24 13:21:08 +0100893 if (!uap->dmarx.chan)
894 goto skip_rx;
895
896 /* Allocate and map DMA RX buffers */
897 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
898 DMA_FROM_DEVICE);
899 if (ret) {
900 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
901 "RX buffer A", ret);
902 goto skip_rx;
903 }
904
905 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
906 DMA_FROM_DEVICE);
907 if (ret) {
908 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
909 "RX buffer B", ret);
910 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
911 DMA_FROM_DEVICE);
912 goto skip_rx;
913 }
914
915 uap->using_rx_dma = true;
916
917skip_rx:
Russell King68b65f72010-12-22 17:24:39 +0000918 /* Turn on DMA error (RX/TX will be enabled on demand) */
919 uap->dmacr |= UART011_DMAONERR;
920 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
Russell King38d62432010-12-22 17:59:16 +0000921
922 /*
923 * ST Micro variants has some specific dma burst threshold
924 * compensation. Set this to 16 bytes, so burst will only
925 * be issued above/below 16 bytes.
926 */
927 if (uap->vendor->dma_threshold)
928 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
929 uap->port.membase + ST_UART011_DMAWM);
Linus Walleijead76f32011-02-24 13:21:08 +0100930
931 if (uap->using_rx_dma) {
932 if (pl011_dma_rx_trigger_dma(uap))
933 dev_dbg(uap->port.dev, "could not trigger initial "
934 "RX DMA job, fall back to interrupt mode\n");
935 }
Russell King68b65f72010-12-22 17:24:39 +0000936}
937
938static void pl011_dma_shutdown(struct uart_amba_port *uap)
939{
Linus Walleijead76f32011-02-24 13:21:08 +0100940 if (!(uap->using_tx_dma || uap->using_rx_dma))
Russell King68b65f72010-12-22 17:24:39 +0000941 return;
942
943 /* Disable RX and TX DMA */
944 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
945 barrier();
946
947 spin_lock_irq(&uap->port.lock);
948 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
949 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
950 spin_unlock_irq(&uap->port.lock);
951
Linus Walleijead76f32011-02-24 13:21:08 +0100952 if (uap->using_tx_dma) {
953 /* In theory, this should already be done by pl011_dma_flush_buffer */
954 dmaengine_terminate_all(uap->dmatx.chan);
955 if (uap->dmatx.queued) {
956 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
957 DMA_TO_DEVICE);
958 uap->dmatx.queued = false;
959 }
960
961 kfree(uap->dmatx.buf);
962 uap->using_tx_dma = false;
Russell King68b65f72010-12-22 17:24:39 +0000963 }
964
Linus Walleijead76f32011-02-24 13:21:08 +0100965 if (uap->using_rx_dma) {
966 dmaengine_terminate_all(uap->dmarx.chan);
967 /* Clean up the RX DMA */
968 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
969 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
970 uap->using_rx_dma = false;
971 }
Russell King68b65f72010-12-22 17:24:39 +0000972}
973
Linus Walleijead76f32011-02-24 13:21:08 +0100974static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
975{
976 return uap->using_rx_dma;
977}
978
979static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
980{
981 return uap->using_rx_dma && uap->dmarx.running;
982}
983
984
Russell King68b65f72010-12-22 17:24:39 +0000985#else
986/* Blank functions if the DMA engine is not available */
987static inline void pl011_dma_probe(struct uart_amba_port *uap)
988{
989}
990
991static inline void pl011_dma_remove(struct uart_amba_port *uap)
992{
993}
994
995static inline void pl011_dma_startup(struct uart_amba_port *uap)
996{
997}
998
999static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1000{
1001}
1002
1003static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1004{
1005 return false;
1006}
1007
1008static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1009{
1010}
1011
1012static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1013{
1014 return false;
1015}
1016
Linus Walleijead76f32011-02-24 13:21:08 +01001017static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1018{
1019}
1020
1021static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1022{
1023}
1024
1025static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1026{
1027 return -EIO;
1028}
1029
1030static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1031{
1032 return false;
1033}
1034
1035static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1036{
1037 return false;
1038}
1039
Russell King68b65f72010-12-22 17:24:39 +00001040#define pl011_dma_flush_buffer NULL
1041#endif
1042
1043
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +02001044/*
1045 * pl011_lockup_wa
1046 * This workaround aims to break the deadlock situation
1047 * when after long transfer over uart in hardware flow
1048 * control, uart interrupt registers cannot be cleared.
1049 * Hence uart transfer gets blocked.
1050 *
1051 * It is seen that during such deadlock condition ICR
1052 * don't get cleared even on multiple write. This leads
1053 * pass_counter to decrease and finally reach zero. This
1054 * can be taken as trigger point to run this UART_BT_WA.
1055 *
1056 */
1057static void pl011_lockup_wa(unsigned long data)
1058{
1059 struct uart_amba_port *uap = amba_ports[0];
1060 void __iomem *base = uap->port.membase;
1061 struct circ_buf *xmit = &uap->port.state->xmit;
1062 struct tty_struct *tty = uap->port.state->port.tty;
1063 int buf_empty_retries = 200;
1064 int loop;
1065
1066 /* Stop HCI layer from submitting data for tx */
1067 tty->hw_stopped = 1;
1068 while (!uart_circ_empty(xmit)) {
1069 if (buf_empty_retries-- == 0)
1070 break;
1071 udelay(100);
1072 }
1073
1074 /* Backup registers */
1075 for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
1076 uart_wa_regdata[loop] = readl(base + uart_wa_reg[loop]);
1077
1078 /* Disable UART so that FIFO data is flushed out */
1079 writew(0x00, uap->port.membase + UART011_CR);
1080
1081 /* Soft reset UART module */
1082 if (uap->port.dev->platform_data) {
1083 struct amba_pl011_data *plat;
1084
1085 plat = uap->port.dev->platform_data;
1086 if (plat->reset)
1087 plat->reset();
1088 }
1089
1090 /* Restore registers */
1091 for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
1092 writew(uart_wa_regdata[loop] ,
1093 uap->port.membase + uart_wa_reg[loop]);
1094
1095 /* Initialise the old status of the modem signals */
1096 uap->old_status = readw(uap->port.membase + UART01x_FR) &
1097 UART01x_FR_MODEM_ANY;
1098
1099 if (readl(base + UART011_MIS) & 0x2)
1100 printk(KERN_EMERG "UART_BT_WA: ***FAILED***\n");
1101
1102 /* Start Tx/Rx */
1103 tty->hw_stopped = 0;
1104}
1105
Russell Kingb129a8c2005-08-31 10:12:14 +01001106static void pl011_stop_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107{
1108 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1109
1110 uap->im &= ~UART011_TXIM;
1111 writew(uap->im, uap->port.membase + UART011_IMSC);
Russell King68b65f72010-12-22 17:24:39 +00001112 pl011_dma_tx_stop(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113}
1114
Russell Kingb129a8c2005-08-31 10:12:14 +01001115static void pl011_start_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116{
1117 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1118
Russell King68b65f72010-12-22 17:24:39 +00001119 if (!pl011_dma_tx_start(uap)) {
1120 uap->im |= UART011_TXIM;
1121 writew(uap->im, uap->port.membase + UART011_IMSC);
1122 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123}
1124
1125static void pl011_stop_rx(struct uart_port *port)
1126{
1127 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1128
1129 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1130 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1131 writew(uap->im, uap->port.membase + UART011_IMSC);
Linus Walleijead76f32011-02-24 13:21:08 +01001132
1133 pl011_dma_rx_stop(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001134}
1135
1136static void pl011_enable_ms(struct uart_port *port)
1137{
1138 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1139
1140 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1141 writew(uap->im, uap->port.membase + UART011_IMSC);
1142}
1143
David Howells7d12e782006-10-05 14:55:46 +01001144static void pl011_rx_chars(struct uart_amba_port *uap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145{
Alan Coxebd2c8f2009-09-19 13:13:28 -07001146 struct tty_struct *tty = uap->port.state->port.tty;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147
Linus Walleij29772c42011-02-24 13:21:36 +01001148 pl011_fifo_to_tty(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149
Thomas Gleixner2389b272007-05-29 21:53:50 +01001150 spin_unlock(&uap->port.lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151 tty_flip_buffer_push(tty);
Linus Walleijead76f32011-02-24 13:21:08 +01001152 /*
1153 * If we were temporarily out of DMA mode for a while,
1154 * attempt to switch back to DMA mode again.
1155 */
1156 if (pl011_dma_rx_available(uap)) {
1157 if (pl011_dma_rx_trigger_dma(uap)) {
1158 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1159 "fall back to interrupt mode again\n");
1160 uap->im |= UART011_RXIM;
1161 } else
1162 uap->im &= ~UART011_RXIM;
1163 writew(uap->im, uap->port.membase + UART011_IMSC);
1164 }
Thomas Gleixner2389b272007-05-29 21:53:50 +01001165 spin_lock(&uap->port.lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166}
1167
1168static void pl011_tx_chars(struct uart_amba_port *uap)
1169{
Alan Coxebd2c8f2009-09-19 13:13:28 -07001170 struct circ_buf *xmit = &uap->port.state->xmit;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171 int count;
1172
1173 if (uap->port.x_char) {
1174 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1175 uap->port.icount.tx++;
1176 uap->port.x_char = 0;
1177 return;
1178 }
1179 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
Russell Kingb129a8c2005-08-31 10:12:14 +01001180 pl011_stop_tx(&uap->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181 return;
1182 }
1183
Russell King68b65f72010-12-22 17:24:39 +00001184 /* If we are using DMA mode, try to send some characters. */
1185 if (pl011_dma_tx_irq(uap))
1186 return;
1187
Russell Kingffca2b12010-12-22 17:13:05 +00001188 count = uap->fifosize >> 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001189 do {
1190 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1191 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1192 uap->port.icount.tx++;
1193 if (uart_circ_empty(xmit))
1194 break;
1195 } while (--count > 0);
1196
1197 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1198 uart_write_wakeup(&uap->port);
1199
1200 if (uart_circ_empty(xmit))
Russell Kingb129a8c2005-08-31 10:12:14 +01001201 pl011_stop_tx(&uap->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001202}
1203
1204static void pl011_modem_status(struct uart_amba_port *uap)
1205{
1206 unsigned int status, delta;
1207
1208 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1209
1210 delta = status ^ uap->old_status;
1211 uap->old_status = status;
1212
1213 if (!delta)
1214 return;
1215
1216 if (delta & UART01x_FR_DCD)
1217 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1218
1219 if (delta & UART01x_FR_DSR)
1220 uap->port.icount.dsr++;
1221
1222 if (delta & UART01x_FR_CTS)
1223 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1224
Alan Coxbdc04e32009-09-19 13:13:31 -07001225 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226}
1227
David Howells7d12e782006-10-05 14:55:46 +01001228static irqreturn_t pl011_int(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229{
1230 struct uart_amba_port *uap = dev_id;
Russell King963cc982010-12-22 17:16:09 +00001231 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001232 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1233 int handled = 0;
1234
Russell King963cc982010-12-22 17:16:09 +00001235 spin_lock_irqsave(&uap->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001236
1237 status = readw(uap->port.membase + UART011_MIS);
1238 if (status) {
1239 do {
1240 writew(status & ~(UART011_TXIS|UART011_RTIS|
1241 UART011_RXIS),
1242 uap->port.membase + UART011_ICR);
1243
Linus Walleijead76f32011-02-24 13:21:08 +01001244 if (status & (UART011_RTIS|UART011_RXIS)) {
1245 if (pl011_dma_rx_running(uap))
1246 pl011_dma_rx_irq(uap);
1247 else
1248 pl011_rx_chars(uap);
1249 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1251 UART011_CTSMIS|UART011_RIMIS))
1252 pl011_modem_status(uap);
1253 if (status & UART011_TXIS)
1254 pl011_tx_chars(uap);
1255
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +02001256 if (pass_counter-- == 0) {
1257 if (uap->interrupt_may_hang)
1258 tasklet_schedule(&pl011_lockup_tlet);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001259 break;
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +02001260 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261
1262 status = readw(uap->port.membase + UART011_MIS);
1263 } while (status != 0);
1264 handled = 1;
1265 }
1266
Russell King963cc982010-12-22 17:16:09 +00001267 spin_unlock_irqrestore(&uap->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268
1269 return IRQ_RETVAL(handled);
1270}
1271
1272static unsigned int pl01x_tx_empty(struct uart_port *port)
1273{
1274 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1275 unsigned int status = readw(uap->port.membase + UART01x_FR);
1276 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1277}
1278
1279static unsigned int pl01x_get_mctrl(struct uart_port *port)
1280{
1281 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1282 unsigned int result = 0;
1283 unsigned int status = readw(uap->port.membase + UART01x_FR);
1284
Jiri Slaby5159f402007-10-18 23:40:31 -07001285#define TIOCMBIT(uartbit, tiocmbit) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001286 if (status & uartbit) \
1287 result |= tiocmbit
1288
Jiri Slaby5159f402007-10-18 23:40:31 -07001289 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1290 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1291 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1292 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1293#undef TIOCMBIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001294 return result;
1295}
1296
1297static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1298{
1299 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1300 unsigned int cr;
1301
1302 cr = readw(uap->port.membase + UART011_CR);
1303
Jiri Slaby5159f402007-10-18 23:40:31 -07001304#define TIOCMBIT(tiocmbit, uartbit) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305 if (mctrl & tiocmbit) \
1306 cr |= uartbit; \
1307 else \
1308 cr &= ~uartbit
1309
Jiri Slaby5159f402007-10-18 23:40:31 -07001310 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1311 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1312 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1313 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1314 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
Rabin Vincent3b438162010-02-12 06:43:11 +01001315
1316 if (uap->autorts) {
1317 /* We need to disable auto-RTS if we want to turn RTS off */
1318 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1319 }
Jiri Slaby5159f402007-10-18 23:40:31 -07001320#undef TIOCMBIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001321
1322 writew(cr, uap->port.membase + UART011_CR);
1323}
1324
1325static void pl011_break_ctl(struct uart_port *port, int break_state)
1326{
1327 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1328 unsigned long flags;
1329 unsigned int lcr_h;
1330
1331 spin_lock_irqsave(&uap->port.lock, flags);
Linus Walleijec489aa2010-06-02 08:13:52 +01001332 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001333 if (break_state == -1)
1334 lcr_h |= UART01x_LCRH_BRK;
1335 else
1336 lcr_h &= ~UART01x_LCRH_BRK;
Linus Walleijec489aa2010-06-02 08:13:52 +01001337 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001338 spin_unlock_irqrestore(&uap->port.lock, flags);
1339}
1340
Jason Wessel84b5ae12008-02-20 13:33:39 -06001341#ifdef CONFIG_CONSOLE_POLL
1342static int pl010_get_poll_char(struct uart_port *port)
1343{
1344 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1345 unsigned int status;
1346
Jason Wesself5316b42010-05-20 21:04:22 -05001347 status = readw(uap->port.membase + UART01x_FR);
1348 if (status & UART01x_FR_RXFE)
1349 return NO_POLL_CHAR;
Jason Wessel84b5ae12008-02-20 13:33:39 -06001350
1351 return readw(uap->port.membase + UART01x_DR);
1352}
1353
1354static void pl010_put_poll_char(struct uart_port *port,
1355 unsigned char ch)
1356{
1357 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1358
1359 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1360 barrier();
1361
1362 writew(ch, uap->port.membase + UART01x_DR);
1363}
1364
1365#endif /* CONFIG_CONSOLE_POLL */
1366
Linus Torvalds1da177e2005-04-16 15:20:36 -07001367static int pl011_startup(struct uart_port *port)
1368{
1369 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1370 unsigned int cr;
1371 int retval;
1372
Russell King4b4851c2011-09-22 11:35:30 +01001373 retval = clk_prepare(uap->clk);
1374 if (retval)
1375 goto out;
1376
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377 /*
1378 * Try to enable the clock producer.
1379 */
1380 retval = clk_enable(uap->clk);
1381 if (retval)
Russell King4b4851c2011-09-22 11:35:30 +01001382 goto clk_unprep;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001383
1384 uap->port.uartclk = clk_get_rate(uap->clk);
1385
1386 /*
1387 * Allocate the IRQ
1388 */
1389 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1390 if (retval)
1391 goto clk_dis;
1392
Russell Kingc19f12b2010-12-22 17:48:26 +00001393 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394
1395 /*
1396 * Provoke TX FIFO interrupt into asserting.
1397 */
1398 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1399 writew(cr, uap->port.membase + UART011_CR);
1400 writew(0, uap->port.membase + UART011_FBRD);
1401 writew(1, uap->port.membase + UART011_IBRD);
Linus Walleijec489aa2010-06-02 08:13:52 +01001402 writew(0, uap->port.membase + uap->lcrh_rx);
1403 if (uap->lcrh_tx != uap->lcrh_rx) {
1404 int i;
1405 /*
1406 * Wait 10 PCLKs before writing LCRH_TX register,
1407 * to get this delay write read only register 10 times
1408 */
1409 for (i = 0; i < 10; ++i)
1410 writew(0xff, uap->port.membase + UART011_MIS);
1411 writew(0, uap->port.membase + uap->lcrh_tx);
1412 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413 writew(0, uap->port.membase + UART01x_DR);
1414 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1415 barrier();
1416
1417 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1418 writew(cr, uap->port.membase + UART011_CR);
1419
Russell King5063e2c2010-12-22 17:09:08 +00001420 /* Clear pending error interrupts */
1421 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
1422 uap->port.membase + UART011_ICR);
1423
Linus Torvalds1da177e2005-04-16 15:20:36 -07001424 /*
1425 * initialise the old status of the modem signals
1426 */
1427 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1428
Russell King68b65f72010-12-22 17:24:39 +00001429 /* Startup DMA */
1430 pl011_dma_startup(uap);
1431
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432 /*
Linus Walleijead76f32011-02-24 13:21:08 +01001433 * Finally, enable interrupts, only timeouts when using DMA
1434 * if initial RX DMA job failed, start in interrupt mode
1435 * as well.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001436 */
1437 spin_lock_irq(&uap->port.lock);
Linus Walleijead76f32011-02-24 13:21:08 +01001438 uap->im = UART011_RTIM;
1439 if (!pl011_dma_rx_running(uap))
1440 uap->im |= UART011_RXIM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001441 writew(uap->im, uap->port.membase + UART011_IMSC);
1442 spin_unlock_irq(&uap->port.lock);
1443
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +02001444 if (uap->port.dev->platform_data) {
1445 struct amba_pl011_data *plat;
1446
1447 plat = uap->port.dev->platform_data;
1448 if (plat->init)
1449 plat->init();
1450 }
1451
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452 return 0;
1453
1454 clk_dis:
1455 clk_disable(uap->clk);
Russell King4b4851c2011-09-22 11:35:30 +01001456 clk_unprep:
1457 clk_unprepare(uap->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001458 out:
1459 return retval;
1460}
1461
Linus Walleijec489aa2010-06-02 08:13:52 +01001462static void pl011_shutdown_channel(struct uart_amba_port *uap,
1463 unsigned int lcrh)
1464{
1465 unsigned long val;
1466
1467 val = readw(uap->port.membase + lcrh);
1468 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1469 writew(val, uap->port.membase + lcrh);
1470}
1471
Linus Torvalds1da177e2005-04-16 15:20:36 -07001472static void pl011_shutdown(struct uart_port *port)
1473{
1474 struct uart_amba_port *uap = (struct uart_amba_port *)port;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001475
1476 /*
1477 * disable all interrupts
1478 */
1479 spin_lock_irq(&uap->port.lock);
1480 uap->im = 0;
1481 writew(uap->im, uap->port.membase + UART011_IMSC);
1482 writew(0xffff, uap->port.membase + UART011_ICR);
1483 spin_unlock_irq(&uap->port.lock);
1484
Russell King68b65f72010-12-22 17:24:39 +00001485 pl011_dma_shutdown(uap);
1486
Linus Torvalds1da177e2005-04-16 15:20:36 -07001487 /*
1488 * Free the interrupt
1489 */
1490 free_irq(uap->port.irq, uap);
1491
1492 /*
1493 * disable the port
1494 */
Rabin Vincent3b438162010-02-12 06:43:11 +01001495 uap->autorts = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
1497
1498 /*
1499 * disable break condition and fifos
1500 */
Linus Walleijec489aa2010-06-02 08:13:52 +01001501 pl011_shutdown_channel(uap, uap->lcrh_rx);
1502 if (uap->lcrh_rx != uap->lcrh_tx)
1503 pl011_shutdown_channel(uap, uap->lcrh_tx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001504
1505 /*
1506 * Shut down the clock producer
1507 */
1508 clk_disable(uap->clk);
Russell King4b4851c2011-09-22 11:35:30 +01001509 clk_unprepare(uap->clk);
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +02001510
1511 if (uap->port.dev->platform_data) {
1512 struct amba_pl011_data *plat;
1513
1514 plat = uap->port.dev->platform_data;
1515 if (plat->exit)
1516 plat->exit();
1517 }
1518
Linus Torvalds1da177e2005-04-16 15:20:36 -07001519}
1520
1521static void
Alan Cox606d0992006-12-08 02:38:45 -08001522pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1523 struct ktermios *old)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524{
Rabin Vincent3b438162010-02-12 06:43:11 +01001525 struct uart_amba_port *uap = (struct uart_amba_port *)port;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526 unsigned int lcr_h, old_cr;
1527 unsigned long flags;
Russell Kingc19f12b2010-12-22 17:48:26 +00001528 unsigned int baud, quot, clkdiv;
1529
1530 if (uap->vendor->oversampling)
1531 clkdiv = 8;
1532 else
1533 clkdiv = 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534
1535 /*
1536 * Ask the core to calculate the divisor for us.
1537 */
Linus Walleijac3e3fb2010-06-02 20:40:22 +01001538 baud = uart_get_baud_rate(port, termios, old, 0,
Russell Kingc19f12b2010-12-22 17:48:26 +00001539 port->uartclk / clkdiv);
Linus Walleijac3e3fb2010-06-02 20:40:22 +01001540
1541 if (baud > port->uartclk/16)
1542 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1543 else
1544 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545
1546 switch (termios->c_cflag & CSIZE) {
1547 case CS5:
1548 lcr_h = UART01x_LCRH_WLEN_5;
1549 break;
1550 case CS6:
1551 lcr_h = UART01x_LCRH_WLEN_6;
1552 break;
1553 case CS7:
1554 lcr_h = UART01x_LCRH_WLEN_7;
1555 break;
1556 default: // CS8
1557 lcr_h = UART01x_LCRH_WLEN_8;
1558 break;
1559 }
1560 if (termios->c_cflag & CSTOPB)
1561 lcr_h |= UART01x_LCRH_STP2;
1562 if (termios->c_cflag & PARENB) {
1563 lcr_h |= UART01x_LCRH_PEN;
1564 if (!(termios->c_cflag & PARODD))
1565 lcr_h |= UART01x_LCRH_EPS;
1566 }
Russell Kingffca2b12010-12-22 17:13:05 +00001567 if (uap->fifosize > 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001568 lcr_h |= UART01x_LCRH_FEN;
1569
1570 spin_lock_irqsave(&port->lock, flags);
1571
1572 /*
1573 * Update the per-port timeout.
1574 */
1575 uart_update_timeout(port, termios->c_cflag, baud);
1576
Russell Kingb63d4f02005-11-19 11:10:35 +00001577 port->read_status_mask = UART011_DR_OE | 255;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001578 if (termios->c_iflag & INPCK)
Russell Kingb63d4f02005-11-19 11:10:35 +00001579 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001580 if (termios->c_iflag & (BRKINT | PARMRK))
Russell Kingb63d4f02005-11-19 11:10:35 +00001581 port->read_status_mask |= UART011_DR_BE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582
1583 /*
1584 * Characters to ignore
1585 */
1586 port->ignore_status_mask = 0;
1587 if (termios->c_iflag & IGNPAR)
Russell Kingb63d4f02005-11-19 11:10:35 +00001588 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001589 if (termios->c_iflag & IGNBRK) {
Russell Kingb63d4f02005-11-19 11:10:35 +00001590 port->ignore_status_mask |= UART011_DR_BE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001591 /*
1592 * If we're ignoring parity and break indicators,
1593 * ignore overruns too (for real raw support).
1594 */
1595 if (termios->c_iflag & IGNPAR)
Russell Kingb63d4f02005-11-19 11:10:35 +00001596 port->ignore_status_mask |= UART011_DR_OE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597 }
1598
1599 /*
1600 * Ignore all characters if CREAD is not set.
1601 */
1602 if ((termios->c_cflag & CREAD) == 0)
Russell Kingb63d4f02005-11-19 11:10:35 +00001603 port->ignore_status_mask |= UART_DUMMY_DR_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604
1605 if (UART_ENABLE_MS(port, termios->c_cflag))
1606 pl011_enable_ms(port);
1607
1608 /* first, disable everything */
1609 old_cr = readw(port->membase + UART011_CR);
1610 writew(0, port->membase + UART011_CR);
1611
Rabin Vincent3b438162010-02-12 06:43:11 +01001612 if (termios->c_cflag & CRTSCTS) {
1613 if (old_cr & UART011_CR_RTS)
1614 old_cr |= UART011_CR_RTSEN;
1615
1616 old_cr |= UART011_CR_CTSEN;
1617 uap->autorts = true;
1618 } else {
1619 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1620 uap->autorts = false;
1621 }
1622
Russell Kingc19f12b2010-12-22 17:48:26 +00001623 if (uap->vendor->oversampling) {
1624 if (baud > port->uartclk / 16)
Linus Walleijac3e3fb2010-06-02 20:40:22 +01001625 old_cr |= ST_UART011_CR_OVSFACT;
1626 else
1627 old_cr &= ~ST_UART011_CR_OVSFACT;
1628 }
1629
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630 /* Set baud rate */
1631 writew(quot & 0x3f, port->membase + UART011_FBRD);
1632 writew(quot >> 6, port->membase + UART011_IBRD);
1633
1634 /*
1635 * ----------v----------v----------v----------v-----
1636 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
1637 * ----------^----------^----------^----------^-----
1638 */
Linus Walleijec489aa2010-06-02 08:13:52 +01001639 writew(lcr_h, port->membase + uap->lcrh_rx);
1640 if (uap->lcrh_rx != uap->lcrh_tx) {
1641 int i;
1642 /*
1643 * Wait 10 PCLKs before writing LCRH_TX register,
1644 * to get this delay write read only register 10 times
1645 */
1646 for (i = 0; i < 10; ++i)
1647 writew(0xff, uap->port.membase + UART011_MIS);
1648 writew(lcr_h, port->membase + uap->lcrh_tx);
1649 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001650 writew(old_cr, port->membase + UART011_CR);
1651
1652 spin_unlock_irqrestore(&port->lock, flags);
1653}
1654
1655static const char *pl011_type(struct uart_port *port)
1656{
Russell Kinge8a7ba82010-12-28 09:16:54 +00001657 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1658 return uap->port.type == PORT_AMBA ? uap->type : NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001659}
1660
1661/*
1662 * Release the memory region(s) being used by 'port'
1663 */
1664static void pl010_release_port(struct uart_port *port)
1665{
1666 release_mem_region(port->mapbase, SZ_4K);
1667}
1668
1669/*
1670 * Request the memory region(s) being used by 'port'
1671 */
1672static int pl010_request_port(struct uart_port *port)
1673{
1674 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1675 != NULL ? 0 : -EBUSY;
1676}
1677
1678/*
1679 * Configure/autoconfigure the port.
1680 */
1681static void pl010_config_port(struct uart_port *port, int flags)
1682{
1683 if (flags & UART_CONFIG_TYPE) {
1684 port->type = PORT_AMBA;
1685 pl010_request_port(port);
1686 }
1687}
1688
1689/*
1690 * verify the new serial_struct (for TIOCSSERIAL).
1691 */
1692static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
1693{
1694 int ret = 0;
1695 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1696 ret = -EINVAL;
Yinghai Lua62c4132008-08-19 20:49:55 -07001697 if (ser->irq < 0 || ser->irq >= nr_irqs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001698 ret = -EINVAL;
1699 if (ser->baud_base < 9600)
1700 ret = -EINVAL;
1701 return ret;
1702}
1703
1704static struct uart_ops amba_pl011_pops = {
1705 .tx_empty = pl01x_tx_empty,
1706 .set_mctrl = pl011_set_mctrl,
1707 .get_mctrl = pl01x_get_mctrl,
1708 .stop_tx = pl011_stop_tx,
1709 .start_tx = pl011_start_tx,
1710 .stop_rx = pl011_stop_rx,
1711 .enable_ms = pl011_enable_ms,
1712 .break_ctl = pl011_break_ctl,
1713 .startup = pl011_startup,
1714 .shutdown = pl011_shutdown,
Russell King68b65f72010-12-22 17:24:39 +00001715 .flush_buffer = pl011_dma_flush_buffer,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001716 .set_termios = pl011_set_termios,
1717 .type = pl011_type,
1718 .release_port = pl010_release_port,
1719 .request_port = pl010_request_port,
1720 .config_port = pl010_config_port,
1721 .verify_port = pl010_verify_port,
Jason Wessel84b5ae12008-02-20 13:33:39 -06001722#ifdef CONFIG_CONSOLE_POLL
1723 .poll_get_char = pl010_get_poll_char,
1724 .poll_put_char = pl010_put_poll_char,
1725#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001726};
1727
1728static struct uart_amba_port *amba_ports[UART_NR];
1729
1730#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1731
Russell Kingd3587882006-03-20 20:00:09 +00001732static void pl011_console_putchar(struct uart_port *port, int ch)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001733{
Russell Kingd3587882006-03-20 20:00:09 +00001734 struct uart_amba_port *uap = (struct uart_amba_port *)port;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001735
Russell Kingd3587882006-03-20 20:00:09 +00001736 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1737 barrier();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001738 writew(ch, uap->port.membase + UART01x_DR);
1739}
1740
1741static void
1742pl011_console_write(struct console *co, const char *s, unsigned int count)
1743{
1744 struct uart_amba_port *uap = amba_ports[co->index];
1745 unsigned int status, old_cr, new_cr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001746
1747 clk_enable(uap->clk);
1748
1749 /*
1750 * First save the CR then disable the interrupts
1751 */
1752 old_cr = readw(uap->port.membase + UART011_CR);
1753 new_cr = old_cr & ~UART011_CR_CTSEN;
1754 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1755 writew(new_cr, uap->port.membase + UART011_CR);
1756
Russell Kingd3587882006-03-20 20:00:09 +00001757 uart_console_write(&uap->port, s, count, pl011_console_putchar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001758
1759 /*
1760 * Finally, wait for transmitter to become empty
1761 * and restore the TCR
1762 */
1763 do {
1764 status = readw(uap->port.membase + UART01x_FR);
1765 } while (status & UART01x_FR_BUSY);
1766 writew(old_cr, uap->port.membase + UART011_CR);
1767
1768 clk_disable(uap->clk);
1769}
1770
1771static void __init
1772pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1773 int *parity, int *bits)
1774{
1775 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1776 unsigned int lcr_h, ibrd, fbrd;
1777
Linus Walleijec489aa2010-06-02 08:13:52 +01001778 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001779
1780 *parity = 'n';
1781 if (lcr_h & UART01x_LCRH_PEN) {
1782 if (lcr_h & UART01x_LCRH_EPS)
1783 *parity = 'e';
1784 else
1785 *parity = 'o';
1786 }
1787
1788 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1789 *bits = 7;
1790 else
1791 *bits = 8;
1792
1793 ibrd = readw(uap->port.membase + UART011_IBRD);
1794 fbrd = readw(uap->port.membase + UART011_FBRD);
1795
1796 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
Linus Walleijac3e3fb2010-06-02 20:40:22 +01001797
Russell Kingc19f12b2010-12-22 17:48:26 +00001798 if (uap->vendor->oversampling) {
Linus Walleijac3e3fb2010-06-02 20:40:22 +01001799 if (readw(uap->port.membase + UART011_CR)
1800 & ST_UART011_CR_OVSFACT)
1801 *baud *= 2;
1802 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001803 }
1804}
1805
1806static int __init pl011_console_setup(struct console *co, char *options)
1807{
1808 struct uart_amba_port *uap;
1809 int baud = 38400;
1810 int bits = 8;
1811 int parity = 'n';
1812 int flow = 'n';
Russell King4b4851c2011-09-22 11:35:30 +01001813 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814
1815 /*
1816 * Check whether an invalid uart number has been specified, and
1817 * if so, search for the first available port that does have
1818 * console support.
1819 */
1820 if (co->index >= UART_NR)
1821 co->index = 0;
1822 uap = amba_ports[co->index];
Russell Kingd28122a2007-01-22 18:59:42 +00001823 if (!uap)
1824 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001825
Russell King4b4851c2011-09-22 11:35:30 +01001826 ret = clk_prepare(uap->clk);
1827 if (ret)
1828 return ret;
1829
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +02001830 if (uap->port.dev->platform_data) {
1831 struct amba_pl011_data *plat;
1832
1833 plat = uap->port.dev->platform_data;
1834 if (plat->init)
1835 plat->init();
1836 }
1837
Linus Torvalds1da177e2005-04-16 15:20:36 -07001838 uap->port.uartclk = clk_get_rate(uap->clk);
1839
1840 if (options)
1841 uart_parse_options(options, &baud, &parity, &bits, &flow);
1842 else
1843 pl011_console_get_options(uap, &baud, &parity, &bits);
1844
1845 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
1846}
1847
Vincent Sanders2d934862005-09-14 22:36:03 +01001848static struct uart_driver amba_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001849static struct console amba_console = {
1850 .name = "ttyAMA",
1851 .write = pl011_console_write,
1852 .device = uart_console_device,
1853 .setup = pl011_console_setup,
1854 .flags = CON_PRINTBUFFER,
1855 .index = -1,
1856 .data = &amba_reg,
1857};
1858
1859#define AMBA_CONSOLE (&amba_console)
1860#else
1861#define AMBA_CONSOLE NULL
1862#endif
1863
1864static struct uart_driver amba_reg = {
1865 .owner = THIS_MODULE,
1866 .driver_name = "ttyAMA",
1867 .dev_name = "ttyAMA",
1868 .major = SERIAL_AMBA_MAJOR,
1869 .minor = SERIAL_AMBA_MINOR,
1870 .nr = UART_NR,
1871 .cons = AMBA_CONSOLE,
1872};
1873
Russell Kingaa25afa2011-02-19 15:55:00 +00001874static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875{
1876 struct uart_amba_port *uap;
Alessandro Rubini5926a292009-06-04 17:43:04 +01001877 struct vendor_data *vendor = id->data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001878 void __iomem *base;
1879 int i, ret;
1880
1881 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1882 if (amba_ports[i] == NULL)
1883 break;
1884
1885 if (i == ARRAY_SIZE(amba_ports)) {
1886 ret = -EBUSY;
1887 goto out;
1888 }
1889
Yoann Padioleaudd00cc42007-07-19 01:49:03 -07001890 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001891 if (uap == NULL) {
1892 ret = -ENOMEM;
1893 goto out;
1894 }
1895
Linus Walleijdc890c22009-06-07 23:27:31 +01001896 base = ioremap(dev->res.start, resource_size(&dev->res));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001897 if (!base) {
1898 ret = -ENOMEM;
1899 goto free;
1900 }
1901
Russell Kingee569c42008-11-30 17:38:14 +00001902 uap->clk = clk_get(&dev->dev, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001903 if (IS_ERR(uap->clk)) {
1904 ret = PTR_ERR(uap->clk);
1905 goto unmap;
1906 }
1907
Russell Kingc19f12b2010-12-22 17:48:26 +00001908 uap->vendor = vendor;
Linus Walleijec489aa2010-06-02 08:13:52 +01001909 uap->lcrh_rx = vendor->lcrh_rx;
1910 uap->lcrh_tx = vendor->lcrh_tx;
Russell Kingffca2b12010-12-22 17:13:05 +00001911 uap->fifosize = vendor->fifosize;
Shreshtha Kumar Sahuc16d51a2011-06-13 10:11:33 +02001912 uap->interrupt_may_hang = vendor->interrupt_may_hang;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001913 uap->port.dev = &dev->dev;
1914 uap->port.mapbase = dev->res.start;
1915 uap->port.membase = base;
1916 uap->port.iotype = UPIO_MEM;
1917 uap->port.irq = dev->irq[0];
Russell Kingffca2b12010-12-22 17:13:05 +00001918 uap->port.fifosize = uap->fifosize;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001919 uap->port.ops = &amba_pl011_pops;
1920 uap->port.flags = UPF_BOOT_AUTOCONF;
1921 uap->port.line = i;
Russell King68b65f72010-12-22 17:24:39 +00001922 pl011_dma_probe(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001923
Russell Kinge8a7ba82010-12-28 09:16:54 +00001924 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
1925
Linus Torvalds1da177e2005-04-16 15:20:36 -07001926 amba_ports[i] = uap;
1927
1928 amba_set_drvdata(dev, uap);
1929 ret = uart_add_one_port(&amba_reg, &uap->port);
1930 if (ret) {
1931 amba_set_drvdata(dev, NULL);
1932 amba_ports[i] = NULL;
Russell King68b65f72010-12-22 17:24:39 +00001933 pl011_dma_remove(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001934 clk_put(uap->clk);
1935 unmap:
1936 iounmap(base);
1937 free:
1938 kfree(uap);
1939 }
1940 out:
1941 return ret;
1942}
1943
1944static int pl011_remove(struct amba_device *dev)
1945{
1946 struct uart_amba_port *uap = amba_get_drvdata(dev);
1947 int i;
1948
1949 amba_set_drvdata(dev, NULL);
1950
1951 uart_remove_one_port(&amba_reg, &uap->port);
1952
1953 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1954 if (amba_ports[i] == uap)
1955 amba_ports[i] = NULL;
1956
Russell King68b65f72010-12-22 17:24:39 +00001957 pl011_dma_remove(uap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001958 iounmap(uap->port.membase);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001959 clk_put(uap->clk);
1960 kfree(uap);
1961 return 0;
1962}
1963
Leo Chenb736b892009-07-28 23:43:33 +01001964#ifdef CONFIG_PM
1965static int pl011_suspend(struct amba_device *dev, pm_message_t state)
1966{
1967 struct uart_amba_port *uap = amba_get_drvdata(dev);
1968
1969 if (!uap)
1970 return -EINVAL;
1971
1972 return uart_suspend_port(&amba_reg, &uap->port);
1973}
1974
1975static int pl011_resume(struct amba_device *dev)
1976{
1977 struct uart_amba_port *uap = amba_get_drvdata(dev);
1978
1979 if (!uap)
1980 return -EINVAL;
1981
1982 return uart_resume_port(&amba_reg, &uap->port);
1983}
1984#endif
1985
Russell King2c39c9e2010-07-27 08:50:16 +01001986static struct amba_id pl011_ids[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001987 {
1988 .id = 0x00041011,
1989 .mask = 0x000fffff,
Alessandro Rubini5926a292009-06-04 17:43:04 +01001990 .data = &vendor_arm,
1991 },
1992 {
1993 .id = 0x00380802,
1994 .mask = 0x00ffffff,
1995 .data = &vendor_st,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001996 },
1997 { 0, 0 },
1998};
1999
Dave Martin60f7a332011-10-05 15:15:22 +01002000MODULE_DEVICE_TABLE(amba, pl011_ids);
2001
Linus Torvalds1da177e2005-04-16 15:20:36 -07002002static struct amba_driver pl011_driver = {
2003 .drv = {
2004 .name = "uart-pl011",
2005 },
2006 .id_table = pl011_ids,
2007 .probe = pl011_probe,
2008 .remove = pl011_remove,
Leo Chenb736b892009-07-28 23:43:33 +01002009#ifdef CONFIG_PM
2010 .suspend = pl011_suspend,
2011 .resume = pl011_resume,
2012#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002013};
2014
2015static int __init pl011_init(void)
2016{
2017 int ret;
2018 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2019
2020 ret = uart_register_driver(&amba_reg);
2021 if (ret == 0) {
2022 ret = amba_driver_register(&pl011_driver);
2023 if (ret)
2024 uart_unregister_driver(&amba_reg);
2025 }
2026 return ret;
2027}
2028
2029static void __exit pl011_exit(void)
2030{
2031 amba_driver_unregister(&pl011_driver);
2032 uart_unregister_driver(&amba_reg);
2033}
2034
Alessandro Rubini4dd9e742009-05-05 05:54:13 +01002035/*
2036 * While this can be a module, if builtin it's most likely the console
2037 * So let's leave module_exit but move module_init to an earlier place
2038 */
2039arch_initcall(pl011_init);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002040module_exit(pl011_exit);
2041
2042MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2043MODULE_DESCRIPTION("ARM AMBA serial port driver");
2044MODULE_LICENSE("GPL");