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Vitaly Wool9325fa32006-06-26 19:31:49 +04001/*
2 * drivers/char/watchdog/pnx4008_wdt.c
3 *
4 * Watchdog driver for PNX4008 board
5 *
6 * Authors: Dmitry Chigirev <source@mvista.com>,
Wim Van Sebroeck5f3b2752011-02-23 20:04:38 +00007 * Vitaly Wool <vitalywool@gmail.com>
Vitaly Wool9325fa32006-06-26 19:31:49 +04008 * Based on sa1100 driver,
9 * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
10 *
Wolfram Sang6b1e8382012-02-02 18:48:11 +010011 * 2005-2006 (c) MontaVista Software, Inc.
12 *
13 * (C) 2012 Wolfram Sang, Pengutronix
14 *
15 * This file is licensed under the terms of the GNU General Public License
16 * version 2. This program is licensed "as is" without any warranty of any
17 * kind, whether express or implied.
Vitaly Wool9325fa32006-06-26 19:31:49 +040018 */
19
Joe Perches27c766a2012-02-15 15:06:19 -080020#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
Vitaly Wool9325fa32006-06-26 19:31:49 +040022#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/types.h>
25#include <linux/kernel.h>
Vitaly Wool9325fa32006-06-26 19:31:49 +040026#include <linux/miscdevice.h>
27#include <linux/watchdog.h>
28#include <linux/init.h>
Vitaly Wool9325fa32006-06-26 19:31:49 +040029#include <linux/platform_device.h>
30#include <linux/clk.h>
Wim Van Sebroeck99d28532006-09-10 12:48:15 +020031#include <linux/spinlock.h>
Alan Cox84ca9952008-05-19 14:07:48 +010032#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Wolfram Sang6b1e8382012-02-02 18:48:11 +010034#include <linux/err.h>
Roland Stigge3ba37742012-04-20 21:55:29 +020035#include <linux/of.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010036#include <mach/hardware.h>
Vitaly Wool9325fa32006-06-26 19:31:49 +040037
Vitaly Wool9325fa32006-06-26 19:31:49 +040038/* WatchDog Timer - Chapter 23 Page 207 */
39
40#define DEFAULT_HEARTBEAT 19
41#define MAX_HEARTBEAT 60
42
43/* Watchdog timer register set definition */
44#define WDTIM_INT(p) ((p) + 0x0)
45#define WDTIM_CTRL(p) ((p) + 0x4)
46#define WDTIM_COUNTER(p) ((p) + 0x8)
47#define WDTIM_MCTRL(p) ((p) + 0xC)
48#define WDTIM_MATCH0(p) ((p) + 0x10)
49#define WDTIM_EMR(p) ((p) + 0x14)
50#define WDTIM_PULSE(p) ((p) + 0x18)
51#define WDTIM_RES(p) ((p) + 0x1C)
52
53/* WDTIM_INT bit definitions */
54#define MATCH_INT 1
55
56/* WDTIM_CTRL bit definitions */
57#define COUNT_ENAB 1
Wim Van Sebroeck143a2e52009-03-18 08:35:09 +000058#define RESET_COUNT (1 << 1)
59#define DEBUG_EN (1 << 2)
Vitaly Wool9325fa32006-06-26 19:31:49 +040060
61/* WDTIM_MCTRL bit definitions */
62#define MR0_INT 1
63#undef RESET_COUNT0
Wim Van Sebroeck143a2e52009-03-18 08:35:09 +000064#define RESET_COUNT0 (1 << 2)
65#define STOP_COUNT0 (1 << 2)
66#define M_RES1 (1 << 3)
67#define M_RES2 (1 << 4)
68#define RESFRC1 (1 << 5)
69#define RESFRC2 (1 << 6)
Vitaly Wool9325fa32006-06-26 19:31:49 +040070
71/* WDTIM_EMR bit definitions */
72#define EXT_MATCH0 1
Wim Van Sebroeck143a2e52009-03-18 08:35:09 +000073#define MATCH_OUTPUT_HIGH (2 << 4) /*a MATCH_CTRL setting */
Vitaly Wool9325fa32006-06-26 19:31:49 +040074
75/* WDTIM_RES bit definitions */
76#define WDOG_RESET 1 /* read only */
77
78#define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */
79
Wim Van Sebroeck86a1e182012-03-05 16:51:11 +010080static bool nowayout = WATCHDOG_NOWAYOUT;
Wolfram Sang6b1e8382012-02-02 18:48:11 +010081static unsigned int heartbeat = DEFAULT_HEARTBEAT;
Vitaly Wool9325fa32006-06-26 19:31:49 +040082
Alexey Dobriyanc7dfd0c2007-11-01 16:27:08 -070083static DEFINE_SPINLOCK(io_lock);
Vitaly Wool9325fa32006-06-26 19:31:49 +040084static void __iomem *wdt_base;
85struct clk *wdt_clk;
86
Wolfram Sang6b1e8382012-02-02 18:48:11 +010087static int pnx4008_wdt_start(struct watchdog_device *wdd)
Vitaly Wool9325fa32006-06-26 19:31:49 +040088{
Wim Van Sebroeck99d28532006-09-10 12:48:15 +020089 spin_lock(&io_lock);
90
Vitaly Wool9325fa32006-06-26 19:31:49 +040091 /* stop counter, initiate counter reset */
Wolfram Sang7cbc3532012-02-02 18:48:09 +010092 writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
Vitaly Wool9325fa32006-06-26 19:31:49 +040093 /*wait for reset to complete. 100% guarantee event */
Wolfram Sang7cbc3532012-02-02 18:48:09 +010094 while (readl(WDTIM_COUNTER(wdt_base)))
Vitaly Wool65a64ec2006-09-11 14:42:39 +040095 cpu_relax();
Vitaly Wool9325fa32006-06-26 19:31:49 +040096 /* internal and external reset, stop after that */
Wolfram Sang7cbc3532012-02-02 18:48:09 +010097 writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
Vitaly Wool9325fa32006-06-26 19:31:49 +040098 /* configure match output */
Wolfram Sang7cbc3532012-02-02 18:48:09 +010099 writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
Vitaly Wool9325fa32006-06-26 19:31:49 +0400100 /* clear interrupt, just in case */
Wolfram Sang7cbc3532012-02-02 18:48:09 +0100101 writel(MATCH_INT, WDTIM_INT(wdt_base));
Vitaly Wool9325fa32006-06-26 19:31:49 +0400102 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
Wolfram Sang7cbc3532012-02-02 18:48:09 +0100103 writel(0xFFFF, WDTIM_PULSE(wdt_base));
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100104 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
Vitaly Wool9325fa32006-06-26 19:31:49 +0400105 /*enable counter, stop when debugger active */
Wolfram Sang7cbc3532012-02-02 18:48:09 +0100106 writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
Wim Van Sebroeck99d28532006-09-10 12:48:15 +0200107
108 spin_unlock(&io_lock);
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100109 return 0;
Vitaly Wool9325fa32006-06-26 19:31:49 +0400110}
111
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100112static int pnx4008_wdt_stop(struct watchdog_device *wdd)
Vitaly Wool9325fa32006-06-26 19:31:49 +0400113{
Wim Van Sebroeck99d28532006-09-10 12:48:15 +0200114 spin_lock(&io_lock);
115
Wolfram Sang7cbc3532012-02-02 18:48:09 +0100116 writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */
Wim Van Sebroeck99d28532006-09-10 12:48:15 +0200117
118 spin_unlock(&io_lock);
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100119 return 0;
Vitaly Wool9325fa32006-06-26 19:31:49 +0400120}
121
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100122static int pnx4008_wdt_set_timeout(struct watchdog_device *wdd,
123 unsigned int new_timeout)
Vitaly Wool9325fa32006-06-26 19:31:49 +0400124{
Wim Van Sebroeck0197c1c2012-02-29 20:20:58 +0100125 wdd->timeout = new_timeout;
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100126 return 0;
Vitaly Wool9325fa32006-06-26 19:31:49 +0400127}
128
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100129static const struct watchdog_info pnx4008_wdt_ident = {
Vitaly Wool9325fa32006-06-26 19:31:49 +0400130 .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
131 WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
132 .identity = "PNX4008 Watchdog",
133};
134
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100135static const struct watchdog_ops pnx4008_wdt_ops = {
Vitaly Wool9325fa32006-06-26 19:31:49 +0400136 .owner = THIS_MODULE,
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100137 .start = pnx4008_wdt_start,
138 .stop = pnx4008_wdt_stop,
139 .set_timeout = pnx4008_wdt_set_timeout,
Vitaly Wool9325fa32006-06-26 19:31:49 +0400140};
141
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100142static struct watchdog_device pnx4008_wdd = {
143 .info = &pnx4008_wdt_ident,
144 .ops = &pnx4008_wdt_ops,
Fabio Porceddac1fd5f62013-02-14 09:14:25 +0100145 .timeout = DEFAULT_HEARTBEAT,
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100146 .min_timeout = 1,
147 .max_timeout = MAX_HEARTBEAT,
Vitaly Wool9325fa32006-06-26 19:31:49 +0400148};
149
Bill Pemberton2d991a12012-11-19 13:21:41 -0500150static int pnx4008_wdt_probe(struct platform_device *pdev)
Vitaly Wool9325fa32006-06-26 19:31:49 +0400151{
Wolfram Sang19f505f2012-02-02 18:48:08 +0100152 struct resource *r;
153 int ret = 0;
Vitaly Wool9325fa32006-06-26 19:31:49 +0400154
Fabio Porceddac1fd5f62013-02-14 09:14:25 +0100155 watchdog_init_timeout(&pnx4008_wdd, heartbeat, &pdev->dev);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400156
Wolfram Sang19f505f2012-02-02 18:48:08 +0100157 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding4c271bb2013-01-21 11:09:25 +0100158 wdt_base = devm_ioremap_resource(&pdev->dev, r);
159 if (IS_ERR(wdt_base))
160 return PTR_ERR(wdt_base);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400161
Russell King9bb787f2009-11-20 13:07:28 +0000162 wdt_clk = clk_get(&pdev->dev, NULL);
Wolfram Sang19f505f2012-02-02 18:48:08 +0100163 if (IS_ERR(wdt_clk))
164 return PTR_ERR(wdt_clk);
Russell King24fd1ed2009-11-20 13:04:14 +0000165
166 ret = clk_enable(wdt_clk);
Wolfram Sang19f505f2012-02-02 18:48:08 +0100167 if (ret)
Russell King24fd1ed2009-11-20 13:04:14 +0000168 goto out;
Wolfram Sang19f505f2012-02-02 18:48:08 +0100169
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100170 pnx4008_wdd.bootstatus = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
Wolfram Sang7cbc3532012-02-02 18:48:09 +0100171 WDIOF_CARDRESET : 0;
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100172 watchdog_set_nowayout(&pnx4008_wdd, nowayout);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400173
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100174 pnx4008_wdt_stop(&pnx4008_wdd); /* disable for now */
175
176 ret = watchdog_register_device(&pnx4008_wdd);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400177 if (ret < 0) {
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100178 dev_err(&pdev->dev, "cannot register watchdog device\n");
179 goto disable_clk;
Vitaly Wool9325fa32006-06-26 19:31:49 +0400180 }
181
Wolfram Sang19f505f2012-02-02 18:48:08 +0100182 dev_info(&pdev->dev, "PNX4008 Watchdog Timer: heartbeat %d sec\n",
Fabio Porceddac1fd5f62013-02-14 09:14:25 +0100183 pnx4008_wdd.timeout);
Wolfram Sang19f505f2012-02-02 18:48:08 +0100184
185 return 0;
186
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100187disable_clk:
188 clk_disable(wdt_clk);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400189out:
Wolfram Sang19f505f2012-02-02 18:48:08 +0100190 clk_put(wdt_clk);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400191 return ret;
192}
193
Bill Pemberton4b12b892012-11-19 13:26:24 -0500194static int pnx4008_wdt_remove(struct platform_device *pdev)
Vitaly Wool9325fa32006-06-26 19:31:49 +0400195{
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100196 watchdog_unregister_device(&pnx4008_wdd);
Russell King24fd1ed2009-11-20 13:04:14 +0000197
198 clk_disable(wdt_clk);
199 clk_put(wdt_clk);
200
Vitaly Wool9325fa32006-06-26 19:31:49 +0400201 return 0;
202}
203
Roland Stigge3ba37742012-04-20 21:55:29 +0200204#ifdef CONFIG_OF
205static const struct of_device_id pnx4008_wdt_match[] = {
206 { .compatible = "nxp,pnx4008-wdt" },
207 { }
208};
209MODULE_DEVICE_TABLE(of, pnx4008_wdt_match);
210#endif
211
Vitaly Wool9325fa32006-06-26 19:31:49 +0400212static struct platform_driver platform_wdt_driver = {
213 .driver = {
Russell King1508c992009-11-20 13:07:57 +0000214 .name = "pnx4008-watchdog",
Kay Sieversf37d1932008-04-10 21:29:23 -0700215 .owner = THIS_MODULE,
Roland Stigge3ba37742012-04-20 21:55:29 +0200216 .of_match_table = of_match_ptr(pnx4008_wdt_match),
Vitaly Wool9325fa32006-06-26 19:31:49 +0400217 },
218 .probe = pnx4008_wdt_probe,
Bill Pemberton82268712012-11-19 13:21:12 -0500219 .remove = pnx4008_wdt_remove,
Vitaly Wool9325fa32006-06-26 19:31:49 +0400220};
221
Axel Linb8ec6112011-11-29 13:56:27 +0800222module_platform_driver(platform_wdt_driver);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400223
224MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100225MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
Vitaly Wool9325fa32006-06-26 19:31:49 +0400226MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
227
Wolfram Sang6b1e8382012-02-02 18:48:11 +0100228module_param(heartbeat, uint, 0);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400229MODULE_PARM_DESC(heartbeat,
230 "Watchdog heartbeat period in seconds from 1 to "
231 __MODULE_STRING(MAX_HEARTBEAT) ", default "
232 __MODULE_STRING(DEFAULT_HEARTBEAT));
233
Wim Van Sebroeck86a1e182012-03-05 16:51:11 +0100234module_param(nowayout, bool, 0);
Vitaly Wool9325fa32006-06-26 19:31:49 +0400235MODULE_PARM_DESC(nowayout,
236 "Set to 1 to keep watchdog running after device release");
237
238MODULE_LICENSE("GPL");
239MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Russell King1508c992009-11-20 13:07:57 +0000240MODULE_ALIAS("platform:pnx4008-watchdog");