blob: f48e54006518e9929cbae1c2af2cf135a4edaa13 [file] [log] [blame]
Linus Walleij61f135b2009-11-19 19:49:17 +01001/*
2 * driver/dma/coh901318.c
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
8 */
9
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/kernel.h> /* printk() */
13#include <linux/fs.h> /* everything... */
14#include <linux/slab.h> /* kmalloc() */
15#include <linux/dmaengine.h>
16#include <linux/platform_device.h>
17#include <linux/device.h>
18#include <linux/irqreturn.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/uaccess.h>
22#include <linux/debugfs.h>
23#include <mach/coh901318.h>
24
25#include "coh901318_lli.h"
26
27#define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
28
29#ifdef VERBOSE_DEBUG
30#define COH_DBG(x) ({ if (1) x; 0; })
31#else
32#define COH_DBG(x) ({ if (0) x; 0; })
33#endif
34
35struct coh901318_desc {
36 struct dma_async_tx_descriptor desc;
37 struct list_head node;
38 struct scatterlist *sg;
39 unsigned int sg_len;
Linus Walleijcecd87d2010-03-04 14:31:47 +010040 struct coh901318_lli *lli;
Linus Walleij61f135b2009-11-19 19:49:17 +010041 enum dma_data_direction dir;
Linus Walleij61f135b2009-11-19 19:49:17 +010042 unsigned long flags;
43};
44
45struct coh901318_base {
46 struct device *dev;
47 void __iomem *virtbase;
48 struct coh901318_pool pool;
49 struct powersave pm;
50 struct dma_device dma_slave;
51 struct dma_device dma_memcpy;
52 struct coh901318_chan *chans;
53 struct coh901318_platform *platform;
54};
55
56struct coh901318_chan {
57 spinlock_t lock;
58 int allocated;
59 int completed;
60 int id;
61 int stopped;
62
63 struct work_struct free_work;
64 struct dma_chan chan;
65
66 struct tasklet_struct tasklet;
67
68 struct list_head active;
69 struct list_head queue;
70 struct list_head free;
71
72 unsigned long nbr_active_done;
73 unsigned long busy;
Linus Walleij61f135b2009-11-19 19:49:17 +010074
Linus Walleij128f9042010-08-04 13:37:53 +020075 u32 runtime_addr;
76 u32 runtime_ctrl;
77
Linus Walleij61f135b2009-11-19 19:49:17 +010078 struct coh901318_base *base;
79};
80
81static void coh901318_list_print(struct coh901318_chan *cohc,
82 struct coh901318_lli *lli)
83{
Linus Walleij848ad122010-03-02 14:17:15 -070084 struct coh901318_lli *l = lli;
Linus Walleij61f135b2009-11-19 19:49:17 +010085 int i = 0;
86
Linus Walleij848ad122010-03-02 14:17:15 -070087 while (l) {
Linus Walleij61f135b2009-11-19 19:49:17 +010088 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
Linus Walleij848ad122010-03-02 14:17:15 -070089 ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
Linus Walleij61f135b2009-11-19 19:49:17 +010090 i, l, l->control, l->src_addr, l->dst_addr,
Linus Walleij848ad122010-03-02 14:17:15 -070091 l->link_addr, l->virt_link_addr);
Linus Walleij61f135b2009-11-19 19:49:17 +010092 i++;
Linus Walleij848ad122010-03-02 14:17:15 -070093 l = l->virt_link_addr;
Linus Walleij61f135b2009-11-19 19:49:17 +010094 }
95}
96
97#ifdef CONFIG_DEBUG_FS
98
99#define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
100
101static struct coh901318_base *debugfs_dma_base;
102static struct dentry *dma_dentry;
103
104static int coh901318_debugfs_open(struct inode *inode, struct file *file)
105{
106
107 file->private_data = inode->i_private;
108 return 0;
109}
110
111static int coh901318_debugfs_read(struct file *file, char __user *buf,
112 size_t count, loff_t *f_pos)
113{
114 u64 started_channels = debugfs_dma_base->pm.started_channels;
115 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
116 int i;
117 int ret = 0;
118 char *dev_buf;
119 char *tmp;
120 int dev_size;
121
122 dev_buf = kmalloc(4*1024, GFP_KERNEL);
123 if (dev_buf == NULL)
124 goto err_kmalloc;
125 tmp = dev_buf;
126
Linus Walleij848ad122010-03-02 14:17:15 -0700127 tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
Linus Walleij61f135b2009-11-19 19:49:17 +0100128
129 for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
130 if (started_channels & (1 << i))
131 tmp += sprintf(tmp, "channel %d\n", i);
132
133 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
134 dev_size = tmp - dev_buf;
135
136 /* No more to read if offset != 0 */
137 if (*f_pos > dev_size)
138 goto out;
139
140 if (count > dev_size - *f_pos)
141 count = dev_size - *f_pos;
142
143 if (copy_to_user(buf, dev_buf + *f_pos, count))
144 ret = -EINVAL;
145 ret = count;
146 *f_pos += count;
147
148 out:
149 kfree(dev_buf);
150 return ret;
151
152 err_kmalloc:
153 return 0;
154}
155
156static const struct file_operations coh901318_debugfs_status_operations = {
157 .owner = THIS_MODULE,
158 .open = coh901318_debugfs_open,
159 .read = coh901318_debugfs_read,
Arnd Bergmann6038f372010-08-15 18:52:59 +0200160 .llseek = default_llseek,
Linus Walleij61f135b2009-11-19 19:49:17 +0100161};
162
163
164static int __init init_coh901318_debugfs(void)
165{
166
167 dma_dentry = debugfs_create_dir("dma", NULL);
168
169 (void) debugfs_create_file("status",
170 S_IFREG | S_IRUGO,
171 dma_dentry, NULL,
172 &coh901318_debugfs_status_operations);
173 return 0;
174}
175
176static void __exit exit_coh901318_debugfs(void)
177{
178 debugfs_remove_recursive(dma_dentry);
179}
180
181module_init(init_coh901318_debugfs);
182module_exit(exit_coh901318_debugfs);
183#else
184
185#define COH901318_DEBUGFS_ASSIGN(x, y)
186
187#endif /* CONFIG_DEBUG_FS */
188
189static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
190{
191 return container_of(chan, struct coh901318_chan, chan);
192}
193
194static inline dma_addr_t
195cohc_dev_addr(struct coh901318_chan *cohc)
196{
Linus Walleij128f9042010-08-04 13:37:53 +0200197 /* Runtime supplied address will take precedence */
198 if (cohc->runtime_addr)
199 return cohc->runtime_addr;
Linus Walleij61f135b2009-11-19 19:49:17 +0100200 return cohc->base->platform->chan_conf[cohc->id].dev_addr;
201}
202
203static inline const struct coh901318_params *
204cohc_chan_param(struct coh901318_chan *cohc)
205{
206 return &cohc->base->platform->chan_conf[cohc->id].param;
207}
208
209static inline const struct coh_dma_channel *
210cohc_chan_conf(struct coh901318_chan *cohc)
211{
212 return &cohc->base->platform->chan_conf[cohc->id];
213}
214
215static void enable_powersave(struct coh901318_chan *cohc)
216{
217 unsigned long flags;
218 struct powersave *pm = &cohc->base->pm;
219
220 spin_lock_irqsave(&pm->lock, flags);
221
222 pm->started_channels &= ~(1ULL << cohc->id);
223
224 if (!pm->started_channels) {
225 /* DMA no longer intends to access memory */
226 cohc->base->platform->access_memory_state(cohc->base->dev,
227 false);
228 }
229
230 spin_unlock_irqrestore(&pm->lock, flags);
231}
232static void disable_powersave(struct coh901318_chan *cohc)
233{
234 unsigned long flags;
235 struct powersave *pm = &cohc->base->pm;
236
237 spin_lock_irqsave(&pm->lock, flags);
238
239 if (!pm->started_channels) {
240 /* DMA intends to access memory */
241 cohc->base->platform->access_memory_state(cohc->base->dev,
242 true);
243 }
244
245 pm->started_channels |= (1ULL << cohc->id);
246
247 spin_unlock_irqrestore(&pm->lock, flags);
248}
249
250static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
251{
252 int channel = cohc->id;
253 void __iomem *virtbase = cohc->base->virtbase;
254
255 writel(control,
256 virtbase + COH901318_CX_CTRL +
257 COH901318_CX_CTRL_SPACING * channel);
258 return 0;
259}
260
261static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
262{
263 int channel = cohc->id;
264 void __iomem *virtbase = cohc->base->virtbase;
265
266 writel(conf,
267 virtbase + COH901318_CX_CFG +
268 COH901318_CX_CFG_SPACING*channel);
269 return 0;
270}
271
272
273static int coh901318_start(struct coh901318_chan *cohc)
274{
275 u32 val;
276 int channel = cohc->id;
277 void __iomem *virtbase = cohc->base->virtbase;
278
279 disable_powersave(cohc);
280
281 val = readl(virtbase + COH901318_CX_CFG +
282 COH901318_CX_CFG_SPACING * channel);
283
284 /* Enable channel */
285 val |= COH901318_CX_CFG_CH_ENABLE;
286 writel(val, virtbase + COH901318_CX_CFG +
287 COH901318_CX_CFG_SPACING * channel);
288
289 return 0;
290}
291
292static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
Linus Walleijcecd87d2010-03-04 14:31:47 +0100293 struct coh901318_lli *lli)
Linus Walleij61f135b2009-11-19 19:49:17 +0100294{
295 int channel = cohc->id;
296 void __iomem *virtbase = cohc->base->virtbase;
297
298 BUG_ON(readl(virtbase + COH901318_CX_STAT +
299 COH901318_CX_STAT_SPACING*channel) &
300 COH901318_CX_STAT_ACTIVE);
301
Linus Walleijcecd87d2010-03-04 14:31:47 +0100302 writel(lli->src_addr,
Linus Walleij61f135b2009-11-19 19:49:17 +0100303 virtbase + COH901318_CX_SRC_ADDR +
304 COH901318_CX_SRC_ADDR_SPACING * channel);
305
Linus Walleijcecd87d2010-03-04 14:31:47 +0100306 writel(lli->dst_addr, virtbase +
Linus Walleij61f135b2009-11-19 19:49:17 +0100307 COH901318_CX_DST_ADDR +
308 COH901318_CX_DST_ADDR_SPACING * channel);
309
Linus Walleijcecd87d2010-03-04 14:31:47 +0100310 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
Linus Walleij61f135b2009-11-19 19:49:17 +0100311 COH901318_CX_LNK_ADDR_SPACING * channel);
312
Linus Walleijcecd87d2010-03-04 14:31:47 +0100313 writel(lli->control, virtbase + COH901318_CX_CTRL +
Linus Walleij61f135b2009-11-19 19:49:17 +0100314 COH901318_CX_CTRL_SPACING * channel);
315
316 return 0;
317}
318static dma_cookie_t
319coh901318_assign_cookie(struct coh901318_chan *cohc,
320 struct coh901318_desc *cohd)
321{
322 dma_cookie_t cookie = cohc->chan.cookie;
323
324 if (++cookie < 0)
325 cookie = 1;
326
327 cohc->chan.cookie = cookie;
328 cohd->desc.cookie = cookie;
329
330 return cookie;
331}
332
333static struct coh901318_desc *
334coh901318_desc_get(struct coh901318_chan *cohc)
335{
336 struct coh901318_desc *desc;
337
338 if (list_empty(&cohc->free)) {
339 /* alloc new desc because we're out of used ones
340 * TODO: alloc a pile of descs instead of just one,
341 * avoid many small allocations.
342 */
Linus Walleijb87108a2010-03-02 14:17:20 -0700343 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
Linus Walleij61f135b2009-11-19 19:49:17 +0100344 if (desc == NULL)
345 goto out;
346 INIT_LIST_HEAD(&desc->node);
Linus Walleijb87108a2010-03-02 14:17:20 -0700347 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
Linus Walleij61f135b2009-11-19 19:49:17 +0100348 } else {
349 /* Reuse an old desc. */
350 desc = list_first_entry(&cohc->free,
351 struct coh901318_desc,
352 node);
353 list_del(&desc->node);
Linus Walleijb87108a2010-03-02 14:17:20 -0700354 /* Initialize it a bit so it's not insane */
355 desc->sg = NULL;
356 desc->sg_len = 0;
357 desc->desc.callback = NULL;
358 desc->desc.callback_param = NULL;
Linus Walleij61f135b2009-11-19 19:49:17 +0100359 }
360
361 out:
362 return desc;
363}
364
365static void
366coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
367{
368 list_add_tail(&cohd->node, &cohc->free);
369}
370
371/* call with irq lock held */
372static void
373coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
374{
375 list_add_tail(&desc->node, &cohc->active);
Linus Walleij61f135b2009-11-19 19:49:17 +0100376}
377
378static struct coh901318_desc *
379coh901318_first_active_get(struct coh901318_chan *cohc)
380{
381 struct coh901318_desc *d;
382
383 if (list_empty(&cohc->active))
384 return NULL;
385
386 d = list_first_entry(&cohc->active,
387 struct coh901318_desc,
388 node);
389 return d;
390}
391
392static void
393coh901318_desc_remove(struct coh901318_desc *cohd)
394{
395 list_del(&cohd->node);
396}
397
398static void
399coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
400{
401 list_add_tail(&desc->node, &cohc->queue);
402}
403
404static struct coh901318_desc *
405coh901318_first_queued(struct coh901318_chan *cohc)
406{
407 struct coh901318_desc *d;
408
409 if (list_empty(&cohc->queue))
410 return NULL;
411
412 d = list_first_entry(&cohc->queue,
413 struct coh901318_desc,
414 node);
415 return d;
416}
417
Linus Walleij84c84472010-03-04 14:40:30 +0100418static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
419{
420 struct coh901318_lli *lli = in_lli;
421 u32 bytes = 0;
422
423 while (lli) {
424 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
425 lli = lli->virt_link_addr;
426 }
427 return bytes;
428}
429
Linus Walleij61f135b2009-11-19 19:49:17 +0100430/*
Linus Walleij84c84472010-03-04 14:40:30 +0100431 * Get the number of bytes left to transfer on this channel,
432 * it is unwise to call this before stopping the channel for
433 * absolute measures, but for a rough guess you can still call
434 * it.
Linus Walleij61f135b2009-11-19 19:49:17 +0100435 */
Linus Walleij07934482010-03-26 16:50:49 -0700436static u32 coh901318_get_bytes_left(struct dma_chan *chan)
Linus Walleij61f135b2009-11-19 19:49:17 +0100437{
Linus Walleij61f135b2009-11-19 19:49:17 +0100438 struct coh901318_chan *cohc = to_coh901318_chan(chan);
Linus Walleij84c84472010-03-04 14:40:30 +0100439 struct coh901318_desc *cohd;
440 struct list_head *pos;
441 unsigned long flags;
442 u32 left = 0;
443 int i = 0;
Linus Walleij61f135b2009-11-19 19:49:17 +0100444
445 spin_lock_irqsave(&cohc->lock, flags);
446
Linus Walleij84c84472010-03-04 14:40:30 +0100447 /*
448 * If there are many queued jobs, we iterate and add the
449 * size of them all. We take a special look on the first
450 * job though, since it is probably active.
451 */
452 list_for_each(pos, &cohc->active) {
453 /*
454 * The first job in the list will be working on the
455 * hardware. The job can be stopped but still active,
456 * so that the transfer counter is somewhere inside
457 * the buffer.
458 */
459 cohd = list_entry(pos, struct coh901318_desc, node);
460
461 if (i == 0) {
462 struct coh901318_lli *lli;
463 dma_addr_t ladd;
464
465 /* Read current transfer count value */
466 left = readl(cohc->base->virtbase +
467 COH901318_CX_CTRL +
468 COH901318_CX_CTRL_SPACING * cohc->id) &
469 COH901318_CX_CTRL_TC_VALUE_MASK;
470
471 /* See if the transfer is linked... */
472 ladd = readl(cohc->base->virtbase +
473 COH901318_CX_LNK_ADDR +
474 COH901318_CX_LNK_ADDR_SPACING *
475 cohc->id) &
476 ~COH901318_CX_LNK_LINK_IMMEDIATE;
477 /* Single transaction */
478 if (!ladd)
479 continue;
480
481 /*
482 * Linked transaction, follow the lli, find the
483 * currently processing lli, and proceed to the next
484 */
485 lli = cohd->lli;
486 while (lli && lli->link_addr != ladd)
487 lli = lli->virt_link_addr;
488
489 if (lli)
490 lli = lli->virt_link_addr;
491
492 /*
493 * Follow remaining lli links around to count the total
494 * number of bytes left
495 */
496 left += coh901318_get_bytes_in_lli(lli);
497 } else {
498 left += coh901318_get_bytes_in_lli(cohd->lli);
499 }
500 i++;
501 }
502
503 /* Also count bytes in the queued jobs */
504 list_for_each(pos, &cohc->queue) {
505 cohd = list_entry(pos, struct coh901318_desc, node);
506 left += coh901318_get_bytes_in_lli(cohd->lli);
507 }
Linus Walleij61f135b2009-11-19 19:49:17 +0100508
509 spin_unlock_irqrestore(&cohc->lock, flags);
510
Linus Walleij84c84472010-03-04 14:40:30 +0100511 return left;
Linus Walleij61f135b2009-11-19 19:49:17 +0100512}
Linus Walleij61f135b2009-11-19 19:49:17 +0100513
Linus Walleijc3635c72010-03-26 16:44:01 -0700514/*
515 * Pauses a transfer without losing data. Enables power save.
516 * Use this function in conjunction with coh901318_resume.
517 */
518static void coh901318_pause(struct dma_chan *chan)
Linus Walleij61f135b2009-11-19 19:49:17 +0100519{
520 u32 val;
521 unsigned long flags;
522 struct coh901318_chan *cohc = to_coh901318_chan(chan);
523 int channel = cohc->id;
524 void __iomem *virtbase = cohc->base->virtbase;
525
526 spin_lock_irqsave(&cohc->lock, flags);
527
528 /* Disable channel in HW */
529 val = readl(virtbase + COH901318_CX_CFG +
530 COH901318_CX_CFG_SPACING * channel);
531
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300532 /* Stopping infinite transfer */
Linus Walleij61f135b2009-11-19 19:49:17 +0100533 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
534 (val & COH901318_CX_CFG_CH_ENABLE))
535 cohc->stopped = 1;
536
537
538 val &= ~COH901318_CX_CFG_CH_ENABLE;
539 /* Enable twice, HW bug work around */
540 writel(val, virtbase + COH901318_CX_CFG +
541 COH901318_CX_CFG_SPACING * channel);
542 writel(val, virtbase + COH901318_CX_CFG +
543 COH901318_CX_CFG_SPACING * channel);
544
545 /* Spin-wait for it to actually go inactive */
546 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
547 channel) & COH901318_CX_STAT_ACTIVE)
548 cpu_relax();
549
550 /* Check if we stopped an active job */
551 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
552 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
553 cohc->stopped = 1;
554
555 enable_powersave(cohc);
556
557 spin_unlock_irqrestore(&cohc->lock, flags);
558}
Linus Walleij61f135b2009-11-19 19:49:17 +0100559
Linus Walleijc3635c72010-03-26 16:44:01 -0700560/* Resumes a transfer that has been stopped via 300_dma_stop(..).
Linus Walleij61f135b2009-11-19 19:49:17 +0100561 Power save is handled.
562*/
Linus Walleijc3635c72010-03-26 16:44:01 -0700563static void coh901318_resume(struct dma_chan *chan)
Linus Walleij61f135b2009-11-19 19:49:17 +0100564{
565 u32 val;
566 unsigned long flags;
567 struct coh901318_chan *cohc = to_coh901318_chan(chan);
568 int channel = cohc->id;
569
570 spin_lock_irqsave(&cohc->lock, flags);
571
572 disable_powersave(cohc);
573
574 if (cohc->stopped) {
575 /* Enable channel in HW */
576 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
577 COH901318_CX_CFG_SPACING * channel);
578
579 val |= COH901318_CX_CFG_CH_ENABLE;
580
581 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
582 COH901318_CX_CFG_SPACING*channel);
583
584 cohc->stopped = 0;
585 }
586
587 spin_unlock_irqrestore(&cohc->lock, flags);
588}
Linus Walleij61f135b2009-11-19 19:49:17 +0100589
590bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
591{
592 unsigned int ch_nr = (unsigned int) chan_id;
593
594 if (ch_nr == to_coh901318_chan(chan)->id)
595 return true;
596
597 return false;
598}
599EXPORT_SYMBOL(coh901318_filter_id);
600
601/*
602 * DMA channel allocation
603 */
604static int coh901318_config(struct coh901318_chan *cohc,
605 struct coh901318_params *param)
606{
607 unsigned long flags;
608 const struct coh901318_params *p;
609 int channel = cohc->id;
610 void __iomem *virtbase = cohc->base->virtbase;
611
612 spin_lock_irqsave(&cohc->lock, flags);
613
614 if (param)
615 p = param;
616 else
617 p = &cohc->base->platform->chan_conf[channel].param;
618
619 /* Clear any pending BE or TC interrupt */
620 if (channel < 32) {
621 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
622 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
623 } else {
624 writel(1 << (channel - 32), virtbase +
625 COH901318_BE_INT_CLEAR2);
626 writel(1 << (channel - 32), virtbase +
627 COH901318_TC_INT_CLEAR2);
628 }
629
630 coh901318_set_conf(cohc, p->config);
631 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
632
633 spin_unlock_irqrestore(&cohc->lock, flags);
634
635 return 0;
636}
637
638/* must lock when calling this function
639 * start queued jobs, if any
640 * TODO: start all queued jobs in one go
641 *
642 * Returns descriptor if queued job is started otherwise NULL.
643 * If the queue is empty NULL is returned.
644 */
645static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
646{
Linus Walleijcecd87d2010-03-04 14:31:47 +0100647 struct coh901318_desc *cohd;
Linus Walleij61f135b2009-11-19 19:49:17 +0100648
Linus Walleijcecd87d2010-03-04 14:31:47 +0100649 /*
650 * start queued jobs, if any
Linus Walleij61f135b2009-11-19 19:49:17 +0100651 * TODO: transmit all queued jobs in one go
652 */
Linus Walleijcecd87d2010-03-04 14:31:47 +0100653 cohd = coh901318_first_queued(cohc);
Linus Walleij61f135b2009-11-19 19:49:17 +0100654
Linus Walleijcecd87d2010-03-04 14:31:47 +0100655 if (cohd != NULL) {
Linus Walleij61f135b2009-11-19 19:49:17 +0100656 /* Remove from queue */
Linus Walleijcecd87d2010-03-04 14:31:47 +0100657 coh901318_desc_remove(cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +0100658 /* initiate DMA job */
659 cohc->busy = 1;
660
Linus Walleijcecd87d2010-03-04 14:31:47 +0100661 coh901318_desc_submit(cohc, cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +0100662
Linus Walleijcecd87d2010-03-04 14:31:47 +0100663 coh901318_prep_linked_list(cohc, cohd->lli);
Linus Walleij61f135b2009-11-19 19:49:17 +0100664
Linus Walleijcecd87d2010-03-04 14:31:47 +0100665 /* start dma job on this channel */
Linus Walleij61f135b2009-11-19 19:49:17 +0100666 coh901318_start(cohc);
667
668 }
669
Linus Walleijcecd87d2010-03-04 14:31:47 +0100670 return cohd;
Linus Walleij61f135b2009-11-19 19:49:17 +0100671}
672
Linus Walleij848ad122010-03-02 14:17:15 -0700673/*
674 * This tasklet is called from the interrupt handler to
675 * handle each descriptor (DMA job) that is sent to a channel.
676 */
Linus Walleij61f135b2009-11-19 19:49:17 +0100677static void dma_tasklet(unsigned long data)
678{
679 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
680 struct coh901318_desc *cohd_fin;
681 unsigned long flags;
682 dma_async_tx_callback callback;
683 void *callback_param;
684
Linus Walleij848ad122010-03-02 14:17:15 -0700685 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
686 " nbr_active_done %ld\n", __func__,
687 cohc->id, cohc->nbr_active_done);
688
Linus Walleij61f135b2009-11-19 19:49:17 +0100689 spin_lock_irqsave(&cohc->lock, flags);
690
Linus Walleij848ad122010-03-02 14:17:15 -0700691 /* get first active descriptor entry from list */
Linus Walleij61f135b2009-11-19 19:49:17 +0100692 cohd_fin = coh901318_first_active_get(cohc);
693
Linus Walleij61f135b2009-11-19 19:49:17 +0100694 if (cohd_fin == NULL)
695 goto err;
696
Linus Walleij0b588282010-03-02 14:17:44 -0700697 /* locate callback to client */
Linus Walleij61f135b2009-11-19 19:49:17 +0100698 callback = cohd_fin->desc.callback;
699 callback_param = cohd_fin->desc.callback_param;
700
Linus Walleij0b588282010-03-02 14:17:44 -0700701 /* sign this job as completed on the channel */
702 cohc->completed = cohd_fin->desc.cookie;
Linus Walleij61f135b2009-11-19 19:49:17 +0100703
Linus Walleij0b588282010-03-02 14:17:44 -0700704 /* release the lli allocation and remove the descriptor */
Linus Walleijcecd87d2010-03-04 14:31:47 +0100705 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
Linus Walleij0b588282010-03-02 14:17:44 -0700706
707 /* return desc to free-list */
708 coh901318_desc_remove(cohd_fin);
709 coh901318_desc_free(cohc, cohd_fin);
710
711 spin_unlock_irqrestore(&cohc->lock, flags);
712
713 /* Call the callback when we're done */
714 if (callback)
715 callback(callback_param);
716
717 spin_lock_irqsave(&cohc->lock, flags);
Linus Walleij61f135b2009-11-19 19:49:17 +0100718
Linus Walleij848ad122010-03-02 14:17:15 -0700719 /*
720 * If another interrupt fired while the tasklet was scheduling,
721 * we don't get called twice, so we have this number of active
722 * counter that keep track of the number of IRQs expected to
723 * be handled for this channel. If there happen to be more than
724 * one IRQ to be ack:ed, we simply schedule this tasklet again.
725 */
Linus Walleij0b588282010-03-02 14:17:44 -0700726 cohc->nbr_active_done--;
Linus Walleij61f135b2009-11-19 19:49:17 +0100727 if (cohc->nbr_active_done) {
Linus Walleij848ad122010-03-02 14:17:15 -0700728 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
729 "came in while we were scheduling this tasklet\n");
Linus Walleij61f135b2009-11-19 19:49:17 +0100730 if (cohc_chan_conf(cohc)->priority_high)
731 tasklet_hi_schedule(&cohc->tasklet);
732 else
733 tasklet_schedule(&cohc->tasklet);
734 }
Linus Walleij61f135b2009-11-19 19:49:17 +0100735
Linus Walleij0b588282010-03-02 14:17:44 -0700736 spin_unlock_irqrestore(&cohc->lock, flags);
Linus Walleij61f135b2009-11-19 19:49:17 +0100737
738 return;
739
740 err:
741 spin_unlock_irqrestore(&cohc->lock, flags);
742 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
743}
744
745
746/* called from interrupt context */
747static void dma_tc_handle(struct coh901318_chan *cohc)
748{
Linus Walleijcecd87d2010-03-04 14:31:47 +0100749 /*
750 * If the channel is not allocated, then we shouldn't have
751 * any TC interrupts on it.
752 */
753 if (!cohc->allocated) {
754 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
755 "unallocated channel\n");
Linus Walleij61f135b2009-11-19 19:49:17 +0100756 return;
Linus Walleijcecd87d2010-03-04 14:31:47 +0100757 }
Linus Walleij61f135b2009-11-19 19:49:17 +0100758
Linus Walleij0b588282010-03-02 14:17:44 -0700759 spin_lock(&cohc->lock);
Linus Walleij61f135b2009-11-19 19:49:17 +0100760
Linus Walleijcecd87d2010-03-04 14:31:47 +0100761 /*
762 * When we reach this point, at least one queue item
763 * should have been moved over from cohc->queue to
764 * cohc->active and run to completion, that is why we're
765 * getting a terminal count interrupt is it not?
766 * If you get this BUG() the most probable cause is that
767 * the individual nodes in the lli chain have IRQ enabled,
768 * so check your platform config for lli chain ctrl.
769 */
770 BUG_ON(list_empty(&cohc->active));
771
Linus Walleij61f135b2009-11-19 19:49:17 +0100772 cohc->nbr_active_done++;
773
Linus Walleijcecd87d2010-03-04 14:31:47 +0100774 /*
775 * This attempt to take a job from cohc->queue, put it
776 * into cohc->active and start it.
777 */
Linus Walleij0b588282010-03-02 14:17:44 -0700778 if (coh901318_queue_start(cohc) == NULL)
Linus Walleij61f135b2009-11-19 19:49:17 +0100779 cohc->busy = 0;
780
Linus Walleij0b588282010-03-02 14:17:44 -0700781 spin_unlock(&cohc->lock);
782
Linus Walleijcecd87d2010-03-04 14:31:47 +0100783 /*
784 * This tasklet will remove items from cohc->active
785 * and thus terminates them.
786 */
Linus Walleij61f135b2009-11-19 19:49:17 +0100787 if (cohc_chan_conf(cohc)->priority_high)
788 tasklet_hi_schedule(&cohc->tasklet);
789 else
790 tasklet_schedule(&cohc->tasklet);
791}
792
793
794static irqreturn_t dma_irq_handler(int irq, void *dev_id)
795{
796 u32 status1;
797 u32 status2;
798 int i;
799 int ch;
800 struct coh901318_base *base = dev_id;
801 struct coh901318_chan *cohc;
802 void __iomem *virtbase = base->virtbase;
803
804 status1 = readl(virtbase + COH901318_INT_STATUS1);
805 status2 = readl(virtbase + COH901318_INT_STATUS2);
806
807 if (unlikely(status1 == 0 && status2 == 0)) {
808 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
809 return IRQ_HANDLED;
810 }
811
812 /* TODO: consider handle IRQ in tasklet here to
813 * minimize interrupt latency */
814
815 /* Check the first 32 DMA channels for IRQ */
816 while (status1) {
817 /* Find first bit set, return as a number. */
818 i = ffs(status1) - 1;
819 ch = i;
820
821 cohc = &base->chans[ch];
822 spin_lock(&cohc->lock);
823
824 /* Mask off this bit */
825 status1 &= ~(1 << i);
826 /* Check the individual channel bits */
827 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
828 dev_crit(COHC_2_DEV(cohc),
829 "DMA bus error on channel %d!\n", ch);
830 BUG_ON(1);
831 /* Clear BE interrupt */
832 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
833 } else {
834 /* Caused by TC, really? */
835 if (unlikely(!test_bit(i, virtbase +
836 COH901318_TC_INT_STATUS1))) {
837 dev_warn(COHC_2_DEV(cohc),
838 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
839 /* Clear TC interrupt */
840 BUG_ON(1);
841 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
842 } else {
843 /* Enable powersave if transfer has finished */
844 if (!(readl(virtbase + COH901318_CX_STAT +
845 COH901318_CX_STAT_SPACING*ch) &
846 COH901318_CX_STAT_ENABLED)) {
847 enable_powersave(cohc);
848 }
849
850 /* Must clear TC interrupt before calling
851 * dma_tc_handle
Justin P. Mattockbc0b44c2011-01-28 11:48:18 -0800852 * in case tc_handle initiate a new dma job
Linus Walleij61f135b2009-11-19 19:49:17 +0100853 */
854 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
855
856 dma_tc_handle(cohc);
857 }
858 }
859 spin_unlock(&cohc->lock);
860 }
861
862 /* Check the remaining 32 DMA channels for IRQ */
863 while (status2) {
864 /* Find first bit set, return as a number. */
865 i = ffs(status2) - 1;
866 ch = i + 32;
867 cohc = &base->chans[ch];
868 spin_lock(&cohc->lock);
869
870 /* Mask off this bit */
871 status2 &= ~(1 << i);
872 /* Check the individual channel bits */
873 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
874 dev_crit(COHC_2_DEV(cohc),
875 "DMA bus error on channel %d!\n", ch);
876 /* Clear BE interrupt */
877 BUG_ON(1);
878 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
879 } else {
880 /* Caused by TC, really? */
881 if (unlikely(!test_bit(i, virtbase +
882 COH901318_TC_INT_STATUS2))) {
883 dev_warn(COHC_2_DEV(cohc),
884 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
885 /* Clear TC interrupt */
886 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
887 BUG_ON(1);
888 } else {
889 /* Enable powersave if transfer has finished */
890 if (!(readl(virtbase + COH901318_CX_STAT +
891 COH901318_CX_STAT_SPACING*ch) &
892 COH901318_CX_STAT_ENABLED)) {
893 enable_powersave(cohc);
894 }
895 /* Must clear TC interrupt before calling
896 * dma_tc_handle
Justin P. Mattockbc0b44c2011-01-28 11:48:18 -0800897 * in case tc_handle initiate a new dma job
Linus Walleij61f135b2009-11-19 19:49:17 +0100898 */
899 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
900
901 dma_tc_handle(cohc);
902 }
903 }
904 spin_unlock(&cohc->lock);
905 }
906
907 return IRQ_HANDLED;
908}
909
910static int coh901318_alloc_chan_resources(struct dma_chan *chan)
911{
912 struct coh901318_chan *cohc = to_coh901318_chan(chan);
Linus Walleij84c84472010-03-04 14:40:30 +0100913 unsigned long flags;
Linus Walleij61f135b2009-11-19 19:49:17 +0100914
915 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
916 __func__, cohc->id);
917
918 if (chan->client_count > 1)
919 return -EBUSY;
920
Linus Walleij84c84472010-03-04 14:40:30 +0100921 spin_lock_irqsave(&cohc->lock, flags);
922
Linus Walleij61f135b2009-11-19 19:49:17 +0100923 coh901318_config(cohc, NULL);
924
925 cohc->allocated = 1;
926 cohc->completed = chan->cookie = 1;
927
Linus Walleij84c84472010-03-04 14:40:30 +0100928 spin_unlock_irqrestore(&cohc->lock, flags);
929
Linus Walleij61f135b2009-11-19 19:49:17 +0100930 return 1;
931}
932
933static void
934coh901318_free_chan_resources(struct dma_chan *chan)
935{
936 struct coh901318_chan *cohc = to_coh901318_chan(chan);
937 int channel = cohc->id;
938 unsigned long flags;
939
940 spin_lock_irqsave(&cohc->lock, flags);
941
942 /* Disable HW */
943 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
944 COH901318_CX_CFG_SPACING*channel);
945 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
946 COH901318_CX_CTRL_SPACING*channel);
947
948 cohc->allocated = 0;
949
950 spin_unlock_irqrestore(&cohc->lock, flags);
951
Linus Walleij05827632010-05-17 16:30:42 -0700952 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
Linus Walleij61f135b2009-11-19 19:49:17 +0100953}
954
955
956static dma_cookie_t
957coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
958{
959 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
960 desc);
961 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
962 unsigned long flags;
963
964 spin_lock_irqsave(&cohc->lock, flags);
965
966 tx->cookie = coh901318_assign_cookie(cohc, cohd);
967
968 coh901318_desc_queue(cohc, cohd);
969
970 spin_unlock_irqrestore(&cohc->lock, flags);
971
972 return tx->cookie;
973}
974
975static struct dma_async_tx_descriptor *
976coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
977 size_t size, unsigned long flags)
978{
Linus Walleijcecd87d2010-03-04 14:31:47 +0100979 struct coh901318_lli *lli;
Linus Walleij61f135b2009-11-19 19:49:17 +0100980 struct coh901318_desc *cohd;
981 unsigned long flg;
982 struct coh901318_chan *cohc = to_coh901318_chan(chan);
983 int lli_len;
984 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
Linus Walleijb87108a2010-03-02 14:17:20 -0700985 int ret;
Linus Walleij61f135b2009-11-19 19:49:17 +0100986
987 spin_lock_irqsave(&cohc->lock, flg);
988
989 dev_vdbg(COHC_2_DEV(cohc),
990 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
991 __func__, cohc->id, src, dest, size);
992
993 if (flags & DMA_PREP_INTERRUPT)
994 /* Trigger interrupt after last lli */
995 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
996
997 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
998 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
999 lli_len++;
1000
Linus Walleijcecd87d2010-03-04 14:31:47 +01001001 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
Linus Walleij61f135b2009-11-19 19:49:17 +01001002
Linus Walleijcecd87d2010-03-04 14:31:47 +01001003 if (lli == NULL)
Linus Walleij61f135b2009-11-19 19:49:17 +01001004 goto err;
1005
Linus Walleijb87108a2010-03-02 14:17:20 -07001006 ret = coh901318_lli_fill_memcpy(
Linus Walleijcecd87d2010-03-04 14:31:47 +01001007 &cohc->base->pool, lli, src, size, dest,
Linus Walleijb87108a2010-03-02 14:17:20 -07001008 cohc_chan_param(cohc)->ctrl_lli_chained,
1009 ctrl_last);
1010 if (ret)
1011 goto err;
Linus Walleij61f135b2009-11-19 19:49:17 +01001012
Linus Walleijcecd87d2010-03-04 14:31:47 +01001013 COH_DBG(coh901318_list_print(cohc, lli));
Linus Walleij61f135b2009-11-19 19:49:17 +01001014
Linus Walleijb87108a2010-03-02 14:17:20 -07001015 /* Pick a descriptor to handle this transfer */
1016 cohd = coh901318_desc_get(cohc);
Linus Walleijcecd87d2010-03-04 14:31:47 +01001017 cohd->lli = lli;
Linus Walleijb87108a2010-03-02 14:17:20 -07001018 cohd->flags = flags;
Linus Walleij61f135b2009-11-19 19:49:17 +01001019 cohd->desc.tx_submit = coh901318_tx_submit;
1020
1021 spin_unlock_irqrestore(&cohc->lock, flg);
1022
1023 return &cohd->desc;
1024 err:
1025 spin_unlock_irqrestore(&cohc->lock, flg);
1026 return NULL;
1027}
1028
1029static struct dma_async_tx_descriptor *
1030coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1031 unsigned int sg_len, enum dma_data_direction direction,
1032 unsigned long flags)
1033{
1034 struct coh901318_chan *cohc = to_coh901318_chan(chan);
Linus Walleijcecd87d2010-03-04 14:31:47 +01001035 struct coh901318_lli *lli;
Linus Walleij61f135b2009-11-19 19:49:17 +01001036 struct coh901318_desc *cohd;
Linus Walleij516fd432010-03-02 20:12:46 +01001037 const struct coh901318_params *params;
Linus Walleij61f135b2009-11-19 19:49:17 +01001038 struct scatterlist *sg;
1039 int len = 0;
1040 int size;
1041 int i;
1042 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
1043 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
1044 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
Linus Walleij516fd432010-03-02 20:12:46 +01001045 u32 config;
Linus Walleij61f135b2009-11-19 19:49:17 +01001046 unsigned long flg;
Linus Walleij0b588282010-03-02 14:17:44 -07001047 int ret;
Linus Walleij61f135b2009-11-19 19:49:17 +01001048
1049 if (!sgl)
1050 goto out;
1051 if (sgl->length == 0)
1052 goto out;
1053
1054 spin_lock_irqsave(&cohc->lock, flg);
1055
1056 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
1057 __func__, sg_len, direction);
1058
1059 if (flags & DMA_PREP_INTERRUPT)
1060 /* Trigger interrupt after last lli */
1061 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
1062
Linus Walleij516fd432010-03-02 20:12:46 +01001063 params = cohc_chan_param(cohc);
1064 config = params->config;
Linus Walleij128f9042010-08-04 13:37:53 +02001065 /*
1066 * Add runtime-specific control on top, make
1067 * sure the bits you set per peripheral channel are
1068 * cleared in the default config from the platform.
1069 */
1070 ctrl_chained |= cohc->runtime_ctrl;
1071 ctrl_last |= cohc->runtime_ctrl;
1072 ctrl |= cohc->runtime_ctrl;
Linus Walleij516fd432010-03-02 20:12:46 +01001073
Linus Walleij61f135b2009-11-19 19:49:17 +01001074 if (direction == DMA_TO_DEVICE) {
1075 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1076 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1077
Linus Walleij516fd432010-03-02 20:12:46 +01001078 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
Linus Walleij61f135b2009-11-19 19:49:17 +01001079 ctrl_chained |= tx_flags;
1080 ctrl_last |= tx_flags;
1081 ctrl |= tx_flags;
1082 } else if (direction == DMA_FROM_DEVICE) {
1083 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1084 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1085
Linus Walleij516fd432010-03-02 20:12:46 +01001086 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
Linus Walleij61f135b2009-11-19 19:49:17 +01001087 ctrl_chained |= rx_flags;
1088 ctrl_last |= rx_flags;
1089 ctrl |= rx_flags;
1090 } else
1091 goto err_direction;
1092
Linus Walleij516fd432010-03-02 20:12:46 +01001093 coh901318_set_conf(cohc, config);
1094
Linus Walleij61f135b2009-11-19 19:49:17 +01001095 /* The dma only supports transmitting packages up to
1096 * MAX_DMA_PACKET_SIZE. Calculate to total number of
1097 * dma elemts required to send the entire sg list
1098 */
1099 for_each_sg(sgl, sg, sg_len, i) {
1100 unsigned int factor;
1101 size = sg_dma_len(sg);
1102
1103 if (size <= MAX_DMA_PACKET_SIZE) {
1104 len++;
1105 continue;
1106 }
1107
1108 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1109 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1110 factor++;
1111
1112 len += factor;
1113 }
1114
Linus Walleij848ad122010-03-02 14:17:15 -07001115 pr_debug("Allocate %d lli:s for this transfer\n", len);
Linus Walleijcecd87d2010-03-04 14:31:47 +01001116 lli = coh901318_lli_alloc(&cohc->base->pool, len);
Linus Walleij61f135b2009-11-19 19:49:17 +01001117
Linus Walleijcecd87d2010-03-04 14:31:47 +01001118 if (lli == NULL)
Linus Walleij61f135b2009-11-19 19:49:17 +01001119 goto err_dma_alloc;
1120
Linus Walleijcecd87d2010-03-04 14:31:47 +01001121 /* initiate allocated lli list */
1122 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
Linus Walleij0b588282010-03-02 14:17:44 -07001123 cohc_dev_addr(cohc),
1124 ctrl_chained,
1125 ctrl,
1126 ctrl_last,
1127 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1128 if (ret)
1129 goto err_lli_fill;
Linus Walleij61f135b2009-11-19 19:49:17 +01001130
Linus Walleij128f9042010-08-04 13:37:53 +02001131 /*
1132 * Set the default ctrl for the channel to the one from the lli,
1133 * things may have changed due to odd buffer alignment etc.
1134 */
1135 coh901318_set_ctrl(cohc, lli->control);
1136
Linus Walleijcecd87d2010-03-04 14:31:47 +01001137 COH_DBG(coh901318_list_print(cohc, lli));
Linus Walleij61f135b2009-11-19 19:49:17 +01001138
Linus Walleijb87108a2010-03-02 14:17:20 -07001139 /* Pick a descriptor to handle this transfer */
1140 cohd = coh901318_desc_get(cohc);
1141 cohd->dir = direction;
1142 cohd->flags = flags;
1143 cohd->desc.tx_submit = coh901318_tx_submit;
Linus Walleijcecd87d2010-03-04 14:31:47 +01001144 cohd->lli = lli;
Linus Walleijb87108a2010-03-02 14:17:20 -07001145
Linus Walleij61f135b2009-11-19 19:49:17 +01001146 spin_unlock_irqrestore(&cohc->lock, flg);
1147
1148 return &cohd->desc;
Linus Walleij0b588282010-03-02 14:17:44 -07001149 err_lli_fill:
Linus Walleij61f135b2009-11-19 19:49:17 +01001150 err_dma_alloc:
1151 err_direction:
Linus Walleij61f135b2009-11-19 19:49:17 +01001152 spin_unlock_irqrestore(&cohc->lock, flg);
1153 out:
1154 return NULL;
1155}
1156
1157static enum dma_status
Linus Walleij07934482010-03-26 16:50:49 -07001158coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1159 struct dma_tx_state *txstate)
Linus Walleij61f135b2009-11-19 19:49:17 +01001160{
1161 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1162 dma_cookie_t last_used;
1163 dma_cookie_t last_complete;
1164 int ret;
1165
1166 last_complete = cohc->completed;
1167 last_used = chan->cookie;
1168
1169 ret = dma_async_is_complete(cookie, last_complete, last_used);
1170
Dan Williamsbca34692010-03-26 16:52:10 -07001171 dma_set_tx_state(txstate, last_complete, last_used,
1172 coh901318_get_bytes_left(chan));
Linus Walleij07934482010-03-26 16:50:49 -07001173 if (ret == DMA_IN_PROGRESS && cohc->stopped)
1174 ret = DMA_PAUSED;
Linus Walleij61f135b2009-11-19 19:49:17 +01001175
1176 return ret;
1177}
1178
1179static void
1180coh901318_issue_pending(struct dma_chan *chan)
1181{
1182 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1183 unsigned long flags;
1184
1185 spin_lock_irqsave(&cohc->lock, flags);
1186
Linus Walleijcecd87d2010-03-04 14:31:47 +01001187 /*
1188 * Busy means that pending jobs are already being processed,
1189 * and then there is no point in starting the queue: the
1190 * terminal count interrupt on the channel will take the next
1191 * job on the queue and execute it anyway.
1192 */
Linus Walleij61f135b2009-11-19 19:49:17 +01001193 if (!cohc->busy)
1194 coh901318_queue_start(cohc);
1195
1196 spin_unlock_irqrestore(&cohc->lock, flags);
1197}
1198
Linus Walleij128f9042010-08-04 13:37:53 +02001199/*
1200 * Here we wrap in the runtime dma control interface
1201 */
1202struct burst_table {
1203 int burst_8bit;
1204 int burst_16bit;
1205 int burst_32bit;
1206 u32 reg;
1207};
1208
1209static const struct burst_table burst_sizes[] = {
1210 {
1211 .burst_8bit = 64,
1212 .burst_16bit = 32,
1213 .burst_32bit = 16,
1214 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
1215 },
1216 {
1217 .burst_8bit = 48,
1218 .burst_16bit = 24,
1219 .burst_32bit = 12,
1220 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
1221 },
1222 {
1223 .burst_8bit = 32,
1224 .burst_16bit = 16,
1225 .burst_32bit = 8,
1226 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
1227 },
1228 {
1229 .burst_8bit = 16,
1230 .burst_16bit = 8,
1231 .burst_32bit = 4,
1232 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
1233 },
1234 {
1235 .burst_8bit = 8,
1236 .burst_16bit = 4,
1237 .burst_32bit = 2,
1238 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
1239 },
1240 {
1241 .burst_8bit = 4,
1242 .burst_16bit = 2,
1243 .burst_32bit = 1,
1244 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
1245 },
1246 {
1247 .burst_8bit = 2,
1248 .burst_16bit = 1,
1249 .burst_32bit = 0,
1250 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
1251 },
1252 {
1253 .burst_8bit = 1,
1254 .burst_16bit = 0,
1255 .burst_32bit = 0,
1256 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
1257 },
1258};
1259
1260static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1261 struct dma_slave_config *config)
1262{
1263 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1264 dma_addr_t addr;
1265 enum dma_slave_buswidth addr_width;
1266 u32 maxburst;
1267 u32 runtime_ctrl = 0;
1268 int i = 0;
1269
1270 /* We only support mem to per or per to mem transfers */
1271 if (config->direction == DMA_FROM_DEVICE) {
1272 addr = config->src_addr;
1273 addr_width = config->src_addr_width;
1274 maxburst = config->src_maxburst;
1275 } else if (config->direction == DMA_TO_DEVICE) {
1276 addr = config->dst_addr;
1277 addr_width = config->dst_addr_width;
1278 maxburst = config->dst_maxburst;
1279 } else {
1280 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
1281 return;
1282 }
1283
1284 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
1285 addr_width);
1286 switch (addr_width) {
1287 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1288 runtime_ctrl |=
1289 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
1290 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
1291
1292 while (i < ARRAY_SIZE(burst_sizes)) {
1293 if (burst_sizes[i].burst_8bit <= maxburst)
1294 break;
1295 i++;
1296 }
1297
1298 break;
1299 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1300 runtime_ctrl |=
1301 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
1302 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
1303
1304 while (i < ARRAY_SIZE(burst_sizes)) {
1305 if (burst_sizes[i].burst_16bit <= maxburst)
1306 break;
1307 i++;
1308 }
1309
1310 break;
1311 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1312 /* Direction doesn't matter here, it's 32/32 bits */
1313 runtime_ctrl |=
1314 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1315 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
1316
1317 while (i < ARRAY_SIZE(burst_sizes)) {
1318 if (burst_sizes[i].burst_32bit <= maxburst)
1319 break;
1320 i++;
1321 }
1322
1323 break;
1324 default:
1325 dev_err(COHC_2_DEV(cohc),
1326 "bad runtimeconfig: alien address width\n");
1327 return;
1328 }
1329
1330 runtime_ctrl |= burst_sizes[i].reg;
1331 dev_dbg(COHC_2_DEV(cohc),
1332 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
1333 burst_sizes[i].burst_8bit, addr_width, maxburst);
1334
1335 cohc->runtime_addr = addr;
1336 cohc->runtime_ctrl = runtime_ctrl;
1337}
1338
Linus Walleijc3635c72010-03-26 16:44:01 -07001339static int
Linus Walleij05827632010-05-17 16:30:42 -07001340coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1341 unsigned long arg)
Linus Walleij61f135b2009-11-19 19:49:17 +01001342{
1343 unsigned long flags;
1344 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1345 struct coh901318_desc *cohd;
1346 void __iomem *virtbase = cohc->base->virtbase;
1347
Linus Walleij128f9042010-08-04 13:37:53 +02001348 if (cmd == DMA_SLAVE_CONFIG) {
1349 struct dma_slave_config *config =
1350 (struct dma_slave_config *) arg;
1351
1352 coh901318_dma_set_runtimeconfig(chan, config);
1353 return 0;
1354 }
1355
Linus Walleijc3635c72010-03-26 16:44:01 -07001356 if (cmd == DMA_PAUSE) {
1357 coh901318_pause(chan);
1358 return 0;
1359 }
Linus Walleij61f135b2009-11-19 19:49:17 +01001360
Linus Walleijc3635c72010-03-26 16:44:01 -07001361 if (cmd == DMA_RESUME) {
1362 coh901318_resume(chan);
1363 return 0;
1364 }
1365
1366 if (cmd != DMA_TERMINATE_ALL)
1367 return -ENXIO;
1368
1369 /* The remainder of this function terminates the transfer */
1370 coh901318_pause(chan);
Linus Walleij61f135b2009-11-19 19:49:17 +01001371 spin_lock_irqsave(&cohc->lock, flags);
1372
1373 /* Clear any pending BE or TC interrupt */
1374 if (cohc->id < 32) {
1375 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1376 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1377 } else {
1378 writel(1 << (cohc->id - 32), virtbase +
1379 COH901318_BE_INT_CLEAR2);
1380 writel(1 << (cohc->id - 32), virtbase +
1381 COH901318_TC_INT_CLEAR2);
1382 }
1383
1384 enable_powersave(cohc);
1385
1386 while ((cohd = coh901318_first_active_get(cohc))) {
1387 /* release the lli allocation*/
Linus Walleijcecd87d2010-03-04 14:31:47 +01001388 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
Linus Walleij61f135b2009-11-19 19:49:17 +01001389
Linus Walleij61f135b2009-11-19 19:49:17 +01001390 /* return desc to free-list */
Linus Walleij848ad122010-03-02 14:17:15 -07001391 coh901318_desc_remove(cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +01001392 coh901318_desc_free(cohc, cohd);
1393 }
1394
1395 while ((cohd = coh901318_first_queued(cohc))) {
1396 /* release the lli allocation*/
Linus Walleijcecd87d2010-03-04 14:31:47 +01001397 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
Linus Walleij61f135b2009-11-19 19:49:17 +01001398
Linus Walleij61f135b2009-11-19 19:49:17 +01001399 /* return desc to free-list */
Linus Walleij848ad122010-03-02 14:17:15 -07001400 coh901318_desc_remove(cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +01001401 coh901318_desc_free(cohc, cohd);
1402 }
1403
1404
1405 cohc->nbr_active_done = 0;
1406 cohc->busy = 0;
Linus Walleij61f135b2009-11-19 19:49:17 +01001407
1408 spin_unlock_irqrestore(&cohc->lock, flags);
Linus Walleijc3635c72010-03-26 16:44:01 -07001409
1410 return 0;
Linus Walleij61f135b2009-11-19 19:49:17 +01001411}
Linus Walleij128f9042010-08-04 13:37:53 +02001412
Linus Walleij61f135b2009-11-19 19:49:17 +01001413void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1414 struct coh901318_base *base)
1415{
1416 int chans_i;
1417 int i = 0;
1418 struct coh901318_chan *cohc;
1419
1420 INIT_LIST_HEAD(&dma->channels);
1421
1422 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1423 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1424 cohc = &base->chans[i];
1425
1426 cohc->base = base;
1427 cohc->chan.device = dma;
1428 cohc->id = i;
1429
1430 /* TODO: do we really need this lock if only one
1431 * client is connected to each channel?
1432 */
1433
1434 spin_lock_init(&cohc->lock);
1435
Linus Walleij61f135b2009-11-19 19:49:17 +01001436 cohc->nbr_active_done = 0;
1437 cohc->busy = 0;
1438 INIT_LIST_HEAD(&cohc->free);
1439 INIT_LIST_HEAD(&cohc->active);
1440 INIT_LIST_HEAD(&cohc->queue);
1441
1442 tasklet_init(&cohc->tasklet, dma_tasklet,
1443 (unsigned long) cohc);
1444
1445 list_add_tail(&cohc->chan.device_node,
1446 &dma->channels);
1447 }
1448 }
1449}
1450
1451static int __init coh901318_probe(struct platform_device *pdev)
1452{
1453 int err = 0;
1454 struct coh901318_platform *pdata;
1455 struct coh901318_base *base;
1456 int irq;
1457 struct resource *io;
1458
1459 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1460 if (!io)
1461 goto err_get_resource;
1462
1463 /* Map DMA controller registers to virtual memory */
1464 if (request_mem_region(io->start,
1465 resource_size(io),
1466 pdev->dev.driver->name) == NULL) {
1467 err = -EBUSY;
1468 goto err_request_mem;
1469 }
1470
1471 pdata = pdev->dev.platform_data;
1472 if (!pdata)
1473 goto err_no_platformdata;
1474
1475 base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1476 pdata->max_channels *
1477 sizeof(struct coh901318_chan),
1478 GFP_KERNEL);
1479 if (!base)
1480 goto err_alloc_coh_dma_channels;
1481
1482 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1483
1484 base->virtbase = ioremap(io->start, resource_size(io));
1485 if (!base->virtbase) {
1486 err = -ENOMEM;
1487 goto err_no_ioremap;
1488 }
1489
1490 base->dev = &pdev->dev;
1491 base->platform = pdata;
1492 spin_lock_init(&base->pm.lock);
1493 base->pm.started_channels = 0;
1494
1495 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1496
1497 platform_set_drvdata(pdev, base);
1498
1499 irq = platform_get_irq(pdev, 0);
1500 if (irq < 0)
1501 goto err_no_irq;
1502
1503 err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1504 "coh901318", base);
1505 if (err) {
1506 dev_crit(&pdev->dev,
1507 "Cannot allocate IRQ for DMA controller!\n");
1508 goto err_request_irq;
1509 }
1510
1511 err = coh901318_pool_create(&base->pool, &pdev->dev,
1512 sizeof(struct coh901318_lli),
1513 32);
1514 if (err)
1515 goto err_pool_create;
1516
1517 /* init channels for device transfers */
1518 coh901318_base_init(&base->dma_slave, base->platform->chans_slave,
1519 base);
1520
1521 dma_cap_zero(base->dma_slave.cap_mask);
1522 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1523
1524 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1525 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1526 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
Linus Walleij07934482010-03-26 16:50:49 -07001527 base->dma_slave.device_tx_status = coh901318_tx_status;
Linus Walleij61f135b2009-11-19 19:49:17 +01001528 base->dma_slave.device_issue_pending = coh901318_issue_pending;
Linus Walleijc3635c72010-03-26 16:44:01 -07001529 base->dma_slave.device_control = coh901318_control;
Linus Walleij61f135b2009-11-19 19:49:17 +01001530 base->dma_slave.dev = &pdev->dev;
1531
1532 err = dma_async_device_register(&base->dma_slave);
1533
1534 if (err)
1535 goto err_register_slave;
1536
1537 /* init channels for memcpy */
1538 coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1539 base);
1540
1541 dma_cap_zero(base->dma_memcpy.cap_mask);
1542 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1543
1544 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1545 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1546 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
Linus Walleij07934482010-03-26 16:50:49 -07001547 base->dma_memcpy.device_tx_status = coh901318_tx_status;
Linus Walleij61f135b2009-11-19 19:49:17 +01001548 base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
Linus Walleijc3635c72010-03-26 16:44:01 -07001549 base->dma_memcpy.device_control = coh901318_control;
Linus Walleij61f135b2009-11-19 19:49:17 +01001550 base->dma_memcpy.dev = &pdev->dev;
Linus Walleij516fd432010-03-02 20:12:46 +01001551 /*
1552 * This controller can only access address at even 32bit boundaries,
1553 * i.e. 2^2
1554 */
1555 base->dma_memcpy.copy_align = 2;
Linus Walleij61f135b2009-11-19 19:49:17 +01001556 err = dma_async_device_register(&base->dma_memcpy);
1557
1558 if (err)
1559 goto err_register_memcpy;
1560
Linus Walleij848ad122010-03-02 14:17:15 -07001561 dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
Linus Walleij61f135b2009-11-19 19:49:17 +01001562 (u32) base->virtbase);
1563
1564 return err;
1565
1566 err_register_memcpy:
1567 dma_async_device_unregister(&base->dma_slave);
1568 err_register_slave:
1569 coh901318_pool_destroy(&base->pool);
1570 err_pool_create:
1571 free_irq(platform_get_irq(pdev, 0), base);
1572 err_request_irq:
1573 err_no_irq:
1574 iounmap(base->virtbase);
1575 err_no_ioremap:
1576 kfree(base);
1577 err_alloc_coh_dma_channels:
1578 err_no_platformdata:
1579 release_mem_region(pdev->resource->start,
1580 resource_size(pdev->resource));
1581 err_request_mem:
1582 err_get_resource:
1583 return err;
1584}
1585
1586static int __exit coh901318_remove(struct platform_device *pdev)
1587{
1588 struct coh901318_base *base = platform_get_drvdata(pdev);
1589
1590 dma_async_device_unregister(&base->dma_memcpy);
1591 dma_async_device_unregister(&base->dma_slave);
1592 coh901318_pool_destroy(&base->pool);
1593 free_irq(platform_get_irq(pdev, 0), base);
Linus Walleij61f135b2009-11-19 19:49:17 +01001594 iounmap(base->virtbase);
Julia Lawall0794ec82009-12-22 21:30:59 +01001595 kfree(base);
Linus Walleij61f135b2009-11-19 19:49:17 +01001596 release_mem_region(pdev->resource->start,
1597 resource_size(pdev->resource));
1598 return 0;
1599}
1600
1601
1602static struct platform_driver coh901318_driver = {
1603 .remove = __exit_p(coh901318_remove),
1604 .driver = {
1605 .name = "coh901318",
1606 },
1607};
1608
1609int __init coh901318_init(void)
1610{
1611 return platform_driver_probe(&coh901318_driver, coh901318_probe);
1612}
Linus Walleij964dc252010-10-21 21:04:38 +02001613arch_initcall(coh901318_init);
Linus Walleij61f135b2009-11-19 19:49:17 +01001614
1615void __exit coh901318_exit(void)
1616{
1617 platform_driver_unregister(&coh901318_driver);
1618}
1619module_exit(coh901318_exit);
1620
1621MODULE_LICENSE("GPL");
1622MODULE_AUTHOR("Per Friden");