Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 1 | /* |
| 2 | * au1550_spi.c - au1550 psc spi controller driver |
| 3 | * may work also with au1200, au1210, au1250 |
| 4 | * will not work on au1000, au1100 and au1500 (no full spi controller there) |
| 5 | * |
| 6 | * Copyright (c) 2006 ATRON electronic GmbH |
| 7 | * Author: Jan Nikitenko <jan.nikitenko@gmail.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/interrupt.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 26 | #include <linux/slab.h> |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 27 | #include <linux/errno.h> |
| 28 | #include <linux/device.h> |
| 29 | #include <linux/platform_device.h> |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 30 | #include <linux/resource.h> |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 31 | #include <linux/spi/spi.h> |
| 32 | #include <linux/spi/spi_bitbang.h> |
| 33 | #include <linux/dma-mapping.h> |
| 34 | #include <linux/completion.h> |
| 35 | #include <asm/mach-au1x00/au1000.h> |
| 36 | #include <asm/mach-au1x00/au1xxx_psc.h> |
| 37 | #include <asm/mach-au1x00/au1xxx_dbdma.h> |
| 38 | |
| 39 | #include <asm/mach-au1x00/au1550_spi.h> |
| 40 | |
| 41 | static unsigned usedma = 1; |
| 42 | module_param(usedma, uint, 0644); |
| 43 | |
| 44 | /* |
| 45 | #define AU1550_SPI_DEBUG_LOOPBACK |
| 46 | */ |
| 47 | |
| 48 | |
| 49 | #define AU1550_SPI_DBDMA_DESCRIPTORS 1 |
| 50 | #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U |
| 51 | |
| 52 | struct au1550_spi { |
| 53 | struct spi_bitbang bitbang; |
| 54 | |
| 55 | volatile psc_spi_t __iomem *regs; |
| 56 | int irq; |
| 57 | unsigned freq_max; |
| 58 | unsigned freq_min; |
| 59 | |
| 60 | unsigned len; |
| 61 | unsigned tx_count; |
| 62 | unsigned rx_count; |
| 63 | const u8 *tx; |
| 64 | u8 *rx; |
| 65 | |
| 66 | void (*rx_word)(struct au1550_spi *hw); |
| 67 | void (*tx_word)(struct au1550_spi *hw); |
| 68 | int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t); |
| 69 | irqreturn_t (*irq_callback)(struct au1550_spi *hw); |
| 70 | |
| 71 | struct completion master_done; |
| 72 | |
| 73 | unsigned usedma; |
| 74 | u32 dma_tx_id; |
| 75 | u32 dma_rx_id; |
| 76 | u32 dma_tx_ch; |
| 77 | u32 dma_rx_ch; |
| 78 | |
| 79 | u8 *dma_rx_tmpbuf; |
| 80 | unsigned dma_rx_tmpbuf_size; |
| 81 | u32 dma_rx_tmpbuf_addr; |
| 82 | |
| 83 | struct spi_master *master; |
| 84 | struct device *dev; |
| 85 | struct au1550_spi_info *pdata; |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 86 | struct resource *ioarea; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 87 | }; |
| 88 | |
| 89 | |
| 90 | /* we use an 8-bit memory device for dma transfers to/from spi fifo */ |
| 91 | static dbdev_tab_t au1550_spi_mem_dbdev = |
| 92 | { |
| 93 | .dev_id = DBDMA_MEM_CHAN, |
| 94 | .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC, |
| 95 | .dev_tsize = 0, |
| 96 | .dev_devwidth = 8, |
| 97 | .dev_physaddr = 0x00000000, |
| 98 | .dev_intlevel = 0, |
| 99 | .dev_intpolarity = 0 |
| 100 | }; |
| 101 | |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 102 | static int ddma_memid; /* id to above mem dma device */ |
| 103 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 104 | static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw); |
| 105 | |
| 106 | |
Jan Nikitenko | 40369e1 | 2008-03-13 12:32:38 -0700 | [diff] [blame] | 107 | /* |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 108 | * compute BRG and DIV bits to setup spi clock based on main input clock rate |
| 109 | * that was specified in platform data structure |
| 110 | * according to au1550 datasheet: |
| 111 | * psc_tempclk = psc_mainclk / (2 << DIV) |
| 112 | * spiclk = psc_tempclk / (2 * (BRG + 1)) |
| 113 | * BRG valid range is 4..63 |
| 114 | * DIV valid range is 0..3 |
| 115 | */ |
| 116 | static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz) |
| 117 | { |
| 118 | u32 mainclk_hz = hw->pdata->mainclk_hz; |
| 119 | u32 div, brg; |
| 120 | |
| 121 | for (div = 0; div < 4; div++) { |
| 122 | brg = mainclk_hz / speed_hz / (4 << div); |
| 123 | /* now we have BRG+1 in brg, so count with that */ |
| 124 | if (brg < (4 + 1)) { |
| 125 | brg = (4 + 1); /* speed_hz too big */ |
| 126 | break; /* set lowest brg (div is == 0) */ |
| 127 | } |
| 128 | if (brg <= (63 + 1)) |
| 129 | break; /* we have valid brg and div */ |
| 130 | } |
| 131 | if (div == 4) { |
| 132 | div = 3; /* speed_hz too small */ |
| 133 | brg = (63 + 1); /* set highest brg and div */ |
| 134 | } |
| 135 | brg--; |
| 136 | return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div); |
| 137 | } |
| 138 | |
| 139 | static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw) |
| 140 | { |
| 141 | hw->regs->psc_spimsk = |
| 142 | PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO |
| 143 | | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO |
| 144 | | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD; |
| 145 | au_sync(); |
| 146 | |
| 147 | hw->regs->psc_spievent = |
| 148 | PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO |
| 149 | | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO |
| 150 | | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD; |
| 151 | au_sync(); |
| 152 | } |
| 153 | |
| 154 | static void au1550_spi_reset_fifos(struct au1550_spi *hw) |
| 155 | { |
| 156 | u32 pcr; |
| 157 | |
| 158 | hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC; |
| 159 | au_sync(); |
| 160 | do { |
| 161 | pcr = hw->regs->psc_spipcr; |
| 162 | au_sync(); |
| 163 | } while (pcr != 0); |
| 164 | } |
| 165 | |
| 166 | /* |
| 167 | * dma transfers are used for the most common spi word size of 8-bits |
| 168 | * we cannot easily change already set up dma channels' width, so if we wanted |
| 169 | * dma support for more than 8-bit words (up to 24 bits), we would need to |
| 170 | * setup dma channels from scratch on each spi transfer, based on bits_per_word |
| 171 | * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits |
| 172 | * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode |
| 173 | * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set() |
| 174 | */ |
| 175 | static void au1550_spi_chipsel(struct spi_device *spi, int value) |
| 176 | { |
| 177 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); |
| 178 | unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; |
| 179 | u32 cfg, stat; |
| 180 | |
| 181 | switch (value) { |
| 182 | case BITBANG_CS_INACTIVE: |
| 183 | if (hw->pdata->deactivate_cs) |
| 184 | hw->pdata->deactivate_cs(hw->pdata, spi->chip_select, |
| 185 | cspol); |
| 186 | break; |
| 187 | |
| 188 | case BITBANG_CS_ACTIVE: |
| 189 | au1550_spi_bits_handlers_set(hw, spi->bits_per_word); |
| 190 | |
| 191 | cfg = hw->regs->psc_spicfg; |
| 192 | au_sync(); |
| 193 | hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; |
| 194 | au_sync(); |
| 195 | |
| 196 | if (spi->mode & SPI_CPOL) |
| 197 | cfg |= PSC_SPICFG_BI; |
| 198 | else |
| 199 | cfg &= ~PSC_SPICFG_BI; |
| 200 | if (spi->mode & SPI_CPHA) |
| 201 | cfg &= ~PSC_SPICFG_CDE; |
| 202 | else |
| 203 | cfg |= PSC_SPICFG_CDE; |
| 204 | |
| 205 | if (spi->mode & SPI_LSB_FIRST) |
| 206 | cfg |= PSC_SPICFG_MLF; |
| 207 | else |
| 208 | cfg &= ~PSC_SPICFG_MLF; |
| 209 | |
| 210 | if (hw->usedma && spi->bits_per_word <= 8) |
| 211 | cfg &= ~PSC_SPICFG_DD_DISABLE; |
| 212 | else |
| 213 | cfg |= PSC_SPICFG_DD_DISABLE; |
| 214 | cfg = PSC_SPICFG_CLR_LEN(cfg); |
| 215 | cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word); |
| 216 | |
| 217 | cfg = PSC_SPICFG_CLR_BAUD(cfg); |
| 218 | cfg &= ~PSC_SPICFG_SET_DIV(3); |
| 219 | cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz); |
| 220 | |
| 221 | hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE; |
| 222 | au_sync(); |
| 223 | do { |
| 224 | stat = hw->regs->psc_spistat; |
| 225 | au_sync(); |
| 226 | } while ((stat & PSC_SPISTAT_DR) == 0); |
| 227 | |
| 228 | if (hw->pdata->activate_cs) |
| 229 | hw->pdata->activate_cs(hw->pdata, spi->chip_select, |
| 230 | cspol); |
| 231 | break; |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t) |
| 236 | { |
| 237 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); |
| 238 | unsigned bpw, hz; |
| 239 | u32 cfg, stat; |
| 240 | |
Jan Nikitenko | 04ba24b | 2009-12-07 12:50:30 +0000 | [diff] [blame] | 241 | bpw = spi->bits_per_word; |
| 242 | hz = spi->max_speed_hz; |
| 243 | if (t) { |
| 244 | if (t->bits_per_word) |
| 245 | bpw = t->bits_per_word; |
| 246 | if (t->speed_hz) |
| 247 | hz = t->speed_hz; |
| 248 | } |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 249 | |
| 250 | if (bpw < 4 || bpw > 24) { |
| 251 | dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n", |
| 252 | bpw); |
| 253 | return -EINVAL; |
| 254 | } |
| 255 | if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) { |
| 256 | dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n", |
| 257 | hz); |
| 258 | return -EINVAL; |
| 259 | } |
| 260 | |
| 261 | au1550_spi_bits_handlers_set(hw, spi->bits_per_word); |
| 262 | |
| 263 | cfg = hw->regs->psc_spicfg; |
| 264 | au_sync(); |
| 265 | hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; |
| 266 | au_sync(); |
| 267 | |
| 268 | if (hw->usedma && bpw <= 8) |
| 269 | cfg &= ~PSC_SPICFG_DD_DISABLE; |
| 270 | else |
| 271 | cfg |= PSC_SPICFG_DD_DISABLE; |
| 272 | cfg = PSC_SPICFG_CLR_LEN(cfg); |
| 273 | cfg |= PSC_SPICFG_SET_LEN(bpw); |
| 274 | |
| 275 | cfg = PSC_SPICFG_CLR_BAUD(cfg); |
| 276 | cfg &= ~PSC_SPICFG_SET_DIV(3); |
| 277 | cfg |= au1550_spi_baudcfg(hw, hz); |
| 278 | |
| 279 | hw->regs->psc_spicfg = cfg; |
| 280 | au_sync(); |
| 281 | |
| 282 | if (cfg & PSC_SPICFG_DE_ENABLE) { |
| 283 | do { |
| 284 | stat = hw->regs->psc_spistat; |
| 285 | au_sync(); |
| 286 | } while ((stat & PSC_SPISTAT_DR) == 0); |
| 287 | } |
| 288 | |
| 289 | au1550_spi_reset_fifos(hw); |
| 290 | au1550_spi_mask_ack_all(hw); |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | static int au1550_spi_setup(struct spi_device *spi) |
| 295 | { |
| 296 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); |
| 297 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 298 | if (spi->bits_per_word < 4 || spi->bits_per_word > 24) { |
| 299 | dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n", |
| 300 | spi->bits_per_word); |
| 301 | return -EINVAL; |
| 302 | } |
| 303 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 304 | if (spi->max_speed_hz == 0) |
| 305 | spi->max_speed_hz = hw->freq_max; |
| 306 | if (spi->max_speed_hz > hw->freq_max |
| 307 | || spi->max_speed_hz < hw->freq_min) |
| 308 | return -EINVAL; |
| 309 | /* |
| 310 | * NOTE: cannot change speed and other hw settings immediately, |
| 311 | * otherwise sharing of spi bus is not possible, |
| 312 | * so do not call setupxfer(spi, NULL) here |
| 313 | */ |
| 314 | return 0; |
| 315 | } |
| 316 | |
| 317 | /* |
| 318 | * for dma spi transfers, we have to setup rx channel, otherwise there is |
| 319 | * no reliable way how to recognize that spi transfer is done |
| 320 | * dma complete callbacks are called before real spi transfer is finished |
| 321 | * and if only tx dma channel is set up (and rx fifo overflow event masked) |
| 322 | * spi master done event irq is not generated unless rx fifo is empty (emptied) |
| 323 | * so we need rx tmp buffer to use for rx dma if user does not provide one |
| 324 | */ |
| 325 | static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size) |
| 326 | { |
| 327 | hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL); |
| 328 | if (!hw->dma_rx_tmpbuf) |
| 329 | return -ENOMEM; |
| 330 | hw->dma_rx_tmpbuf_size = size; |
| 331 | hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf, |
| 332 | size, DMA_FROM_DEVICE); |
FUJITA Tomonori | 8d8bb39 | 2008-07-25 19:44:49 -0700 | [diff] [blame] | 333 | if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) { |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 334 | kfree(hw->dma_rx_tmpbuf); |
| 335 | hw->dma_rx_tmpbuf = 0; |
| 336 | hw->dma_rx_tmpbuf_size = 0; |
| 337 | return -EFAULT; |
| 338 | } |
| 339 | return 0; |
| 340 | } |
| 341 | |
| 342 | static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw) |
| 343 | { |
| 344 | dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr, |
| 345 | hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE); |
| 346 | kfree(hw->dma_rx_tmpbuf); |
| 347 | hw->dma_rx_tmpbuf = 0; |
| 348 | hw->dma_rx_tmpbuf_size = 0; |
| 349 | } |
| 350 | |
| 351 | static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t) |
| 352 | { |
| 353 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); |
| 354 | dma_addr_t dma_tx_addr; |
| 355 | dma_addr_t dma_rx_addr; |
| 356 | u32 res; |
| 357 | |
| 358 | hw->len = t->len; |
| 359 | hw->tx_count = 0; |
| 360 | hw->rx_count = 0; |
| 361 | |
| 362 | hw->tx = t->tx_buf; |
| 363 | hw->rx = t->rx_buf; |
| 364 | dma_tx_addr = t->tx_dma; |
| 365 | dma_rx_addr = t->rx_dma; |
| 366 | |
| 367 | /* |
Jan Nikitenko | 4e253d2 | 2008-12-01 13:13:56 -0800 | [diff] [blame] | 368 | * check if buffers are already dma mapped, map them otherwise: |
| 369 | * - first map the TX buffer, so cache data gets written to memory |
| 370 | * - then map the RX buffer, so that cache entries (with |
| 371 | * soon-to-be-stale data) get removed |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 372 | * use rx buffer in place of tx if tx buffer was not provided |
| 373 | * use temp rx buffer (preallocated or realloc to fit) for rx dma |
| 374 | */ |
Jan Nikitenko | 4e253d2 | 2008-12-01 13:13:56 -0800 | [diff] [blame] | 375 | if (t->tx_buf) { |
| 376 | if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */ |
| 377 | dma_tx_addr = dma_map_single(hw->dev, |
| 378 | (void *)t->tx_buf, |
| 379 | t->len, DMA_TO_DEVICE); |
| 380 | if (dma_mapping_error(hw->dev, dma_tx_addr)) |
| 381 | dev_err(hw->dev, "tx dma map error\n"); |
| 382 | } |
| 383 | } |
| 384 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 385 | if (t->rx_buf) { |
| 386 | if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */ |
| 387 | dma_rx_addr = dma_map_single(hw->dev, |
| 388 | (void *)t->rx_buf, |
| 389 | t->len, DMA_FROM_DEVICE); |
FUJITA Tomonori | 8d8bb39 | 2008-07-25 19:44:49 -0700 | [diff] [blame] | 390 | if (dma_mapping_error(hw->dev, dma_rx_addr)) |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 391 | dev_err(hw->dev, "rx dma map error\n"); |
| 392 | } |
| 393 | } else { |
| 394 | if (t->len > hw->dma_rx_tmpbuf_size) { |
| 395 | int ret; |
| 396 | |
| 397 | au1550_spi_dma_rxtmp_free(hw); |
| 398 | ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len, |
| 399 | AU1550_SPI_DMA_RXTMP_MINSIZE)); |
| 400 | if (ret < 0) |
| 401 | return ret; |
| 402 | } |
| 403 | hw->rx = hw->dma_rx_tmpbuf; |
| 404 | dma_rx_addr = hw->dma_rx_tmpbuf_addr; |
| 405 | dma_sync_single_for_device(hw->dev, dma_rx_addr, |
| 406 | t->len, DMA_FROM_DEVICE); |
| 407 | } |
Jan Nikitenko | 4e253d2 | 2008-12-01 13:13:56 -0800 | [diff] [blame] | 408 | |
| 409 | if (!t->tx_buf) { |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 410 | dma_sync_single_for_device(hw->dev, dma_rx_addr, |
| 411 | t->len, DMA_BIDIRECTIONAL); |
| 412 | hw->tx = hw->rx; |
| 413 | } |
| 414 | |
| 415 | /* put buffers on the ring */ |
Manuel Lauss | 963accb | 2009-10-13 20:22:35 +0200 | [diff] [blame] | 416 | res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx), |
Manuel Lauss | ea071cc | 2009-10-13 20:22:34 +0200 | [diff] [blame] | 417 | t->len, DDMA_FLAGS_IE); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 418 | if (!res) |
| 419 | dev_err(hw->dev, "rx dma put dest error\n"); |
| 420 | |
Manuel Lauss | 963accb | 2009-10-13 20:22:35 +0200 | [diff] [blame] | 421 | res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx), |
Manuel Lauss | ea071cc | 2009-10-13 20:22:34 +0200 | [diff] [blame] | 422 | t->len, DDMA_FLAGS_IE); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 423 | if (!res) |
| 424 | dev_err(hw->dev, "tx dma put source error\n"); |
| 425 | |
| 426 | au1xxx_dbdma_start(hw->dma_rx_ch); |
| 427 | au1xxx_dbdma_start(hw->dma_tx_ch); |
| 428 | |
| 429 | /* by default enable nearly all events interrupt */ |
| 430 | hw->regs->psc_spimsk = PSC_SPIMSK_SD; |
| 431 | au_sync(); |
| 432 | |
| 433 | /* start the transfer */ |
| 434 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; |
| 435 | au_sync(); |
| 436 | |
| 437 | wait_for_completion(&hw->master_done); |
| 438 | |
| 439 | au1xxx_dbdma_stop(hw->dma_tx_ch); |
| 440 | au1xxx_dbdma_stop(hw->dma_rx_ch); |
| 441 | |
| 442 | if (!t->rx_buf) { |
| 443 | /* using the temporal preallocated and premapped buffer */ |
| 444 | dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len, |
| 445 | DMA_FROM_DEVICE); |
| 446 | } |
| 447 | /* unmap buffers if mapped above */ |
| 448 | if (t->rx_buf && t->rx_dma == 0 ) |
| 449 | dma_unmap_single(hw->dev, dma_rx_addr, t->len, |
| 450 | DMA_FROM_DEVICE); |
| 451 | if (t->tx_buf && t->tx_dma == 0 ) |
| 452 | dma_unmap_single(hw->dev, dma_tx_addr, t->len, |
| 453 | DMA_TO_DEVICE); |
| 454 | |
| 455 | return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count; |
| 456 | } |
| 457 | |
| 458 | static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw) |
| 459 | { |
| 460 | u32 stat, evnt; |
| 461 | |
| 462 | stat = hw->regs->psc_spistat; |
| 463 | evnt = hw->regs->psc_spievent; |
| 464 | au_sync(); |
| 465 | if ((stat & PSC_SPISTAT_DI) == 0) { |
| 466 | dev_err(hw->dev, "Unexpected IRQ!\n"); |
| 467 | return IRQ_NONE; |
| 468 | } |
| 469 | |
| 470 | if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO |
| 471 | | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO |
| 472 | | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD)) |
| 473 | != 0) { |
| 474 | /* |
| 475 | * due to an spi error we consider transfer as done, |
| 476 | * so mask all events until before next transfer start |
| 477 | * and stop the possibly running dma immediatelly |
| 478 | */ |
| 479 | au1550_spi_mask_ack_all(hw); |
| 480 | au1xxx_dbdma_stop(hw->dma_rx_ch); |
| 481 | au1xxx_dbdma_stop(hw->dma_tx_ch); |
| 482 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame^] | 483 | /* get number of transferred bytes */ |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 484 | hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch); |
| 485 | hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch); |
| 486 | |
| 487 | au1xxx_dbdma_reset(hw->dma_rx_ch); |
| 488 | au1xxx_dbdma_reset(hw->dma_tx_ch); |
| 489 | au1550_spi_reset_fifos(hw); |
| 490 | |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 491 | if (evnt == PSC_SPIEVNT_RO) |
| 492 | dev_err(hw->dev, |
| 493 | "dma transfer: receive FIFO overflow!\n"); |
| 494 | else |
| 495 | dev_err(hw->dev, |
| 496 | "dma transfer: unexpected SPI error " |
| 497 | "(event=0x%x stat=0x%x)!\n", evnt, stat); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 498 | |
| 499 | complete(&hw->master_done); |
| 500 | return IRQ_HANDLED; |
| 501 | } |
| 502 | |
| 503 | if ((evnt & PSC_SPIEVNT_MD) != 0) { |
| 504 | /* transfer completed successfully */ |
| 505 | au1550_spi_mask_ack_all(hw); |
| 506 | hw->rx_count = hw->len; |
| 507 | hw->tx_count = hw->len; |
| 508 | complete(&hw->master_done); |
| 509 | } |
| 510 | return IRQ_HANDLED; |
| 511 | } |
| 512 | |
| 513 | |
| 514 | /* routines to handle different word sizes in pio mode */ |
| 515 | #define AU1550_SPI_RX_WORD(size, mask) \ |
| 516 | static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \ |
| 517 | { \ |
| 518 | u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \ |
| 519 | au_sync(); \ |
| 520 | if (hw->rx) { \ |
| 521 | *(u##size *)hw->rx = (u##size)fifoword; \ |
| 522 | hw->rx += (size) / 8; \ |
| 523 | } \ |
| 524 | hw->rx_count += (size) / 8; \ |
| 525 | } |
| 526 | |
| 527 | #define AU1550_SPI_TX_WORD(size, mask) \ |
| 528 | static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \ |
| 529 | { \ |
| 530 | u32 fifoword = 0; \ |
| 531 | if (hw->tx) { \ |
| 532 | fifoword = *(u##size *)hw->tx & (u32)(mask); \ |
| 533 | hw->tx += (size) / 8; \ |
| 534 | } \ |
| 535 | hw->tx_count += (size) / 8; \ |
| 536 | if (hw->tx_count >= hw->len) \ |
| 537 | fifoword |= PSC_SPITXRX_LC; \ |
| 538 | hw->regs->psc_spitxrx = fifoword; \ |
| 539 | au_sync(); \ |
| 540 | } |
| 541 | |
| 542 | AU1550_SPI_RX_WORD(8,0xff) |
| 543 | AU1550_SPI_RX_WORD(16,0xffff) |
| 544 | AU1550_SPI_RX_WORD(32,0xffffff) |
| 545 | AU1550_SPI_TX_WORD(8,0xff) |
| 546 | AU1550_SPI_TX_WORD(16,0xffff) |
| 547 | AU1550_SPI_TX_WORD(32,0xffffff) |
| 548 | |
| 549 | static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t) |
| 550 | { |
| 551 | u32 stat, mask; |
| 552 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); |
| 553 | |
| 554 | hw->tx = t->tx_buf; |
| 555 | hw->rx = t->rx_buf; |
| 556 | hw->len = t->len; |
| 557 | hw->tx_count = 0; |
| 558 | hw->rx_count = 0; |
| 559 | |
| 560 | /* by default enable nearly all events after filling tx fifo */ |
| 561 | mask = PSC_SPIMSK_SD; |
| 562 | |
| 563 | /* fill the transmit FIFO */ |
| 564 | while (hw->tx_count < hw->len) { |
| 565 | |
| 566 | hw->tx_word(hw); |
| 567 | |
| 568 | if (hw->tx_count >= hw->len) { |
| 569 | /* mask tx fifo request interrupt as we are done */ |
| 570 | mask |= PSC_SPIMSK_TR; |
| 571 | } |
| 572 | |
| 573 | stat = hw->regs->psc_spistat; |
| 574 | au_sync(); |
| 575 | if (stat & PSC_SPISTAT_TF) |
| 576 | break; |
| 577 | } |
| 578 | |
| 579 | /* enable event interrupts */ |
| 580 | hw->regs->psc_spimsk = mask; |
| 581 | au_sync(); |
| 582 | |
| 583 | /* start the transfer */ |
| 584 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; |
| 585 | au_sync(); |
| 586 | |
| 587 | wait_for_completion(&hw->master_done); |
| 588 | |
| 589 | return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count; |
| 590 | } |
| 591 | |
| 592 | static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) |
| 593 | { |
| 594 | int busy; |
| 595 | u32 stat, evnt; |
| 596 | |
| 597 | stat = hw->regs->psc_spistat; |
| 598 | evnt = hw->regs->psc_spievent; |
| 599 | au_sync(); |
| 600 | if ((stat & PSC_SPISTAT_DI) == 0) { |
| 601 | dev_err(hw->dev, "Unexpected IRQ!\n"); |
| 602 | return IRQ_NONE; |
| 603 | } |
| 604 | |
| 605 | if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO |
| 606 | | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 607 | | PSC_SPIEVNT_SD)) |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 608 | != 0) { |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 609 | /* |
| 610 | * due to an error we consider transfer as done, |
| 611 | * so mask all events until before next transfer start |
| 612 | */ |
| 613 | au1550_spi_mask_ack_all(hw); |
| 614 | au1550_spi_reset_fifos(hw); |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 615 | dev_err(hw->dev, |
| 616 | "pio transfer: unexpected SPI error " |
| 617 | "(event=0x%x stat=0x%x)!\n", evnt, stat); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 618 | complete(&hw->master_done); |
| 619 | return IRQ_HANDLED; |
| 620 | } |
| 621 | |
| 622 | /* |
| 623 | * while there is something to read from rx fifo |
| 624 | * or there is a space to write to tx fifo: |
| 625 | */ |
| 626 | do { |
| 627 | busy = 0; |
| 628 | stat = hw->regs->psc_spistat; |
| 629 | au_sync(); |
| 630 | |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 631 | /* |
| 632 | * Take care to not let the Rx FIFO overflow. |
| 633 | * |
| 634 | * We only write a byte if we have read one at least. Initially, |
| 635 | * the write fifo is full, so we should read from the read fifo |
| 636 | * first. |
| 637 | * In case we miss a word from the read fifo, we should get a |
| 638 | * RO event and should back out. |
| 639 | */ |
| 640 | if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) { |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 641 | hw->rx_word(hw); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 642 | busy = 1; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 643 | |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 644 | if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len) |
| 645 | hw->tx_word(hw); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 646 | } |
| 647 | } while (busy); |
| 648 | |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 649 | hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 650 | au_sync(); |
| 651 | |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 652 | /* |
| 653 | * Restart the SPI transmission in case of a transmit underflow. |
| 654 | * This seems to work despite the notes in the Au1550 data book |
| 655 | * of Figure 8-4 with flowchart for SPI master operation: |
| 656 | * |
| 657 | * """Note 1: An XFR Error Interrupt occurs, unless masked, |
| 658 | * for any of the following events: Tx FIFO Underflow, |
| 659 | * Rx FIFO Overflow, or Multiple-master Error |
| 660 | * Note 2: In case of a Tx Underflow Error, all zeroes are |
| 661 | * transmitted.""" |
| 662 | * |
| 663 | * By simply restarting the spi transfer on Tx Underflow Error, |
| 664 | * we assume that spi transfer was paused instead of zeroes |
| 665 | * transmittion mentioned in the Note 2 of Au1550 data book. |
| 666 | */ |
| 667 | if (evnt & PSC_SPIEVNT_TU) { |
| 668 | hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD; |
| 669 | au_sync(); |
| 670 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; |
| 671 | au_sync(); |
| 672 | } |
| 673 | |
| 674 | if (hw->rx_count >= hw->len) { |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 675 | /* transfer completed successfully */ |
| 676 | au1550_spi_mask_ack_all(hw); |
| 677 | complete(&hw->master_done); |
| 678 | } |
| 679 | return IRQ_HANDLED; |
| 680 | } |
| 681 | |
| 682 | static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) |
| 683 | { |
| 684 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); |
| 685 | return hw->txrx_bufs(spi, t); |
| 686 | } |
| 687 | |
Jan Nikitenko | 40369e1 | 2008-03-13 12:32:38 -0700 | [diff] [blame] | 688 | static irqreturn_t au1550_spi_irq(int irq, void *dev) |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 689 | { |
| 690 | struct au1550_spi *hw = dev; |
| 691 | return hw->irq_callback(hw); |
| 692 | } |
| 693 | |
| 694 | static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw) |
| 695 | { |
| 696 | if (bpw <= 8) { |
| 697 | if (hw->usedma) { |
| 698 | hw->txrx_bufs = &au1550_spi_dma_txrxb; |
| 699 | hw->irq_callback = &au1550_spi_dma_irq_callback; |
| 700 | } else { |
| 701 | hw->rx_word = &au1550_spi_rx_word_8; |
| 702 | hw->tx_word = &au1550_spi_tx_word_8; |
| 703 | hw->txrx_bufs = &au1550_spi_pio_txrxb; |
| 704 | hw->irq_callback = &au1550_spi_pio_irq_callback; |
| 705 | } |
| 706 | } else if (bpw <= 16) { |
| 707 | hw->rx_word = &au1550_spi_rx_word_16; |
| 708 | hw->tx_word = &au1550_spi_tx_word_16; |
| 709 | hw->txrx_bufs = &au1550_spi_pio_txrxb; |
| 710 | hw->irq_callback = &au1550_spi_pio_irq_callback; |
| 711 | } else { |
| 712 | hw->rx_word = &au1550_spi_rx_word_32; |
| 713 | hw->tx_word = &au1550_spi_tx_word_32; |
| 714 | hw->txrx_bufs = &au1550_spi_pio_txrxb; |
| 715 | hw->irq_callback = &au1550_spi_pio_irq_callback; |
| 716 | } |
| 717 | } |
| 718 | |
| 719 | static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) |
| 720 | { |
| 721 | u32 stat, cfg; |
| 722 | |
| 723 | /* set up the PSC for SPI mode */ |
| 724 | hw->regs->psc_ctrl = PSC_CTRL_DISABLE; |
| 725 | au_sync(); |
| 726 | hw->regs->psc_sel = PSC_SEL_PS_SPIMODE; |
| 727 | au_sync(); |
| 728 | |
| 729 | hw->regs->psc_spicfg = 0; |
| 730 | au_sync(); |
| 731 | |
| 732 | hw->regs->psc_ctrl = PSC_CTRL_ENABLE; |
| 733 | au_sync(); |
| 734 | |
| 735 | do { |
| 736 | stat = hw->regs->psc_spistat; |
| 737 | au_sync(); |
| 738 | } while ((stat & PSC_SPISTAT_SR) == 0); |
| 739 | |
| 740 | |
| 741 | cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE; |
| 742 | cfg |= PSC_SPICFG_SET_LEN(8); |
| 743 | cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8; |
| 744 | /* use minimal allowed brg and div values as initial setting: */ |
| 745 | cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0); |
| 746 | |
| 747 | #ifdef AU1550_SPI_DEBUG_LOOPBACK |
| 748 | cfg |= PSC_SPICFG_LB; |
| 749 | #endif |
| 750 | |
| 751 | hw->regs->psc_spicfg = cfg; |
| 752 | au_sync(); |
| 753 | |
| 754 | au1550_spi_mask_ack_all(hw); |
| 755 | |
| 756 | hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE; |
| 757 | au_sync(); |
| 758 | |
| 759 | do { |
| 760 | stat = hw->regs->psc_spistat; |
| 761 | au_sync(); |
| 762 | } while ((stat & PSC_SPISTAT_DR) == 0); |
Jan Nikitenko | bbe48ec | 2008-07-23 21:29:57 -0700 | [diff] [blame] | 763 | |
| 764 | au1550_spi_reset_fifos(hw); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 765 | } |
| 766 | |
| 767 | |
| 768 | static int __init au1550_spi_probe(struct platform_device *pdev) |
| 769 | { |
| 770 | struct au1550_spi *hw; |
| 771 | struct spi_master *master; |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 772 | struct resource *r; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 773 | int err = 0; |
| 774 | |
| 775 | master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi)); |
| 776 | if (master == NULL) { |
| 777 | dev_err(&pdev->dev, "No memory for spi_master\n"); |
| 778 | err = -ENOMEM; |
| 779 | goto err_nomem; |
| 780 | } |
| 781 | |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 782 | /* the spi->mode bits understood by this driver: */ |
| 783 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; |
| 784 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 785 | hw = spi_master_get_devdata(master); |
| 786 | |
| 787 | hw->master = spi_master_get(master); |
| 788 | hw->pdata = pdev->dev.platform_data; |
| 789 | hw->dev = &pdev->dev; |
| 790 | |
| 791 | if (hw->pdata == NULL) { |
| 792 | dev_err(&pdev->dev, "No platform data supplied\n"); |
| 793 | err = -ENOENT; |
| 794 | goto err_no_pdata; |
| 795 | } |
| 796 | |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 797 | r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 798 | if (!r) { |
| 799 | dev_err(&pdev->dev, "no IRQ\n"); |
| 800 | err = -ENODEV; |
| 801 | goto err_no_iores; |
| 802 | } |
| 803 | hw->irq = r->start; |
| 804 | |
| 805 | hw->usedma = 0; |
| 806 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
| 807 | if (r) { |
| 808 | hw->dma_tx_id = r->start; |
| 809 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 810 | if (r) { |
| 811 | hw->dma_rx_id = r->start; |
| 812 | if (usedma && ddma_memid) { |
| 813 | if (pdev->dev.dma_mask == NULL) |
| 814 | dev_warn(&pdev->dev, "no dma mask\n"); |
| 815 | else |
| 816 | hw->usedma = 1; |
| 817 | } |
| 818 | } |
| 819 | } |
| 820 | |
| 821 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 822 | if (!r) { |
| 823 | dev_err(&pdev->dev, "no mmio resource\n"); |
| 824 | err = -ENODEV; |
| 825 | goto err_no_iores; |
| 826 | } |
| 827 | |
| 828 | hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t), |
| 829 | pdev->name); |
| 830 | if (!hw->ioarea) { |
| 831 | dev_err(&pdev->dev, "Cannot reserve iomem region\n"); |
| 832 | err = -ENXIO; |
| 833 | goto err_no_iores; |
| 834 | } |
| 835 | |
| 836 | hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t)); |
| 837 | if (!hw->regs) { |
| 838 | dev_err(&pdev->dev, "cannot ioremap\n"); |
| 839 | err = -ENXIO; |
| 840 | goto err_ioremap; |
| 841 | } |
| 842 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 843 | platform_set_drvdata(pdev, hw); |
| 844 | |
| 845 | init_completion(&hw->master_done); |
| 846 | |
| 847 | hw->bitbang.master = hw->master; |
| 848 | hw->bitbang.setup_transfer = au1550_spi_setupxfer; |
| 849 | hw->bitbang.chipselect = au1550_spi_chipsel; |
| 850 | hw->bitbang.master->setup = au1550_spi_setup; |
| 851 | hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs; |
| 852 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 853 | if (hw->usedma) { |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 854 | hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid, |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 855 | hw->dma_tx_id, NULL, (void *)hw); |
| 856 | if (hw->dma_tx_ch == 0) { |
| 857 | dev_err(&pdev->dev, |
| 858 | "Cannot allocate tx dma channel\n"); |
| 859 | err = -ENXIO; |
| 860 | goto err_no_txdma; |
| 861 | } |
| 862 | au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8); |
| 863 | if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch, |
| 864 | AU1550_SPI_DBDMA_DESCRIPTORS) == 0) { |
| 865 | dev_err(&pdev->dev, |
| 866 | "Cannot allocate tx dma descriptors\n"); |
| 867 | err = -ENXIO; |
| 868 | goto err_no_txdma_descr; |
| 869 | } |
| 870 | |
| 871 | |
| 872 | hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id, |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 873 | ddma_memid, NULL, (void *)hw); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 874 | if (hw->dma_rx_ch == 0) { |
| 875 | dev_err(&pdev->dev, |
| 876 | "Cannot allocate rx dma channel\n"); |
| 877 | err = -ENXIO; |
| 878 | goto err_no_rxdma; |
| 879 | } |
| 880 | au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8); |
| 881 | if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch, |
| 882 | AU1550_SPI_DBDMA_DESCRIPTORS) == 0) { |
| 883 | dev_err(&pdev->dev, |
| 884 | "Cannot allocate rx dma descriptors\n"); |
| 885 | err = -ENXIO; |
| 886 | goto err_no_rxdma_descr; |
| 887 | } |
| 888 | |
| 889 | err = au1550_spi_dma_rxtmp_alloc(hw, |
| 890 | AU1550_SPI_DMA_RXTMP_MINSIZE); |
| 891 | if (err < 0) { |
| 892 | dev_err(&pdev->dev, |
| 893 | "Cannot allocate initial rx dma tmp buffer\n"); |
| 894 | goto err_dma_rxtmp_alloc; |
| 895 | } |
| 896 | } |
| 897 | |
| 898 | au1550_spi_bits_handlers_set(hw, 8); |
| 899 | |
| 900 | err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw); |
| 901 | if (err) { |
| 902 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); |
| 903 | goto err_no_irq; |
| 904 | } |
| 905 | |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 906 | master->bus_num = pdev->id; |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 907 | master->num_chipselect = hw->pdata->num_chipselect; |
| 908 | |
| 909 | /* |
| 910 | * precompute valid range for spi freq - from au1550 datasheet: |
| 911 | * psc_tempclk = psc_mainclk / (2 << DIV) |
| 912 | * spiclk = psc_tempclk / (2 * (BRG + 1)) |
| 913 | * BRG valid range is 4..63 |
| 914 | * DIV valid range is 0..3 |
| 915 | * round the min and max frequencies to values that would still |
| 916 | * produce valid brg and div |
| 917 | */ |
| 918 | { |
| 919 | int min_div = (2 << 0) * (2 * (4 + 1)); |
| 920 | int max_div = (2 << 3) * (2 * (63 + 1)); |
| 921 | hw->freq_max = hw->pdata->mainclk_hz / min_div; |
| 922 | hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1; |
| 923 | } |
| 924 | |
| 925 | au1550_spi_setup_psc_as_spi(hw); |
| 926 | |
| 927 | err = spi_bitbang_start(&hw->bitbang); |
| 928 | if (err) { |
| 929 | dev_err(&pdev->dev, "Failed to register SPI master\n"); |
| 930 | goto err_register; |
| 931 | } |
| 932 | |
| 933 | dev_info(&pdev->dev, |
| 934 | "spi master registered: bus_num=%d num_chipselect=%d\n", |
| 935 | master->bus_num, master->num_chipselect); |
| 936 | |
| 937 | return 0; |
| 938 | |
| 939 | err_register: |
| 940 | free_irq(hw->irq, hw); |
| 941 | |
| 942 | err_no_irq: |
| 943 | au1550_spi_dma_rxtmp_free(hw); |
| 944 | |
| 945 | err_dma_rxtmp_alloc: |
| 946 | err_no_rxdma_descr: |
| 947 | if (hw->usedma) |
| 948 | au1xxx_dbdma_chan_free(hw->dma_rx_ch); |
| 949 | |
| 950 | err_no_rxdma: |
| 951 | err_no_txdma_descr: |
| 952 | if (hw->usedma) |
| 953 | au1xxx_dbdma_chan_free(hw->dma_tx_ch); |
| 954 | |
| 955 | err_no_txdma: |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 956 | iounmap((void __iomem *)hw->regs); |
| 957 | |
| 958 | err_ioremap: |
| 959 | release_resource(hw->ioarea); |
| 960 | kfree(hw->ioarea); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 961 | |
| 962 | err_no_iores: |
| 963 | err_no_pdata: |
| 964 | spi_master_put(hw->master); |
| 965 | |
| 966 | err_nomem: |
| 967 | return err; |
| 968 | } |
| 969 | |
| 970 | static int __exit au1550_spi_remove(struct platform_device *pdev) |
| 971 | { |
| 972 | struct au1550_spi *hw = platform_get_drvdata(pdev); |
| 973 | |
| 974 | dev_info(&pdev->dev, "spi master remove: bus_num=%d\n", |
| 975 | hw->master->bus_num); |
| 976 | |
| 977 | spi_bitbang_stop(&hw->bitbang); |
| 978 | free_irq(hw->irq, hw); |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 979 | iounmap((void __iomem *)hw->regs); |
| 980 | release_resource(hw->ioarea); |
| 981 | kfree(hw->ioarea); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 982 | |
| 983 | if (hw->usedma) { |
| 984 | au1550_spi_dma_rxtmp_free(hw); |
| 985 | au1xxx_dbdma_chan_free(hw->dma_rx_ch); |
| 986 | au1xxx_dbdma_chan_free(hw->dma_tx_ch); |
| 987 | } |
| 988 | |
| 989 | platform_set_drvdata(pdev, NULL); |
| 990 | |
| 991 | spi_master_put(hw->master); |
| 992 | return 0; |
| 993 | } |
| 994 | |
Kay Sievers | 7e38c3c | 2008-04-10 21:29:20 -0700 | [diff] [blame] | 995 | /* work with hotplug and coldplug */ |
| 996 | MODULE_ALIAS("platform:au1550-spi"); |
| 997 | |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 998 | static struct platform_driver au1550_spi_drv = { |
| 999 | .remove = __exit_p(au1550_spi_remove), |
| 1000 | .driver = { |
| 1001 | .name = "au1550-spi", |
| 1002 | .owner = THIS_MODULE, |
| 1003 | }, |
| 1004 | }; |
| 1005 | |
| 1006 | static int __init au1550_spi_init(void) |
| 1007 | { |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 1008 | /* |
| 1009 | * create memory device with 8 bits dev_devwidth |
| 1010 | * needed for proper byte ordering to spi fifo |
| 1011 | */ |
| 1012 | if (usedma) { |
| 1013 | ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev); |
| 1014 | if (!ddma_memid) |
| 1015 | printk(KERN_ERR "au1550-spi: cannot add memory" |
| 1016 | "dbdma device\n"); |
| 1017 | } |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 1018 | return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe); |
| 1019 | } |
| 1020 | module_init(au1550_spi_init); |
| 1021 | |
| 1022 | static void __exit au1550_spi_exit(void) |
| 1023 | { |
Manuel Lauss | 3a93a15 | 2008-07-23 21:29:56 -0700 | [diff] [blame] | 1024 | if (usedma && ddma_memid) |
| 1025 | au1xxx_ddma_del_device(ddma_memid); |
Jan Nikitenko | 63bd235 | 2007-05-08 00:32:25 -0700 | [diff] [blame] | 1026 | platform_driver_unregister(&au1550_spi_drv); |
| 1027 | } |
| 1028 | module_exit(au1550_spi_exit); |
| 1029 | |
| 1030 | MODULE_DESCRIPTION("Au1550 PSC SPI Driver"); |
| 1031 | MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>"); |
| 1032 | MODULE_LICENSE("GPL"); |