blob: c5eea6ae12ca2d0b1643d79cad766ce7d7150467 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
8 * Copyright (C) 2004,2005 by Thiemo Seufer
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00009 * Copyright (C) 2005 Maciej W. Rozycki
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 */
11
12#include <stdarg.h>
13
14#include <linux/config.h>
15#include <linux/mm.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/string.h>
19#include <linux/init.h>
20
21#include <asm/pgtable.h>
22#include <asm/cacheflush.h>
23#include <asm/mmu_context.h>
24#include <asm/inst.h>
25#include <asm/elf.h>
26#include <asm/smp.h>
27#include <asm/war.h>
28
29/* #define DEBUG_TLB */
30
31static __init int __attribute__((unused)) r45k_bvahwbug(void)
32{
33 /* XXX: We should probe for the presence of this bug, but we don't. */
34 return 0;
35}
36
37static __init int __attribute__((unused)) r4k_250MHZhwbug(void)
38{
39 /* XXX: We should probe for the presence of this bug, but we don't. */
40 return 0;
41}
42
43static __init int __attribute__((unused)) bcm1250_m3_war(void)
44{
45 return BCM1250_M3_WAR;
46}
47
48static __init int __attribute__((unused)) r10000_llsc_war(void)
49{
50 return R10000_LLSC_WAR;
51}
52
53/*
54 * A little micro-assembler, intended for TLB refill handler
55 * synthesizing. It is intentionally kept simple, does only support
56 * a subset of instructions, and does not try to hide pipeline effects
57 * like branch delay slots.
58 */
59
60enum fields
61{
62 RS = 0x001,
63 RT = 0x002,
64 RD = 0x004,
65 RE = 0x008,
66 SIMM = 0x010,
67 UIMM = 0x020,
68 BIMM = 0x040,
69 JIMM = 0x080,
70 FUNC = 0x100,
71};
72
73#define OP_MASK 0x2f
74#define OP_SH 26
75#define RS_MASK 0x1f
76#define RS_SH 21
77#define RT_MASK 0x1f
78#define RT_SH 16
79#define RD_MASK 0x1f
80#define RD_SH 11
81#define RE_MASK 0x1f
82#define RE_SH 6
83#define IMM_MASK 0xffff
84#define IMM_SH 0
85#define JIMM_MASK 0x3ffffff
86#define JIMM_SH 0
87#define FUNC_MASK 0x2f
88#define FUNC_SH 0
89
90enum opcode {
91 insn_invalid,
92 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
93 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
94 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +000095 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
Linus Torvalds1da177e2005-04-16 15:20:36 -070096 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
97 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
98 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
99 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi,
100 insn_tlbwr, insn_xor, insn_xori
101};
102
103struct insn {
104 enum opcode opcode;
105 u32 match;
106 enum fields fields;
107};
108
109/* This macro sets the non-variable bits of an instruction. */
110#define M(a, b, c, d, e, f) \
111 ((a) << OP_SH \
112 | (b) << RS_SH \
113 | (c) << RT_SH \
114 | (d) << RD_SH \
115 | (e) << RE_SH \
116 | (f) << FUNC_SH)
117
118static __initdata struct insn insn_table[] = {
119 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM },
120 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD },
121 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD },
122 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM },
123 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM },
124 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM },
125 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM },
126 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM },
127 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM },
128 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM },
129 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM },
130 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM },
131 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD },
132 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD },
133 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD },
134 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE },
135 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE },
136 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE },
137 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD },
139 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 },
140 { insn_j, M(j_op,0,0,0,0,0), JIMM },
141 { insn_jal, M(jal_op,0,0,0,0,0), JIMM },
142 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS },
143 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM },
144 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM },
145 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM },
146 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM },
147 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM },
148 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD },
149 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD },
150 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM },
151 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 },
152 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM },
153 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM },
154 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM },
155 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE },
156 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE },
157 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE },
158 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD },
159 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM },
160 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 },
161 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 },
162 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 },
163 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD },
164 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM },
165 { insn_invalid, 0, 0 }
166};
167
168#undef M
169
170static __init u32 build_rs(u32 arg)
171{
172 if (arg & ~RS_MASK)
173 printk(KERN_WARNING "TLB synthesizer field overflow\n");
174
175 return (arg & RS_MASK) << RS_SH;
176}
177
178static __init u32 build_rt(u32 arg)
179{
180 if (arg & ~RT_MASK)
181 printk(KERN_WARNING "TLB synthesizer field overflow\n");
182
183 return (arg & RT_MASK) << RT_SH;
184}
185
186static __init u32 build_rd(u32 arg)
187{
188 if (arg & ~RD_MASK)
189 printk(KERN_WARNING "TLB synthesizer field overflow\n");
190
191 return (arg & RD_MASK) << RD_SH;
192}
193
194static __init u32 build_re(u32 arg)
195{
196 if (arg & ~RE_MASK)
197 printk(KERN_WARNING "TLB synthesizer field overflow\n");
198
199 return (arg & RE_MASK) << RE_SH;
200}
201
202static __init u32 build_simm(s32 arg)
203{
204 if (arg > 0x7fff || arg < -0x8000)
205 printk(KERN_WARNING "TLB synthesizer field overflow\n");
206
207 return arg & 0xffff;
208}
209
210static __init u32 build_uimm(u32 arg)
211{
212 if (arg & ~IMM_MASK)
213 printk(KERN_WARNING "TLB synthesizer field overflow\n");
214
215 return arg & IMM_MASK;
216}
217
218static __init u32 build_bimm(s32 arg)
219{
220 if (arg > 0x1ffff || arg < -0x20000)
221 printk(KERN_WARNING "TLB synthesizer field overflow\n");
222
223 if (arg & 0x3)
224 printk(KERN_WARNING "Invalid TLB synthesizer branch target\n");
225
226 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
227}
228
229static __init u32 build_jimm(u32 arg)
230{
231 if (arg & ~((JIMM_MASK) << 2))
232 printk(KERN_WARNING "TLB synthesizer field overflow\n");
233
234 return (arg >> 2) & JIMM_MASK;
235}
236
237static __init u32 build_func(u32 arg)
238{
239 if (arg & ~FUNC_MASK)
240 printk(KERN_WARNING "TLB synthesizer field overflow\n");
241
242 return arg & FUNC_MASK;
243}
244
245/*
246 * The order of opcode arguments is implicitly left to right,
247 * starting with RS and ending with FUNC or IMM.
248 */
249static void __init build_insn(u32 **buf, enum opcode opc, ...)
250{
251 struct insn *ip = NULL;
252 unsigned int i;
253 va_list ap;
254 u32 op;
255
256 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
257 if (insn_table[i].opcode == opc) {
258 ip = &insn_table[i];
259 break;
260 }
261
262 if (!ip)
263 panic("Unsupported TLB synthesizer instruction %d", opc);
264
265 op = ip->match;
266 va_start(ap, opc);
267 if (ip->fields & RS) op |= build_rs(va_arg(ap, u32));
268 if (ip->fields & RT) op |= build_rt(va_arg(ap, u32));
269 if (ip->fields & RD) op |= build_rd(va_arg(ap, u32));
270 if (ip->fields & RE) op |= build_re(va_arg(ap, u32));
271 if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32));
272 if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32));
273 if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32));
274 if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32));
275 if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32));
276 va_end(ap);
277
278 **buf = op;
279 (*buf)++;
280}
281
282#define I_u1u2u3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000283 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284 unsigned int b, unsigned int c) \
285 { \
286 build_insn(buf, insn##op, a, b, c); \
287 }
288
289#define I_u2u1u3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000290 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291 unsigned int b, unsigned int c) \
292 { \
293 build_insn(buf, insn##op, b, a, c); \
294 }
295
296#define I_u3u1u2(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000297 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 unsigned int b, unsigned int c) \
299 { \
300 build_insn(buf, insn##op, b, c, a); \
301 }
302
303#define I_u1u2s3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000304 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 unsigned int b, signed int c) \
306 { \
307 build_insn(buf, insn##op, a, b, c); \
308 }
309
310#define I_u2s3u1(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000311 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 signed int b, unsigned int c) \
313 { \
314 build_insn(buf, insn##op, c, a, b); \
315 }
316
317#define I_u2u1s3(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000318 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 unsigned int b, signed int c) \
320 { \
321 build_insn(buf, insn##op, b, a, c); \
322 }
323
324#define I_u1u2(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000325 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326 unsigned int b) \
327 { \
328 build_insn(buf, insn##op, a, b); \
329 }
330
331#define I_u1s2(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000332 static inline void __init i##op(u32 **buf, unsigned int a, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 signed int b) \
334 { \
335 build_insn(buf, insn##op, a, b); \
336 }
337
338#define I_u1(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000339 static inline void __init i##op(u32 **buf, unsigned int a) \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 { \
341 build_insn(buf, insn##op, a); \
342 }
343
344#define I_0(op) \
Ralf Baechle1443e482006-03-08 15:37:26 +0000345 static inline void __init i##op(u32 **buf) \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346 { \
347 build_insn(buf, insn##op); \
348 }
349
350I_u2u1s3(_addiu);
351I_u3u1u2(_addu);
352I_u2u1u3(_andi);
353I_u3u1u2(_and);
354I_u1u2s3(_beq);
355I_u1u2s3(_beql);
356I_u1s2(_bgez);
357I_u1s2(_bgezl);
358I_u1s2(_bltz);
359I_u1s2(_bltzl);
360I_u1u2s3(_bne);
361I_u1u2(_dmfc0);
362I_u1u2(_dmtc0);
363I_u2u1s3(_daddiu);
364I_u3u1u2(_daddu);
365I_u2u1u3(_dsll);
366I_u2u1u3(_dsll32);
367I_u2u1u3(_dsra);
368I_u2u1u3(_dsrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369I_u3u1u2(_dsubu);
370I_0(_eret);
371I_u1(_j);
372I_u1(_jal);
373I_u1(_jr);
374I_u2s3u1(_ld);
375I_u2s3u1(_ll);
376I_u2s3u1(_lld);
377I_u1s2(_lui);
378I_u2s3u1(_lw);
379I_u1u2(_mfc0);
380I_u1u2(_mtc0);
381I_u2u1u3(_ori);
382I_0(_rfe);
383I_u2s3u1(_sc);
384I_u2s3u1(_scd);
385I_u2s3u1(_sd);
386I_u2u1u3(_sll);
387I_u2u1u3(_sra);
388I_u2u1u3(_srl);
389I_u3u1u2(_subu);
390I_u2s3u1(_sw);
391I_0(_tlbp);
392I_0(_tlbwi);
393I_0(_tlbwr);
394I_u3u1u2(_xor)
395I_u2u1u3(_xori);
396
397/*
398 * handling labels
399 */
400
401enum label_id {
402 label_invalid,
403 label_second_part,
404 label_leave,
405 label_vmalloc,
406 label_vmalloc_done,
407 label_tlbw_hazard,
408 label_split,
409 label_nopage_tlbl,
410 label_nopage_tlbs,
411 label_nopage_tlbm,
412 label_smp_pgtable_change,
413 label_r3000_write_probe_fail,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414};
415
416struct label {
417 u32 *addr;
418 enum label_id lab;
419};
420
421static __init void build_label(struct label **lab, u32 *addr,
422 enum label_id l)
423{
424 (*lab)->addr = addr;
425 (*lab)->lab = l;
426 (*lab)++;
427}
428
429#define L_LA(lb) \
430 static inline void l##lb(struct label **lab, u32 *addr) \
431 { \
432 build_label(lab, addr, label##lb); \
433 }
434
435L_LA(_second_part)
436L_LA(_leave)
437L_LA(_vmalloc)
438L_LA(_vmalloc_done)
439L_LA(_tlbw_hazard)
440L_LA(_split)
441L_LA(_nopage_tlbl)
442L_LA(_nopage_tlbs)
443L_LA(_nopage_tlbm)
444L_LA(_smp_pgtable_change)
445L_LA(_r3000_write_probe_fail)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446
447/* convenience macros for instructions */
Ralf Baechle875d43e2005-09-03 15:56:16 -0700448#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449# define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off)
450# define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off)
451# define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh)
452# define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh)
453# define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh)
454# define i_MFC0(buf, rt, rd) i_dmfc0(buf, rt, rd)
455# define i_MTC0(buf, rt, rd) i_dmtc0(buf, rt, rd)
456# define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val)
457# define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd)
458# define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd)
459# define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off)
460# define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off)
461#else
462# define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off)
463# define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off)
464# define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh)
465# define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh)
466# define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh)
467# define i_MFC0(buf, rt, rd) i_mfc0(buf, rt, rd)
468# define i_MTC0(buf, rt, rd) i_mtc0(buf, rt, rd)
469# define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val)
470# define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd)
471# define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd)
472# define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off)
473# define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off)
474#endif
475
476#define i_b(buf, off) i_beq(buf, 0, 0, off)
477#define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off)
478#define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off)
479#define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off)
480#define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off)
481#define i_move(buf, a, b) i_ADDU(buf, a, 0, b)
482#define i_nop(buf) i_sll(buf, 0, 0, 0)
483#define i_ssnop(buf) i_sll(buf, 0, 0, 1)
484#define i_ehb(buf) i_sll(buf, 0, 0, 3)
485
Ralf Baechle875d43e2005-09-03 15:56:16 -0700486#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487static __init int __attribute__((unused)) in_compat_space_p(long addr)
488{
489 /* Is this address in 32bit compat space? */
Ralf Baechle3ef33e62005-07-08 20:10:17 +0000490 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491}
492
493static __init int __attribute__((unused)) rel_highest(long val)
494{
495 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
496}
497
498static __init int __attribute__((unused)) rel_higher(long val)
499{
500 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
501}
502#endif
503
504static __init int rel_hi(long val)
505{
506 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
507}
508
509static __init int rel_lo(long val)
510{
511 return ((val & 0xffff) ^ 0x8000) - 0x8000;
512}
513
514static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
515{
Yoichi Yuasa766160c2005-09-03 15:56:22 -0700516#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517 if (!in_compat_space_p(addr)) {
518 i_lui(buf, rs, rel_highest(addr));
519 if (rel_higher(addr))
520 i_daddiu(buf, rs, rs, rel_higher(addr));
521 if (rel_hi(addr)) {
522 i_dsll(buf, rs, rs, 16);
523 i_daddiu(buf, rs, rs, rel_hi(addr));
524 i_dsll(buf, rs, rs, 16);
525 } else
526 i_dsll32(buf, rs, rs, 0);
527 } else
528#endif
529 i_lui(buf, rs, rel_hi(addr));
530}
531
532static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs,
533 long addr)
534{
535 i_LA_mostly(buf, rs, addr);
536 if (rel_lo(addr))
537 i_ADDIU(buf, rs, rs, rel_lo(addr));
538}
539
540/*
541 * handle relocations
542 */
543
544struct reloc {
545 u32 *addr;
546 unsigned int type;
547 enum label_id lab;
548};
549
550static __init void r_mips_pc16(struct reloc **rel, u32 *addr,
551 enum label_id l)
552{
553 (*rel)->addr = addr;
554 (*rel)->type = R_MIPS_PC16;
555 (*rel)->lab = l;
556 (*rel)++;
557}
558
559static inline void __resolve_relocs(struct reloc *rel, struct label *lab)
560{
561 long laddr = (long)lab->addr;
562 long raddr = (long)rel->addr;
563
564 switch (rel->type) {
565 case R_MIPS_PC16:
566 *rel->addr |= build_bimm(laddr - (raddr + 4));
567 break;
568
569 default:
570 panic("Unsupported TLB synthesizer relocation %d",
571 rel->type);
572 }
573}
574
575static __init void resolve_relocs(struct reloc *rel, struct label *lab)
576{
577 struct label *l;
578
579 for (; rel->lab != label_invalid; rel++)
580 for (l = lab; l->lab != label_invalid; l++)
581 if (rel->lab == l->lab)
582 __resolve_relocs(rel, l);
583}
584
585static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end,
586 long off)
587{
588 for (; rel->lab != label_invalid; rel++)
589 if (rel->addr >= first && rel->addr < end)
590 rel->addr += off;
591}
592
593static __init void move_labels(struct label *lab, u32 *first, u32 *end,
594 long off)
595{
596 for (; lab->lab != label_invalid; lab++)
597 if (lab->addr >= first && lab->addr < end)
598 lab->addr += off;
599}
600
601static __init void copy_handler(struct reloc *rel, struct label *lab,
602 u32 *first, u32 *end, u32 *target)
603{
604 long off = (long)(target - first);
605
606 memcpy(target, first, (end - first) * sizeof(u32));
607
608 move_relocs(rel, first, end, off);
609 move_labels(lab, first, end, off);
610}
611
612static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel,
613 u32 *addr)
614{
615 for (; rel->lab != label_invalid; rel++) {
616 if (rel->addr == addr
617 && (rel->type == R_MIPS_PC16
618 || rel->type == R_MIPS_26))
619 return 1;
620 }
621
622 return 0;
623}
624
625/* convenience functions for labeled branches */
Ralf Baechle1443e482006-03-08 15:37:26 +0000626static void __init __attribute__((unused))
627 il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628{
629 r_mips_pc16(r, *p, l);
630 i_bltz(p, reg, 0);
631}
632
Ralf Baechle1443e482006-03-08 15:37:26 +0000633static void __init __attribute__((unused)) il_b(u32 **p, struct reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 enum label_id l)
635{
636 r_mips_pc16(r, *p, l);
637 i_b(p, 0);
638}
639
Ralf Baechle1443e482006-03-08 15:37:26 +0000640static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 enum label_id l)
642{
643 r_mips_pc16(r, *p, l);
644 i_beqz(p, reg, 0);
645}
646
Ralf Baechle1443e482006-03-08 15:37:26 +0000647static void __init __attribute__((unused))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
649{
650 r_mips_pc16(r, *p, l);
651 i_beqzl(p, reg, 0);
652}
653
Ralf Baechle1443e482006-03-08 15:37:26 +0000654static void __init il_bnez(u32 **p, struct reloc **r, unsigned int reg,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655 enum label_id l)
656{
657 r_mips_pc16(r, *p, l);
658 i_bnez(p, reg, 0);
659}
660
Ralf Baechle1443e482006-03-08 15:37:26 +0000661static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662 enum label_id l)
663{
664 r_mips_pc16(r, *p, l);
665 i_bgezl(p, reg, 0);
666}
667
668/* The only general purpose registers allowed in TLB handlers. */
669#define K0 26
670#define K1 27
671
672/* Some CP0 registers */
673#define C0_INDEX 0
674#define C0_ENTRYLO0 2
675#define C0_ENTRYLO1 3
676#define C0_CONTEXT 4
677#define C0_BADVADDR 8
678#define C0_ENTRYHI 10
679#define C0_EPC 14
680#define C0_XCONTEXT 20
681
Ralf Baechle875d43e2005-09-03 15:56:16 -0700682#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT)
684#else
685# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT)
686#endif
687
688/* The worst case length of the handler is around 18 instructions for
689 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
690 * Maximum space available is 32 instructions for R3000 and 64
691 * instructions for R4000.
692 *
693 * We deliberately chose a buffer size of 128, so we won't scribble
694 * over anything important on overflow before we panic.
695 */
696static __initdata u32 tlb_handler[128];
697
698/* simply assume worst case size for labels and relocs */
699static __initdata struct label labels[128];
700static __initdata struct reloc relocs[128];
701
702/*
703 * The R3000 TLB handler is simple.
704 */
705static void __init build_r3000_tlb_refill_handler(void)
706{
707 long pgdc = (long)pgd_current;
708 u32 *p;
709
710 memset(tlb_handler, 0, sizeof(tlb_handler));
711 p = tlb_handler;
712
713 i_mfc0(&p, K0, C0_BADVADDR);
714 i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */
715 i_lw(&p, K1, rel_lo(pgdc), K1);
716 i_srl(&p, K0, K0, 22); /* load delay */
717 i_sll(&p, K0, K0, 2);
718 i_addu(&p, K1, K1, K0);
719 i_mfc0(&p, K0, C0_CONTEXT);
720 i_lw(&p, K1, 0, K1); /* cp0 delay */
721 i_andi(&p, K0, K0, 0xffc); /* load delay */
722 i_addu(&p, K1, K1, K0);
723 i_lw(&p, K0, 0, K1);
724 i_nop(&p); /* load delay */
725 i_mtc0(&p, K0, C0_ENTRYLO0);
726 i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
727 i_tlbwr(&p); /* cp0 delay */
728 i_jr(&p, K1);
729 i_rfe(&p); /* branch delay */
730
731 if (p > tlb_handler + 32)
732 panic("TLB refill handler space exceeded");
733
Maciej W. Rozycki41986a62005-06-29 10:24:21 +0000734 printk("Synthesized TLB refill handler (%u instructions).\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700735 (unsigned int)(p - tlb_handler));
736#ifdef DEBUG_TLB
737 {
738 int i;
739
740 for (i = 0; i < (p - tlb_handler); i++)
741 printk("%08x\n", tlb_handler[i]);
742 }
743#endif
744
Ralf Baechle91b05e62006-03-29 18:53:00 +0100745 memcpy((void *)ebase, tlb_handler, 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746}
747
748/*
749 * The R4000 TLB handler is much more complicated. We have two
750 * consecutive handler areas with 32 instructions space each.
751 * Since they aren't used at the same time, we can overflow in the
752 * other one.To keep things simple, we first assume linear space,
753 * then we relocate it to the final handler layout as needed.
754 */
755static __initdata u32 final_handler[64];
756
757/*
758 * Hazards
759 *
760 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
761 * 2. A timing hazard exists for the TLBP instruction.
762 *
763 * stalling_instruction
764 * TLBP
765 *
766 * The JTLB is being read for the TLBP throughout the stall generated by the
767 * previous instruction. This is not really correct as the stalling instruction
768 * can modify the address used to access the JTLB. The failure symptom is that
769 * the TLBP instruction will use an address created for the stalling instruction
770 * and not the address held in C0_ENHI and thus report the wrong results.
771 *
772 * The software work-around is to not allow the instruction preceding the TLBP
773 * to stall - make it an NOP or some other instruction guaranteed not to stall.
774 *
775 * Errata 2 will not be fixed. This errata is also on the R5000.
776 *
777 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
778 */
779static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p)
780{
781 switch (current_cpu_data.cputype) {
Thiemo Seuferf5b4d952005-09-09 17:11:50 +0000782 /* Found by experiment: R4600 v2.0 needs this, too. */
783 case CPU_R4600:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784 case CPU_R5000:
785 case CPU_R5000A:
786 case CPU_NEVADA:
787 i_nop(p);
788 i_tlbp(p);
789 break;
790
791 default:
792 i_tlbp(p);
793 break;
794 }
795}
796
797/*
798 * Write random or indexed TLB entry, and care about the hazards from
799 * the preceeding mtc0 and for the following eret.
800 */
801enum tlb_write_entry { tlb_random, tlb_indexed };
802
803static __init void build_tlb_write_entry(u32 **p, struct label **l,
804 struct reloc **r,
805 enum tlb_write_entry wmode)
806{
807 void(*tlbw)(u32 **) = NULL;
808
809 switch (wmode) {
810 case tlb_random: tlbw = i_tlbwr; break;
811 case tlb_indexed: tlbw = i_tlbwi; break;
812 }
813
814 switch (current_cpu_data.cputype) {
815 case CPU_R4000PC:
816 case CPU_R4000SC:
817 case CPU_R4000MC:
818 case CPU_R4400PC:
819 case CPU_R4400SC:
820 case CPU_R4400MC:
821 /*
822 * This branch uses up a mtc0 hazard nop slot and saves
823 * two nops after the tlbw instruction.
824 */
825 il_bgezl(p, r, 0, label_tlbw_hazard);
826 tlbw(p);
827 l_tlbw_hazard(l, *p);
828 i_nop(p);
829 break;
830
831 case CPU_R4600:
832 case CPU_R4700:
833 case CPU_R5000:
834 case CPU_R5000A:
Maciej W. Rozycki2c93e122005-06-30 10:51:01 +0000835 i_nop(p);
836 tlbw(p);
837 i_nop(p);
838 break;
839
840 case CPU_R4300:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841 case CPU_5KC:
842 case CPU_TX49XX:
843 case CPU_AU1000:
844 case CPU_AU1100:
845 case CPU_AU1500:
846 case CPU_AU1550:
Pete Popove3ad1c22005-03-01 06:33:16 +0000847 case CPU_AU1200:
Pete Popovbdf21b12005-07-14 17:47:57 +0000848 case CPU_PR4450:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849 i_nop(p);
850 tlbw(p);
851 break;
852
853 case CPU_R10000:
854 case CPU_R12000:
855 case CPU_4KC:
856 case CPU_SB1:
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700857 case CPU_SB1A:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 case CPU_4KSC:
859 case CPU_20KC:
860 case CPU_25KF:
861 tlbw(p);
862 break;
863
864 case CPU_NEVADA:
865 i_nop(p); /* QED specifies 2 nops hazard */
866 /*
867 * This branch uses up a mtc0 hazard nop slot and saves
868 * a nop after the tlbw instruction.
869 */
870 il_bgezl(p, r, 0, label_tlbw_hazard);
871 tlbw(p);
872 l_tlbw_hazard(l, *p);
873 break;
874
875 case CPU_RM7000:
876 i_nop(p);
877 i_nop(p);
878 i_nop(p);
879 i_nop(p);
880 tlbw(p);
881 break;
882
883 case CPU_4KEC:
884 case CPU_24K:
Ralf Baechlebbc7f222005-07-12 16:12:05 +0000885 case CPU_34K:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886 i_ehb(p);
887 tlbw(p);
888 break;
889
890 case CPU_RM9000:
891 /*
892 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
893 * use of the JTLB for instructions should not occur for 4
894 * cpu cycles and use for data translations should not occur
895 * for 3 cpu cycles.
896 */
897 i_ssnop(p);
898 i_ssnop(p);
899 i_ssnop(p);
900 i_ssnop(p);
901 tlbw(p);
902 i_ssnop(p);
903 i_ssnop(p);
904 i_ssnop(p);
905 i_ssnop(p);
906 break;
907
908 case CPU_VR4111:
909 case CPU_VR4121:
910 case CPU_VR4122:
911 case CPU_VR4181:
912 case CPU_VR4181A:
913 i_nop(p);
914 i_nop(p);
915 tlbw(p);
916 i_nop(p);
917 i_nop(p);
918 break;
919
920 case CPU_VR4131:
921 case CPU_VR4133:
Ralf Baechle7623deb2005-08-29 16:49:55 +0000922 case CPU_R5432:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700923 i_nop(p);
924 i_nop(p);
925 tlbw(p);
926 break;
927
928 default:
929 panic("No TLB refill handler yet (CPU type: %d)",
930 current_cpu_data.cputype);
931 break;
932 }
933}
934
Ralf Baechle875d43e2005-09-03 15:56:16 -0700935#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936/*
937 * TMP and PTR are scratch.
938 * TMP will be clobbered, PTR will hold the pmd entry.
939 */
940static __init void
941build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
942 unsigned int tmp, unsigned int ptr)
943{
944 long pgdc = (long)pgd_current;
945
946 /*
947 * The vmalloc handling is not in the hotpath.
948 */
949 i_dmfc0(p, tmp, C0_BADVADDR);
950 il_bltz(p, r, tmp, label_vmalloc);
951 /* No i_nop needed here, since the next insn doesn't touch TMP. */
952
953#ifdef CONFIG_SMP
954 /*
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +0000955 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956 * stored in CONTEXT.
957 */
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +0000958 i_dmfc0(p, ptr, C0_CONTEXT);
959 i_dsrl(p, ptr, ptr, 23);
960 i_LA_mostly(p, tmp, pgdc);
961 i_daddu(p, ptr, ptr, tmp);
962 i_dmfc0(p, tmp, C0_BADVADDR);
963 i_ld(p, ptr, rel_lo(pgdc), ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964#else
965 i_LA_mostly(p, ptr, pgdc);
966 i_ld(p, ptr, rel_lo(pgdc), ptr);
967#endif
968
969 l_vmalloc_done(l, *p);
970 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */
971 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
972 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
973 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
974 i_ld(p, ptr, 0, ptr); /* get pmd pointer */
975 i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
976 i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
977 i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
978}
979
980/*
981 * BVADDR is the faulting address, PTR is scratch.
982 * PTR will hold the pgd for vmalloc.
983 */
984static __init void
985build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
986 unsigned int bvaddr, unsigned int ptr)
987{
988 long swpd = (long)swapper_pg_dir;
989
990 l_vmalloc(l, *p);
991 i_LA(p, ptr, VMALLOC_START);
992 i_dsubu(p, bvaddr, bvaddr, ptr);
993
994 if (in_compat_space_p(swpd) && !rel_lo(swpd)) {
995 il_b(p, r, label_vmalloc_done);
996 i_lui(p, ptr, rel_hi(swpd));
997 } else {
998 i_LA_mostly(p, ptr, swpd);
999 il_b(p, r, label_vmalloc_done);
1000 i_daddiu(p, ptr, ptr, rel_lo(swpd));
1001 }
1002}
1003
Ralf Baechle875d43e2005-09-03 15:56:16 -07001004#else /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005
1006/*
1007 * TMP and PTR are scratch.
1008 * TMP will be clobbered, PTR will hold the pgd entry.
1009 */
1010static __init void __attribute__((unused))
1011build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1012{
1013 long pgdc = (long)pgd_current;
1014
1015 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
1016#ifdef CONFIG_SMP
1017 i_mfc0(p, ptr, C0_CONTEXT);
1018 i_LA_mostly(p, tmp, pgdc);
1019 i_srl(p, ptr, ptr, 23);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020 i_addu(p, ptr, tmp, ptr);
1021#else
1022 i_LA_mostly(p, ptr, pgdc);
1023#endif
1024 i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
1025 i_lw(p, ptr, rel_lo(pgdc), ptr);
1026 i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
1027 i_sll(p, tmp, tmp, PGD_T_LOG2);
1028 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
1029}
1030
Ralf Baechle875d43e2005-09-03 15:56:16 -07001031#endif /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001032
1033static __init void build_adjust_context(u32 **p, unsigned int ctx)
1034{
1035 unsigned int shift = 4 - (PTE_T_LOG2 + 1);
1036 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1037
1038 switch (current_cpu_data.cputype) {
1039 case CPU_VR41XX:
1040 case CPU_VR4111:
1041 case CPU_VR4121:
1042 case CPU_VR4122:
1043 case CPU_VR4131:
1044 case CPU_VR4181:
1045 case CPU_VR4181A:
1046 case CPU_VR4133:
1047 shift += 2;
1048 break;
1049
1050 default:
1051 break;
1052 }
1053
1054 if (shift)
1055 i_SRL(p, ctx, ctx, shift);
1056 i_andi(p, ctx, ctx, mask);
1057}
1058
1059static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1060{
1061 /*
1062 * Bug workaround for the Nevada. It seems as if under certain
1063 * circumstances the move from cp0_context might produce a
1064 * bogus result when the mfc0 instruction and its consumer are
1065 * in a different cacheline or a load instruction, probably any
1066 * memory reference, is between them.
1067 */
1068 switch (current_cpu_data.cputype) {
1069 case CPU_NEVADA:
1070 i_LW(p, ptr, 0, ptr);
1071 GET_CONTEXT(p, tmp); /* get context reg */
1072 break;
1073
1074 default:
1075 GET_CONTEXT(p, tmp); /* get context reg */
1076 i_LW(p, ptr, 0, ptr);
1077 break;
1078 }
1079
1080 build_adjust_context(p, tmp);
1081 i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1082}
1083
1084static __init void build_update_entries(u32 **p, unsigned int tmp,
1085 unsigned int ptep)
1086{
1087 /*
1088 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1089 * Kernel is a special case. Only a few CPUs use it.
1090 */
1091#ifdef CONFIG_64BIT_PHYS_ADDR
1092 if (cpu_has_64bits) {
1093 i_ld(p, tmp, 0, ptep); /* get even pte */
1094 i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1095 i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */
1096 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1097 i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */
1098 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1099 } else {
1100 int pte_off_even = sizeof(pte_t) / 2;
1101 int pte_off_odd = pte_off_even + sizeof(pte_t);
1102
1103 /* The pte entries are pre-shifted */
1104 i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1105 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1106 i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1107 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1108 }
1109#else
1110 i_LW(p, tmp, 0, ptep); /* get even pte */
1111 i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1112 if (r45k_bvahwbug())
1113 build_tlb_probe_entry(p);
1114 i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */
1115 if (r4k_250MHZhwbug())
1116 i_mtc0(p, 0, C0_ENTRYLO0);
1117 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1118 i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */
1119 if (r45k_bvahwbug())
1120 i_mfc0(p, tmp, C0_INDEX);
1121 if (r4k_250MHZhwbug())
1122 i_mtc0(p, 0, C0_ENTRYLO1);
1123 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1124#endif
1125}
1126
1127static void __init build_r4000_tlb_refill_handler(void)
1128{
1129 u32 *p = tlb_handler;
1130 struct label *l = labels;
1131 struct reloc *r = relocs;
1132 u32 *f;
1133 unsigned int final_len;
1134
1135 memset(tlb_handler, 0, sizeof(tlb_handler));
1136 memset(labels, 0, sizeof(labels));
1137 memset(relocs, 0, sizeof(relocs));
1138 memset(final_handler, 0, sizeof(final_handler));
1139
1140 /*
1141 * create the plain linear handler
1142 */
1143 if (bcm1250_m3_war()) {
1144 i_MFC0(&p, K0, C0_BADVADDR);
1145 i_MFC0(&p, K1, C0_ENTRYHI);
1146 i_xor(&p, K0, K0, K1);
1147 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1148 il_bnez(&p, &r, K0, label_leave);
1149 /* No need for i_nop */
1150 }
1151
Ralf Baechle875d43e2005-09-03 15:56:16 -07001152#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1154#else
1155 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1156#endif
1157
1158 build_get_ptep(&p, K0, K1);
1159 build_update_entries(&p, K0, K1);
1160 build_tlb_write_entry(&p, &l, &r, tlb_random);
1161 l_leave(&l, p);
1162 i_eret(&p); /* return from trap */
1163
Ralf Baechle875d43e2005-09-03 15:56:16 -07001164#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001165 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
1166#endif
1167
1168 /*
1169 * Overflow check: For the 64bit handler, we need at least one
1170 * free instruction slot for the wrap-around branch. In worst
1171 * case, if the intended insertion point is a delay slot, we
1172 * need three, with the the second nop'ed and the third being
1173 * unused.
1174 */
Ralf Baechle875d43e2005-09-03 15:56:16 -07001175#ifdef CONFIG_32BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001176 if ((p - tlb_handler) > 64)
1177 panic("TLB refill handler space exceeded");
1178#else
1179 if (((p - tlb_handler) > 63)
1180 || (((p - tlb_handler) > 61)
1181 && insn_has_bdelay(relocs, tlb_handler + 29)))
1182 panic("TLB refill handler space exceeded");
1183#endif
1184
1185 /*
1186 * Now fold the handler in the TLB refill handler space.
1187 */
Ralf Baechle875d43e2005-09-03 15:56:16 -07001188#ifdef CONFIG_32BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001189 f = final_handler;
1190 /* Simplest case, just copy the handler. */
1191 copy_handler(relocs, labels, tlb_handler, p, f);
1192 final_len = p - tlb_handler;
Ralf Baechle875d43e2005-09-03 15:56:16 -07001193#else /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001194 f = final_handler + 32;
1195 if ((p - tlb_handler) <= 32) {
1196 /* Just copy the handler. */
1197 copy_handler(relocs, labels, tlb_handler, p, f);
1198 final_len = p - tlb_handler;
1199 } else {
1200 u32 *split = tlb_handler + 30;
1201
1202 /*
1203 * Find the split point.
1204 */
1205 if (insn_has_bdelay(relocs, split - 1))
1206 split--;
1207
1208 /* Copy first part of the handler. */
1209 copy_handler(relocs, labels, tlb_handler, split, f);
1210 f += split - tlb_handler;
1211
1212 /* Insert branch. */
1213 l_split(&l, final_handler);
1214 il_b(&f, &r, label_split);
1215 if (insn_has_bdelay(relocs, split))
1216 i_nop(&f);
1217 else {
1218 copy_handler(relocs, labels, split, split + 1, f);
1219 move_labels(labels, f, f + 1, -1);
1220 f++;
1221 split++;
1222 }
1223
1224 /* Copy the rest of the handler. */
1225 copy_handler(relocs, labels, split, p, final_handler);
1226 final_len = (f - (final_handler + 32)) + (p - split);
1227 }
Ralf Baechle875d43e2005-09-03 15:56:16 -07001228#endif /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229
1230 resolve_relocs(relocs, labels);
1231 printk("Synthesized TLB refill handler (%u instructions).\n",
1232 final_len);
1233
1234#ifdef DEBUG_TLB
1235 {
1236 int i;
1237
Maciej W. Rozycki4c0a2d42005-06-29 10:43:51 +00001238 f = final_handler;
1239#ifdef CONFIG_64BIT
1240 if (final_len > 32)
1241 final_len = 64;
1242 else
1243 f = final_handler + 32;
1244#endif /* CONFIG_64BIT */
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001245 for (i = 0; i < final_len; i++)
Maciej W. Rozycki4c0a2d42005-06-29 10:43:51 +00001246 printk("%08x\n", f[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001247 }
1248#endif
1249
Ralf Baechle91b05e62006-03-29 18:53:00 +01001250 memcpy((void *)ebase, final_handler, 0x100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251}
1252
1253/*
1254 * TLB load/store/modify handlers.
1255 *
1256 * Only the fastpath gets synthesized at runtime, the slowpath for
1257 * do_page_fault remains normal asm.
1258 */
1259extern void tlb_do_page_fault_0(void);
1260extern void tlb_do_page_fault_1(void);
1261
1262#define __tlb_handler_align \
1263 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT)))
1264
1265/*
1266 * 128 instructions for the fastpath handler is generous and should
1267 * never be exceeded.
1268 */
1269#define FASTPATH_SIZE 128
1270
1271u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE];
1272u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE];
1273u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE];
1274
1275static void __init
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001276iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001277{
1278#ifdef CONFIG_SMP
1279# ifdef CONFIG_64BIT_PHYS_ADDR
1280 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001281 i_lld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001282 else
1283# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001284 i_LL(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285#else
1286# ifdef CONFIG_64BIT_PHYS_ADDR
1287 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001288 i_ld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001289 else
1290# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001291 i_LW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001292#endif
1293}
1294
1295static void __init
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001296iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr,
1297 unsigned int mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001298{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001299#ifdef CONFIG_64BIT_PHYS_ADDR
1300 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1301#endif
1302
1303 i_ori(p, pte, pte, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001304#ifdef CONFIG_SMP
1305# ifdef CONFIG_64BIT_PHYS_ADDR
1306 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001307 i_scd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001308 else
1309# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001310 i_SC(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001311
1312 if (r10000_llsc_war())
1313 il_beqzl(p, r, pte, label_smp_pgtable_change);
1314 else
1315 il_beqz(p, r, pte, label_smp_pgtable_change);
1316
1317# ifdef CONFIG_64BIT_PHYS_ADDR
1318 if (!cpu_has_64bits) {
1319 /* no i_nop needed */
1320 i_ll(p, pte, sizeof(pte_t) / 2, ptr);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001321 i_ori(p, pte, pte, hwmode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001322 i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1323 il_beqz(p, r, pte, label_smp_pgtable_change);
1324 /* no i_nop needed */
1325 i_lw(p, pte, 0, ptr);
1326 } else
1327 i_nop(p);
1328# else
1329 i_nop(p);
1330# endif
1331#else
1332# ifdef CONFIG_64BIT_PHYS_ADDR
1333 if (cpu_has_64bits)
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001334 i_sd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001335 else
1336# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001337 i_SW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001338
1339# ifdef CONFIG_64BIT_PHYS_ADDR
1340 if (!cpu_has_64bits) {
1341 i_lw(p, pte, sizeof(pte_t) / 2, ptr);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001342 i_ori(p, pte, pte, hwmode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001343 i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1344 i_lw(p, pte, 0, ptr);
1345 }
1346# endif
1347#endif
1348}
1349
1350/*
1351 * Check if PTE is present, if not then jump to LABEL. PTR points to
1352 * the page table where this PTE is located, PTE will be re-loaded
1353 * with it's original value.
1354 */
1355static void __init
1356build_pte_present(u32 **p, struct label **l, struct reloc **r,
1357 unsigned int pte, unsigned int ptr, enum label_id lid)
1358{
1359 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1360 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1361 il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001362 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363}
1364
1365/* Make PTE valid, store result in PTR. */
1366static void __init
1367build_make_valid(u32 **p, struct reloc **r, unsigned int pte,
1368 unsigned int ptr)
1369{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001370 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1371
1372 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001373}
1374
1375/*
1376 * Check if PTE can be written to, if not branch to LABEL. Regardless
1377 * restore PTE with value from PTR when done.
1378 */
1379static void __init
1380build_pte_writable(u32 **p, struct label **l, struct reloc **r,
1381 unsigned int pte, unsigned int ptr, enum label_id lid)
1382{
1383 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1384 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1385 il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001386 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001387}
1388
1389/* Make PTE writable, update software status bits as well, then store
1390 * at PTR.
1391 */
1392static void __init
1393build_make_write(u32 **p, struct reloc **r, unsigned int pte,
1394 unsigned int ptr)
1395{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001396 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1397 | _PAGE_DIRTY);
1398
1399 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001400}
1401
1402/*
1403 * Check if PTE can be modified, if not branch to LABEL. Regardless
1404 * restore PTE with value from PTR when done.
1405 */
1406static void __init
1407build_pte_modifiable(u32 **p, struct label **l, struct reloc **r,
1408 unsigned int pte, unsigned int ptr, enum label_id lid)
1409{
1410 i_andi(p, pte, pte, _PAGE_WRITE);
1411 il_beqz(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001412 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413}
1414
1415/*
1416 * R3000 style TLB load/store/modify handlers.
1417 */
1418
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001419/*
1420 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1421 * Then it returns.
1422 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001423static void __init
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001424build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001425{
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001426 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1427 i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1428 i_tlbwi(p);
1429 i_jr(p, tmp);
1430 i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001431}
1432
1433/*
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001434 * This places the pte into ENTRYLO0 and writes it with tlbwi
1435 * or tlbwr as appropriate. This is because the index register
1436 * may have the probe fail bit set as a result of a trap on a
1437 * kseg2 access, i.e. without refill. Then it returns.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001438 */
1439static void __init
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001440build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r,
1441 unsigned int pte, unsigned int tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001442{
1443 i_mfc0(p, tmp, C0_INDEX);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001444 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1445 il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1446 i_mfc0(p, tmp, C0_EPC); /* branch delay */
1447 i_tlbwi(p); /* cp0 delay */
1448 i_jr(p, tmp);
1449 i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450 l_r3000_write_probe_fail(l, *p);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001451 i_tlbwr(p); /* cp0 delay */
1452 i_jr(p, tmp);
1453 i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454}
1455
1456static void __init
1457build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1458 unsigned int ptr)
1459{
1460 long pgdc = (long)pgd_current;
1461
1462 i_mfc0(p, pte, C0_BADVADDR);
1463 i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */
1464 i_lw(p, ptr, rel_lo(pgdc), ptr);
1465 i_srl(p, pte, pte, 22); /* load delay */
1466 i_sll(p, pte, pte, 2);
1467 i_addu(p, ptr, ptr, pte);
1468 i_mfc0(p, pte, C0_CONTEXT);
1469 i_lw(p, ptr, 0, ptr); /* cp0 delay */
1470 i_andi(p, pte, pte, 0xffc); /* load delay */
1471 i_addu(p, ptr, ptr, pte);
1472 i_lw(p, pte, 0, ptr);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001473 i_tlbp(p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001474}
1475
1476static void __init build_r3000_tlb_load_handler(void)
1477{
1478 u32 *p = handle_tlbl;
1479 struct label *l = labels;
1480 struct reloc *r = relocs;
1481
1482 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1483 memset(labels, 0, sizeof(labels));
1484 memset(relocs, 0, sizeof(relocs));
1485
1486 build_r3000_tlbchange_handler_head(&p, K0, K1);
1487 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001488 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001489 build_make_valid(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001490 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001491
1492 l_nopage_tlbl(&l, p);
1493 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1494 i_nop(&p);
1495
1496 if ((p - handle_tlbl) > FASTPATH_SIZE)
1497 panic("TLB load handler fastpath space exceeded");
1498
1499 resolve_relocs(relocs, labels);
1500 printk("Synthesized TLB load handler fastpath (%u instructions).\n",
1501 (unsigned int)(p - handle_tlbl));
1502
1503#ifdef DEBUG_TLB
1504 {
1505 int i;
1506
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001507 for (i = 0; i < (p - handle_tlbl); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001508 printk("%08x\n", handle_tlbl[i]);
1509 }
1510#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511}
1512
1513static void __init build_r3000_tlb_store_handler(void)
1514{
1515 u32 *p = handle_tlbs;
1516 struct label *l = labels;
1517 struct reloc *r = relocs;
1518
1519 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1520 memset(labels, 0, sizeof(labels));
1521 memset(relocs, 0, sizeof(relocs));
1522
1523 build_r3000_tlbchange_handler_head(&p, K0, K1);
1524 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001525 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526 build_make_write(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001527 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528
1529 l_nopage_tlbs(&l, p);
1530 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1531 i_nop(&p);
1532
1533 if ((p - handle_tlbs) > FASTPATH_SIZE)
1534 panic("TLB store handler fastpath space exceeded");
1535
1536 resolve_relocs(relocs, labels);
1537 printk("Synthesized TLB store handler fastpath (%u instructions).\n",
1538 (unsigned int)(p - handle_tlbs));
1539
1540#ifdef DEBUG_TLB
1541 {
1542 int i;
1543
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001544 for (i = 0; i < (p - handle_tlbs); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545 printk("%08x\n", handle_tlbs[i]);
1546 }
1547#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001548}
1549
1550static void __init build_r3000_tlb_modify_handler(void)
1551{
1552 u32 *p = handle_tlbm;
1553 struct label *l = labels;
1554 struct reloc *r = relocs;
1555
1556 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1557 memset(labels, 0, sizeof(labels));
1558 memset(relocs, 0, sizeof(relocs));
1559
1560 build_r3000_tlbchange_handler_head(&p, K0, K1);
1561 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
Maciej W. Rozyckid925c262005-06-13 20:12:01 +00001562 i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001563 build_make_write(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001564 build_r3000_pte_reload_tlbwi(&p, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001565
1566 l_nopage_tlbm(&l, p);
1567 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1568 i_nop(&p);
1569
1570 if ((p - handle_tlbm) > FASTPATH_SIZE)
1571 panic("TLB modify handler fastpath space exceeded");
1572
1573 resolve_relocs(relocs, labels);
1574 printk("Synthesized TLB modify handler fastpath (%u instructions).\n",
1575 (unsigned int)(p - handle_tlbm));
1576
1577#ifdef DEBUG_TLB
1578 {
1579 int i;
1580
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001581 for (i = 0; i < (p - handle_tlbm); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001582 printk("%08x\n", handle_tlbm[i]);
1583 }
1584#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585}
1586
1587/*
1588 * R4000 style TLB load/store/modify handlers.
1589 */
1590static void __init
1591build_r4000_tlbchange_handler_head(u32 **p, struct label **l,
1592 struct reloc **r, unsigned int pte,
1593 unsigned int ptr)
1594{
Ralf Baechle875d43e2005-09-03 15:56:16 -07001595#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001596 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1597#else
1598 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1599#endif
1600
1601 i_MFC0(p, pte, C0_BADVADDR);
1602 i_LW(p, ptr, 0, ptr);
1603 i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1604 i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1605 i_ADDU(p, ptr, ptr, pte);
1606
1607#ifdef CONFIG_SMP
1608 l_smp_pgtable_change(l, *p);
1609# endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001610 iPTE_LW(p, l, pte, ptr); /* get even pte */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611 build_tlb_probe_entry(p);
1612}
1613
1614static void __init
1615build_r4000_tlbchange_handler_tail(u32 **p, struct label **l,
1616 struct reloc **r, unsigned int tmp,
1617 unsigned int ptr)
1618{
1619 i_ori(p, ptr, ptr, sizeof(pte_t));
1620 i_xori(p, ptr, ptr, sizeof(pte_t));
1621 build_update_entries(p, tmp, ptr);
1622 build_tlb_write_entry(p, l, r, tlb_indexed);
1623 l_leave(l, *p);
1624 i_eret(p); /* return from trap */
1625
Ralf Baechle875d43e2005-09-03 15:56:16 -07001626#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001627 build_get_pgd_vmalloc64(p, l, r, tmp, ptr);
1628#endif
1629}
1630
1631static void __init build_r4000_tlb_load_handler(void)
1632{
1633 u32 *p = handle_tlbl;
1634 struct label *l = labels;
1635 struct reloc *r = relocs;
1636
1637 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1638 memset(labels, 0, sizeof(labels));
1639 memset(relocs, 0, sizeof(relocs));
1640
1641 if (bcm1250_m3_war()) {
1642 i_MFC0(&p, K0, C0_BADVADDR);
1643 i_MFC0(&p, K1, C0_ENTRYHI);
1644 i_xor(&p, K0, K0, K1);
1645 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1646 il_bnez(&p, &r, K0, label_leave);
1647 /* No need for i_nop */
1648 }
1649
1650 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1651 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
1652 build_make_valid(&p, &r, K0, K1);
1653 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1654
1655 l_nopage_tlbl(&l, p);
1656 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1657 i_nop(&p);
1658
1659 if ((p - handle_tlbl) > FASTPATH_SIZE)
1660 panic("TLB load handler fastpath space exceeded");
1661
1662 resolve_relocs(relocs, labels);
1663 printk("Synthesized TLB load handler fastpath (%u instructions).\n",
1664 (unsigned int)(p - handle_tlbl));
1665
1666#ifdef DEBUG_TLB
1667 {
1668 int i;
1669
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001670 for (i = 0; i < (p - handle_tlbl); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001671 printk("%08x\n", handle_tlbl[i]);
1672 }
1673#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001674}
1675
1676static void __init build_r4000_tlb_store_handler(void)
1677{
1678 u32 *p = handle_tlbs;
1679 struct label *l = labels;
1680 struct reloc *r = relocs;
1681
1682 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1683 memset(labels, 0, sizeof(labels));
1684 memset(relocs, 0, sizeof(relocs));
1685
1686 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1687 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
1688 build_make_write(&p, &r, K0, K1);
1689 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1690
1691 l_nopage_tlbs(&l, p);
1692 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1693 i_nop(&p);
1694
1695 if ((p - handle_tlbs) > FASTPATH_SIZE)
1696 panic("TLB store handler fastpath space exceeded");
1697
1698 resolve_relocs(relocs, labels);
1699 printk("Synthesized TLB store handler fastpath (%u instructions).\n",
1700 (unsigned int)(p - handle_tlbs));
1701
1702#ifdef DEBUG_TLB
1703 {
1704 int i;
1705
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001706 for (i = 0; i < (p - handle_tlbs); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001707 printk("%08x\n", handle_tlbs[i]);
1708 }
1709#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001710}
1711
1712static void __init build_r4000_tlb_modify_handler(void)
1713{
1714 u32 *p = handle_tlbm;
1715 struct label *l = labels;
1716 struct reloc *r = relocs;
1717
1718 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1719 memset(labels, 0, sizeof(labels));
1720 memset(relocs, 0, sizeof(relocs));
1721
1722 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1723 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
1724 /* Present and writable bits set, set accessed and dirty bits. */
1725 build_make_write(&p, &r, K0, K1);
1726 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1727
1728 l_nopage_tlbm(&l, p);
1729 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1730 i_nop(&p);
1731
1732 if ((p - handle_tlbm) > FASTPATH_SIZE)
1733 panic("TLB modify handler fastpath space exceeded");
1734
1735 resolve_relocs(relocs, labels);
1736 printk("Synthesized TLB modify handler fastpath (%u instructions).\n",
1737 (unsigned int)(p - handle_tlbm));
1738
1739#ifdef DEBUG_TLB
1740 {
1741 int i;
1742
Maciej W. Rozycki9678e282005-06-13 20:09:32 +00001743 for (i = 0; i < (p - handle_tlbm); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001744 printk("%08x\n", handle_tlbm[i]);
1745 }
1746#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001747}
1748
1749void __init build_tlb_refill_handler(void)
1750{
1751 /*
1752 * The refill handler is generated per-CPU, multi-node systems
1753 * may have local storage for it. The other handlers are only
1754 * needed once.
1755 */
1756 static int run_once = 0;
1757
1758 switch (current_cpu_data.cputype) {
1759 case CPU_R2000:
1760 case CPU_R3000:
1761 case CPU_R3000A:
1762 case CPU_R3081E:
1763 case CPU_TX3912:
1764 case CPU_TX3922:
1765 case CPU_TX3927:
1766 build_r3000_tlb_refill_handler();
1767 if (!run_once) {
1768 build_r3000_tlb_load_handler();
1769 build_r3000_tlb_store_handler();
1770 build_r3000_tlb_modify_handler();
1771 run_once++;
1772 }
1773 break;
1774
1775 case CPU_R6000:
1776 case CPU_R6000A:
1777 panic("No R6000 TLB refill handler yet");
1778 break;
1779
1780 case CPU_R8000:
1781 panic("No R8000 TLB refill handler yet");
1782 break;
1783
1784 default:
1785 build_r4000_tlb_refill_handler();
1786 if (!run_once) {
1787 build_r4000_tlb_load_handler();
1788 build_r4000_tlb_store_handler();
1789 build_r4000_tlb_modify_handler();
1790 run_once++;
1791 }
1792 }
1793}
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001794
1795void __init flush_tlb_handlers(void)
1796{
1797 flush_icache_range((unsigned long)handle_tlbl,
1798 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
1799 flush_icache_range((unsigned long)handle_tlbs,
1800 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
1801 flush_icache_range((unsigned long)handle_tlbm,
1802 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
1803}