Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __AMDGPU_OBJECT_H__ |
| 29 | #define __AMDGPU_OBJECT_H__ |
| 30 | |
| 31 | #include <drm/amdgpu_drm.h> |
| 32 | #include "amdgpu.h" |
| 33 | |
| 34 | /** |
| 35 | * amdgpu_mem_type_to_domain - return domain corresponding to mem_type |
| 36 | * @mem_type: ttm memory type |
| 37 | * |
| 38 | * Returns corresponding domain of the ttm mem_type |
| 39 | */ |
| 40 | static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) |
| 41 | { |
| 42 | switch (mem_type) { |
| 43 | case TTM_PL_VRAM: |
| 44 | return AMDGPU_GEM_DOMAIN_VRAM; |
| 45 | case TTM_PL_TT: |
| 46 | return AMDGPU_GEM_DOMAIN_GTT; |
| 47 | case TTM_PL_SYSTEM: |
| 48 | return AMDGPU_GEM_DOMAIN_CPU; |
| 49 | case AMDGPU_PL_GDS: |
| 50 | return AMDGPU_GEM_DOMAIN_GDS; |
| 51 | case AMDGPU_PL_GWS: |
| 52 | return AMDGPU_GEM_DOMAIN_GWS; |
| 53 | case AMDGPU_PL_OA: |
| 54 | return AMDGPU_GEM_DOMAIN_OA; |
| 55 | default: |
| 56 | break; |
| 57 | } |
| 58 | return 0; |
| 59 | } |
| 60 | |
| 61 | /** |
| 62 | * amdgpu_bo_reserve - reserve bo |
| 63 | * @bo: bo structure |
| 64 | * @no_intr: don't return -ERESTARTSYS on pending signal |
| 65 | * |
| 66 | * Returns: |
| 67 | * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by |
| 68 | * a signal. Release all buffer reservations and return to user-space. |
| 69 | */ |
| 70 | static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) |
| 71 | { |
| 72 | int r; |
| 73 | |
| 74 | r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0); |
| 75 | if (unlikely(r != 0)) { |
| 76 | if (r != -ERESTARTSYS) |
| 77 | dev_err(bo->adev->dev, "%p reserve failed\n", bo); |
| 78 | return r; |
| 79 | } |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo) |
| 84 | { |
| 85 | ttm_bo_unreserve(&bo->tbo); |
| 86 | } |
| 87 | |
| 88 | /** |
| 89 | * amdgpu_bo_gpu_offset - return GPU offset of bo |
| 90 | * @bo: amdgpu object for which we query the offset |
| 91 | * |
| 92 | * Returns current GPU offset of the object. |
| 93 | * |
| 94 | * Note: object should either be pinned or reserved when calling this |
| 95 | * function, it might be useful to add check for this for debugging. |
| 96 | */ |
| 97 | static inline u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) |
| 98 | { |
| 99 | return bo->tbo.offset; |
| 100 | } |
| 101 | |
| 102 | static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo) |
| 103 | { |
| 104 | return bo->tbo.num_pages << PAGE_SHIFT; |
| 105 | } |
| 106 | |
| 107 | static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo) |
| 108 | { |
| 109 | return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; |
| 110 | } |
| 111 | |
| 112 | static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo) |
| 113 | { |
| 114 | return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; |
| 115 | } |
| 116 | |
| 117 | /** |
| 118 | * amdgpu_bo_mmap_offset - return mmap offset of bo |
| 119 | * @bo: amdgpu object for which we query the offset |
| 120 | * |
| 121 | * Returns mmap offset of the object. |
| 122 | */ |
| 123 | static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) |
| 124 | { |
| 125 | return drm_vma_node_offset_addr(&bo->tbo.vma_node); |
| 126 | } |
| 127 | |
| 128 | int amdgpu_bo_create(struct amdgpu_device *adev, |
| 129 | unsigned long size, int byte_align, |
| 130 | bool kernel, u32 domain, u64 flags, |
| 131 | struct sg_table *sg, |
Christian König | 72d7668 | 2015-09-03 17:34:59 +0200 | [diff] [blame] | 132 | struct reservation_object *resv, |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 133 | struct amdgpu_bo **bo_ptr); |
Chunming Zhou | 7e5a547 | 2015-04-24 17:37:30 +0800 | [diff] [blame] | 134 | int amdgpu_bo_create_restricted(struct amdgpu_device *adev, |
| 135 | unsigned long size, int byte_align, |
| 136 | bool kernel, u32 domain, u64 flags, |
| 137 | struct sg_table *sg, |
| 138 | struct ttm_placement *placement, |
Christian König | 72d7668 | 2015-09-03 17:34:59 +0200 | [diff] [blame] | 139 | struct reservation_object *resv, |
Chunming Zhou | 7e5a547 | 2015-04-24 17:37:30 +0800 | [diff] [blame] | 140 | struct amdgpu_bo **bo_ptr); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 141 | int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); |
| 142 | void amdgpu_bo_kunmap(struct amdgpu_bo *bo); |
| 143 | struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); |
| 144 | void amdgpu_bo_unref(struct amdgpu_bo **bo); |
| 145 | int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr); |
| 146 | int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, |
Chunming Zhou | 7e5a547 | 2015-04-24 17:37:30 +0800 | [diff] [blame] | 147 | u64 min_offset, u64 max_offset, |
| 148 | u64 *gpu_addr); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 149 | int amdgpu_bo_unpin(struct amdgpu_bo *bo); |
| 150 | int amdgpu_bo_evict_vram(struct amdgpu_device *adev); |
| 151 | void amdgpu_bo_force_delete(struct amdgpu_device *adev); |
| 152 | int amdgpu_bo_init(struct amdgpu_device *adev); |
| 153 | void amdgpu_bo_fini(struct amdgpu_device *adev); |
| 154 | int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, |
| 155 | struct vm_area_struct *vma); |
| 156 | int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); |
| 157 | void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags); |
| 158 | int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, |
| 159 | uint32_t metadata_size, uint64_t flags); |
| 160 | int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, |
| 161 | size_t buffer_size, uint32_t *metadata_size, |
| 162 | uint64_t *flags); |
| 163 | void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, |
| 164 | struct ttm_mem_reg *new_mem); |
| 165 | int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); |
Chunming Zhou | e40a311 | 2015-08-03 11:38:09 +0800 | [diff] [blame] | 166 | void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence, |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 167 | bool shared); |
| 168 | |
| 169 | /* |
| 170 | * sub allocation |
| 171 | */ |
| 172 | |
| 173 | static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo) |
| 174 | { |
| 175 | return sa_bo->manager->gpu_addr + sa_bo->soffset; |
| 176 | } |
| 177 | |
| 178 | static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo) |
| 179 | { |
| 180 | return sa_bo->manager->cpu_ptr + sa_bo->soffset; |
| 181 | } |
| 182 | |
| 183 | int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, |
| 184 | struct amdgpu_sa_manager *sa_manager, |
| 185 | unsigned size, u32 align, u32 domain); |
| 186 | void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev, |
| 187 | struct amdgpu_sa_manager *sa_manager); |
| 188 | int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev, |
| 189 | struct amdgpu_sa_manager *sa_manager); |
| 190 | int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev, |
| 191 | struct amdgpu_sa_manager *sa_manager); |
| 192 | int amdgpu_sa_bo_new(struct amdgpu_device *adev, |
| 193 | struct amdgpu_sa_manager *sa_manager, |
| 194 | struct amdgpu_sa_bo **sa_bo, |
| 195 | unsigned size, unsigned align); |
| 196 | void amdgpu_sa_bo_free(struct amdgpu_device *adev, |
| 197 | struct amdgpu_sa_bo **sa_bo, |
Chunming Zhou | 4ce9891 | 2015-08-19 16:41:19 +0800 | [diff] [blame] | 198 | struct fence *fence); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 199 | #if defined(CONFIG_DEBUG_FS) |
| 200 | void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, |
| 201 | struct seq_file *m); |
| 202 | #endif |
| 203 | |
| 204 | |
| 205 | #endif |