Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/i915_drm.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 33 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 34 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 35 | |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 36 | bool |
| 37 | intel_ring_initialized(struct intel_engine_cs *ring) |
| 38 | { |
| 39 | struct drm_device *dev = ring->dev; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 40 | |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 41 | if (!dev) |
| 42 | return false; |
| 43 | |
| 44 | if (i915.enable_execlists) { |
| 45 | struct intel_context *dctx = ring->default_context; |
| 46 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; |
| 47 | |
| 48 | return ringbuf->obj; |
| 49 | } else |
| 50 | return ring->buffer && ring->buffer->obj; |
| 51 | } |
| 52 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 53 | int __intel_ring_space(int head, int tail, int size) |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 54 | { |
| 55 | int space = head - (tail + I915_RING_FREE_SPACE); |
| 56 | if (space < 0) |
| 57 | space += size; |
| 58 | return space; |
| 59 | } |
| 60 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 61 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 62 | { |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 63 | return __intel_ring_space(ringbuf->head & HEAD_ADDR, |
| 64 | ringbuf->tail, ringbuf->size); |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 65 | } |
| 66 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 67 | bool intel_ring_stopped(struct intel_engine_cs *ring) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 68 | { |
| 69 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 70 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
| 71 | } |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 72 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 73 | void __intel_ring_advance(struct intel_engine_cs *ring) |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 74 | { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 75 | struct intel_ringbuffer *ringbuf = ring->buffer; |
| 76 | ringbuf->tail &= ringbuf->size - 1; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 77 | if (intel_ring_stopped(ring)) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 78 | return; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 79 | ring->write_tail(ring, ringbuf->tail); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 80 | } |
| 81 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 82 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 83 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 84 | u32 invalidate_domains, |
| 85 | u32 flush_domains) |
| 86 | { |
| 87 | u32 cmd; |
| 88 | int ret; |
| 89 | |
| 90 | cmd = MI_FLUSH; |
Daniel Vetter | 31b14c9 | 2012-04-19 16:45:22 +0200 | [diff] [blame] | 91 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 92 | cmd |= MI_NO_WRITE_FLUSH; |
| 93 | |
| 94 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 95 | cmd |= MI_READ_FLUSH; |
| 96 | |
| 97 | ret = intel_ring_begin(ring, 2); |
| 98 | if (ret) |
| 99 | return ret; |
| 100 | |
| 101 | intel_ring_emit(ring, cmd); |
| 102 | intel_ring_emit(ring, MI_NOOP); |
| 103 | intel_ring_advance(ring); |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 109 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 110 | u32 invalidate_domains, |
| 111 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 112 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 113 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 114 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 115 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 116 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 117 | /* |
| 118 | * read/write caches: |
| 119 | * |
| 120 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 121 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 122 | * also flushed at 2d versus 3d pipeline switches. |
| 123 | * |
| 124 | * read-only caches: |
| 125 | * |
| 126 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 127 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 128 | * |
| 129 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 130 | * |
| 131 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 132 | * invalidated when MI_EXE_FLUSH is set. |
| 133 | * |
| 134 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 135 | * invalidated with every MI_FLUSH. |
| 136 | * |
| 137 | * TLBs: |
| 138 | * |
| 139 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 140 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 141 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 142 | * are flushed at any MI_FLUSH. |
| 143 | */ |
| 144 | |
| 145 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 146 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 147 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 148 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 149 | cmd |= MI_EXE_FLUSH; |
| 150 | |
| 151 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 152 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 153 | cmd |= MI_INVALIDATE_ISP; |
| 154 | |
| 155 | ret = intel_ring_begin(ring, 2); |
| 156 | if (ret) |
| 157 | return ret; |
| 158 | |
| 159 | intel_ring_emit(ring, cmd); |
| 160 | intel_ring_emit(ring, MI_NOOP); |
| 161 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 162 | |
| 163 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 164 | } |
| 165 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 166 | /** |
| 167 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 168 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 169 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 170 | * |
| 171 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 172 | * produced by non-pipelined state commands), software needs to first |
| 173 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 174 | * 0. |
| 175 | * |
| 176 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 177 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 178 | * |
| 179 | * And the workaround for these two requires this workaround first: |
| 180 | * |
| 181 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 182 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 183 | * flushes. |
| 184 | * |
| 185 | * And this last workaround is tricky because of the requirements on |
| 186 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 187 | * volume 2 part 1: |
| 188 | * |
| 189 | * "1 of the following must also be set: |
| 190 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 191 | * - Depth Cache Flush Enable ([0] of DW1) |
| 192 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 193 | * - Depth Stall ([13] of DW1) |
| 194 | * - Post-Sync Operation ([13] of DW1) |
| 195 | * - Notify Enable ([8] of DW1)" |
| 196 | * |
| 197 | * The cache flushes require the workaround flush that triggered this |
| 198 | * one, so we can't use it. Depth stall would trigger the same. |
| 199 | * Post-sync nonzero is what triggered this second workaround, so we |
| 200 | * can't use that one either. Notify enable is IRQs, which aren't |
| 201 | * really our business. That leaves only stall at scoreboard. |
| 202 | */ |
| 203 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 204 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 205 | { |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 206 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 207 | int ret; |
| 208 | |
| 209 | |
| 210 | ret = intel_ring_begin(ring, 6); |
| 211 | if (ret) |
| 212 | return ret; |
| 213 | |
| 214 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 215 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 216 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 217 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 218 | intel_ring_emit(ring, 0); /* low dword */ |
| 219 | intel_ring_emit(ring, 0); /* high dword */ |
| 220 | intel_ring_emit(ring, MI_NOOP); |
| 221 | intel_ring_advance(ring); |
| 222 | |
| 223 | ret = intel_ring_begin(ring, 6); |
| 224 | if (ret) |
| 225 | return ret; |
| 226 | |
| 227 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 228 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 229 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 230 | intel_ring_emit(ring, 0); |
| 231 | intel_ring_emit(ring, 0); |
| 232 | intel_ring_emit(ring, MI_NOOP); |
| 233 | intel_ring_advance(ring); |
| 234 | |
| 235 | return 0; |
| 236 | } |
| 237 | |
| 238 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 239 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 240 | u32 invalidate_domains, u32 flush_domains) |
| 241 | { |
| 242 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 243 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 244 | int ret; |
| 245 | |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 246 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 247 | ret = intel_emit_post_sync_nonzero_flush(ring); |
| 248 | if (ret) |
| 249 | return ret; |
| 250 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 251 | /* Just flush everything. Experiments have shown that reducing the |
| 252 | * number of bits based on the write domains has little performance |
| 253 | * impact. |
| 254 | */ |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 255 | if (flush_domains) { |
| 256 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 257 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 258 | /* |
| 259 | * Ensure that any following seqno writes only happen |
| 260 | * when the render cache is indeed flushed. |
| 261 | */ |
Daniel Vetter | 97f209b | 2012-06-28 09:48:42 +0200 | [diff] [blame] | 262 | flags |= PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 263 | } |
| 264 | if (invalidate_domains) { |
| 265 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 266 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 267 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 268 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 269 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 270 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 271 | /* |
| 272 | * TLB invalidate requires a post-sync write. |
| 273 | */ |
Jesse Barnes | 3ac7831 | 2012-10-25 12:15:47 -0700 | [diff] [blame] | 274 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 275 | } |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 276 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 277 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 278 | if (ret) |
| 279 | return ret; |
| 280 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 281 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 282 | intel_ring_emit(ring, flags); |
| 283 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 284 | intel_ring_emit(ring, 0); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 285 | intel_ring_advance(ring); |
| 286 | |
| 287 | return 0; |
| 288 | } |
| 289 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 290 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 291 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 292 | { |
| 293 | int ret; |
| 294 | |
| 295 | ret = intel_ring_begin(ring, 4); |
| 296 | if (ret) |
| 297 | return ret; |
| 298 | |
| 299 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 300 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 301 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 302 | intel_ring_emit(ring, 0); |
| 303 | intel_ring_emit(ring, 0); |
| 304 | intel_ring_advance(ring); |
| 305 | |
| 306 | return 0; |
| 307 | } |
| 308 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 309 | static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 310 | { |
| 311 | int ret; |
| 312 | |
| 313 | if (!ring->fbc_dirty) |
| 314 | return 0; |
| 315 | |
Ville Syrjälä | 37c1d94 | 2013-11-06 23:02:20 +0200 | [diff] [blame] | 316 | ret = intel_ring_begin(ring, 6); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 317 | if (ret) |
| 318 | return ret; |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 319 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
| 320 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 321 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
| 322 | intel_ring_emit(ring, value); |
Ville Syrjälä | 37c1d94 | 2013-11-06 23:02:20 +0200 | [diff] [blame] | 323 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
| 324 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
| 325 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 326 | intel_ring_advance(ring); |
| 327 | |
| 328 | ring->fbc_dirty = false; |
| 329 | return 0; |
| 330 | } |
| 331 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 332 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 333 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 334 | u32 invalidate_domains, u32 flush_domains) |
| 335 | { |
| 336 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 337 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 338 | int ret; |
| 339 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 340 | /* |
| 341 | * Ensure that any following seqno writes only happen when the render |
| 342 | * cache is indeed flushed. |
| 343 | * |
| 344 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
| 345 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
| 346 | * don't try to be clever and just set it unconditionally. |
| 347 | */ |
| 348 | flags |= PIPE_CONTROL_CS_STALL; |
| 349 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 350 | /* Just flush everything. Experiments have shown that reducing the |
| 351 | * number of bits based on the write domains has little performance |
| 352 | * impact. |
| 353 | */ |
| 354 | if (flush_domains) { |
| 355 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 356 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 357 | } |
| 358 | if (invalidate_domains) { |
| 359 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 360 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 361 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 362 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 363 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 364 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 365 | /* |
| 366 | * TLB invalidate requires a post-sync write. |
| 367 | */ |
| 368 | flags |= PIPE_CONTROL_QW_WRITE; |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 369 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 370 | |
| 371 | /* Workaround: we must issue a pipe_control with CS-stall bit |
| 372 | * set before a pipe_control command that has the state cache |
| 373 | * invalidate bit set. */ |
| 374 | gen7_render_ring_cs_stall_wa(ring); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | ret = intel_ring_begin(ring, 4); |
| 378 | if (ret) |
| 379 | return ret; |
| 380 | |
| 381 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 382 | intel_ring_emit(ring, flags); |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 383 | intel_ring_emit(ring, scratch_addr); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 384 | intel_ring_emit(ring, 0); |
| 385 | intel_ring_advance(ring); |
| 386 | |
Ville Syrjälä | 9688eca | 2013-11-06 23:02:19 +0200 | [diff] [blame] | 387 | if (!invalidate_domains && flush_domains) |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 388 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
| 389 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 390 | return 0; |
| 391 | } |
| 392 | |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 393 | static int |
Kenneth Graunke | 884ceac | 2014-06-28 02:04:20 +0300 | [diff] [blame] | 394 | gen8_emit_pipe_control(struct intel_engine_cs *ring, |
| 395 | u32 flags, u32 scratch_addr) |
| 396 | { |
| 397 | int ret; |
| 398 | |
| 399 | ret = intel_ring_begin(ring, 6); |
| 400 | if (ret) |
| 401 | return ret; |
| 402 | |
| 403 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
| 404 | intel_ring_emit(ring, flags); |
| 405 | intel_ring_emit(ring, scratch_addr); |
| 406 | intel_ring_emit(ring, 0); |
| 407 | intel_ring_emit(ring, 0); |
| 408 | intel_ring_emit(ring, 0); |
| 409 | intel_ring_advance(ring); |
| 410 | |
| 411 | return 0; |
| 412 | } |
| 413 | |
| 414 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 415 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 416 | u32 invalidate_domains, u32 flush_domains) |
| 417 | { |
| 418 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 419 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 420 | int ret; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 421 | |
| 422 | flags |= PIPE_CONTROL_CS_STALL; |
| 423 | |
| 424 | if (flush_domains) { |
| 425 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 426 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 427 | } |
| 428 | if (invalidate_domains) { |
| 429 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 430 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 431 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 432 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 433 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 434 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 435 | flags |= PIPE_CONTROL_QW_WRITE; |
| 436 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 437 | |
| 438 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ |
| 439 | ret = gen8_emit_pipe_control(ring, |
| 440 | PIPE_CONTROL_CS_STALL | |
| 441 | PIPE_CONTROL_STALL_AT_SCOREBOARD, |
| 442 | 0); |
| 443 | if (ret) |
| 444 | return ret; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 445 | } |
| 446 | |
Rodrigo Vivi | c5ad011 | 2014-08-04 03:51:38 -0700 | [diff] [blame] | 447 | ret = gen8_emit_pipe_control(ring, flags, scratch_addr); |
| 448 | if (ret) |
| 449 | return ret; |
| 450 | |
| 451 | if (!invalidate_domains && flush_domains) |
| 452 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
| 453 | |
| 454 | return 0; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 455 | } |
| 456 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 457 | static void ring_write_tail(struct intel_engine_cs *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 458 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 459 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 460 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 461 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 462 | } |
| 463 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 464 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 465 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 466 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 467 | u64 acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 468 | |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 469 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 470 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), |
| 471 | RING_ACTHD_UDW(ring->mmio_base)); |
| 472 | else if (INTEL_INFO(ring->dev)->gen >= 4) |
| 473 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); |
| 474 | else |
| 475 | acthd = I915_READ(ACTHD); |
| 476 | |
| 477 | return acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 478 | } |
| 479 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 480 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 481 | { |
| 482 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 483 | u32 addr; |
| 484 | |
| 485 | addr = dev_priv->status_page_dmah->busaddr; |
| 486 | if (INTEL_INFO(ring->dev)->gen >= 4) |
| 487 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 488 | I915_WRITE(HWS_PGA, addr); |
| 489 | } |
| 490 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 491 | static bool stop_ring(struct intel_engine_cs *ring) |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 492 | { |
| 493 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
| 494 | |
| 495 | if (!IS_GEN2(ring->dev)) { |
| 496 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); |
Daniel Vetter | 403bdd1 | 2014-08-07 16:05:39 +0200 | [diff] [blame] | 497 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
| 498 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); |
Chris Wilson | 9bec9b1 | 2014-08-11 09:21:35 +0100 | [diff] [blame] | 499 | /* Sometimes we observe that the idle flag is not |
| 500 | * set even though the ring is empty. So double |
| 501 | * check before giving up. |
| 502 | */ |
| 503 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) |
| 504 | return false; |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 505 | } |
| 506 | } |
| 507 | |
| 508 | I915_WRITE_CTL(ring, 0); |
| 509 | I915_WRITE_HEAD(ring, 0); |
| 510 | ring->write_tail(ring, 0); |
| 511 | |
| 512 | if (!IS_GEN2(ring->dev)) { |
| 513 | (void)I915_READ_CTL(ring); |
| 514 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); |
| 515 | } |
| 516 | |
| 517 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
| 518 | } |
| 519 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 520 | static int init_ring_common(struct intel_engine_cs *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 521 | { |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 522 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 523 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 524 | struct intel_ringbuffer *ringbuf = ring->buffer; |
| 525 | struct drm_i915_gem_object *obj = ringbuf->obj; |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 526 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 527 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 528 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 529 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 530 | if (!stop_ring(ring)) { |
| 531 | /* G45 ring initialization often fails to reset head to zero */ |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 532 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 533 | "ctl %08x head %08x tail %08x start %08x\n", |
| 534 | ring->name, |
| 535 | I915_READ_CTL(ring), |
| 536 | I915_READ_HEAD(ring), |
| 537 | I915_READ_TAIL(ring), |
| 538 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 539 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 540 | if (!stop_ring(ring)) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 541 | DRM_ERROR("failed to set %s head to zero " |
| 542 | "ctl %08x head %08x tail %08x start %08x\n", |
| 543 | ring->name, |
| 544 | I915_READ_CTL(ring), |
| 545 | I915_READ_HEAD(ring), |
| 546 | I915_READ_TAIL(ring), |
| 547 | I915_READ_START(ring)); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 548 | ret = -EIO; |
| 549 | goto out; |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 550 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 551 | } |
| 552 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 553 | if (I915_NEED_GFX_HWS(dev)) |
| 554 | intel_ring_setup_status_page(ring); |
| 555 | else |
| 556 | ring_setup_phys_status_page(ring); |
| 557 | |
Jiri Kosina | ece4a17 | 2014-08-07 16:29:53 +0200 | [diff] [blame] | 558 | /* Enforce ordering by reading HEAD register back */ |
| 559 | I915_READ_HEAD(ring); |
| 560 | |
Daniel Vetter | 0d8957c | 2012-08-07 09:54:14 +0200 | [diff] [blame] | 561 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
| 562 | * registers with the above sequence (the readback of the HEAD registers |
| 563 | * also enforces ordering), otherwise the hw might lose the new ring |
| 564 | * register values. */ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 565 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
Chris Wilson | 9546889 | 2014-08-07 15:39:54 +0100 | [diff] [blame] | 566 | |
| 567 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ |
| 568 | if (I915_READ_HEAD(ring)) |
| 569 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
| 570 | ring->name, I915_READ_HEAD(ring)); |
| 571 | I915_WRITE_HEAD(ring, 0); |
| 572 | (void)I915_READ_HEAD(ring); |
| 573 | |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 574 | I915_WRITE_CTL(ring, |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 575 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 576 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 577 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 578 | /* If the head is still not zero, the ring is dead */ |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 579 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 580 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 581 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 582 | DRM_ERROR("%s initialization failed " |
Chris Wilson | 48e48a0 | 2014-04-09 09:19:44 +0100 | [diff] [blame] | 583 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
| 584 | ring->name, |
| 585 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, |
| 586 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), |
| 587 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 588 | ret = -EIO; |
| 589 | goto out; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 590 | } |
| 591 | |
Chris Wilson | 5c6c600 | 2014-09-06 10:28:27 +0100 | [diff] [blame] | 592 | ringbuf->head = I915_READ_HEAD(ring); |
| 593 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
| 594 | ringbuf->space = intel_ring_space(ringbuf); |
| 595 | ringbuf->last_retired_head = -1; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 596 | |
Chris Wilson | 50f018d | 2013-06-10 11:20:19 +0100 | [diff] [blame] | 597 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
| 598 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 599 | out: |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 600 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 601 | |
| 602 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 603 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 604 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 605 | void |
| 606 | intel_fini_pipe_control(struct intel_engine_cs *ring) |
| 607 | { |
| 608 | struct drm_device *dev = ring->dev; |
| 609 | |
| 610 | if (ring->scratch.obj == NULL) |
| 611 | return; |
| 612 | |
| 613 | if (INTEL_INFO(dev)->gen >= 5) { |
| 614 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 615 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
| 616 | } |
| 617 | |
| 618 | drm_gem_object_unreference(&ring->scratch.obj->base); |
| 619 | ring->scratch.obj = NULL; |
| 620 | } |
| 621 | |
| 622 | int |
| 623 | intel_init_pipe_control(struct intel_engine_cs *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 624 | { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 625 | int ret; |
| 626 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 627 | if (ring->scratch.obj) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 628 | return 0; |
| 629 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 630 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
| 631 | if (ring->scratch.obj == NULL) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 632 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 633 | ret = -ENOMEM; |
| 634 | goto err; |
| 635 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 636 | |
Daniel Vetter | a9cc726 | 2014-02-14 14:01:13 +0100 | [diff] [blame] | 637 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
| 638 | if (ret) |
| 639 | goto err_unref; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 640 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 641 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 642 | if (ret) |
| 643 | goto err_unref; |
| 644 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 645 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
| 646 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 647 | if (ring->scratch.cpu_page == NULL) { |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 648 | ret = -ENOMEM; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 649 | goto err_unpin; |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 650 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 651 | |
Ville Syrjälä | 2b1086c | 2013-02-12 22:01:38 +0200 | [diff] [blame] | 652 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 653 | ring->name, ring->scratch.gtt_offset); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 654 | return 0; |
| 655 | |
| 656 | err_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 657 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 658 | err_unref: |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 659 | drm_gem_object_unreference(&ring->scratch.obj->base); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 660 | err: |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 661 | return ret; |
| 662 | } |
| 663 | |
Michel Thierry | 771b9a5 | 2014-11-11 16:47:33 +0000 | [diff] [blame] | 664 | static int intel_ring_workarounds_emit(struct intel_engine_cs *ring, |
| 665 | struct intel_context *ctx) |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 666 | { |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 667 | int ret, i; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 668 | struct drm_device *dev = ring->dev; |
| 669 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 670 | struct i915_workarounds *w = &dev_priv->workarounds; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 671 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 672 | if (WARN_ON(w->count == 0)) |
| 673 | return 0; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 674 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 675 | ring->gpu_caches_dirty = true; |
| 676 | ret = intel_ring_flush_all_caches(ring); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 677 | if (ret) |
| 678 | return ret; |
| 679 | |
Arun Siluvery | 22a916a | 2014-10-22 18:59:52 +0100 | [diff] [blame] | 680 | ret = intel_ring_begin(ring, (w->count * 2 + 2)); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 681 | if (ret) |
| 682 | return ret; |
| 683 | |
Arun Siluvery | 22a916a | 2014-10-22 18:59:52 +0100 | [diff] [blame] | 684 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 685 | for (i = 0; i < w->count; i++) { |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 686 | intel_ring_emit(ring, w->reg[i].addr); |
| 687 | intel_ring_emit(ring, w->reg[i].value); |
| 688 | } |
Arun Siluvery | 22a916a | 2014-10-22 18:59:52 +0100 | [diff] [blame] | 689 | intel_ring_emit(ring, MI_NOOP); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 690 | |
| 691 | intel_ring_advance(ring); |
| 692 | |
| 693 | ring->gpu_caches_dirty = true; |
| 694 | ret = intel_ring_flush_all_caches(ring); |
| 695 | if (ret) |
| 696 | return ret; |
| 697 | |
| 698 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
| 699 | |
| 700 | return 0; |
| 701 | } |
| 702 | |
| 703 | static int wa_add(struct drm_i915_private *dev_priv, |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 704 | const u32 addr, const u32 mask, const u32 val) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 705 | { |
| 706 | const u32 idx = dev_priv->workarounds.count; |
| 707 | |
| 708 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) |
| 709 | return -ENOSPC; |
| 710 | |
| 711 | dev_priv->workarounds.reg[idx].addr = addr; |
| 712 | dev_priv->workarounds.reg[idx].value = val; |
| 713 | dev_priv->workarounds.reg[idx].mask = mask; |
| 714 | |
| 715 | dev_priv->workarounds.count++; |
| 716 | |
| 717 | return 0; |
| 718 | } |
| 719 | |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 720 | #define WA_REG(addr, mask, val) { \ |
| 721 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 722 | if (r) \ |
| 723 | return r; \ |
| 724 | } |
| 725 | |
| 726 | #define WA_SET_BIT_MASKED(addr, mask) \ |
Damien Lespiau | 2645934 | 2014-12-08 17:35:38 +0000 | [diff] [blame^] | 727 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 728 | |
| 729 | #define WA_CLR_BIT_MASKED(addr, mask) \ |
Damien Lespiau | 2645934 | 2014-12-08 17:35:38 +0000 | [diff] [blame^] | 730 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 731 | |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 732 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 733 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 734 | |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 735 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
| 736 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 737 | |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 738 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 739 | |
| 740 | static int bdw_init_workarounds(struct intel_engine_cs *ring) |
| 741 | { |
| 742 | struct drm_device *dev = ring->dev; |
| 743 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 744 | |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 745 | /* WaDisablePartialInstShootdown:bdw */ |
Rodrigo Vivi | 101b376 | 2014-10-09 07:11:47 -0700 | [diff] [blame] | 746 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 747 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
| 748 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | |
| 749 | STALL_DOP_GATING_DISABLE); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 750 | |
Rodrigo Vivi | 101b376 | 2014-10-09 07:11:47 -0700 | [diff] [blame] | 751 | /* WaDisableDopClockGating:bdw */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 752 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
| 753 | DOP_CLOCK_GATING_DISABLE); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 754 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 755 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
| 756 | GEN8_SAMPLER_POWER_BYPASS_DIS); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 757 | |
| 758 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
| 759 | * workaround for for a possible hang in the unlikely event a TLB |
| 760 | * invalidation occurs during a PSD flush. |
| 761 | */ |
Rodrigo Vivi | da09654 | 2014-09-19 20:16:27 -0400 | [diff] [blame] | 762 | /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 763 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
| 764 | HDC_FORCE_NON_COHERENT | |
| 765 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 766 | |
| 767 | /* Wa4x4STCOptimizationDisable:bdw */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 768 | WA_SET_BIT_MASKED(CACHE_MODE_1, |
| 769 | GEN8_4x4_STC_OPTIMIZATION_DISABLE); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 770 | |
| 771 | /* |
| 772 | * BSpec recommends 8x4 when MSAA is used, |
| 773 | * however in practice 16x4 seems fastest. |
| 774 | * |
| 775 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 776 | * disable bit, which we don't touch here, but it's good |
| 777 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
| 778 | */ |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 779 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, |
| 780 | GEN6_WIZ_HASHING_MASK, |
| 781 | GEN6_WIZ_HASHING_16x4); |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 782 | |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 783 | return 0; |
| 784 | } |
| 785 | |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 786 | static int chv_init_workarounds(struct intel_engine_cs *ring) |
| 787 | { |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 788 | struct drm_device *dev = ring->dev; |
| 789 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 790 | |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 791 | /* WaDisablePartialInstShootdown:chv */ |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 792 | /* WaDisableThreadStallDopClockGating:chv */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 793 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
Arun Siluvery | 605f143 | 2014-10-28 18:33:13 +0000 | [diff] [blame] | 794 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | |
| 795 | STALL_DOP_GATING_DISABLE); |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 796 | |
Arun Siluvery | 95289009 | 2014-10-28 18:33:14 +0000 | [diff] [blame] | 797 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
| 798 | * workaround for a possible hang in the unlikely event a TLB |
| 799 | * invalidation occurs during a PSD flush. |
| 800 | */ |
| 801 | /* WaForceEnableNonCoherent:chv */ |
| 802 | /* WaHdcDisableFetchWhenMasked:chv */ |
| 803 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
| 804 | HDC_FORCE_NON_COHERENT | |
| 805 | HDC_DONOT_FETCH_MEM_WHEN_MASKED); |
| 806 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 807 | return 0; |
| 808 | } |
| 809 | |
Michel Thierry | 771b9a5 | 2014-11-11 16:47:33 +0000 | [diff] [blame] | 810 | int init_workarounds_ring(struct intel_engine_cs *ring) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 811 | { |
| 812 | struct drm_device *dev = ring->dev; |
| 813 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 814 | |
| 815 | WARN_ON(ring->id != RCS); |
| 816 | |
| 817 | dev_priv->workarounds.count = 0; |
| 818 | |
| 819 | if (IS_BROADWELL(dev)) |
| 820 | return bdw_init_workarounds(ring); |
| 821 | |
| 822 | if (IS_CHERRYVIEW(dev)) |
| 823 | return chv_init_workarounds(ring); |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 824 | |
| 825 | return 0; |
| 826 | } |
| 827 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 828 | static int init_render_ring(struct intel_engine_cs *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 829 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 830 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 831 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 832 | int ret = init_ring_common(ring); |
Konrad Zapalowicz | 9c33baa | 2014-06-19 19:07:15 +0200 | [diff] [blame] | 833 | if (ret) |
| 834 | return ret; |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 835 | |
Akash Goel | 61a563a | 2014-03-25 18:01:50 +0530 | [diff] [blame] | 836 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
| 837 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 838 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 839 | |
| 840 | /* We need to disable the AsyncFlip performance optimisations in order |
| 841 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 842 | * programmed to '1' on all products. |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 843 | * |
Ville Syrjälä | b3f797a | 2014-04-28 14:31:09 +0300 | [diff] [blame] | 844 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 845 | */ |
Imre Deak | fbdcb06 | 2013-02-13 15:27:34 +0000 | [diff] [blame] | 846 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9) |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 847 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 848 | |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 849 | /* Required for the hardware to program scanline values for waiting */ |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 850 | /* WaEnableFlushTlbInvalidationMode:snb */ |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 851 | if (INTEL_INFO(dev)->gen == 6) |
| 852 | I915_WRITE(GFX_MODE, |
Chris Wilson | aa83e30 | 2014-03-21 17:18:54 +0000 | [diff] [blame] | 853 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 854 | |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 855 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 856 | if (IS_GEN7(dev)) |
| 857 | I915_WRITE(GFX_MODE_GEN7, |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 858 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 859 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 860 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 861 | if (INTEL_INFO(dev)->gen >= 5) { |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 862 | ret = intel_init_pipe_control(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 863 | if (ret) |
| 864 | return ret; |
| 865 | } |
| 866 | |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 867 | if (IS_GEN6(dev)) { |
Kenneth Graunke | 3a69ddd | 2012-04-27 12:44:41 -0700 | [diff] [blame] | 868 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 869 | * "If this bit is set, STCunit will have LRA as replacement |
| 870 | * policy. [...] This bit must be reset. LRA replacement |
| 871 | * policy is not supported." |
| 872 | */ |
| 873 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 874 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 875 | } |
| 876 | |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 877 | if (INTEL_INFO(dev)->gen >= 6) |
| 878 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 879 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 880 | if (HAS_L3_DPF(dev)) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 881 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 882 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 883 | return init_workarounds_ring(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 884 | } |
| 885 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 886 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 887 | { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 888 | struct drm_device *dev = ring->dev; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 889 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 890 | |
| 891 | if (dev_priv->semaphore_obj) { |
| 892 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); |
| 893 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); |
| 894 | dev_priv->semaphore_obj = NULL; |
| 895 | } |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 896 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 897 | intel_fini_pipe_control(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 898 | } |
| 899 | |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 900 | static int gen8_rcs_signal(struct intel_engine_cs *signaller, |
| 901 | unsigned int num_dwords) |
| 902 | { |
| 903 | #define MBOX_UPDATE_DWORDS 8 |
| 904 | struct drm_device *dev = signaller->dev; |
| 905 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 906 | struct intel_engine_cs *waiter; |
| 907 | int i, ret, num_rings; |
| 908 | |
| 909 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 910 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
| 911 | #undef MBOX_UPDATE_DWORDS |
| 912 | |
| 913 | ret = intel_ring_begin(signaller, num_dwords); |
| 914 | if (ret) |
| 915 | return ret; |
| 916 | |
| 917 | for_each_ring(waiter, dev_priv, i) { |
| 918 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
| 919 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
| 920 | continue; |
| 921 | |
| 922 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
| 923 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | |
| 924 | PIPE_CONTROL_QW_WRITE | |
| 925 | PIPE_CONTROL_FLUSH_ENABLE); |
| 926 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); |
| 927 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
| 928 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); |
| 929 | intel_ring_emit(signaller, 0); |
| 930 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
| 931 | MI_SEMAPHORE_TARGET(waiter->id)); |
| 932 | intel_ring_emit(signaller, 0); |
| 933 | } |
| 934 | |
| 935 | return 0; |
| 936 | } |
| 937 | |
| 938 | static int gen8_xcs_signal(struct intel_engine_cs *signaller, |
| 939 | unsigned int num_dwords) |
| 940 | { |
| 941 | #define MBOX_UPDATE_DWORDS 6 |
| 942 | struct drm_device *dev = signaller->dev; |
| 943 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 944 | struct intel_engine_cs *waiter; |
| 945 | int i, ret, num_rings; |
| 946 | |
| 947 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 948 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
| 949 | #undef MBOX_UPDATE_DWORDS |
| 950 | |
| 951 | ret = intel_ring_begin(signaller, num_dwords); |
| 952 | if (ret) |
| 953 | return ret; |
| 954 | |
| 955 | for_each_ring(waiter, dev_priv, i) { |
| 956 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
| 957 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
| 958 | continue; |
| 959 | |
| 960 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
| 961 | MI_FLUSH_DW_OP_STOREDW); |
| 962 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | |
| 963 | MI_FLUSH_DW_USE_GTT); |
| 964 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
| 965 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); |
| 966 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
| 967 | MI_SEMAPHORE_TARGET(waiter->id)); |
| 968 | intel_ring_emit(signaller, 0); |
| 969 | } |
| 970 | |
| 971 | return 0; |
| 972 | } |
| 973 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 974 | static int gen6_signal(struct intel_engine_cs *signaller, |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 975 | unsigned int num_dwords) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 976 | { |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 977 | struct drm_device *dev = signaller->dev; |
| 978 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 979 | struct intel_engine_cs *useless; |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 980 | int i, ret, num_rings; |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 981 | |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 982 | #define MBOX_UPDATE_DWORDS 3 |
| 983 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 984 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); |
| 985 | #undef MBOX_UPDATE_DWORDS |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 986 | |
| 987 | ret = intel_ring_begin(signaller, num_dwords); |
| 988 | if (ret) |
| 989 | return ret; |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 990 | |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 991 | for_each_ring(useless, dev_priv, i) { |
| 992 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; |
| 993 | if (mbox_reg != GEN6_NOSYNC) { |
| 994 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
| 995 | intel_ring_emit(signaller, mbox_reg); |
| 996 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 997 | } |
| 998 | } |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 999 | |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 1000 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
| 1001 | if (num_rings % 2 == 0) |
| 1002 | intel_ring_emit(signaller, MI_NOOP); |
| 1003 | |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1004 | return 0; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1005 | } |
| 1006 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1007 | /** |
| 1008 | * gen6_add_request - Update the semaphore mailbox registers |
| 1009 | * |
| 1010 | * @ring - ring that is adding a request |
| 1011 | * @seqno - return seqno stuck into the ring |
| 1012 | * |
| 1013 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 1014 | * This acts like a signal in the canonical semaphore. |
| 1015 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1016 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1017 | gen6_add_request(struct intel_engine_cs *ring) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1018 | { |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1019 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1020 | |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 1021 | if (ring->semaphore.signal) |
| 1022 | ret = ring->semaphore.signal(ring, 4); |
| 1023 | else |
| 1024 | ret = intel_ring_begin(ring, 4); |
| 1025 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1026 | if (ret) |
| 1027 | return ret; |
| 1028 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1029 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 1030 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1031 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1032 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1033 | __intel_ring_advance(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1034 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1035 | return 0; |
| 1036 | } |
| 1037 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1038 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
| 1039 | u32 seqno) |
| 1040 | { |
| 1041 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1042 | return dev_priv->last_seqno < seqno; |
| 1043 | } |
| 1044 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1045 | /** |
| 1046 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 1047 | * |
| 1048 | * @waiter - ring that is waiting |
| 1049 | * @signaller - ring which has, or will signal |
| 1050 | * @seqno - seqno which the waiter will block on |
| 1051 | */ |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1052 | |
| 1053 | static int |
| 1054 | gen8_ring_sync(struct intel_engine_cs *waiter, |
| 1055 | struct intel_engine_cs *signaller, |
| 1056 | u32 seqno) |
| 1057 | { |
| 1058 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; |
| 1059 | int ret; |
| 1060 | |
| 1061 | ret = intel_ring_begin(waiter, 4); |
| 1062 | if (ret) |
| 1063 | return ret; |
| 1064 | |
| 1065 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | |
| 1066 | MI_SEMAPHORE_GLOBAL_GTT | |
Ben Widawsky | bae4fcd | 2014-06-30 09:53:43 -0700 | [diff] [blame] | 1067 | MI_SEMAPHORE_POLL | |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1068 | MI_SEMAPHORE_SAD_GTE_SDD); |
| 1069 | intel_ring_emit(waiter, seqno); |
| 1070 | intel_ring_emit(waiter, |
| 1071 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); |
| 1072 | intel_ring_emit(waiter, |
| 1073 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); |
| 1074 | intel_ring_advance(waiter); |
| 1075 | return 0; |
| 1076 | } |
| 1077 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1078 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1079 | gen6_ring_sync(struct intel_engine_cs *waiter, |
| 1080 | struct intel_engine_cs *signaller, |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1081 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1082 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1083 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 1084 | MI_SEMAPHORE_COMPARE | |
| 1085 | MI_SEMAPHORE_REGISTER; |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1086 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
| 1087 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1088 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 1089 | /* Throughout all of the GEM code, seqno passed implies our current |
| 1090 | * seqno is >= the last seqno executed. However for hardware the |
| 1091 | * comparison is strictly greater than. |
| 1092 | */ |
| 1093 | seqno -= 1; |
| 1094 | |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1095 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1096 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1097 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1098 | if (ret) |
| 1099 | return ret; |
| 1100 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1101 | /* If seqno wrap happened, omit the wait with no-ops */ |
| 1102 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1103 | intel_ring_emit(waiter, dw1 | wait_mbox); |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1104 | intel_ring_emit(waiter, seqno); |
| 1105 | intel_ring_emit(waiter, 0); |
| 1106 | intel_ring_emit(waiter, MI_NOOP); |
| 1107 | } else { |
| 1108 | intel_ring_emit(waiter, MI_NOOP); |
| 1109 | intel_ring_emit(waiter, MI_NOOP); |
| 1110 | intel_ring_emit(waiter, MI_NOOP); |
| 1111 | intel_ring_emit(waiter, MI_NOOP); |
| 1112 | } |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1113 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1114 | |
| 1115 | return 0; |
| 1116 | } |
| 1117 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1118 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 1119 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 1120 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 1121 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1122 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 1123 | intel_ring_emit(ring__, 0); \ |
| 1124 | intel_ring_emit(ring__, 0); \ |
| 1125 | } while (0) |
| 1126 | |
| 1127 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1128 | pc_render_add_request(struct intel_engine_cs *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1129 | { |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1130 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1131 | int ret; |
| 1132 | |
| 1133 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 1134 | * incoherent with writes to memory, i.e. completely fubar, |
| 1135 | * so we need to use PIPE_NOTIFY instead. |
| 1136 | * |
| 1137 | * However, we also need to workaround the qword write |
| 1138 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 1139 | * memory before requesting an interrupt. |
| 1140 | */ |
| 1141 | ret = intel_ring_begin(ring, 32); |
| 1142 | if (ret) |
| 1143 | return ret; |
| 1144 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 1145 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 1146 | PIPE_CONTROL_WRITE_FLUSH | |
| 1147 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1148 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1149 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1150 | intel_ring_emit(ring, 0); |
| 1151 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1152 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1153 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1154 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1155 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1156 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1157 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1158 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1159 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1160 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1161 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1162 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 1163 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 1164 | PIPE_CONTROL_WRITE_FLUSH | |
| 1165 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1166 | PIPE_CONTROL_NOTIFY); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1167 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1168 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1169 | intel_ring_emit(ring, 0); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1170 | __intel_ring_advance(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1171 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1172 | return 0; |
| 1173 | } |
| 1174 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1175 | static u32 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1176 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1177 | { |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1178 | /* Workaround to force correct ordering between irq and seqno writes on |
| 1179 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 1180 | * ACTHD) before reading the status page. */ |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 1181 | if (!lazy_coherency) { |
| 1182 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1183 | POSTING_READ(RING_ACTHD(ring->mmio_base)); |
| 1184 | } |
| 1185 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1186 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 1187 | } |
| 1188 | |
| 1189 | static u32 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1190 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1191 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1192 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 1193 | } |
| 1194 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1195 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1196 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1197 | { |
| 1198 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
| 1199 | } |
| 1200 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1201 | static u32 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1202 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1203 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1204 | return ring->scratch.cpu_page[0]; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1205 | } |
| 1206 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1207 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1208 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1209 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1210 | ring->scratch.cpu_page[0] = seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1211 | } |
| 1212 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1213 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1214 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1215 | { |
| 1216 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1217 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1218 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1219 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1220 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1221 | return false; |
| 1222 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1223 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1224 | if (ring->irq_refcount++ == 0) |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1225 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1226 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1227 | |
| 1228 | return true; |
| 1229 | } |
| 1230 | |
| 1231 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1232 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1233 | { |
| 1234 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1235 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1236 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1237 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1238 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1239 | if (--ring->irq_refcount == 0) |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1240 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1241 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1242 | } |
| 1243 | |
| 1244 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1245 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1246 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1247 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1248 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1249 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1250 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1251 | if (!intel_irqs_enabled(dev_priv)) |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1252 | return false; |
| 1253 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1254 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1255 | if (ring->irq_refcount++ == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 1256 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 1257 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 1258 | POSTING_READ(IMR); |
| 1259 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1260 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1261 | |
| 1262 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1263 | } |
| 1264 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1265 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1266 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1267 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1268 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1269 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1270 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1271 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1272 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1273 | if (--ring->irq_refcount == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 1274 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 1275 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 1276 | POSTING_READ(IMR); |
| 1277 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1278 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1279 | } |
| 1280 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1281 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1282 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1283 | { |
| 1284 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1285 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1286 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1287 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1288 | if (!intel_irqs_enabled(dev_priv)) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1289 | return false; |
| 1290 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1291 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1292 | if (ring->irq_refcount++ == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1293 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 1294 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 1295 | POSTING_READ16(IMR); |
| 1296 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1297 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1298 | |
| 1299 | return true; |
| 1300 | } |
| 1301 | |
| 1302 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1303 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1304 | { |
| 1305 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1306 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1307 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1308 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1309 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1310 | if (--ring->irq_refcount == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1311 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 1312 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 1313 | POSTING_READ16(IMR); |
| 1314 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1315 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1316 | } |
| 1317 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1318 | void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1319 | { |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1320 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1321 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1322 | u32 mmio = 0; |
| 1323 | |
| 1324 | /* The ring status page addresses are no longer next to the rest of |
| 1325 | * the ring registers as of gen7. |
| 1326 | */ |
| 1327 | if (IS_GEN7(dev)) { |
| 1328 | switch (ring->id) { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 1329 | case RCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1330 | mmio = RENDER_HWS_PGA_GEN7; |
| 1331 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 1332 | case BCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1333 | mmio = BLT_HWS_PGA_GEN7; |
| 1334 | break; |
Zhao Yakui | 77fe2ff | 2014-04-17 10:37:39 +0800 | [diff] [blame] | 1335 | /* |
| 1336 | * VCS2 actually doesn't exist on Gen7. Only shut up |
| 1337 | * gcc switch check warning |
| 1338 | */ |
| 1339 | case VCS2: |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 1340 | case VCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1341 | mmio = BSD_HWS_PGA_GEN7; |
| 1342 | break; |
Ben Widawsky | 4a3dd19 | 2013-05-28 19:22:19 -0700 | [diff] [blame] | 1343 | case VECS: |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 1344 | mmio = VEBOX_HWS_PGA_GEN7; |
| 1345 | break; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1346 | } |
| 1347 | } else if (IS_GEN6(ring->dev)) { |
| 1348 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 1349 | } else { |
Ben Widawsky | eb0d4b7 | 2013-11-07 21:40:50 -0800 | [diff] [blame] | 1350 | /* XXX: gen8 returns to sanity */ |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1351 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 1352 | } |
| 1353 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1354 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 1355 | POSTING_READ(mmio); |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1356 | |
Damien Lespiau | dc616b8 | 2014-03-13 01:40:28 +0000 | [diff] [blame] | 1357 | /* |
| 1358 | * Flush the TLB for this page |
| 1359 | * |
| 1360 | * FIXME: These two bits have disappeared on gen8, so a question |
| 1361 | * arises: do we still need this and if so how should we go about |
| 1362 | * invalidating the TLB? |
| 1363 | */ |
| 1364 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1365 | u32 reg = RING_INSTPM(ring->mmio_base); |
Naresh Kumar Kachhi | 02f6a1e | 2014-03-12 16:39:42 +0530 | [diff] [blame] | 1366 | |
| 1367 | /* ring should be idle before issuing a sync flush*/ |
| 1368 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); |
| 1369 | |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1370 | I915_WRITE(reg, |
| 1371 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | |
| 1372 | INSTPM_SYNC_FLUSH)); |
| 1373 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, |
| 1374 | 1000)) |
| 1375 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
| 1376 | ring->name); |
| 1377 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1378 | } |
| 1379 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1380 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1381 | bsd_ring_flush(struct intel_engine_cs *ring, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1382 | u32 invalidate_domains, |
| 1383 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1384 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1385 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1386 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1387 | ret = intel_ring_begin(ring, 2); |
| 1388 | if (ret) |
| 1389 | return ret; |
| 1390 | |
| 1391 | intel_ring_emit(ring, MI_FLUSH); |
| 1392 | intel_ring_emit(ring, MI_NOOP); |
| 1393 | intel_ring_advance(ring); |
| 1394 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1395 | } |
| 1396 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1397 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1398 | i9xx_add_request(struct intel_engine_cs *ring) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1399 | { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1400 | int ret; |
| 1401 | |
| 1402 | ret = intel_ring_begin(ring, 4); |
| 1403 | if (ret) |
| 1404 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 1405 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1406 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 1407 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1408 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1409 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1410 | __intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1411 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1412 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1413 | } |
| 1414 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1415 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1416 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1417 | { |
| 1418 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1419 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1420 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1421 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1422 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
| 1423 | return false; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1424 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1425 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1426 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1427 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1428 | I915_WRITE_IMR(ring, |
| 1429 | ~(ring->irq_enable_mask | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1430 | GT_PARITY_ERROR(dev))); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1431 | else |
| 1432 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1433 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1434 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1435 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1436 | |
| 1437 | return true; |
| 1438 | } |
| 1439 | |
| 1440 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1441 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1442 | { |
| 1443 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1444 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1445 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1446 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1447 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1448 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1449 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1450 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1451 | else |
| 1452 | I915_WRITE_IMR(ring, ~0); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1453 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1454 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1455 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1456 | } |
| 1457 | |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1458 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1459 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1460 | { |
| 1461 | struct drm_device *dev = ring->dev; |
| 1462 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1463 | unsigned long flags; |
| 1464 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1465 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1466 | return false; |
| 1467 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1468 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1469 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1470 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1471 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1472 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1473 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1474 | |
| 1475 | return true; |
| 1476 | } |
| 1477 | |
| 1478 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1479 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1480 | { |
| 1481 | struct drm_device *dev = ring->dev; |
| 1482 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1483 | unsigned long flags; |
| 1484 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1485 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1486 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1487 | I915_WRITE_IMR(ring, ~0); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1488 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1489 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1490 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1491 | } |
| 1492 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1493 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1494 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1495 | { |
| 1496 | struct drm_device *dev = ring->dev; |
| 1497 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1498 | unsigned long flags; |
| 1499 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1500 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1501 | return false; |
| 1502 | |
| 1503 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1504 | if (ring->irq_refcount++ == 0) { |
| 1505 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1506 | I915_WRITE_IMR(ring, |
| 1507 | ~(ring->irq_enable_mask | |
| 1508 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
| 1509 | } else { |
| 1510 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
| 1511 | } |
| 1512 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1513 | } |
| 1514 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1515 | |
| 1516 | return true; |
| 1517 | } |
| 1518 | |
| 1519 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1520 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1521 | { |
| 1522 | struct drm_device *dev = ring->dev; |
| 1523 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1524 | unsigned long flags; |
| 1525 | |
| 1526 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1527 | if (--ring->irq_refcount == 0) { |
| 1528 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1529 | I915_WRITE_IMR(ring, |
| 1530 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
| 1531 | } else { |
| 1532 | I915_WRITE_IMR(ring, ~0); |
| 1533 | } |
| 1534 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1535 | } |
| 1536 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1537 | } |
| 1538 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1539 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1540 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 1541 | u64 offset, u32 length, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1542 | unsigned flags) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1543 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1544 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1545 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1546 | ret = intel_ring_begin(ring, 2); |
| 1547 | if (ret) |
| 1548 | return ret; |
| 1549 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1550 | intel_ring_emit(ring, |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1551 | MI_BATCH_BUFFER_START | |
| 1552 | MI_BATCH_GTT | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1553 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1554 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1555 | intel_ring_advance(ring); |
| 1556 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1557 | return 0; |
| 1558 | } |
| 1559 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1560 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| 1561 | #define I830_BATCH_LIMIT (256*1024) |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1562 | #define I830_TLB_ENTRIES (2) |
| 1563 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1564 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1565 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 1566 | u64 offset, u32 len, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1567 | unsigned flags) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1568 | { |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1569 | u32 cs_offset = ring->scratch.gtt_offset; |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1570 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1571 | |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1572 | ret = intel_ring_begin(ring, 6); |
| 1573 | if (ret) |
| 1574 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1575 | |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1576 | /* Evict the invalid PTE TLBs */ |
| 1577 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
| 1578 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); |
| 1579 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ |
| 1580 | intel_ring_emit(ring, cs_offset); |
| 1581 | intel_ring_emit(ring, 0xdeadbeef); |
| 1582 | intel_ring_emit(ring, MI_NOOP); |
| 1583 | intel_ring_advance(ring); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1584 | |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1585 | if ((flags & I915_DISPATCH_PINNED) == 0) { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1586 | if (len > I830_BATCH_LIMIT) |
| 1587 | return -ENOSPC; |
| 1588 | |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1589 | ret = intel_ring_begin(ring, 6 + 2); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1590 | if (ret) |
| 1591 | return ret; |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1592 | |
| 1593 | /* Blit the batch (which has now all relocs applied) to the |
| 1594 | * stable batch scratch bo area (so that the CS never |
| 1595 | * stumbles over its tlb invalidation bug) ... |
| 1596 | */ |
| 1597 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
| 1598 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); |
Chris Wilson | 611a7a4 | 2014-09-12 07:37:42 +0100 | [diff] [blame] | 1599 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1600 | intel_ring_emit(ring, cs_offset); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1601 | intel_ring_emit(ring, 4096); |
| 1602 | intel_ring_emit(ring, offset); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1603 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1604 | intel_ring_emit(ring, MI_FLUSH); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1605 | intel_ring_emit(ring, MI_NOOP); |
| 1606 | intel_ring_advance(ring); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1607 | |
| 1608 | /* ... and execute it. */ |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1609 | offset = cs_offset; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1610 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1611 | |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1612 | ret = intel_ring_begin(ring, 4); |
| 1613 | if (ret) |
| 1614 | return ret; |
| 1615 | |
| 1616 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1617 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1618 | intel_ring_emit(ring, offset + len - 8); |
| 1619 | intel_ring_emit(ring, MI_NOOP); |
| 1620 | intel_ring_advance(ring); |
| 1621 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1622 | return 0; |
| 1623 | } |
| 1624 | |
| 1625 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1626 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 1627 | u64 offset, u32 len, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1628 | unsigned flags) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1629 | { |
| 1630 | int ret; |
| 1631 | |
| 1632 | ret = intel_ring_begin(ring, 2); |
| 1633 | if (ret) |
| 1634 | return ret; |
| 1635 | |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1636 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1637 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1638 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1639 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1640 | return 0; |
| 1641 | } |
| 1642 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1643 | static void cleanup_status_page(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1644 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1645 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1646 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1647 | obj = ring->status_page.obj; |
| 1648 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1649 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1650 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1651 | kunmap(sg_page(obj->pages->sgl)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1652 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1653 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1654 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1655 | } |
| 1656 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1657 | static int init_status_page(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1658 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1659 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1660 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1661 | if ((obj = ring->status_page.obj) == NULL) { |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 1662 | unsigned flags; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1663 | int ret; |
| 1664 | |
| 1665 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 1666 | if (obj == NULL) { |
| 1667 | DRM_ERROR("Failed to allocate status page\n"); |
| 1668 | return -ENOMEM; |
| 1669 | } |
| 1670 | |
| 1671 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 1672 | if (ret) |
| 1673 | goto err_unref; |
| 1674 | |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 1675 | flags = 0; |
| 1676 | if (!HAS_LLC(ring->dev)) |
| 1677 | /* On g33, we cannot place HWS above 256MiB, so |
| 1678 | * restrict its pinning to the low mappable arena. |
| 1679 | * Though this restriction is not documented for |
| 1680 | * gen4, gen5, or byt, they also behave similarly |
| 1681 | * and hang if the HWS is placed at the top of the |
| 1682 | * GTT. To generalise, it appears that all !llc |
| 1683 | * platforms have issues with us placing the HWS |
| 1684 | * above the mappable region (even though we never |
| 1685 | * actualy map it). |
| 1686 | */ |
| 1687 | flags |= PIN_MAPPABLE; |
| 1688 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1689 | if (ret) { |
| 1690 | err_unref: |
| 1691 | drm_gem_object_unreference(&obj->base); |
| 1692 | return ret; |
| 1693 | } |
| 1694 | |
| 1695 | ring->status_page.obj = obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1696 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 1697 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1698 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1699 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1700 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1701 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1702 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 1703 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1704 | |
| 1705 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1706 | } |
| 1707 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1708 | static int init_phys_status_page(struct intel_engine_cs *ring) |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1709 | { |
| 1710 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1711 | |
| 1712 | if (!dev_priv->status_page_dmah) { |
| 1713 | dev_priv->status_page_dmah = |
| 1714 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); |
| 1715 | if (!dev_priv->status_page_dmah) |
| 1716 | return -ENOMEM; |
| 1717 | } |
| 1718 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1719 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1720 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1721 | |
| 1722 | return 0; |
| 1723 | } |
| 1724 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1725 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
| 1726 | { |
| 1727 | iounmap(ringbuf->virtual_start); |
| 1728 | ringbuf->virtual_start = NULL; |
| 1729 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
| 1730 | } |
| 1731 | |
| 1732 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
| 1733 | struct intel_ringbuffer *ringbuf) |
| 1734 | { |
| 1735 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 1736 | struct drm_i915_gem_object *obj = ringbuf->obj; |
| 1737 | int ret; |
| 1738 | |
| 1739 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
| 1740 | if (ret) |
| 1741 | return ret; |
| 1742 | |
| 1743 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 1744 | if (ret) { |
| 1745 | i915_gem_object_ggtt_unpin(obj); |
| 1746 | return ret; |
| 1747 | } |
| 1748 | |
| 1749 | ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + |
| 1750 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); |
| 1751 | if (ringbuf->virtual_start == NULL) { |
| 1752 | i915_gem_object_ggtt_unpin(obj); |
| 1753 | return -EINVAL; |
| 1754 | } |
| 1755 | |
| 1756 | return 0; |
| 1757 | } |
| 1758 | |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1759 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1760 | { |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 1761 | drm_gem_object_unreference(&ringbuf->obj->base); |
| 1762 | ringbuf->obj = NULL; |
| 1763 | } |
| 1764 | |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1765 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
| 1766 | struct intel_ringbuffer *ringbuf) |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 1767 | { |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1768 | struct drm_i915_gem_object *obj; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1769 | |
| 1770 | obj = NULL; |
| 1771 | if (!HAS_LLC(dev)) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1772 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1773 | if (obj == NULL) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1774 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1775 | if (obj == NULL) |
| 1776 | return -ENOMEM; |
| 1777 | |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1778 | /* mark ring buffers as read-only from GPU side by default */ |
| 1779 | obj->gt_ro = 1; |
| 1780 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1781 | ringbuf->obj = obj; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1782 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1783 | return 0; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1784 | } |
| 1785 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1786 | static int intel_init_ring_buffer(struct drm_device *dev, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1787 | struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1788 | { |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1789 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1790 | int ret; |
| 1791 | |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1792 | if (ringbuf == NULL) { |
| 1793 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
| 1794 | if (!ringbuf) |
| 1795 | return -ENOMEM; |
| 1796 | ring->buffer = ringbuf; |
| 1797 | } |
| 1798 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1799 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1800 | INIT_LIST_HEAD(&ring->active_list); |
| 1801 | INIT_LIST_HEAD(&ring->request_list); |
Oscar Mateo | cc9130b | 2014-07-24 17:04:42 +0100 | [diff] [blame] | 1802 | INIT_LIST_HEAD(&ring->execlist_queue); |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1803 | ringbuf->size = 32 * PAGE_SIZE; |
Daniel Vetter | 0c7dd53 | 2014-08-11 16:17:44 +0200 | [diff] [blame] | 1804 | ringbuf->ring = ring; |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1805 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 1806 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 1807 | init_waitqueue_head(&ring->irq_queue); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1808 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1809 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1810 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1811 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1812 | goto error; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1813 | } else { |
| 1814 | BUG_ON(ring->id != RCS); |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 1815 | ret = init_phys_status_page(ring); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1816 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1817 | goto error; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1818 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1819 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1820 | if (ringbuf->obj == NULL) { |
| 1821 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
| 1822 | if (ret) { |
| 1823 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", |
| 1824 | ring->name, ret); |
| 1825 | goto error; |
| 1826 | } |
| 1827 | |
| 1828 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); |
| 1829 | if (ret) { |
| 1830 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", |
| 1831 | ring->name, ret); |
| 1832 | intel_destroy_ringbuffer_obj(ringbuf); |
| 1833 | goto error; |
| 1834 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1835 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1836 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1837 | /* Workaround an erratum on the i830 which causes a hang if |
| 1838 | * the TAIL pointer points to within the last 2 cachelines |
| 1839 | * of the buffer. |
| 1840 | */ |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1841 | ringbuf->effective_size = ringbuf->size; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1842 | if (IS_I830(dev) || IS_845G(dev)) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1843 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1844 | |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 1845 | ret = i915_cmd_parser_init_ring(ring); |
| 1846 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1847 | goto error; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 1848 | |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1849 | ret = ring->init(ring); |
| 1850 | if (ret) |
| 1851 | goto error; |
| 1852 | |
| 1853 | return 0; |
| 1854 | |
| 1855 | error: |
| 1856 | kfree(ringbuf); |
| 1857 | ring->buffer = NULL; |
| 1858 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1859 | } |
| 1860 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1861 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1862 | { |
John Harrison | 6402c33 | 2014-10-31 12:00:26 +0000 | [diff] [blame] | 1863 | struct drm_i915_private *dev_priv; |
| 1864 | struct intel_ringbuffer *ringbuf; |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1865 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1866 | if (!intel_ring_initialized(ring)) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1867 | return; |
| 1868 | |
John Harrison | 6402c33 | 2014-10-31 12:00:26 +0000 | [diff] [blame] | 1869 | dev_priv = to_i915(ring->dev); |
| 1870 | ringbuf = ring->buffer; |
| 1871 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1872 | intel_stop_ring_buffer(ring); |
Ville Syrjälä | de8f0a5 | 2014-05-28 19:12:13 +0300 | [diff] [blame] | 1873 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1874 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1875 | intel_unpin_ringbuffer_obj(ringbuf); |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 1876 | intel_destroy_ringbuffer_obj(ringbuf); |
Ben Widawsky | 3d57e5b | 2013-10-14 10:01:36 -0700 | [diff] [blame] | 1877 | ring->preallocated_lazy_request = NULL; |
| 1878 | ring->outstanding_lazy_seqno = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1879 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1880 | if (ring->cleanup) |
| 1881 | ring->cleanup(ring); |
| 1882 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1883 | cleanup_status_page(ring); |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 1884 | |
| 1885 | i915_cmd_parser_fini_ring(ring); |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1886 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1887 | kfree(ringbuf); |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1888 | ring->buffer = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1889 | } |
| 1890 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1891 | static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1892 | { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1893 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1894 | struct drm_i915_gem_request *request; |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 1895 | u32 seqno = 0; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1896 | int ret; |
| 1897 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1898 | if (ringbuf->last_retired_head != -1) { |
| 1899 | ringbuf->head = ringbuf->last_retired_head; |
| 1900 | ringbuf->last_retired_head = -1; |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1901 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1902 | ringbuf->space = intel_ring_space(ringbuf); |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1903 | if (ringbuf->space >= n) |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1904 | return 0; |
| 1905 | } |
| 1906 | |
| 1907 | list_for_each_entry(request, &ring->request_list, list) { |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1908 | if (__intel_ring_space(request->tail, ringbuf->tail, |
| 1909 | ringbuf->size) >= n) { |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1910 | seqno = request->seqno; |
| 1911 | break; |
| 1912 | } |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1913 | } |
| 1914 | |
| 1915 | if (seqno == 0) |
| 1916 | return -ENOSPC; |
| 1917 | |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1918 | ret = i915_wait_seqno(ring, seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1919 | if (ret) |
| 1920 | return ret; |
| 1921 | |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 1922 | i915_gem_retire_requests_ring(ring); |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1923 | ringbuf->head = ringbuf->last_retired_head; |
| 1924 | ringbuf->last_retired_head = -1; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1925 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1926 | ringbuf->space = intel_ring_space(ringbuf); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1927 | return 0; |
| 1928 | } |
| 1929 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1930 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1931 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1932 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1933 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1934 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1935 | unsigned long end; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1936 | int ret; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1937 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1938 | ret = intel_ring_wait_request(ring, n); |
| 1939 | if (ret != -ENOSPC) |
| 1940 | return ret; |
| 1941 | |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1942 | /* force the tail write in case we have been skipping them */ |
| 1943 | __intel_ring_advance(ring); |
| 1944 | |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 1945 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1946 | * leaving it early runs the risk of corrupting GEM state (due |
| 1947 | * to running on almost untested codepaths). But on resume |
| 1948 | * timers don't work yet, so prevent a complete hang in that |
| 1949 | * case by choosing an insanely large timeout. */ |
| 1950 | end = jiffies + 60 * HZ; |
Daniel Vetter | e6bfaf8 | 2011-12-14 13:56:59 +0100 | [diff] [blame] | 1951 | |
Chris Wilson | dcfe050 | 2014-05-05 09:07:32 +0100 | [diff] [blame] | 1952 | trace_i915_ring_wait_begin(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1953 | do { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1954 | ringbuf->head = I915_READ_HEAD(ring); |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1955 | ringbuf->space = intel_ring_space(ringbuf); |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1956 | if (ringbuf->space >= n) { |
Chris Wilson | dcfe050 | 2014-05-05 09:07:32 +0100 | [diff] [blame] | 1957 | ret = 0; |
| 1958 | break; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1959 | } |
| 1960 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 1961 | msleep(1); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1962 | |
Chris Wilson | dcfe050 | 2014-05-05 09:07:32 +0100 | [diff] [blame] | 1963 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
| 1964 | ret = -ERESTARTSYS; |
| 1965 | break; |
| 1966 | } |
| 1967 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1968 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1969 | dev_priv->mm.interruptible); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1970 | if (ret) |
Chris Wilson | dcfe050 | 2014-05-05 09:07:32 +0100 | [diff] [blame] | 1971 | break; |
| 1972 | |
| 1973 | if (time_after(jiffies, end)) { |
| 1974 | ret = -EBUSY; |
| 1975 | break; |
| 1976 | } |
| 1977 | } while (1); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1978 | trace_i915_ring_wait_end(ring); |
Chris Wilson | dcfe050 | 2014-05-05 09:07:32 +0100 | [diff] [blame] | 1979 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1980 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1981 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1982 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1983 | { |
| 1984 | uint32_t __iomem *virt; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1985 | struct intel_ringbuffer *ringbuf = ring->buffer; |
| 1986 | int rem = ringbuf->size - ringbuf->tail; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1987 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1988 | if (ringbuf->space < rem) { |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1989 | int ret = ring_wait_for_space(ring, rem); |
| 1990 | if (ret) |
| 1991 | return ret; |
| 1992 | } |
| 1993 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1994 | virt = ringbuf->virtual_start + ringbuf->tail; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1995 | rem /= 4; |
| 1996 | while (rem--) |
| 1997 | iowrite32(MI_NOOP, virt++); |
| 1998 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1999 | ringbuf->tail = 0; |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 2000 | ringbuf->space = intel_ring_space(ringbuf); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2001 | |
| 2002 | return 0; |
| 2003 | } |
| 2004 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2005 | int intel_ring_idle(struct intel_engine_cs *ring) |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2006 | { |
| 2007 | u32 seqno; |
| 2008 | int ret; |
| 2009 | |
| 2010 | /* We need to add any requests required to flush the objects and ring */ |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 2011 | if (ring->outstanding_lazy_seqno) { |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2012 | ret = i915_add_request(ring, NULL); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2013 | if (ret) |
| 2014 | return ret; |
| 2015 | } |
| 2016 | |
| 2017 | /* Wait upon the last request to be completed */ |
| 2018 | if (list_empty(&ring->request_list)) |
| 2019 | return 0; |
| 2020 | |
| 2021 | seqno = list_entry(ring->request_list.prev, |
| 2022 | struct drm_i915_gem_request, |
| 2023 | list)->seqno; |
| 2024 | |
| 2025 | return i915_wait_seqno(ring, seqno); |
| 2026 | } |
| 2027 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2028 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2029 | intel_ring_alloc_seqno(struct intel_engine_cs *ring) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2030 | { |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 2031 | if (ring->outstanding_lazy_seqno) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2032 | return 0; |
| 2033 | |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 2034 | if (ring->preallocated_lazy_request == NULL) { |
| 2035 | struct drm_i915_gem_request *request; |
| 2036 | |
| 2037 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
| 2038 | if (request == NULL) |
| 2039 | return -ENOMEM; |
| 2040 | |
| 2041 | ring->preallocated_lazy_request = request; |
| 2042 | } |
| 2043 | |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 2044 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2045 | } |
| 2046 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2047 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2048 | int bytes) |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2049 | { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2050 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2051 | int ret; |
| 2052 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2053 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2054 | ret = intel_wrap_ring_buffer(ring); |
| 2055 | if (unlikely(ret)) |
| 2056 | return ret; |
| 2057 | } |
| 2058 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2059 | if (unlikely(ringbuf->space < bytes)) { |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2060 | ret = ring_wait_for_space(ring, bytes); |
| 2061 | if (unlikely(ret)) |
| 2062 | return ret; |
| 2063 | } |
| 2064 | |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2065 | return 0; |
| 2066 | } |
| 2067 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2068 | int intel_ring_begin(struct intel_engine_cs *ring, |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2069 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2070 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2071 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2072 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2073 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 2074 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 2075 | dev_priv->mm.interruptible); |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 2076 | if (ret) |
| 2077 | return ret; |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 2078 | |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2079 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
| 2080 | if (ret) |
| 2081 | return ret; |
| 2082 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2083 | /* Preallocate the olr before touching the ring */ |
| 2084 | ret = intel_ring_alloc_seqno(ring); |
| 2085 | if (ret) |
| 2086 | return ret; |
| 2087 | |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 2088 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2089 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2090 | } |
| 2091 | |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2092 | /* Align the ring tail to a cacheline boundary */ |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2093 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2094 | { |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 2095 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2096 | int ret; |
| 2097 | |
| 2098 | if (num_dwords == 0) |
| 2099 | return 0; |
| 2100 | |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 2101 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2102 | ret = intel_ring_begin(ring, num_dwords); |
| 2103 | if (ret) |
| 2104 | return ret; |
| 2105 | |
| 2106 | while (num_dwords--) |
| 2107 | intel_ring_emit(ring, MI_NOOP); |
| 2108 | |
| 2109 | intel_ring_advance(ring); |
| 2110 | |
| 2111 | return 0; |
| 2112 | } |
| 2113 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2114 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2115 | { |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2116 | struct drm_device *dev = ring->dev; |
| 2117 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2118 | |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 2119 | BUG_ON(ring->outstanding_lazy_seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2120 | |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2121 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 2122 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
| 2123 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2124 | if (HAS_VEBOX(dev)) |
Ben Widawsky | 5020150 | 2013-08-12 16:53:03 -0700 | [diff] [blame] | 2125 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2126 | } |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 2127 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 2128 | ring->set_seqno(ring, seqno); |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 2129 | ring->hangcheck.seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2130 | } |
| 2131 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2132 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2133 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2134 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2135 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2136 | |
| 2137 | /* Every tail move must follow the sequence below */ |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2138 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2139 | /* Disable notification that the ring is IDLE. The GT |
| 2140 | * will then assume that it is busy and bring it out of rc6. |
| 2141 | */ |
| 2142 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 2143 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 2144 | |
| 2145 | /* Clear the context id. Here be magic! */ |
| 2146 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
| 2147 | |
| 2148 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2149 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2150 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
| 2151 | 50)) |
| 2152 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2153 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2154 | /* Now that the ring is fully powered up, update the tail */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2155 | I915_WRITE_TAIL(ring, value); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2156 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
| 2157 | |
| 2158 | /* Let the ring send IDLE messages to the GT again, |
| 2159 | * and so let it sleep to conserve power when idle. |
| 2160 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2161 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2162 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2163 | } |
| 2164 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2165 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2166 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2167 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2168 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2169 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2170 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2171 | ret = intel_ring_begin(ring, 4); |
| 2172 | if (ret) |
| 2173 | return ret; |
| 2174 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2175 | cmd = MI_FLUSH_DW; |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2176 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 2177 | cmd += 1; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2178 | /* |
| 2179 | * Bspec vol 1c.5 - video engine command streamer: |
| 2180 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 2181 | * operation is complete. This bit is only valid when the |
| 2182 | * Post-Sync Operation field is a value of 1h or 3h." |
| 2183 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2184 | if (invalidate & I915_GEM_GPU_DOMAINS) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2185 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
| 2186 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2187 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2188 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2189 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 2190 | intel_ring_emit(ring, 0); /* upper addr */ |
| 2191 | intel_ring_emit(ring, 0); /* value */ |
| 2192 | } else { |
| 2193 | intel_ring_emit(ring, 0); |
| 2194 | intel_ring_emit(ring, MI_NOOP); |
| 2195 | } |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2196 | intel_ring_advance(ring); |
| 2197 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2198 | } |
| 2199 | |
| 2200 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2201 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2202 | u64 offset, u32 len, |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2203 | unsigned flags) |
| 2204 | { |
Daniel Vetter | 896ab1a | 2014-08-06 15:04:51 +0200 | [diff] [blame] | 2205 | bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2206 | int ret; |
| 2207 | |
| 2208 | ret = intel_ring_begin(ring, 4); |
| 2209 | if (ret) |
| 2210 | return ret; |
| 2211 | |
| 2212 | /* FIXME(BDW): Address space and security selectors. */ |
Ben Widawsky | 28cf541 | 2013-11-02 21:07:26 -0700 | [diff] [blame] | 2213 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2214 | intel_ring_emit(ring, lower_32_bits(offset)); |
| 2215 | intel_ring_emit(ring, upper_32_bits(offset)); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2216 | intel_ring_emit(ring, MI_NOOP); |
| 2217 | intel_ring_advance(ring); |
| 2218 | |
| 2219 | return 0; |
| 2220 | } |
| 2221 | |
| 2222 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2223 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2224 | u64 offset, u32 len, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2225 | unsigned flags) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2226 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2227 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2228 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2229 | ret = intel_ring_begin(ring, 2); |
| 2230 | if (ret) |
| 2231 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2232 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2233 | intel_ring_emit(ring, |
Chris Wilson | 7707225 | 2014-09-10 12:18:27 +0100 | [diff] [blame] | 2234 | MI_BATCH_BUFFER_START | |
| 2235 | (flags & I915_DISPATCH_SECURE ? |
| 2236 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW)); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2237 | /* bit0-7 is the length on GEN6+ */ |
| 2238 | intel_ring_emit(ring, offset); |
| 2239 | intel_ring_advance(ring); |
| 2240 | |
| 2241 | return 0; |
| 2242 | } |
| 2243 | |
| 2244 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2245 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2246 | u64 offset, u32 len, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2247 | unsigned flags) |
| 2248 | { |
| 2249 | int ret; |
| 2250 | |
| 2251 | ret = intel_ring_begin(ring, 2); |
| 2252 | if (ret) |
| 2253 | return ret; |
| 2254 | |
| 2255 | intel_ring_emit(ring, |
| 2256 | MI_BATCH_BUFFER_START | |
| 2257 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2258 | /* bit0-7 is the length on GEN6+ */ |
| 2259 | intel_ring_emit(ring, offset); |
| 2260 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2261 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2262 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2263 | } |
| 2264 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2265 | /* Blitter support (SandyBridge+) */ |
| 2266 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2267 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2268 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2269 | { |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 2270 | struct drm_device *dev = ring->dev; |
Rodrigo Vivi | 1d73c2a | 2014-09-24 19:50:59 -0400 | [diff] [blame] | 2271 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2272 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2273 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2274 | |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 2275 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2276 | if (ret) |
| 2277 | return ret; |
| 2278 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2279 | cmd = MI_FLUSH_DW; |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2280 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 2281 | cmd += 1; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2282 | /* |
| 2283 | * Bspec vol 1c.3 - blitter engine command streamer: |
| 2284 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 2285 | * operation is complete. This bit is only valid when the |
| 2286 | * Post-Sync Operation field is a value of 1h or 3h." |
| 2287 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2288 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2289 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
Daniel Vetter | b3fcabb | 2012-11-04 12:24:47 +0100 | [diff] [blame] | 2290 | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2291 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2292 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2293 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 2294 | intel_ring_emit(ring, 0); /* upper addr */ |
| 2295 | intel_ring_emit(ring, 0); /* value */ |
| 2296 | } else { |
| 2297 | intel_ring_emit(ring, 0); |
| 2298 | intel_ring_emit(ring, MI_NOOP); |
| 2299 | } |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2300 | intel_ring_advance(ring); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 2301 | |
Rodrigo Vivi | 1d73c2a | 2014-09-24 19:50:59 -0400 | [diff] [blame] | 2302 | if (!invalidate && flush) { |
| 2303 | if (IS_GEN7(dev)) |
| 2304 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
| 2305 | else if (IS_BROADWELL(dev)) |
| 2306 | dev_priv->fbc.need_sw_cache_clean = true; |
| 2307 | } |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 2308 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2309 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2310 | } |
| 2311 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2312 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 2313 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2314 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2315 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2316 | struct drm_i915_gem_object *obj; |
| 2317 | int ret; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2318 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2319 | ring->name = "render ring"; |
| 2320 | ring->id = RCS; |
| 2321 | ring->mmio_base = RENDER_RING_BASE; |
| 2322 | |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2323 | if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2324 | if (i915_semaphore_is_enabled(dev)) { |
| 2325 | obj = i915_gem_alloc_object(dev, 4096); |
| 2326 | if (obj == NULL) { |
| 2327 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); |
| 2328 | i915.semaphores = 0; |
| 2329 | } else { |
| 2330 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 2331 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); |
| 2332 | if (ret != 0) { |
| 2333 | drm_gem_object_unreference(&obj->base); |
| 2334 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); |
| 2335 | i915.semaphores = 0; |
| 2336 | } else |
| 2337 | dev_priv->semaphore_obj = obj; |
| 2338 | } |
| 2339 | } |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 2340 | |
| 2341 | ring->init_context = intel_ring_workarounds_emit; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2342 | ring->add_request = gen6_add_request; |
| 2343 | ring->flush = gen8_render_ring_flush; |
| 2344 | ring->irq_get = gen8_ring_get_irq; |
| 2345 | ring->irq_put = gen8_ring_put_irq; |
| 2346 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
| 2347 | ring->get_seqno = gen6_ring_get_seqno; |
| 2348 | ring->set_seqno = ring_set_seqno; |
| 2349 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2350 | WARN_ON(!dev_priv->semaphore_obj); |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2351 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2352 | ring->semaphore.signal = gen8_rcs_signal; |
| 2353 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2354 | } |
| 2355 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2356 | ring->add_request = gen6_add_request; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 2357 | ring->flush = gen7_render_ring_flush; |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 2358 | if (INTEL_INFO(dev)->gen == 6) |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 2359 | ring->flush = gen6_render_ring_flush; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2360 | ring->irq_get = gen6_ring_get_irq; |
| 2361 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2362 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 2363 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2364 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2365 | if (i915_semaphore_is_enabled(dev)) { |
| 2366 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2367 | ring->semaphore.signal = gen6_signal; |
| 2368 | /* |
| 2369 | * The current semaphore is only applied on pre-gen8 |
| 2370 | * platform. And there is no VCS2 ring on the pre-gen8 |
| 2371 | * platform. So the semaphore between RCS and VCS2 is |
| 2372 | * initialized as INVALID. Gen8 will initialize the |
| 2373 | * sema between VCS2 and RCS later. |
| 2374 | */ |
| 2375 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2376 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; |
| 2377 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; |
| 2378 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; |
| 2379 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2380 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; |
| 2381 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; |
| 2382 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; |
| 2383 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; |
| 2384 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2385 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 2386 | } else if (IS_GEN5(dev)) { |
| 2387 | ring->add_request = pc_render_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 2388 | ring->flush = gen4_render_ring_flush; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 2389 | ring->get_seqno = pc_render_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2390 | ring->set_seqno = pc_render_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2391 | ring->irq_get = gen5_ring_get_irq; |
| 2392 | ring->irq_put = gen5_ring_put_irq; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2393 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
| 2394 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2395 | } else { |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 2396 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 2397 | if (INTEL_INFO(dev)->gen < 4) |
| 2398 | ring->flush = gen2_render_ring_flush; |
| 2399 | else |
| 2400 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2401 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2402 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2403 | if (IS_GEN2(dev)) { |
| 2404 | ring->irq_get = i8xx_ring_get_irq; |
| 2405 | ring->irq_put = i8xx_ring_put_irq; |
| 2406 | } else { |
| 2407 | ring->irq_get = i9xx_ring_get_irq; |
| 2408 | ring->irq_put = i9xx_ring_put_irq; |
| 2409 | } |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 2410 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2411 | } |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2412 | ring->write_tail = ring_write_tail; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2413 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2414 | if (IS_HASWELL(dev)) |
| 2415 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2416 | else if (IS_GEN8(dev)) |
| 2417 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2418 | else if (INTEL_INFO(dev)->gen >= 6) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2419 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 2420 | else if (INTEL_INFO(dev)->gen >= 4) |
| 2421 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 2422 | else if (IS_I830(dev) || IS_845G(dev)) |
| 2423 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 2424 | else |
| 2425 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2426 | ring->init = init_render_ring; |
| 2427 | ring->cleanup = render_ring_cleanup; |
| 2428 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2429 | /* Workaround batchbuffer to combat CS tlb bug. */ |
| 2430 | if (HAS_BROKEN_CS_TLB(dev)) { |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 2431 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2432 | if (obj == NULL) { |
| 2433 | DRM_ERROR("Failed to allocate batch bo\n"); |
| 2434 | return -ENOMEM; |
| 2435 | } |
| 2436 | |
Daniel Vetter | be1fa12 | 2014-02-14 14:01:14 +0100 | [diff] [blame] | 2437 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2438 | if (ret != 0) { |
| 2439 | drm_gem_object_unreference(&obj->base); |
| 2440 | DRM_ERROR("Failed to ping batch bo\n"); |
| 2441 | return ret; |
| 2442 | } |
| 2443 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 2444 | ring->scratch.obj = obj; |
| 2445 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2446 | } |
| 2447 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2448 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2449 | } |
| 2450 | |
| 2451 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 2452 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2453 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2454 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2455 | |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2456 | ring->name = "bsd ring"; |
| 2457 | ring->id = VCS; |
| 2458 | |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 2459 | ring->write_tail = ring_write_tail; |
Ben Widawsky | 780f18c | 2013-11-02 21:07:28 -0700 | [diff] [blame] | 2460 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2461 | ring->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 2462 | /* gen6 bsd needs a special wa for tail updates */ |
| 2463 | if (IS_GEN6(dev)) |
| 2464 | ring->write_tail = gen6_bsd_ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2465 | ring->flush = gen6_bsd_ring_flush; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2466 | ring->add_request = gen6_add_request; |
| 2467 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2468 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2469 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2470 | ring->irq_enable_mask = |
| 2471 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
| 2472 | ring->irq_get = gen8_ring_get_irq; |
| 2473 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2474 | ring->dispatch_execbuffer = |
| 2475 | gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2476 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2477 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2478 | ring->semaphore.signal = gen8_xcs_signal; |
| 2479 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2480 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2481 | } else { |
| 2482 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
| 2483 | ring->irq_get = gen6_ring_get_irq; |
| 2484 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2485 | ring->dispatch_execbuffer = |
| 2486 | gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2487 | if (i915_semaphore_is_enabled(dev)) { |
| 2488 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2489 | ring->semaphore.signal = gen6_signal; |
| 2490 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; |
| 2491 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2492 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; |
| 2493 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; |
| 2494 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2495 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; |
| 2496 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; |
| 2497 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; |
| 2498 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; |
| 2499 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2500 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2501 | } |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2502 | } else { |
| 2503 | ring->mmio_base = BSD_RING_BASE; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2504 | ring->flush = bsd_ring_flush; |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 2505 | ring->add_request = i9xx_add_request; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2506 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2507 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2508 | if (IS_GEN5(dev)) { |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2509 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2510 | ring->irq_get = gen5_ring_get_irq; |
| 2511 | ring->irq_put = gen5_ring_put_irq; |
| 2512 | } else { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 2513 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2514 | ring->irq_get = i9xx_ring_get_irq; |
| 2515 | ring->irq_put = i9xx_ring_put_irq; |
| 2516 | } |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2517 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2518 | } |
| 2519 | ring->init = init_ring_common; |
| 2520 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2521 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2522 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2523 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2524 | /** |
| 2525 | * Initialize the second BSD ring for Broadwell GT3. |
| 2526 | * It is noted that this only exists on Broadwell GT3. |
| 2527 | */ |
| 2528 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) |
| 2529 | { |
| 2530 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2531 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2532 | |
| 2533 | if ((INTEL_INFO(dev)->gen != 8)) { |
| 2534 | DRM_ERROR("No dual-BSD ring on non-BDW machine\n"); |
| 2535 | return -EINVAL; |
| 2536 | } |
| 2537 | |
Rodrigo Vivi | f7b6423 | 2014-07-01 02:41:36 -0700 | [diff] [blame] | 2538 | ring->name = "bsd2 ring"; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2539 | ring->id = VCS2; |
| 2540 | |
| 2541 | ring->write_tail = ring_write_tail; |
| 2542 | ring->mmio_base = GEN8_BSD2_RING_BASE; |
| 2543 | ring->flush = gen6_bsd_ring_flush; |
| 2544 | ring->add_request = gen6_add_request; |
| 2545 | ring->get_seqno = gen6_ring_get_seqno; |
| 2546 | ring->set_seqno = ring_set_seqno; |
| 2547 | ring->irq_enable_mask = |
| 2548 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
| 2549 | ring->irq_get = gen8_ring_get_irq; |
| 2550 | ring->irq_put = gen8_ring_put_irq; |
| 2551 | ring->dispatch_execbuffer = |
| 2552 | gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2553 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2554 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2555 | ring->semaphore.signal = gen8_xcs_signal; |
| 2556 | GEN8_RING_SEMAPHORE_INIT; |
| 2557 | } |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2558 | ring->init = init_ring_common; |
| 2559 | |
| 2560 | return intel_init_ring_buffer(dev, ring); |
| 2561 | } |
| 2562 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2563 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 2564 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2565 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2566 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2567 | |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2568 | ring->name = "blitter ring"; |
| 2569 | ring->id = BCS; |
| 2570 | |
| 2571 | ring->mmio_base = BLT_RING_BASE; |
| 2572 | ring->write_tail = ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2573 | ring->flush = gen6_ring_flush; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2574 | ring->add_request = gen6_add_request; |
| 2575 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2576 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2577 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2578 | ring->irq_enable_mask = |
| 2579 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
| 2580 | ring->irq_get = gen8_ring_get_irq; |
| 2581 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2582 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2583 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2584 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2585 | ring->semaphore.signal = gen8_xcs_signal; |
| 2586 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2587 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2588 | } else { |
| 2589 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
| 2590 | ring->irq_get = gen6_ring_get_irq; |
| 2591 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2592 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2593 | if (i915_semaphore_is_enabled(dev)) { |
| 2594 | ring->semaphore.signal = gen6_signal; |
| 2595 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2596 | /* |
| 2597 | * The current semaphore is only applied on pre-gen8 |
| 2598 | * platform. And there is no VCS2 ring on the pre-gen8 |
| 2599 | * platform. So the semaphore between BCS and VCS2 is |
| 2600 | * initialized as INVALID. Gen8 will initialize the |
| 2601 | * sema between BCS and VCS2 later. |
| 2602 | */ |
| 2603 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
| 2604 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; |
| 2605 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2606 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; |
| 2607 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2608 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; |
| 2609 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; |
| 2610 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; |
| 2611 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; |
| 2612 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2613 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2614 | } |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2615 | ring->init = init_ring_common; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2616 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2617 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2618 | } |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2619 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2620 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
| 2621 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2622 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2623 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2624 | |
| 2625 | ring->name = "video enhancement ring"; |
| 2626 | ring->id = VECS; |
| 2627 | |
| 2628 | ring->mmio_base = VEBOX_RING_BASE; |
| 2629 | ring->write_tail = ring_write_tail; |
| 2630 | ring->flush = gen6_ring_flush; |
| 2631 | ring->add_request = gen6_add_request; |
| 2632 | ring->get_seqno = gen6_ring_get_seqno; |
| 2633 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2634 | |
| 2635 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2636 | ring->irq_enable_mask = |
Daniel Vetter | 40c499f | 2013-11-07 21:40:39 -0800 | [diff] [blame] | 2637 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2638 | ring->irq_get = gen8_ring_get_irq; |
| 2639 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2640 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2641 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2642 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2643 | ring->semaphore.signal = gen8_xcs_signal; |
| 2644 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2645 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2646 | } else { |
| 2647 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
| 2648 | ring->irq_get = hsw_vebox_get_irq; |
| 2649 | ring->irq_put = hsw_vebox_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2650 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2651 | if (i915_semaphore_is_enabled(dev)) { |
| 2652 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2653 | ring->semaphore.signal = gen6_signal; |
| 2654 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; |
| 2655 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; |
| 2656 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; |
| 2657 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2658 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2659 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; |
| 2660 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; |
| 2661 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; |
| 2662 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; |
| 2663 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2664 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2665 | } |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2666 | ring->init = init_ring_common; |
| 2667 | |
| 2668 | return intel_init_ring_buffer(dev, ring); |
| 2669 | } |
| 2670 | |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2671 | int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2672 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2673 | { |
| 2674 | int ret; |
| 2675 | |
| 2676 | if (!ring->gpu_caches_dirty) |
| 2677 | return 0; |
| 2678 | |
| 2679 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2680 | if (ret) |
| 2681 | return ret; |
| 2682 | |
| 2683 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2684 | |
| 2685 | ring->gpu_caches_dirty = false; |
| 2686 | return 0; |
| 2687 | } |
| 2688 | |
| 2689 | int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2690 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2691 | { |
| 2692 | uint32_t flush_domains; |
| 2693 | int ret; |
| 2694 | |
| 2695 | flush_domains = 0; |
| 2696 | if (ring->gpu_caches_dirty) |
| 2697 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 2698 | |
| 2699 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2700 | if (ret) |
| 2701 | return ret; |
| 2702 | |
| 2703 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2704 | |
| 2705 | ring->gpu_caches_dirty = false; |
| 2706 | return 0; |
| 2707 | } |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2708 | |
| 2709 | void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2710 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2711 | { |
| 2712 | int ret; |
| 2713 | |
| 2714 | if (!intel_ring_initialized(ring)) |
| 2715 | return; |
| 2716 | |
| 2717 | ret = intel_ring_idle(ring); |
| 2718 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) |
| 2719 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 2720 | ring->name, ret); |
| 2721 | |
| 2722 | stop_ring(ring); |
| 2723 | } |