Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1 | /* |
| 2 | * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips |
| 3 | * |
| 4 | * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * This file is automatically generated from the AM33XX hardware databases. |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation version 2. |
| 10 | * |
| 11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 12 | * kind, whether express or implied; without even the implied warranty |
| 13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Tony Lindgren | 3a8761c | 2012-10-08 09:11:22 -0700 | [diff] [blame] | 17 | #include <linux/i2c-omap.h> |
| 18 | |
Tony Lindgren | 2a296c8 | 2012-10-02 17:41:35 -0700 | [diff] [blame] | 19 | #include "omap_hwmod.h" |
Tony Lindgren | 11964f5 | 2012-09-12 21:29:07 -0700 | [diff] [blame] | 20 | #include <linux/platform_data/gpio-omap.h> |
Kevin Hilman | aa817b2 | 2012-09-20 09:38:14 -0700 | [diff] [blame] | 21 | #include <linux/platform_data/spi-omap2-mcspi.h> |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 22 | |
| 23 | #include "omap_hwmod_common_data.h" |
| 24 | |
| 25 | #include "control.h" |
| 26 | #include "cm33xx.h" |
| 27 | #include "prm33xx.h" |
| 28 | #include "prm-regbits-33xx.h" |
Tony Lindgren | 3a8761c | 2012-10-08 09:11:22 -0700 | [diff] [blame] | 29 | #include "i2c.h" |
Tony Lindgren | 68f39e7 | 2012-10-15 12:09:43 -0700 | [diff] [blame] | 30 | #include "mmc.h" |
Vaibhav Hiremath | 05cf03b | 2013-03-31 20:22:21 -0600 | [diff] [blame] | 31 | #include "wd_timer.h" |
Afzal Mohammed | 2664946 | 2013-10-12 15:44:46 +0530 | [diff] [blame^] | 32 | #include "omap_hwmod_33xx_43xx_common_data.h" |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 33 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 34 | /* |
| 35 | * IP blocks |
| 36 | */ |
| 37 | |
| 38 | /* |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 39 | * 'emif' class |
| 40 | * instance(s): emif |
| 41 | */ |
| 42 | static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = { |
| 43 | .rev_offs = 0x0000, |
| 44 | }; |
| 45 | |
| 46 | static struct omap_hwmod_class am33xx_emif_hwmod_class = { |
| 47 | .name = "emif", |
| 48 | .sysc = &am33xx_emif_sysc, |
| 49 | }; |
| 50 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 51 | /* emif */ |
| 52 | static struct omap_hwmod am33xx_emif_hwmod = { |
| 53 | .name = "emif", |
| 54 | .class = &am33xx_emif_hwmod_class, |
| 55 | .clkdm_name = "l3_clkdm", |
Rajendra Nayak | b2eb000 | 2013-08-20 13:02:44 +0530 | [diff] [blame] | 56 | .flags = HWMOD_INIT_NO_IDLE, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 57 | .main_clk = "dpll_ddr_m2_div2_ck", |
| 58 | .prcm = { |
| 59 | .omap4 = { |
| 60 | .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET, |
| 61 | .modulemode = MODULEMODE_SWCTRL, |
| 62 | }, |
| 63 | }, |
| 64 | }; |
| 65 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 66 | /* l4_hs */ |
| 67 | static struct omap_hwmod am33xx_l4_hs_hwmod = { |
| 68 | .name = "l4_hs", |
| 69 | .class = &am33xx_l4_hwmod_class, |
| 70 | .clkdm_name = "l4hs_clkdm", |
Rajendra Nayak | b2eb000 | 2013-08-20 13:02:44 +0530 | [diff] [blame] | 71 | .flags = HWMOD_INIT_NO_IDLE, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 72 | .main_clk = "l4hs_gclk", |
| 73 | .prcm = { |
| 74 | .omap4 = { |
| 75 | .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET, |
| 76 | .modulemode = MODULEMODE_SWCTRL, |
| 77 | }, |
| 78 | }, |
| 79 | }; |
| 80 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 81 | static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { |
| 82 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, |
| 83 | }; |
| 84 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 85 | /* wkup_m3 */ |
| 86 | static struct omap_hwmod am33xx_wkup_m3_hwmod = { |
| 87 | .name = "wkup_m3", |
| 88 | .class = &am33xx_wkup_m3_hwmod_class, |
| 89 | .clkdm_name = "l4_wkup_aon_clkdm", |
Hebbar Gururaja | 092bda6 | 2013-02-08 08:21:10 -0700 | [diff] [blame] | 90 | /* Keep hardreset asserted */ |
| 91 | .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 92 | .main_clk = "dpll_core_m4_div2_ck", |
| 93 | .prcm = { |
| 94 | .omap4 = { |
| 95 | .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, |
| 96 | .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, |
Vaibhav Bedia | 3077fe6 | 2013-01-29 16:45:05 +0530 | [diff] [blame] | 97 | .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 98 | .modulemode = MODULEMODE_SWCTRL, |
| 99 | }, |
| 100 | }, |
| 101 | .rst_lines = am33xx_wkup_m3_resets, |
| 102 | .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), |
| 103 | }; |
| 104 | |
| 105 | /* |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 106 | * 'adc/tsc' class |
| 107 | * TouchScreen Controller (Anolog-To-Digital Converter) |
| 108 | */ |
| 109 | static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = { |
| 110 | .rev_offs = 0x00, |
| 111 | .sysc_offs = 0x10, |
| 112 | .sysc_flags = SYSC_HAS_SIDLEMODE, |
| 113 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 114 | SIDLE_SMART_WKUP), |
| 115 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 116 | }; |
| 117 | |
| 118 | static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { |
| 119 | .name = "adc_tsc", |
| 120 | .sysc = &am33xx_adc_tsc_sysc, |
| 121 | }; |
| 122 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 123 | static struct omap_hwmod am33xx_adc_tsc_hwmod = { |
| 124 | .name = "adc_tsc", |
| 125 | .class = &am33xx_adc_tsc_hwmod_class, |
| 126 | .clkdm_name = "l4_wkup_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 127 | .main_clk = "adc_tsc_fck", |
| 128 | .prcm = { |
| 129 | .omap4 = { |
| 130 | .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, |
| 131 | .modulemode = MODULEMODE_SWCTRL, |
| 132 | }, |
| 133 | }, |
| 134 | }; |
| 135 | |
| 136 | /* |
| 137 | * Modules omap_hwmod structures |
| 138 | * |
| 139 | * The following IPs are excluded for the moment because: |
| 140 | * - They do not need an explicit SW control using omap_hwmod API. |
| 141 | * - They still need to be validated with the driver |
| 142 | * properly adapted to omap_hwmod / omap_device |
| 143 | * |
| 144 | * - cEFUSE (doesn't fall under any ocp_if) |
| 145 | * - clkdiv32k |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 146 | * - ocp watch point |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 147 | */ |
| 148 | #if 0 |
| 149 | /* |
| 150 | * 'cefuse' class |
| 151 | */ |
| 152 | static struct omap_hwmod_class am33xx_cefuse_hwmod_class = { |
| 153 | .name = "cefuse", |
| 154 | }; |
| 155 | |
| 156 | static struct omap_hwmod am33xx_cefuse_hwmod = { |
| 157 | .name = "cefuse", |
| 158 | .class = &am33xx_cefuse_hwmod_class, |
| 159 | .clkdm_name = "l4_cefuse_clkdm", |
| 160 | .main_clk = "cefuse_fck", |
| 161 | .prcm = { |
| 162 | .omap4 = { |
| 163 | .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET, |
| 164 | .modulemode = MODULEMODE_SWCTRL, |
| 165 | }, |
| 166 | }, |
| 167 | }; |
| 168 | |
| 169 | /* |
| 170 | * 'clkdiv32k' class |
| 171 | */ |
| 172 | static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = { |
| 173 | .name = "clkdiv32k", |
| 174 | }; |
| 175 | |
| 176 | static struct omap_hwmod am33xx_clkdiv32k_hwmod = { |
| 177 | .name = "clkdiv32k", |
| 178 | .class = &am33xx_clkdiv32k_hwmod_class, |
| 179 | .clkdm_name = "clk_24mhz_clkdm", |
| 180 | .main_clk = "clkdiv32k_ick", |
| 181 | .prcm = { |
| 182 | .omap4 = { |
| 183 | .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET, |
| 184 | .modulemode = MODULEMODE_SWCTRL, |
| 185 | }, |
| 186 | }, |
| 187 | }; |
| 188 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 189 | /* ocpwp */ |
| 190 | static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { |
| 191 | .name = "ocpwp", |
| 192 | }; |
| 193 | |
| 194 | static struct omap_hwmod am33xx_ocpwp_hwmod = { |
| 195 | .name = "ocpwp", |
| 196 | .class = &am33xx_ocpwp_hwmod_class, |
| 197 | .clkdm_name = "l4ls_clkdm", |
| 198 | .main_clk = "l4ls_gclk", |
| 199 | .prcm = { |
| 200 | .omap4 = { |
| 201 | .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET, |
| 202 | .modulemode = MODULEMODE_SWCTRL, |
| 203 | }, |
| 204 | }, |
| 205 | }; |
Mark A. Greer | 1cb804b | 2012-12-21 09:28:14 -0700 | [diff] [blame] | 206 | #endif |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 207 | |
| 208 | /* |
Vaibhav Hiremath | 1721c70 | 2013-08-20 18:54:09 -0600 | [diff] [blame] | 209 | * 'debugss' class |
| 210 | * debug sub system |
| 211 | */ |
| 212 | static struct omap_hwmod_opt_clk debugss_opt_clks[] = { |
| 213 | { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" }, |
| 214 | { .role = "dbg_clka", .clk = "dbg_clka_ck" }, |
| 215 | }; |
| 216 | |
| 217 | static struct omap_hwmod_class am33xx_debugss_hwmod_class = { |
| 218 | .name = "debugss", |
| 219 | }; |
| 220 | |
| 221 | static struct omap_hwmod am33xx_debugss_hwmod = { |
| 222 | .name = "debugss", |
| 223 | .class = &am33xx_debugss_hwmod_class, |
| 224 | .clkdm_name = "l3_aon_clkdm", |
| 225 | .main_clk = "trace_clk_div_ck", |
| 226 | .prcm = { |
| 227 | .omap4 = { |
| 228 | .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, |
| 229 | .modulemode = MODULEMODE_SWCTRL, |
| 230 | }, |
| 231 | }, |
| 232 | .opt_clks = debugss_opt_clks, |
| 233 | .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks), |
| 234 | }; |
| 235 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 236 | static struct omap_hwmod am33xx_control_hwmod = { |
| 237 | .name = "control", |
| 238 | .class = &am33xx_control_hwmod_class, |
| 239 | .clkdm_name = "l4_wkup_clkdm", |
Rajendra Nayak | b2eb000 | 2013-08-20 13:02:44 +0530 | [diff] [blame] | 240 | .flags = HWMOD_INIT_NO_IDLE, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 241 | .main_clk = "dpll_core_m4_div2_ck", |
| 242 | .prcm = { |
| 243 | .omap4 = { |
| 244 | .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, |
| 245 | .modulemode = MODULEMODE_SWCTRL, |
| 246 | }, |
| 247 | }, |
| 248 | }; |
| 249 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 250 | /* gpio0 */ |
| 251 | static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { |
| 252 | { .role = "dbclk", .clk = "gpio0_dbclk" }, |
| 253 | }; |
| 254 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 255 | static struct omap_hwmod am33xx_gpio0_hwmod = { |
| 256 | .name = "gpio1", |
| 257 | .class = &am33xx_gpio_hwmod_class, |
| 258 | .clkdm_name = "l4_wkup_clkdm", |
| 259 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 260 | .main_clk = "dpll_core_m4_div2_ck", |
| 261 | .prcm = { |
| 262 | .omap4 = { |
| 263 | .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, |
| 264 | .modulemode = MODULEMODE_SWCTRL, |
| 265 | }, |
| 266 | }, |
| 267 | .opt_clks = gpio0_opt_clks, |
| 268 | .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), |
| 269 | .dev_attr = &gpio_dev_attr, |
| 270 | }; |
| 271 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 272 | /* lcdc */ |
| 273 | static struct omap_hwmod_class_sysconfig lcdc_sysc = { |
| 274 | .rev_offs = 0x0, |
| 275 | .sysc_offs = 0x54, |
| 276 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), |
| 277 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 278 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 279 | }; |
| 280 | |
| 281 | static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { |
| 282 | .name = "lcdc", |
| 283 | .sysc = &lcdc_sysc, |
| 284 | }; |
| 285 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 286 | static struct omap_hwmod am33xx_lcdc_hwmod = { |
| 287 | .name = "lcdc", |
| 288 | .class = &am33xx_lcdc_hwmod_class, |
| 289 | .clkdm_name = "lcdc_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 290 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
| 291 | .main_clk = "lcd_gclk", |
| 292 | .prcm = { |
| 293 | .omap4 = { |
| 294 | .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET, |
| 295 | .modulemode = MODULEMODE_SWCTRL, |
| 296 | }, |
| 297 | }, |
| 298 | }; |
| 299 | |
| 300 | /* |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 301 | * 'usb_otg' class |
| 302 | * high-speed on-the-go universal serial bus (usb_otg) controller |
| 303 | */ |
| 304 | static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = { |
| 305 | .rev_offs = 0x0, |
| 306 | .sysc_offs = 0x10, |
| 307 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), |
| 308 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 309 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 310 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 311 | }; |
| 312 | |
| 313 | static struct omap_hwmod_class am33xx_usbotg_class = { |
| 314 | .name = "usbotg", |
| 315 | .sysc = &am33xx_usbhsotg_sysc, |
| 316 | }; |
| 317 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 318 | static struct omap_hwmod am33xx_usbss_hwmod = { |
| 319 | .name = "usb_otg_hs", |
| 320 | .class = &am33xx_usbotg_class, |
| 321 | .clkdm_name = "l3s_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 322 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
| 323 | .main_clk = "usbotg_fck", |
| 324 | .prcm = { |
| 325 | .omap4 = { |
| 326 | .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET, |
| 327 | .modulemode = MODULEMODE_SWCTRL, |
| 328 | }, |
| 329 | }, |
| 330 | }; |
| 331 | |
| 332 | |
| 333 | /* |
| 334 | * Interfaces |
| 335 | */ |
| 336 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 337 | static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { |
| 338 | { |
| 339 | .pa_start = 0x4c000000, |
| 340 | .pa_end = 0x4c000fff, |
| 341 | .flags = ADDR_TYPE_RT |
| 342 | }, |
| 343 | { } |
| 344 | }; |
| 345 | /* l3 main -> emif */ |
| 346 | static struct omap_hwmod_ocp_if am33xx_l3_main__emif = { |
| 347 | .master = &am33xx_l3_main_hwmod, |
| 348 | .slave = &am33xx_emif_hwmod, |
| 349 | .clk = "dpll_core_m4_ck", |
| 350 | .addr = am33xx_emif_addrs, |
| 351 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 352 | }; |
| 353 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 354 | /* l3 main -> l4 hs */ |
| 355 | static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { |
| 356 | .master = &am33xx_l3_main_hwmod, |
| 357 | .slave = &am33xx_l4_hs_hwmod, |
| 358 | .clk = "l3s_gclk", |
| 359 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 360 | }; |
| 361 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 362 | /* wkup m3 -> l4 wkup */ |
| 363 | static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { |
| 364 | .master = &am33xx_wkup_m3_hwmod, |
| 365 | .slave = &am33xx_l4_wkup_hwmod, |
| 366 | .clk = "dpll_core_m4_div2_ck", |
| 367 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 368 | }; |
| 369 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 370 | /* l4 wkup -> wkup m3 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 371 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { |
| 372 | .master = &am33xx_l4_wkup_hwmod, |
| 373 | .slave = &am33xx_wkup_m3_hwmod, |
| 374 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 375 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 376 | }; |
| 377 | |
| 378 | /* l4 hs -> pru-icss */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 379 | static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { |
| 380 | .master = &am33xx_l4_hs_hwmod, |
| 381 | .slave = &am33xx_pruss_hwmod, |
| 382 | .clk = "dpll_core_m4_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 383 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 384 | }; |
| 385 | |
Vaibhav Hiremath | 1721c70 | 2013-08-20 18:54:09 -0600 | [diff] [blame] | 386 | /* l3_main -> debugss */ |
| 387 | static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = { |
| 388 | { |
| 389 | .pa_start = 0x4b000000, |
| 390 | .pa_end = 0x4b000000 + SZ_16M - 1, |
| 391 | .flags = ADDR_TYPE_RT |
| 392 | }, |
| 393 | { } |
| 394 | }; |
| 395 | |
| 396 | static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = { |
| 397 | .master = &am33xx_l3_main_hwmod, |
| 398 | .slave = &am33xx_debugss_hwmod, |
| 399 | .clk = "dpll_core_m4_ck", |
| 400 | .addr = am33xx_debugss_addrs, |
| 401 | .user = OCP_USER_MPU, |
| 402 | }; |
| 403 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 404 | /* l4 wkup -> smartreflex0 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 405 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { |
| 406 | .master = &am33xx_l4_wkup_hwmod, |
| 407 | .slave = &am33xx_smartreflex0_hwmod, |
| 408 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 409 | .user = OCP_USER_MPU, |
| 410 | }; |
| 411 | |
| 412 | /* l4 wkup -> smartreflex1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 413 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { |
| 414 | .master = &am33xx_l4_wkup_hwmod, |
| 415 | .slave = &am33xx_smartreflex1_hwmod, |
| 416 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 417 | .user = OCP_USER_MPU, |
| 418 | }; |
| 419 | |
| 420 | /* l4 wkup -> control */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 421 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { |
| 422 | .master = &am33xx_l4_wkup_hwmod, |
| 423 | .slave = &am33xx_control_hwmod, |
| 424 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 425 | .user = OCP_USER_MPU, |
| 426 | }; |
| 427 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 428 | /* L4 WKUP -> I2C1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 429 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { |
| 430 | .master = &am33xx_l4_wkup_hwmod, |
| 431 | .slave = &am33xx_i2c1_hwmod, |
| 432 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 433 | .user = OCP_USER_MPU, |
| 434 | }; |
| 435 | |
| 436 | /* L4 WKUP -> GPIO1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 437 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { |
| 438 | .master = &am33xx_l4_wkup_hwmod, |
| 439 | .slave = &am33xx_gpio0_hwmod, |
| 440 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 441 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 442 | }; |
| 443 | |
| 444 | /* L4 WKUP -> ADC_TSC */ |
| 445 | static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = { |
| 446 | { |
| 447 | .pa_start = 0x44E0D000, |
| 448 | .pa_end = 0x44E0D000 + SZ_8K - 1, |
| 449 | .flags = ADDR_TYPE_RT |
| 450 | }, |
| 451 | { } |
| 452 | }; |
| 453 | |
| 454 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { |
| 455 | .master = &am33xx_l4_wkup_hwmod, |
| 456 | .slave = &am33xx_adc_tsc_hwmod, |
| 457 | .clk = "dpll_core_m4_div2_ck", |
| 458 | .addr = am33xx_adc_tsc_addrs, |
| 459 | .user = OCP_USER_MPU, |
| 460 | }; |
| 461 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 462 | static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { |
| 463 | .master = &am33xx_l4_hs_hwmod, |
| 464 | .slave = &am33xx_cpgmac0_hwmod, |
| 465 | .clk = "cpsw_125mhz_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 466 | .user = OCP_USER_MPU, |
| 467 | }; |
| 468 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 469 | static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { |
| 470 | { |
| 471 | .pa_start = 0x4830E000, |
| 472 | .pa_end = 0x4830E000 + SZ_8K - 1, |
| 473 | .flags = ADDR_TYPE_RT, |
| 474 | }, |
| 475 | { } |
| 476 | }; |
| 477 | |
| 478 | static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { |
| 479 | .master = &am33xx_l3_main_hwmod, |
| 480 | .slave = &am33xx_lcdc_hwmod, |
| 481 | .clk = "dpll_core_m4_ck", |
| 482 | .addr = am33xx_lcdc_addr_space, |
| 483 | .user = OCP_USER_MPU, |
| 484 | }; |
| 485 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 486 | /* l4 wkup -> timer1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 487 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { |
| 488 | .master = &am33xx_l4_wkup_hwmod, |
| 489 | .slave = &am33xx_timer1_hwmod, |
| 490 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 491 | .user = OCP_USER_MPU, |
| 492 | }; |
| 493 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 494 | /* l4 wkup -> uart1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 495 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { |
| 496 | .master = &am33xx_l4_wkup_hwmod, |
| 497 | .slave = &am33xx_uart1_hwmod, |
| 498 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 499 | .user = OCP_USER_MPU, |
| 500 | }; |
| 501 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 502 | /* l4 wkup -> wd_timer1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 503 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { |
| 504 | .master = &am33xx_l4_wkup_hwmod, |
| 505 | .slave = &am33xx_wd_timer1_hwmod, |
| 506 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 507 | .user = OCP_USER_MPU, |
| 508 | }; |
| 509 | |
| 510 | /* usbss */ |
| 511 | /* l3 s -> USBSS interface */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 512 | static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { |
| 513 | .master = &am33xx_l3_s_hwmod, |
| 514 | .slave = &am33xx_usbss_hwmod, |
| 515 | .clk = "l3s_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 516 | .user = OCP_USER_MPU, |
| 517 | .flags = OCPIF_SWSUP_IDLE, |
| 518 | }; |
| 519 | |
Lokesh Vutla | ace1e3e | 2013-08-29 18:22:10 +0530 | [diff] [blame] | 520 | /* rng */ |
| 521 | static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = { |
| 522 | .rev_offs = 0x1fe0, |
| 523 | .sysc_offs = 0x1fe4, |
| 524 | .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE, |
| 525 | .idlemodes = SIDLE_FORCE | SIDLE_NO, |
| 526 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 527 | }; |
| 528 | |
| 529 | static struct omap_hwmod_class am33xx_rng_hwmod_class = { |
| 530 | .name = "rng", |
| 531 | .sysc = &am33xx_rng_sysc, |
| 532 | }; |
| 533 | |
| 534 | static struct omap_hwmod am33xx_rng_hwmod = { |
| 535 | .name = "rng", |
| 536 | .class = &am33xx_rng_hwmod_class, |
| 537 | .clkdm_name = "l4ls_clkdm", |
| 538 | .flags = HWMOD_SWSUP_SIDLE, |
| 539 | .main_clk = "rng_fck", |
| 540 | .prcm = { |
| 541 | .omap4 = { |
| 542 | .clkctrl_offs = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET, |
| 543 | .modulemode = MODULEMODE_SWCTRL, |
| 544 | }, |
| 545 | }, |
| 546 | }; |
| 547 | |
| 548 | static struct omap_hwmod_ocp_if am33xx_l4_per__rng = { |
| 549 | .master = &am33xx_l4_ls_hwmod, |
| 550 | .slave = &am33xx_rng_hwmod, |
| 551 | .clk = "rng_fck", |
| 552 | .user = OCP_USER_MPU, |
| 553 | }; |
| 554 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 555 | static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 556 | &am33xx_l3_main__emif, |
| 557 | &am33xx_mpu__l3_main, |
| 558 | &am33xx_mpu__prcm, |
| 559 | &am33xx_l3_s__l4_ls, |
| 560 | &am33xx_l3_s__l4_wkup, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 561 | &am33xx_l3_main__l4_hs, |
| 562 | &am33xx_l3_main__l3_s, |
| 563 | &am33xx_l3_main__l3_instr, |
| 564 | &am33xx_l3_main__gfx, |
| 565 | &am33xx_l3_s__l3_main, |
| 566 | &am33xx_pruss__l3_main, |
| 567 | &am33xx_wkup_m3__l4_wkup, |
| 568 | &am33xx_gfx__l3_main, |
Vaibhav Hiremath | 1721c70 | 2013-08-20 18:54:09 -0600 | [diff] [blame] | 569 | &am33xx_l3_main__debugss, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 570 | &am33xx_l4_wkup__wkup_m3, |
| 571 | &am33xx_l4_wkup__control, |
| 572 | &am33xx_l4_wkup__smartreflex0, |
| 573 | &am33xx_l4_wkup__smartreflex1, |
| 574 | &am33xx_l4_wkup__uart1, |
| 575 | &am33xx_l4_wkup__timer1, |
| 576 | &am33xx_l4_wkup__rtc, |
| 577 | &am33xx_l4_wkup__i2c1, |
| 578 | &am33xx_l4_wkup__gpio0, |
| 579 | &am33xx_l4_wkup__adc_tsc, |
| 580 | &am33xx_l4_wkup__wd_timer1, |
| 581 | &am33xx_l4_hs__pruss, |
| 582 | &am33xx_l4_per__dcan0, |
| 583 | &am33xx_l4_per__dcan1, |
| 584 | &am33xx_l4_per__gpio1, |
| 585 | &am33xx_l4_per__gpio2, |
| 586 | &am33xx_l4_per__gpio3, |
| 587 | &am33xx_l4_per__i2c2, |
| 588 | &am33xx_l4_per__i2c3, |
| 589 | &am33xx_l4_per__mailbox, |
| 590 | &am33xx_l4_ls__mcasp0, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 591 | &am33xx_l4_ls__mcasp1, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 592 | &am33xx_l4_ls__mmc0, |
| 593 | &am33xx_l4_ls__mmc1, |
| 594 | &am33xx_l3_s__mmc2, |
| 595 | &am33xx_l4_ls__timer2, |
| 596 | &am33xx_l4_ls__timer3, |
| 597 | &am33xx_l4_ls__timer4, |
| 598 | &am33xx_l4_ls__timer5, |
| 599 | &am33xx_l4_ls__timer6, |
| 600 | &am33xx_l4_ls__timer7, |
| 601 | &am33xx_l3_main__tpcc, |
| 602 | &am33xx_l4_ls__uart2, |
| 603 | &am33xx_l4_ls__uart3, |
| 604 | &am33xx_l4_ls__uart4, |
| 605 | &am33xx_l4_ls__uart5, |
| 606 | &am33xx_l4_ls__uart6, |
| 607 | &am33xx_l4_ls__spinlock, |
| 608 | &am33xx_l4_ls__elm, |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 609 | &am33xx_l4_ls__epwmss0, |
| 610 | &am33xx_epwmss0__ecap0, |
| 611 | &am33xx_epwmss0__eqep0, |
| 612 | &am33xx_epwmss0__ehrpwm0, |
| 613 | &am33xx_l4_ls__epwmss1, |
| 614 | &am33xx_epwmss1__ecap1, |
| 615 | &am33xx_epwmss1__eqep1, |
| 616 | &am33xx_epwmss1__ehrpwm1, |
| 617 | &am33xx_l4_ls__epwmss2, |
| 618 | &am33xx_epwmss2__ecap2, |
| 619 | &am33xx_epwmss2__eqep2, |
| 620 | &am33xx_epwmss2__ehrpwm2, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 621 | &am33xx_l3_s__gpmc, |
| 622 | &am33xx_l3_main__lcdc, |
| 623 | &am33xx_l4_ls__mcspi0, |
| 624 | &am33xx_l4_ls__mcspi1, |
| 625 | &am33xx_l3_main__tptc0, |
| 626 | &am33xx_l3_main__tptc1, |
| 627 | &am33xx_l3_main__tptc2, |
Vaibhav Bedia | ca903b6 | 2013-01-29 16:45:02 +0530 | [diff] [blame] | 628 | &am33xx_l3_main__ocmc, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 629 | &am33xx_l3_s__usbss, |
| 630 | &am33xx_l4_hs__cpgmac0, |
Mugunthan V N | 70384a6 | 2012-11-14 09:07:58 +0000 | [diff] [blame] | 631 | &am33xx_cpgmac0__mdio, |
Mark A. Greer | aec94bf | 2013-03-18 10:06:35 -0600 | [diff] [blame] | 632 | &am33xx_l3_main__sha0, |
Mark A. Greer | 1cb804b | 2012-12-21 09:28:14 -0700 | [diff] [blame] | 633 | &am33xx_l3_main__aes0, |
Lokesh Vutla | ace1e3e | 2013-08-29 18:22:10 +0530 | [diff] [blame] | 634 | &am33xx_l4_per__rng, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 635 | NULL, |
| 636 | }; |
| 637 | |
| 638 | int __init am33xx_hwmod_init(void) |
| 639 | { |
| 640 | omap_hwmod_init(); |
| 641 | return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); |
| 642 | } |