H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Defines x86 CPU feature bits |
| 3 | */ |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 4 | #ifndef _ASM_X86_CPUFEATURE_H |
| 5 | #define _ASM_X86_CPUFEATURE_H |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 6 | |
David Howells | abbf159 | 2012-10-02 18:01:26 +0100 | [diff] [blame] | 7 | #ifndef _ASM_X86_REQUIRED_FEATURES_H |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 8 | #include <asm/required-features.h> |
David Howells | abbf159 | 2012-10-02 18:01:26 +0100 | [diff] [blame] | 9 | #endif |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 10 | |
Dave Hansen | 381aa07 | 2014-09-11 14:15:13 -0700 | [diff] [blame] | 11 | #ifndef _ASM_X86_DISABLED_FEATURES_H |
| 12 | #include <asm/disabled-features.h> |
| 13 | #endif |
| 14 | |
Peter P Waskiewicz Jr | cbc82b1 | 2015-01-23 18:45:43 +0000 | [diff] [blame] | 15 | #define NCAPINTS 13 /* N 32-bit words worth of info */ |
Borislav Petkov | 65fc985 | 2013-03-20 15:07:23 +0100 | [diff] [blame] | 16 | #define NBUGINTS 1 /* N 32-bit bug flags */ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 17 | |
H. Peter Anvin | 7414aa4 | 2008-08-27 17:56:44 -0700 | [diff] [blame] | 18 | /* |
| 19 | * Note: If the comment begins with a quoted string, that string is used |
| 20 | * in /proc/cpuinfo instead of the macro name. If the string is "", |
| 21 | * this feature bit is not displayed in /proc/cpuinfo at all. |
| 22 | */ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 23 | |
| 24 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 25 | #define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */ |
| 26 | #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */ |
| 27 | #define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */ |
| 28 | #define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */ |
| 29 | #define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */ |
| 30 | #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */ |
| 31 | #define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */ |
| 32 | #define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */ |
| 33 | #define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */ |
| 34 | #define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */ |
| 35 | #define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */ |
| 36 | #define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */ |
| 37 | #define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */ |
| 38 | #define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */ |
| 39 | #define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */ |
H. Peter Anvin | 2798c63 | 2008-08-27 21:20:07 -0700 | [diff] [blame] | 40 | /* (plus FCMOVcc, FCOMI with FPU) */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 41 | #define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */ |
| 42 | #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */ |
| 43 | #define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */ |
| 44 | #define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */ |
| 45 | #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */ |
| 46 | #define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */ |
| 47 | #define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */ |
| 48 | #define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ |
| 49 | #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */ |
| 50 | #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */ |
| 51 | #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */ |
| 52 | #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */ |
| 53 | #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */ |
| 54 | #define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */ |
| 55 | #define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 56 | |
| 57 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ |
| 58 | /* Don't duplicate feature flags which are redundant with Intel! */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 59 | #define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */ |
| 60 | #define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */ |
| 61 | #define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */ |
| 62 | #define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */ |
| 63 | #define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */ |
| 64 | #define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */ |
| 65 | #define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */ |
| 66 | #define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */ |
| 67 | #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */ |
| 68 | #define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 69 | |
| 70 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 71 | #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */ |
| 72 | #define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */ |
| 73 | #define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 74 | |
| 75 | /* Other features, Linux-defined mapping, word 3 */ |
| 76 | /* This range is used for feature bits which conflict or are synthesized */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 77 | #define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */ |
| 78 | #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */ |
| 79 | #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */ |
| 80 | #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 81 | /* cpu types for specific tunings: */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 82 | #define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */ |
| 83 | #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ |
| 84 | #define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */ |
| 85 | #define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */ |
| 86 | #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */ |
| 87 | #define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */ |
Borislav Petkov | 9b13a93 | 2014-06-18 00:06:23 +0200 | [diff] [blame] | 88 | /* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 89 | #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */ |
| 90 | #define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */ |
| 91 | #define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */ |
| 92 | #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */ |
| 93 | #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */ |
| 94 | #define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */ |
| 95 | #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */ |
| 96 | #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */ |
Borislav Petkov | 9b13a93 | 2014-06-18 00:06:23 +0200 | [diff] [blame] | 97 | /* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 98 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ |
| 99 | #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ |
| 100 | #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ |
| 101 | #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ |
| 102 | #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ |
Borislav Petkov | 9b13a93 | 2014-06-18 00:06:23 +0200 | [diff] [blame] | 103 | /* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 104 | #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ |
| 105 | #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ |
| 106 | #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ |
| 107 | #define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */ |
| 108 | #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 109 | |
| 110 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 111 | #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */ |
| 112 | #define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */ |
| 113 | #define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */ |
| 114 | #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */ |
| 115 | #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ |
| 116 | #define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */ |
| 117 | #define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */ |
| 118 | #define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */ |
| 119 | #define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */ |
| 120 | #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */ |
| 121 | #define X86_FEATURE_CID ( 4*32+10) /* Context ID */ |
| 122 | #define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */ |
| 123 | #define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */ |
| 124 | #define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */ |
| 125 | #define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */ |
| 126 | #define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */ |
| 127 | #define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */ |
| 128 | #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */ |
| 129 | #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */ |
| 130 | #define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */ |
| 131 | #define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */ |
| 132 | #define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */ |
| 133 | #define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */ |
| 134 | #define X86_FEATURE_AES ( 4*32+25) /* AES instructions */ |
| 135 | #define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ |
| 136 | #define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */ |
| 137 | #define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */ |
| 138 | #define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */ |
| 139 | #define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */ |
| 140 | #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 141 | |
| 142 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 143 | #define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */ |
| 144 | #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */ |
| 145 | #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ |
| 146 | #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */ |
| 147 | #define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */ |
| 148 | #define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */ |
| 149 | #define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */ |
| 150 | #define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */ |
| 151 | #define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */ |
| 152 | #define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 153 | |
| 154 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 155 | #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */ |
| 156 | #define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */ |
| 157 | #define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */ |
| 158 | #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */ |
| 159 | #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */ |
| 160 | #define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */ |
| 161 | #define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */ |
| 162 | #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */ |
| 163 | #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */ |
| 164 | #define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */ |
| 165 | #define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */ |
| 166 | #define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */ |
| 167 | #define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */ |
| 168 | #define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */ |
| 169 | #define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */ |
| 170 | #define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */ |
| 171 | #define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */ |
| 172 | #define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */ |
| 173 | #define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */ |
| 174 | #define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */ |
| 175 | #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */ |
| 176 | #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ |
Jacob Shin | d6d55f0 | 2014-05-29 17:26:50 +0200 | [diff] [blame] | 177 | #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 178 | #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 179 | |
| 180 | /* |
| 181 | * Auxiliary flags: Linux defined - For features scattered in various |
H. Peter Anvin | bdc802d | 2010-07-07 17:29:18 -0700 | [diff] [blame] | 182 | * CPUID levels like 0x6, 0xA etc, word 7 |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 183 | */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 184 | #define X86_FEATURE_IDA ( 7*32+ 0) /* Intel Dynamic Acceleration */ |
| 185 | #define X86_FEATURE_ARAT ( 7*32+ 1) /* Always Running APIC Timer */ |
| 186 | #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ |
| 187 | #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 188 | #define X86_FEATURE_PLN ( 7*32+ 5) /* Intel Power Limit Notification */ |
| 189 | #define X86_FEATURE_PTS ( 7*32+ 6) /* Intel Package Thermal Status */ |
| 190 | #define X86_FEATURE_DTHERM ( 7*32+ 7) /* Digital Thermal Sensor */ |
| 191 | #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ |
| 192 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ |
Dirk Brandewie | 7787388 | 2014-11-06 09:40:46 -0800 | [diff] [blame] | 193 | #define X86_FEATURE_HWP ( 7*32+ 10) /* "hwp" Intel HWP */ |
| 194 | #define X86_FEATURE_HWP_NOITFY ( 7*32+ 11) /* Intel HWP_NOTIFY */ |
| 195 | #define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */ |
| 196 | #define X86_FEATURE_HWP_EPP ( 7*32+13) /* Intel HWP_EPP */ |
| 197 | #define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */ |
Alexander Shishkin | ed69628 | 2015-01-14 14:18:19 +0200 | [diff] [blame] | 198 | #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 199 | |
H. Peter Anvin | bdc802d | 2010-07-07 17:29:18 -0700 | [diff] [blame] | 200 | /* Virtualization flags: Linux defined, word 8 */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 201 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ |
| 202 | #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */ |
| 203 | #define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */ |
| 204 | #define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */ |
| 205 | #define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */ |
| 206 | #define X86_FEATURE_NPT ( 8*32+ 5) /* AMD Nested Page Table support */ |
| 207 | #define X86_FEATURE_LBRV ( 8*32+ 6) /* AMD LBR Virtualization support */ |
| 208 | #define X86_FEATURE_SVML ( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ |
| 209 | #define X86_FEATURE_NRIPS ( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ |
| 210 | #define X86_FEATURE_TSCRATEMSR ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ |
| 211 | #define X86_FEATURE_VMCBCLEAN ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ |
| 212 | #define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */ |
| 213 | #define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */ |
| 214 | #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */ |
| 215 | #define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */ |
Paolo Bonzini | c1118b3 | 2014-09-22 13:17:48 +0200 | [diff] [blame] | 216 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */ |
Andre Przywara | aeb9c7d | 2010-09-06 15:14:20 +0200 | [diff] [blame] | 217 | |
Sheng Yang | e38e05a | 2008-09-10 18:53:34 +0800 | [diff] [blame] | 218 | |
H. Peter Anvin | bdc802d | 2010-07-07 17:29:18 -0700 | [diff] [blame] | 219 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 220 | #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ |
| 221 | #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */ |
| 222 | #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ |
| 223 | #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ |
| 224 | #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ |
| 225 | #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ |
| 226 | #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ |
| 227 | #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ |
| 228 | #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ |
| 229 | #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ |
Peter P Waskiewicz Jr | cbc82b1 | 2015-01-23 18:45:43 +0000 | [diff] [blame] | 230 | #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 231 | #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ |
| 232 | #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ |
| 233 | #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ |
| 234 | #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ |
| 235 | #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ |
Ross Zwisler | 719d359 | 2015-02-19 10:37:28 -0700 | [diff] [blame] | 236 | #define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 237 | #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ |
Ross Zwisler | d9dc64f | 2015-01-27 09:53:51 -0700 | [diff] [blame] | 238 | #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ |
Fenghua Yu | 446fd80 | 2014-05-29 11:12:29 -0700 | [diff] [blame] | 239 | #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ |
| 240 | #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ |
| 241 | #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ |
H. Peter Anvin | bdc802d | 2010-07-07 17:29:18 -0700 | [diff] [blame] | 242 | |
Fenghua Yu | 6229ad2 | 2014-05-29 11:12:30 -0700 | [diff] [blame] | 243 | /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ |
| 244 | #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ |
| 245 | #define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */ |
| 246 | #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ |
| 247 | #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ |
| 248 | |
Peter P Waskiewicz Jr | cbc82b1 | 2015-01-23 18:45:43 +0000 | [diff] [blame] | 249 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ |
| 250 | #define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ |
| 251 | |
| 252 | /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ |
| 253 | #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ |
| 254 | |
Borislav Petkov | 65fc985 | 2013-03-20 15:07:23 +0100 | [diff] [blame] | 255 | /* |
| 256 | * BUG word(s) |
| 257 | */ |
| 258 | #define X86_BUG(x) (NCAPINTS*32 + (x)) |
| 259 | |
Borislav Petkov | e2604b4 | 2013-03-20 15:07:24 +0100 | [diff] [blame] | 260 | #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */ |
Borislav Petkov | 93a829e | 2013-03-20 15:07:25 +0100 | [diff] [blame] | 261 | #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */ |
Borislav Petkov | c5b41a6 | 2013-03-20 15:07:26 +0100 | [diff] [blame] | 262 | #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */ |
Borislav Petkov | 80a208b | 2014-06-24 13:25:03 +0200 | [diff] [blame] | 263 | #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */ |
| 264 | #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */ |
Borislav Petkov | 9b13a93 | 2014-06-18 00:06:23 +0200 | [diff] [blame] | 265 | #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ |
| 266 | #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ |
| 267 | #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ |
Andy Lutomirski | 61f01dd | 2015-04-26 16:47:59 -0700 | [diff] [blame] | 268 | #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */ |
Borislav Petkov | e2604b4 | 2013-03-20 15:07:24 +0100 | [diff] [blame] | 269 | |
H. Peter Anvin | fa1408e | 2008-02-04 16:48:00 +0100 | [diff] [blame] | 270 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
| 271 | |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 272 | #include <asm/asm.h> |
H. Peter Anvin | fa1408e | 2008-02-04 16:48:00 +0100 | [diff] [blame] | 273 | #include <linux/bitops.h> |
| 274 | |
Josh Triplett | 9def39be | 2013-10-30 08:09:45 -0700 | [diff] [blame] | 275 | #ifdef CONFIG_X86_FEATURE_NAMES |
H. Peter Anvin | fa1408e | 2008-02-04 16:48:00 +0100 | [diff] [blame] | 276 | extern const char * const x86_cap_flags[NCAPINTS*32]; |
| 277 | extern const char * const x86_power_flags[32]; |
Josh Triplett | 9def39be | 2013-10-30 08:09:45 -0700 | [diff] [blame] | 278 | #define X86_CAP_FMT "%s" |
| 279 | #define x86_cap_flag(flag) x86_cap_flags[flag] |
| 280 | #else |
| 281 | #define X86_CAP_FMT "%d:%d" |
| 282 | #define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31) |
| 283 | #endif |
H. Peter Anvin | fa1408e | 2008-02-04 16:48:00 +0100 | [diff] [blame] | 284 | |
Borislav Petkov | 80a208b | 2014-06-24 13:25:03 +0200 | [diff] [blame] | 285 | /* |
| 286 | * In order to save room, we index into this array by doing |
| 287 | * X86_BUG_<name> - NCAPINTS*32. |
| 288 | */ |
| 289 | extern const char * const x86_bug_flags[NBUGINTS*32]; |
| 290 | |
Ingo Molnar | 0f8d2b9 | 2008-02-26 08:34:21 +0100 | [diff] [blame] | 291 | #define test_cpu_cap(c, bit) \ |
| 292 | test_bit(bit, (unsigned long *)((c)->x86_capability)) |
| 293 | |
Christoph Lameter | 349c004 | 2011-03-12 12:50:10 +0100 | [diff] [blame] | 294 | #define REQUIRED_MASK_BIT_SET(bit) \ |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 295 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ |
| 296 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ |
| 297 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ |
| 298 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ |
| 299 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ |
| 300 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ |
| 301 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ |
H. Peter Anvin | bdc802d | 2010-07-07 17:29:18 -0700 | [diff] [blame] | 302 | (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \ |
| 303 | (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \ |
Christoph Lameter | 349c004 | 2011-03-12 12:50:10 +0100 | [diff] [blame] | 304 | (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) ) |
| 305 | |
Dave Hansen | 381aa07 | 2014-09-11 14:15:13 -0700 | [diff] [blame] | 306 | #define DISABLED_MASK_BIT_SET(bit) \ |
| 307 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0)) || \ |
| 308 | (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1)) || \ |
| 309 | (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2)) || \ |
| 310 | (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3)) || \ |
| 311 | (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4)) || \ |
| 312 | (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5)) || \ |
| 313 | (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6)) || \ |
| 314 | (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7)) || \ |
| 315 | (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8)) || \ |
| 316 | (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9)) ) |
| 317 | |
Christoph Lameter | 349c004 | 2011-03-12 12:50:10 +0100 | [diff] [blame] | 318 | #define cpu_has(c, bit) \ |
| 319 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ |
Ingo Molnar | 0f8d2b9 | 2008-02-26 08:34:21 +0100 | [diff] [blame] | 320 | test_cpu_cap(c, bit)) |
| 321 | |
Christoph Lameter | 349c004 | 2011-03-12 12:50:10 +0100 | [diff] [blame] | 322 | #define this_cpu_has(bit) \ |
| 323 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ |
| 324 | x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability)) |
| 325 | |
Dave Hansen | 381aa07 | 2014-09-11 14:15:13 -0700 | [diff] [blame] | 326 | /* |
| 327 | * This macro is for detection of features which need kernel |
| 328 | * infrastructure to be used. It may *not* directly test the CPU |
| 329 | * itself. Use the cpu_has() family if you want true runtime |
| 330 | * testing of CPU features, like in hypervisor code where you are |
| 331 | * supporting a possible guest feature where host support for it |
| 332 | * is not relevant. |
| 333 | */ |
| 334 | #define cpu_feature_enabled(bit) \ |
| 335 | (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : \ |
| 336 | cpu_has(&boot_cpu_data, bit)) |
| 337 | |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 338 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
| 339 | |
Jeremy Fitzhardinge | 53756d3 | 2008-01-30 13:30:55 +0100 | [diff] [blame] | 340 | #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) |
| 341 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) |
Andi Kleen | 7d851c8 | 2008-01-30 13:33:20 +0100 | [diff] [blame] | 342 | #define setup_clear_cpu_cap(bit) do { \ |
| 343 | clear_cpu_cap(&boot_cpu_data, bit); \ |
Yinghai Lu | 3e0c373 | 2009-05-09 23:47:42 -0700 | [diff] [blame] | 344 | set_bit(bit, (unsigned long *)cpu_caps_cleared); \ |
Andi Kleen | 7d851c8 | 2008-01-30 13:33:20 +0100 | [diff] [blame] | 345 | } while (0) |
Andi Kleen | 404ee5b | 2008-01-30 13:33:20 +0100 | [diff] [blame] | 346 | #define setup_force_cpu_cap(bit) do { \ |
| 347 | set_cpu_cap(&boot_cpu_data, bit); \ |
Yinghai Lu | 3e0c373 | 2009-05-09 23:47:42 -0700 | [diff] [blame] | 348 | set_bit(bit, (unsigned long *)cpu_caps_set); \ |
Andi Kleen | 404ee5b | 2008-01-30 13:33:20 +0100 | [diff] [blame] | 349 | } while (0) |
Jeremy Fitzhardinge | 53756d3 | 2008-01-30 13:30:55 +0100 | [diff] [blame] | 350 | |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 351 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 352 | #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) |
| 353 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) |
| 354 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 355 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) |
| 356 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) |
| 357 | #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) |
| 358 | #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) |
| 359 | #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) |
| 360 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) |
| 361 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) |
| 362 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) |
| 363 | #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) |
Mathias Krause | 66be895 | 2011-08-04 20:19:25 +0200 | [diff] [blame] | 364 | #define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3) |
Huang Ying | 54b6a1b | 2009-01-18 16:28:34 +1100 | [diff] [blame] | 365 | #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) |
Mathias Krause | 66be895 | 2011-08-04 20:19:25 +0200 | [diff] [blame] | 366 | #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) |
Jussi Kivilinna | 6048801 | 2013-04-13 13:46:45 +0300 | [diff] [blame] | 367 | #define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2) |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 368 | #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 369 | #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 370 | #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) |
| 371 | #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) |
| 372 | #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) |
| 373 | #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) |
| 374 | #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) |
| 375 | #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) |
| 376 | #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) |
| 377 | #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) |
| 378 | #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) |
| 379 | #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) |
| 380 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) |
| 381 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) |
H. Peter Anvin | 840d283 | 2014-02-27 08:31:30 -0800 | [diff] [blame] | 382 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH) |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 383 | #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) |
Andi Kleen | 019c3e7 | 2008-02-04 16:48:09 +0100 | [diff] [blame] | 384 | #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) |
stephane eranian | 8697510 | 2008-03-07 13:05:27 -0800 | [diff] [blame] | 385 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) |
venkatesh.pallipadi@intel.com | 2e5d9c8 | 2008-03-18 17:00:14 -0700 | [diff] [blame] | 386 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) |
H. Peter Anvin | f1240c0 | 2008-08-27 18:53:07 -0700 | [diff] [blame] | 387 | #define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1) |
Austin Zhang | 2a61812 | 2008-08-25 11:14:51 -0400 | [diff] [blame] | 388 | #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) |
Suresh Siddha | 32e1d0a | 2008-07-10 11:16:50 -0700 | [diff] [blame] | 389 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
H. Peter Anvin | f1240c0 | 2008-08-27 18:53:07 -0700 | [diff] [blame] | 390 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
Suresh Siddha | 212b021 | 2012-09-06 15:05:18 -0700 | [diff] [blame] | 391 | #define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT) |
Fenghua Yu | 6229ad2 | 2014-05-29 11:12:30 -0700 | [diff] [blame] | 392 | #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) |
Mathias Krause | 66be895 | 2011-08-04 20:19:25 +0200 | [diff] [blame] | 393 | #define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) |
Alok Kataria | 49ab56a | 2008-11-01 18:34:37 -0700 | [diff] [blame] | 394 | #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) |
Huang Ying | 0e1227d | 2009-10-19 11:53:06 +0900 | [diff] [blame] | 395 | #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) |
Robert Richter | 4979d27 | 2011-02-02 17:36:12 +0100 | [diff] [blame] | 396 | #define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) |
Jacob Shin | e259514 | 2013-02-06 11:26:29 -0600 | [diff] [blame] | 397 | #define cpu_has_perfctr_nb boot_cpu_has(X86_FEATURE_PERFCTR_NB) |
Jacob Shin | c43ca50 | 2013-04-19 16:34:28 -0500 | [diff] [blame] | 398 | #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) |
Christoph Lameter | 3824abd | 2011-06-01 12:25:47 -0500 | [diff] [blame] | 399 | #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) |
| 400 | #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) |
Suresh Siddha | 5d2bd70 | 2012-09-06 14:58:52 -0700 | [diff] [blame] | 401 | #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) |
Andreas Herrmann | 193f3fc | 2012-10-19 10:58:13 +0200 | [diff] [blame] | 402 | #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) |
Jacob Shin | d6d55f0 | 2014-05-29 17:26:50 +0200 | [diff] [blame] | 403 | #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT) |
H. Peter Anvin | 7b11fb5 | 2008-01-30 13:30:07 +0100 | [diff] [blame] | 404 | |
Tetsuo Handa | 2fd8186 | 2010-08-30 09:45:40 +0900 | [diff] [blame] | 405 | #if __GNUC__ >= 4 |
Borislav Petkov | 5700f74 | 2013-06-09 12:07:32 +0200 | [diff] [blame] | 406 | extern void warn_pre_alternatives(void); |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 407 | extern bool __static_cpu_has_safe(u16 bit); |
Borislav Petkov | 5700f74 | 2013-06-09 12:07:32 +0200 | [diff] [blame] | 408 | |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 409 | /* |
| 410 | * Static testing of CPU features. Used the same as boot_cpu_has(). |
| 411 | * These are only valid after alternatives have run, but will statically |
| 412 | * patch the target code for additional performance. |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 413 | */ |
H. Peter Anvin | 83a7a2a | 2010-06-10 00:10:43 +0000 | [diff] [blame] | 414 | static __always_inline __pure bool __static_cpu_has(u16 bit) |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 415 | { |
Borislav Petkov | 62122fd | 2013-06-28 18:41:41 +0200 | [diff] [blame] | 416 | #ifdef CC_HAVE_ASM_GOTO |
Borislav Petkov | 5700f74 | 2013-06-09 12:07:32 +0200 | [diff] [blame] | 417 | |
| 418 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS |
Borislav Petkov | 62122fd | 2013-06-28 18:41:41 +0200 | [diff] [blame] | 419 | |
Borislav Petkov | 5700f74 | 2013-06-09 12:07:32 +0200 | [diff] [blame] | 420 | /* |
| 421 | * Catch too early usage of this before alternatives |
| 422 | * have run. |
| 423 | */ |
Ingo Molnar | 3f0116c | 2013-10-10 10:16:30 +0200 | [diff] [blame] | 424 | asm_volatile_goto("1: jmp %l[t_warn]\n" |
Borislav Petkov | 5700f74 | 2013-06-09 12:07:32 +0200 | [diff] [blame] | 425 | "2:\n" |
| 426 | ".section .altinstructions,\"a\"\n" |
| 427 | " .long 1b - .\n" |
| 428 | " .long 0\n" /* no replacement */ |
| 429 | " .word %P0\n" /* 1: do replace */ |
| 430 | " .byte 2b - 1b\n" /* source len */ |
| 431 | " .byte 0\n" /* replacement len */ |
Borislav Petkov | 4332195 | 2014-12-27 10:41:52 +0100 | [diff] [blame] | 432 | " .byte 0\n" /* pad len */ |
Borislav Petkov | 5700f74 | 2013-06-09 12:07:32 +0200 | [diff] [blame] | 433 | ".previous\n" |
| 434 | /* skipping size check since replacement size = 0 */ |
| 435 | : : "i" (X86_FEATURE_ALWAYS) : : t_warn); |
Borislav Petkov | 62122fd | 2013-06-28 18:41:41 +0200 | [diff] [blame] | 436 | |
Borislav Petkov | 5700f74 | 2013-06-09 12:07:32 +0200 | [diff] [blame] | 437 | #endif |
| 438 | |
Ingo Molnar | 3f0116c | 2013-10-10 10:16:30 +0200 | [diff] [blame] | 439 | asm_volatile_goto("1: jmp %l[t_no]\n" |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 440 | "2:\n" |
| 441 | ".section .altinstructions,\"a\"\n" |
Andy Lutomirski | 59e97e4 | 2011-07-13 09:24:10 -0400 | [diff] [blame] | 442 | " .long 1b - .\n" |
| 443 | " .long 0\n" /* no replacement */ |
H. Peter Anvin | 83a7a2a | 2010-06-10 00:10:43 +0000 | [diff] [blame] | 444 | " .word %P0\n" /* feature bit */ |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 445 | " .byte 2b - 1b\n" /* source len */ |
| 446 | " .byte 0\n" /* replacement len */ |
Borislav Petkov | 4332195 | 2014-12-27 10:41:52 +0100 | [diff] [blame] | 447 | " .byte 0\n" /* pad len */ |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 448 | ".previous\n" |
H. Peter Anvin | 83a7a2a | 2010-06-10 00:10:43 +0000 | [diff] [blame] | 449 | /* skipping size check since replacement size = 0 */ |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 450 | : : "i" (bit) : : t_no); |
| 451 | return true; |
| 452 | t_no: |
| 453 | return false; |
Borislav Petkov | 5700f74 | 2013-06-09 12:07:32 +0200 | [diff] [blame] | 454 | |
| 455 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS |
| 456 | t_warn: |
| 457 | warn_pre_alternatives(); |
| 458 | return false; |
| 459 | #endif |
Borislav Petkov | 62122fd | 2013-06-28 18:41:41 +0200 | [diff] [blame] | 460 | |
| 461 | #else /* CC_HAVE_ASM_GOTO */ |
| 462 | |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 463 | u8 flag; |
| 464 | /* Open-coded due to __stringify() in ALTERNATIVE() */ |
| 465 | asm volatile("1: movb $0,%0\n" |
| 466 | "2:\n" |
| 467 | ".section .altinstructions,\"a\"\n" |
Andy Lutomirski | 59e97e4 | 2011-07-13 09:24:10 -0400 | [diff] [blame] | 468 | " .long 1b - .\n" |
| 469 | " .long 3f - .\n" |
H. Peter Anvin | 83a7a2a | 2010-06-10 00:10:43 +0000 | [diff] [blame] | 470 | " .word %P1\n" /* feature bit */ |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 471 | " .byte 2b - 1b\n" /* source len */ |
| 472 | " .byte 4f - 3f\n" /* replacement len */ |
Borislav Petkov | 4332195 | 2014-12-27 10:41:52 +0100 | [diff] [blame] | 473 | " .byte 0\n" /* pad len */ |
H. Peter Anvin | 83a7a2a | 2010-06-10 00:10:43 +0000 | [diff] [blame] | 474 | ".previous\n" |
| 475 | ".section .discard,\"aw\",@progbits\n" |
| 476 | " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 477 | ".previous\n" |
| 478 | ".section .altinstr_replacement,\"ax\"\n" |
| 479 | "3: movb $1,%0\n" |
| 480 | "4:\n" |
| 481 | ".previous\n" |
| 482 | : "=qm" (flag) : "i" (bit)); |
| 483 | return flag; |
Borislav Petkov | 62122fd | 2013-06-28 18:41:41 +0200 | [diff] [blame] | 484 | |
| 485 | #endif /* CC_HAVE_ASM_GOTO */ |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 486 | } |
| 487 | |
| 488 | #define static_cpu_has(bit) \ |
| 489 | ( \ |
| 490 | __builtin_constant_p(boot_cpu_has(bit)) ? \ |
| 491 | boot_cpu_has(bit) : \ |
H. Peter Anvin | 83a7a2a | 2010-06-10 00:10:43 +0000 | [diff] [blame] | 492 | __builtin_constant_p(bit) ? \ |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 493 | __static_cpu_has(bit) : \ |
| 494 | boot_cpu_has(bit) \ |
| 495 | ) |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 496 | |
| 497 | static __always_inline __pure bool _static_cpu_has_safe(u16 bit) |
| 498 | { |
Borislav Petkov | 62122fd | 2013-06-28 18:41:41 +0200 | [diff] [blame] | 499 | #ifdef CC_HAVE_ASM_GOTO |
Borislav Petkov | 48c7a25 | 2015-01-05 13:48:41 +0100 | [diff] [blame] | 500 | asm_volatile_goto("1: jmp %l[t_dynamic]\n" |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 501 | "2:\n" |
Borislav Petkov | 4332195 | 2014-12-27 10:41:52 +0100 | [diff] [blame] | 502 | ".skip -(((5f-4f) - (2b-1b)) > 0) * " |
| 503 | "((5f-4f) - (2b-1b)),0x90\n" |
| 504 | "3:\n" |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 505 | ".section .altinstructions,\"a\"\n" |
| 506 | " .long 1b - .\n" /* src offset */ |
Borislav Petkov | 4332195 | 2014-12-27 10:41:52 +0100 | [diff] [blame] | 507 | " .long 4f - .\n" /* repl offset */ |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 508 | " .word %P1\n" /* always replace */ |
Borislav Petkov | 4332195 | 2014-12-27 10:41:52 +0100 | [diff] [blame] | 509 | " .byte 3b - 1b\n" /* src len */ |
| 510 | " .byte 5f - 4f\n" /* repl len */ |
| 511 | " .byte 3b - 2b\n" /* pad len */ |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 512 | ".previous\n" |
| 513 | ".section .altinstr_replacement,\"ax\"\n" |
Borislav Petkov | 48c7a25 | 2015-01-05 13:48:41 +0100 | [diff] [blame] | 514 | "4: jmp %l[t_no]\n" |
Borislav Petkov | 4332195 | 2014-12-27 10:41:52 +0100 | [diff] [blame] | 515 | "5:\n" |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 516 | ".previous\n" |
| 517 | ".section .altinstructions,\"a\"\n" |
| 518 | " .long 1b - .\n" /* src offset */ |
| 519 | " .long 0\n" /* no replacement */ |
| 520 | " .word %P0\n" /* feature bit */ |
Borislav Petkov | 4332195 | 2014-12-27 10:41:52 +0100 | [diff] [blame] | 521 | " .byte 3b - 1b\n" /* src len */ |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 522 | " .byte 0\n" /* repl len */ |
Borislav Petkov | 4332195 | 2014-12-27 10:41:52 +0100 | [diff] [blame] | 523 | " .byte 0\n" /* pad len */ |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 524 | ".previous\n" |
| 525 | : : "i" (bit), "i" (X86_FEATURE_ALWAYS) |
| 526 | : : t_dynamic, t_no); |
| 527 | return true; |
| 528 | t_no: |
| 529 | return false; |
| 530 | t_dynamic: |
| 531 | return __static_cpu_has_safe(bit); |
Borislav Petkov | 62122fd | 2013-06-28 18:41:41 +0200 | [diff] [blame] | 532 | #else |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 533 | u8 flag; |
| 534 | /* Open-coded due to __stringify() in ALTERNATIVE() */ |
| 535 | asm volatile("1: movb $2,%0\n" |
| 536 | "2:\n" |
| 537 | ".section .altinstructions,\"a\"\n" |
| 538 | " .long 1b - .\n" /* src offset */ |
| 539 | " .long 3f - .\n" /* repl offset */ |
| 540 | " .word %P2\n" /* always replace */ |
| 541 | " .byte 2b - 1b\n" /* source len */ |
| 542 | " .byte 4f - 3f\n" /* replacement len */ |
Borislav Petkov | 4332195 | 2014-12-27 10:41:52 +0100 | [diff] [blame] | 543 | " .byte 0\n" /* pad len */ |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 544 | ".previous\n" |
| 545 | ".section .discard,\"aw\",@progbits\n" |
| 546 | " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */ |
| 547 | ".previous\n" |
| 548 | ".section .altinstr_replacement,\"ax\"\n" |
| 549 | "3: movb $0,%0\n" |
| 550 | "4:\n" |
| 551 | ".previous\n" |
| 552 | ".section .altinstructions,\"a\"\n" |
| 553 | " .long 1b - .\n" /* src offset */ |
| 554 | " .long 5f - .\n" /* repl offset */ |
| 555 | " .word %P1\n" /* feature bit */ |
| 556 | " .byte 4b - 3b\n" /* src len */ |
| 557 | " .byte 6f - 5f\n" /* repl len */ |
Borislav Petkov | 4332195 | 2014-12-27 10:41:52 +0100 | [diff] [blame] | 558 | " .byte 0\n" /* pad len */ |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 559 | ".previous\n" |
| 560 | ".section .discard,\"aw\",@progbits\n" |
| 561 | " .byte 0xff + (6f-5f) - (4b-3b)\n" /* size check */ |
| 562 | ".previous\n" |
| 563 | ".section .altinstr_replacement,\"ax\"\n" |
| 564 | "5: movb $1,%0\n" |
| 565 | "6:\n" |
| 566 | ".previous\n" |
| 567 | : "=qm" (flag) |
| 568 | : "i" (bit), "i" (X86_FEATURE_ALWAYS)); |
| 569 | return (flag == 2 ? __static_cpu_has_safe(bit) : flag); |
Borislav Petkov | 62122fd | 2013-06-28 18:41:41 +0200 | [diff] [blame] | 570 | #endif /* CC_HAVE_ASM_GOTO */ |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 571 | } |
| 572 | |
| 573 | #define static_cpu_has_safe(bit) \ |
| 574 | ( \ |
| 575 | __builtin_constant_p(boot_cpu_has(bit)) ? \ |
| 576 | boot_cpu_has(bit) : \ |
| 577 | _static_cpu_has_safe(bit) \ |
| 578 | ) |
H. Peter Anvin | 1ba4f22 | 2010-05-27 12:02:00 -0700 | [diff] [blame] | 579 | #else |
| 580 | /* |
| 581 | * gcc 3.x is too stupid to do the static test; fall back to dynamic. |
| 582 | */ |
Borislav Petkov | 4a90a99 | 2013-06-09 12:07:33 +0200 | [diff] [blame] | 583 | #define static_cpu_has(bit) boot_cpu_has(bit) |
| 584 | #define static_cpu_has_safe(bit) boot_cpu_has(bit) |
H. Peter Anvin | 1ba4f22 | 2010-05-27 12:02:00 -0700 | [diff] [blame] | 585 | #endif |
H. Peter Anvin | a3c8acd | 2010-05-11 17:47:07 -0700 | [diff] [blame] | 586 | |
Borislav Petkov | 9b13a93 | 2014-06-18 00:06:23 +0200 | [diff] [blame] | 587 | #define cpu_has_bug(c, bit) cpu_has(c, (bit)) |
| 588 | #define set_cpu_bug(c, bit) set_cpu_cap(c, (bit)) |
| 589 | #define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)) |
Borislav Petkov | 65fc985 | 2013-03-20 15:07:23 +0100 | [diff] [blame] | 590 | |
Borislav Petkov | 9b13a93 | 2014-06-18 00:06:23 +0200 | [diff] [blame] | 591 | #define static_cpu_has_bug(bit) static_cpu_has((bit)) |
| 592 | #define static_cpu_has_bug_safe(bit) static_cpu_has_safe((bit)) |
| 593 | #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) |
Borislav Petkov | 65fc985 | 2013-03-20 15:07:23 +0100 | [diff] [blame] | 594 | |
Borislav Petkov | 9b13a93 | 2014-06-18 00:06:23 +0200 | [diff] [blame] | 595 | #define MAX_CPU_FEATURES (NCAPINTS * 32) |
| 596 | #define cpu_have_feature boot_cpu_has |
Ard Biesheuvel | 2b9c1f0 | 2014-02-08 13:34:10 +0100 | [diff] [blame] | 597 | |
Borislav Petkov | 9b13a93 | 2014-06-18 00:06:23 +0200 | [diff] [blame] | 598 | #define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X" |
| 599 | #define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \ |
| 600 | boot_cpu_data.x86_model |
Ard Biesheuvel | 2b9c1f0 | 2014-02-08 13:34:10 +0100 | [diff] [blame] | 601 | |
H. Peter Anvin | fa1408e | 2008-02-04 16:48:00 +0100 | [diff] [blame] | 602 | #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 603 | #endif /* _ASM_X86_CPUFEATURE_H */ |