Li, Aubrey | 93e5ead | 2014-06-30 14:08:42 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Intel Atom SOC Power Management Controller Header File |
| 3 | * Copyright (c) 2014, Intel Corporation. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | #ifndef PMC_ATOM_H |
| 17 | #define PMC_ATOM_H |
| 18 | |
| 19 | /* ValleyView Power Control Unit PCI Device ID */ |
| 20 | #define PCI_DEVICE_ID_VLV_PMC 0x0F1C |
| 21 | |
Li, Aubrey | b00055c | 2014-06-30 14:09:38 +0800 | [diff] [blame] | 22 | /* PMC Memory mapped IO registers */ |
| 23 | #define PMC_BASE_ADDR_OFFSET 0x44 |
| 24 | #define PMC_BASE_ADDR_MASK 0xFFFFFE00 |
| 25 | #define PMC_MMIO_REG_LEN 0x100 |
| 26 | #define PMC_REG_BIT_WIDTH 32 |
| 27 | |
Li, Aubrey | f855911 | 2014-06-30 14:10:33 +0800 | [diff] [blame] | 28 | /* BIOS uses FUNC_DIS to disable specific function */ |
| 29 | #define PMC_FUNC_DIS 0x34 |
| 30 | #define PMC_FUNC_DIS_2 0x38 |
| 31 | |
Li, Aubrey | b00055c | 2014-06-30 14:09:38 +0800 | [diff] [blame] | 32 | /* S0ix wake event control */ |
| 33 | #define PMC_S0IX_WAKE_EN 0x3C |
| 34 | |
| 35 | #define BIT_LPC_CLOCK_RUN BIT(4) |
| 36 | #define BIT_SHARED_IRQ_GPSC BIT(5) |
| 37 | #define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18) |
| 38 | #define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19) |
| 39 | #define BIT_SHARED_IRQ_GPSS BIT(20) |
| 40 | |
| 41 | #define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \ |
| 42 | BIT_SHARED_IRQ_GPSC | \ |
| 43 | BIT_ORED_DEDICATED_IRQ_GPSS | \ |
| 44 | BIT_ORED_DEDICATED_IRQ_GPSC | \ |
| 45 | BIT_SHARED_IRQ_GPSS) |
| 46 | |
Li, Aubrey | f855911 | 2014-06-30 14:10:33 +0800 | [diff] [blame] | 47 | /* The timers acumulate time spent in sleep state */ |
| 48 | #define PMC_S0IR_TMR 0x80 |
| 49 | #define PMC_S0I1_TMR 0x84 |
| 50 | #define PMC_S0I2_TMR 0x88 |
| 51 | #define PMC_S0I3_TMR 0x8C |
| 52 | #define PMC_S0_TMR 0x90 |
| 53 | /* Sleep state counter is in units of of 32us */ |
| 54 | #define PMC_TMR_SHIFT 5 |
| 55 | |
Andy Shevchenko | 0e15402 | 2015-01-14 18:39:35 +0200 | [diff] [blame] | 56 | /* Power status of power islands */ |
| 57 | #define PMC_PSS 0x98 |
| 58 | |
| 59 | #define PMC_PSS_BIT_GBE BIT(0) |
| 60 | #define PMC_PSS_BIT_SATA BIT(1) |
| 61 | #define PMC_PSS_BIT_HDA BIT(2) |
| 62 | #define PMC_PSS_BIT_SEC BIT(3) |
| 63 | #define PMC_PSS_BIT_PCIE BIT(4) |
| 64 | #define PMC_PSS_BIT_LPSS BIT(5) |
| 65 | #define PMC_PSS_BIT_LPE BIT(6) |
| 66 | #define PMC_PSS_BIT_DFX BIT(7) |
| 67 | #define PMC_PSS_BIT_USH_CTRL BIT(8) |
| 68 | #define PMC_PSS_BIT_USH_SUS BIT(9) |
| 69 | #define PMC_PSS_BIT_USH_VCCS BIT(10) |
| 70 | #define PMC_PSS_BIT_USH_VCCA BIT(11) |
| 71 | #define PMC_PSS_BIT_OTG_CTRL BIT(12) |
| 72 | #define PMC_PSS_BIT_OTG_VCCS BIT(13) |
| 73 | #define PMC_PSS_BIT_OTG_VCCA_CLK BIT(14) |
| 74 | #define PMC_PSS_BIT_OTG_VCCA BIT(15) |
| 75 | #define PMC_PSS_BIT_USB BIT(16) |
| 76 | #define PMC_PSS_BIT_USB_SUS BIT(17) |
| 77 | |
Li, Aubrey | f855911 | 2014-06-30 14:10:33 +0800 | [diff] [blame] | 78 | /* These registers reflect D3 status of functions */ |
| 79 | #define PMC_D3_STS_0 0xA0 |
| 80 | |
| 81 | #define BIT_LPSS1_F0_DMA BIT(0) |
| 82 | #define BIT_LPSS1_F1_PWM1 BIT(1) |
| 83 | #define BIT_LPSS1_F2_PWM2 BIT(2) |
| 84 | #define BIT_LPSS1_F3_HSUART1 BIT(3) |
| 85 | #define BIT_LPSS1_F4_HSUART2 BIT(4) |
| 86 | #define BIT_LPSS1_F5_SPI BIT(5) |
| 87 | #define BIT_LPSS1_F6_XXX BIT(6) |
| 88 | #define BIT_LPSS1_F7_XXX BIT(7) |
| 89 | #define BIT_SCC_EMMC BIT(8) |
| 90 | #define BIT_SCC_SDIO BIT(9) |
| 91 | #define BIT_SCC_SDCARD BIT(10) |
| 92 | #define BIT_SCC_MIPI BIT(11) |
| 93 | #define BIT_HDA BIT(12) |
| 94 | #define BIT_LPE BIT(13) |
| 95 | #define BIT_OTG BIT(14) |
| 96 | #define BIT_USH BIT(15) |
| 97 | #define BIT_GBE BIT(16) |
| 98 | #define BIT_SATA BIT(17) |
| 99 | #define BIT_USB_EHCI BIT(18) |
| 100 | #define BIT_SEC BIT(19) |
| 101 | #define BIT_PCIE_PORT0 BIT(20) |
| 102 | #define BIT_PCIE_PORT1 BIT(21) |
| 103 | #define BIT_PCIE_PORT2 BIT(22) |
| 104 | #define BIT_PCIE_PORT3 BIT(23) |
| 105 | #define BIT_LPSS2_F0_DMA BIT(24) |
| 106 | #define BIT_LPSS2_F1_I2C1 BIT(25) |
| 107 | #define BIT_LPSS2_F2_I2C2 BIT(26) |
| 108 | #define BIT_LPSS2_F3_I2C3 BIT(27) |
| 109 | #define BIT_LPSS2_F4_I2C4 BIT(28) |
| 110 | #define BIT_LPSS2_F5_I2C5 BIT(29) |
| 111 | #define BIT_LPSS2_F6_I2C6 BIT(30) |
| 112 | #define BIT_LPSS2_F7_I2C7 BIT(31) |
| 113 | |
| 114 | #define PMC_D3_STS_1 0xA4 |
| 115 | #define BIT_SMB BIT(0) |
| 116 | #define BIT_OTG_SS_PHY BIT(1) |
| 117 | #define BIT_USH_SS_PHY BIT(2) |
| 118 | #define BIT_DFX BIT(3) |
| 119 | |
Li, Aubrey | 93e5ead | 2014-06-30 14:08:42 +0800 | [diff] [blame] | 120 | /* PMC I/O Registers */ |
| 121 | #define ACPI_BASE_ADDR_OFFSET 0x40 |
| 122 | #define ACPI_BASE_ADDR_MASK 0xFFFFFE00 |
| 123 | #define ACPI_MMIO_REG_LEN 0x100 |
| 124 | |
| 125 | #define PM1_CNT 0x4 |
| 126 | #define SLEEP_TYPE_MASK 0xFFFFECFF |
| 127 | #define SLEEP_TYPE_S5 0x1C00 |
| 128 | #define SLEEP_ENABLE 0x2000 |
| 129 | #endif /* PMC_ATOM_H */ |