Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 1 | /* |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 2 | * linux/drivers/ide/pci/cmd64x.c Version 1.50 May 10, 2007 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Due to massive hardware bugs, UltraDMA is only supported |
| 6 | * on the 646U2 and not on the 646U. |
| 7 | * |
| 8 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
| 9 | * Copyright (C) 1998 David S. Miller (davem@redhat.com) |
| 10 | * |
| 11 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 12 | * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | */ |
| 14 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/types.h> |
| 17 | #include <linux/pci.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/hdreg.h> |
| 20 | #include <linux/ide.h> |
| 21 | #include <linux/init.h> |
| 22 | |
| 23 | #include <asm/io.h> |
| 24 | |
| 25 | #define DISPLAY_CMD64X_TIMINGS |
| 26 | |
| 27 | #define CMD_DEBUG 0 |
| 28 | |
| 29 | #if CMD_DEBUG |
| 30 | #define cmdprintk(x...) printk(x) |
| 31 | #else |
| 32 | #define cmdprintk(x...) |
| 33 | #endif |
| 34 | |
| 35 | /* |
| 36 | * CMD64x specific registers definition. |
| 37 | */ |
| 38 | #define CFR 0x50 |
Sergei Shtylyov | e51e252 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 39 | #define CFR_INTR_CH0 0x04 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | #define CNTRL 0x51 |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 41 | #define CNTRL_ENA_1ST 0x04 |
| 42 | #define CNTRL_ENA_2ND 0x08 |
| 43 | #define CNTRL_DIS_RA0 0x40 |
| 44 | #define CNTRL_DIS_RA1 0x80 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | |
| 46 | #define CMDTIM 0x52 |
| 47 | #define ARTTIM0 0x53 |
| 48 | #define DRWTIM0 0x54 |
| 49 | #define ARTTIM1 0x55 |
| 50 | #define DRWTIM1 0x56 |
| 51 | #define ARTTIM23 0x57 |
| 52 | #define ARTTIM23_DIS_RA2 0x04 |
| 53 | #define ARTTIM23_DIS_RA3 0x08 |
| 54 | #define ARTTIM23_INTR_CH1 0x10 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | #define DRWTIM2 0x58 |
| 56 | #define BRST 0x59 |
| 57 | #define DRWTIM3 0x5b |
| 58 | |
| 59 | #define BMIDECR0 0x70 |
| 60 | #define MRDMODE 0x71 |
| 61 | #define MRDMODE_INTR_CH0 0x04 |
| 62 | #define MRDMODE_INTR_CH1 0x08 |
| 63 | #define MRDMODE_BLK_CH0 0x10 |
| 64 | #define MRDMODE_BLK_CH1 0x20 |
| 65 | #define BMIDESR0 0x72 |
| 66 | #define UDIDETCR0 0x73 |
| 67 | #define DTPR0 0x74 |
| 68 | #define BMIDECR1 0x78 |
| 69 | #define BMIDECSR 0x79 |
| 70 | #define BMIDESR1 0x7A |
| 71 | #define UDIDETCR1 0x7B |
| 72 | #define DTPR1 0x7C |
| 73 | |
Bartlomiej Zolnierkiewicz | ecfd80e | 2007-05-10 00:01:09 +0200 | [diff] [blame] | 74 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | #include <linux/stat.h> |
| 76 | #include <linux/proc_fs.h> |
| 77 | |
| 78 | static u8 cmd64x_proc = 0; |
| 79 | |
| 80 | #define CMD_MAX_DEVS 5 |
| 81 | |
| 82 | static struct pci_dev *cmd_devs[CMD_MAX_DEVS]; |
| 83 | static int n_cmd_devs; |
| 84 | |
| 85 | static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index) |
| 86 | { |
| 87 | char *p = buf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | u8 reg72 = 0, reg73 = 0; /* primary */ |
| 89 | u8 reg7a = 0, reg7b = 0; /* secondary */ |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 90 | u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | |
| 92 | p += sprintf(p, "\nController: %d\n", index); |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 93 | p += sprintf(p, "PCI-%x Chipset.\n", dev->device); |
| 94 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | (void) pci_read_config_byte(dev, CFR, ®50); |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 96 | (void) pci_read_config_byte(dev, CNTRL, ®51); |
| 97 | (void) pci_read_config_byte(dev, ARTTIM23, ®57); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | (void) pci_read_config_byte(dev, MRDMODE, ®71); |
| 99 | (void) pci_read_config_byte(dev, BMIDESR0, ®72); |
| 100 | (void) pci_read_config_byte(dev, UDIDETCR0, ®73); |
| 101 | (void) pci_read_config_byte(dev, BMIDESR1, ®7a); |
| 102 | (void) pci_read_config_byte(dev, UDIDETCR1, ®7b); |
| 103 | |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 104 | /* PCI0643/6 originally didn't have the primary channel enable bit */ |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 105 | if ((dev->device == PCI_DEVICE_ID_CMD_643) || |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 106 | (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 3)) |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 107 | reg51 |= CNTRL_ENA_1ST; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | |
Sergei Shtylyov | 5826b31 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 109 | p += sprintf(p, "---------------- Primary Channel " |
| 110 | "---------------- Secondary Channel ------------\n"); |
| 111 | p += sprintf(p, " %s %s\n", |
| 112 | (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled", |
| 113 | (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled"); |
| 114 | p += sprintf(p, "---------------- drive0 --------- drive1 " |
| 115 | "-------- drive0 --------- drive1 ------\n"); |
| 116 | p += sprintf(p, "DMA enabled: %s %s" |
| 117 | " %s %s\n", |
| 118 | (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ", |
| 119 | (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no "); |
| 120 | p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)", |
| 121 | ( reg73 & 0x01) ? " on" : "off", |
| 122 | ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') : |
| 123 | ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') : |
| 124 | ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') : |
| 125 | ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?', |
| 126 | ( reg73 & 0x02) ? " on" : "off", |
| 127 | ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') : |
| 128 | ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') : |
| 129 | ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') : |
| 130 | ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?'); |
| 131 | p += sprintf(p, " %s (%c) %s (%c)\n", |
| 132 | ( reg7b & 0x01) ? " on" : "off", |
| 133 | ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') : |
| 134 | ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') : |
| 135 | ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') : |
| 136 | ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?', |
| 137 | ( reg7b & 0x02) ? " on" : "off", |
| 138 | ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') : |
| 139 | ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') : |
| 140 | ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') : |
| 141 | ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?'); |
| 142 | p += sprintf(p, "Interrupt: %s, %s %s, %s\n", |
| 143 | (reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled", |
| 144 | (reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ", |
| 145 | (reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled", |
| 146 | (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear "); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | |
| 148 | return (char *)p; |
| 149 | } |
| 150 | |
| 151 | static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count) |
| 152 | { |
| 153 | char *p = buffer; |
| 154 | int i; |
| 155 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | for (i = 0; i < n_cmd_devs; i++) { |
| 157 | struct pci_dev *dev = cmd_devs[i]; |
| 158 | p = print_cmd64x_get_info(p, dev, i); |
| 159 | } |
| 160 | return p-buffer; /* => must be less than 4k! */ |
| 161 | } |
| 162 | |
Bartlomiej Zolnierkiewicz | ecfd80e | 2007-05-10 00:01:09 +0200 | [diff] [blame] | 163 | #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | |
Sergei Shtylyov | e277a1a | 2007-03-17 21:57:24 +0100 | [diff] [blame] | 165 | static u8 quantize_timing(int timing, int quant) |
| 166 | { |
| 167 | return (timing + quant - 1) / quant; |
| 168 | } |
| 169 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | /* |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 171 | * This routine calculates active/recovery counts and then writes them into |
| 172 | * the chipset registers. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | */ |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 174 | static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | { |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 176 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
| 177 | int clock_time = 1000 / system_bus_clock(); |
| 178 | u8 cycle_count, active_count, recovery_count, drwtim; |
| 179 | static const u8 recovery_values[] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 181 | static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 182 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 183 | cmdprintk("program_cycle_times parameters: total=%d, active=%d\n", |
| 184 | cycle_time, active_time); |
| 185 | |
| 186 | cycle_count = quantize_timing( cycle_time, clock_time); |
| 187 | active_count = quantize_timing(active_time, clock_time); |
| 188 | recovery_count = cycle_count - active_count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | |
| 190 | /* |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 191 | * In case we've got too long recovery phase, try to lengthen |
| 192 | * the active phase |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | if (recovery_count > 16) { |
| 195 | active_count += recovery_count - 16; |
| 196 | recovery_count = 16; |
| 197 | } |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 198 | if (active_count > 16) /* shouldn't actually happen... */ |
| 199 | active_count = 16; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 201 | cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n", |
| 202 | cycle_count, active_count, recovery_count); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 204 | /* |
| 205 | * Convert values to internal chipset representation |
| 206 | */ |
| 207 | recovery_count = recovery_values[recovery_count]; |
| 208 | active_count &= 0x0f; |
| 209 | |
| 210 | /* Program the active/recovery counts into the DRWTIM register */ |
| 211 | drwtim = (active_count << 4) | recovery_count; |
| 212 | (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); |
| 213 | cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]); |
| 214 | } |
| 215 | |
| 216 | /* |
| 217 | * This routine selects drive's best PIO mode and writes into the chipset |
| 218 | * registers setup/active/recovery timings. |
| 219 | */ |
| 220 | static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted) |
| 221 | { |
| 222 | ide_hwif_t *hwif = HWIF(drive); |
| 223 | struct pci_dev *dev = hwif->pci_dev; |
Bartlomiej Zolnierkiewicz | 7dd0008 | 2007-07-20 01:11:56 +0200 | [diff] [blame] | 224 | unsigned int cycle_time; |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 225 | u8 pio_mode, setup_count, arttim = 0; |
| 226 | static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0}; |
| 227 | static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23}; |
Bartlomiej Zolnierkiewicz | 7dd0008 | 2007-07-20 01:11:56 +0200 | [diff] [blame] | 228 | |
Bartlomiej Zolnierkiewicz | 2134758 | 2007-07-20 01:11:58 +0200 | [diff] [blame] | 229 | pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5); |
Bartlomiej Zolnierkiewicz | 7dd0008 | 2007-07-20 01:11:56 +0200 | [diff] [blame] | 230 | cycle_time = ide_pio_cycle_time(drive, pio_mode); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 231 | |
Bartlomiej Zolnierkiewicz | 342cdb6 | 2007-07-20 01:11:55 +0200 | [diff] [blame] | 232 | cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)\n", |
Bartlomiej Zolnierkiewicz | 7dd0008 | 2007-07-20 01:11:56 +0200 | [diff] [blame] | 233 | drive->name, mode_wanted, pio_mode, cycle_time); |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 234 | |
Bartlomiej Zolnierkiewicz | 7dd0008 | 2007-07-20 01:11:56 +0200 | [diff] [blame] | 235 | program_cycle_times(drive, cycle_time, |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 236 | ide_pio_timings[pio_mode].active_time); |
| 237 | |
| 238 | setup_count = quantize_timing(ide_pio_timings[pio_mode].setup_time, |
| 239 | 1000 / system_bus_clock()); |
| 240 | |
| 241 | /* |
| 242 | * The primary channel has individual address setup timing registers |
| 243 | * for each drive and the hardware selects the slowest timing itself. |
| 244 | * The secondary channel has one common register and we have to select |
| 245 | * the slowest address setup timing ourselves. |
| 246 | */ |
| 247 | if (hwif->channel) { |
| 248 | ide_drive_t *drives = hwif->drives; |
| 249 | |
| 250 | drive->drive_data = setup_count; |
| 251 | setup_count = max(drives[0].drive_data, drives[1].drive_data); |
| 252 | } |
| 253 | |
| 254 | if (setup_count > 5) /* shouldn't actually happen... */ |
| 255 | setup_count = 5; |
| 256 | cmdprintk("Final address setup count: %d\n", setup_count); |
| 257 | |
| 258 | /* |
| 259 | * Program the address setup clocks into the ARTTIM registers. |
| 260 | * Avoid clearing the secondary channel's interrupt bit. |
| 261 | */ |
| 262 | (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim); |
| 263 | if (hwif->channel) |
| 264 | arttim &= ~ARTTIM23_INTR_CH1; |
| 265 | arttim &= ~0xc0; |
| 266 | arttim |= setup_values[setup_count]; |
| 267 | (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); |
| 268 | cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]); |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 269 | |
| 270 | return pio_mode; |
| 271 | } |
| 272 | |
| 273 | /* |
| 274 | * Attempts to set drive's PIO mode. |
| 275 | * Special cases are 8: prefetch off, 9: prefetch on (both never worked), |
| 276 | * and 255: auto-select best mode (used at boot time). |
| 277 | */ |
| 278 | static void cmd64x_tune_drive (ide_drive_t *drive, u8 pio) |
| 279 | { |
| 280 | /* |
| 281 | * Filter out the prefetch control values |
| 282 | * to prevent PIO5 from being programmed |
| 283 | */ |
| 284 | if (pio == 8 || pio == 9) |
| 285 | return; |
| 286 | |
| 287 | pio = cmd64x_tune_pio(drive, pio); |
| 288 | (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | } |
| 290 | |
Bartlomiej Zolnierkiewicz | f212ff2 | 2007-10-11 23:53:59 +0200 | [diff] [blame] | 291 | static int cmd64x_tune_chipset(ide_drive_t *drive, const u8 speed) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | { |
| 293 | ide_hwif_t *hwif = HWIF(drive); |
| 294 | struct pci_dev *dev = hwif->pci_dev; |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 295 | u8 unit = drive->dn & 0x01; |
| 296 | u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 298 | if (speed >= XFER_SW_DMA_0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | (void) pci_read_config_byte(dev, pciU, ®U); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 300 | regU &= ~(unit ? 0xCA : 0x35); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | } |
| 302 | |
| 303 | switch(speed) { |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 304 | case XFER_UDMA_5: |
| 305 | regU |= unit ? 0x0A : 0x05; |
| 306 | break; |
| 307 | case XFER_UDMA_4: |
| 308 | regU |= unit ? 0x4A : 0x15; |
| 309 | break; |
| 310 | case XFER_UDMA_3: |
| 311 | regU |= unit ? 0x8A : 0x25; |
| 312 | break; |
| 313 | case XFER_UDMA_2: |
| 314 | regU |= unit ? 0x42 : 0x11; |
| 315 | break; |
| 316 | case XFER_UDMA_1: |
| 317 | regU |= unit ? 0x82 : 0x21; |
| 318 | break; |
| 319 | case XFER_UDMA_0: |
| 320 | regU |= unit ? 0xC2 : 0x31; |
| 321 | break; |
| 322 | case XFER_MW_DMA_2: |
| 323 | program_cycle_times(drive, 120, 70); |
| 324 | break; |
| 325 | case XFER_MW_DMA_1: |
| 326 | program_cycle_times(drive, 150, 80); |
| 327 | break; |
| 328 | case XFER_MW_DMA_0: |
| 329 | program_cycle_times(drive, 480, 215); |
| 330 | break; |
| 331 | case XFER_PIO_5: |
| 332 | case XFER_PIO_4: |
| 333 | case XFER_PIO_3: |
| 334 | case XFER_PIO_2: |
| 335 | case XFER_PIO_1: |
| 336 | case XFER_PIO_0: |
| 337 | (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0); |
| 338 | break; |
| 339 | default: |
| 340 | return 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 341 | } |
| 342 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 343 | if (speed >= XFER_SW_DMA_0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 344 | (void) pci_write_config_byte(dev, pciU, regU); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 345 | |
Sergei Shtylyov | 60e7a82 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 346 | return ide_config_drive_speed(drive, speed); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 347 | } |
| 348 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 349 | static int cmd64x_config_drive_for_dma (ide_drive_t *drive) |
| 350 | { |
Bartlomiej Zolnierkiewicz | 4728d54 | 2007-05-16 00:51:46 +0200 | [diff] [blame] | 351 | if (ide_tune_dma(drive)) |
Bartlomiej Zolnierkiewicz | 3608b5d | 2007-02-17 02:40:26 +0100 | [diff] [blame] | 352 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | |
Bartlomiej Zolnierkiewicz | d8f4469 | 2007-02-17 02:40:25 +0100 | [diff] [blame] | 354 | if (ide_use_fast_pio(drive)) |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 355 | cmd64x_tune_drive(drive, 255); |
Bartlomiej Zolnierkiewicz | d8f4469 | 2007-02-17 02:40:25 +0100 | [diff] [blame] | 356 | |
Bartlomiej Zolnierkiewicz | 3608b5d | 2007-02-17 02:40:26 +0100 | [diff] [blame] | 357 | return -1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 358 | } |
| 359 | |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 360 | static int cmd648_ide_dma_end (ide_drive_t *drive) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | { |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 362 | ide_hwif_t *hwif = HWIF(drive); |
| 363 | int err = __ide_dma_end(drive); |
| 364 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : |
| 365 | MRDMODE_INTR_CH0; |
| 366 | u8 mrdmode = inb(hwif->dma_master + 0x01); |
| 367 | |
| 368 | /* clear the interrupt bit */ |
| 369 | outb(mrdmode | irq_mask, hwif->dma_master + 0x01); |
| 370 | |
| 371 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 372 | } |
| 373 | |
| 374 | static int cmd64x_ide_dma_end (ide_drive_t *drive) |
| 375 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 376 | ide_hwif_t *hwif = HWIF(drive); |
| 377 | struct pci_dev *dev = hwif->pci_dev; |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 378 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
| 379 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : |
| 380 | CFR_INTR_CH0; |
| 381 | u8 irq_stat = 0; |
| 382 | int err = __ide_dma_end(drive); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 383 | |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 384 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); |
| 385 | /* clear the interrupt bit */ |
| 386 | (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask); |
| 387 | |
| 388 | return err; |
| 389 | } |
| 390 | |
| 391 | static int cmd648_ide_dma_test_irq (ide_drive_t *drive) |
| 392 | { |
| 393 | ide_hwif_t *hwif = HWIF(drive); |
| 394 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : |
| 395 | MRDMODE_INTR_CH0; |
| 396 | u8 dma_stat = inb(hwif->dma_status); |
| 397 | u8 mrdmode = inb(hwif->dma_master + 0x01); |
| 398 | |
| 399 | #ifdef DEBUG |
| 400 | printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n", |
| 401 | drive->name, dma_stat, mrdmode, irq_mask); |
| 402 | #endif |
| 403 | if (!(mrdmode & irq_mask)) |
| 404 | return 0; |
| 405 | |
| 406 | /* return 1 if INTR asserted */ |
| 407 | if (dma_stat & 4) |
| 408 | return 1; |
| 409 | |
| 410 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 411 | } |
| 412 | |
| 413 | static int cmd64x_ide_dma_test_irq (ide_drive_t *drive) |
| 414 | { |
Sergei Shtylyov | e51e252 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 415 | ide_hwif_t *hwif = HWIF(drive); |
| 416 | struct pci_dev *dev = hwif->pci_dev; |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 417 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
| 418 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : |
| 419 | CFR_INTR_CH0; |
| 420 | u8 dma_stat = inb(hwif->dma_status); |
| 421 | u8 irq_stat = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 422 | |
Sergei Shtylyov | e51e252 | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 423 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); |
| 424 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 425 | #ifdef DEBUG |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 426 | printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n", |
| 427 | drive->name, dma_stat, irq_stat, irq_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 428 | #endif |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 429 | if (!(irq_stat & irq_mask)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 430 | return 0; |
| 431 | |
| 432 | /* return 1 if INTR asserted */ |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 433 | if (dma_stat & 4) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 434 | return 1; |
| 435 | |
| 436 | return 0; |
| 437 | } |
| 438 | |
| 439 | /* |
| 440 | * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old |
| 441 | * event order for DMA transfers. |
| 442 | */ |
| 443 | |
| 444 | static int cmd646_1_ide_dma_end (ide_drive_t *drive) |
| 445 | { |
| 446 | ide_hwif_t *hwif = HWIF(drive); |
| 447 | u8 dma_stat = 0, dma_cmd = 0; |
| 448 | |
| 449 | drive->waiting_for_dma = 0; |
| 450 | /* get DMA status */ |
Bartlomiej Zolnierkiewicz | 0ecdca2 | 2007-02-17 02:40:25 +0100 | [diff] [blame] | 451 | dma_stat = inb(hwif->dma_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 452 | /* read DMA command state */ |
Bartlomiej Zolnierkiewicz | 0ecdca2 | 2007-02-17 02:40:25 +0100 | [diff] [blame] | 453 | dma_cmd = inb(hwif->dma_command); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | /* stop DMA */ |
Bartlomiej Zolnierkiewicz | 0ecdca2 | 2007-02-17 02:40:25 +0100 | [diff] [blame] | 455 | outb(dma_cmd & ~1, hwif->dma_command); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | /* clear the INTR & ERROR bits */ |
Bartlomiej Zolnierkiewicz | 0ecdca2 | 2007-02-17 02:40:25 +0100 | [diff] [blame] | 457 | outb(dma_stat | 6, hwif->dma_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 458 | /* and free any DMA resources */ |
| 459 | ide_destroy_dmatable(drive); |
| 460 | /* verify good DMA status */ |
| 461 | return (dma_stat & 7) != 4; |
| 462 | } |
| 463 | |
| 464 | static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name) |
| 465 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 466 | u8 mrdmode = 0; |
| 467 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 468 | if (dev->device == PCI_DEVICE_ID_CMD_646) { |
| 469 | u8 rev = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 470 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 471 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); |
| 472 | |
| 473 | switch (rev) { |
| 474 | case 0x07: |
| 475 | case 0x05: |
Meelis Roos | b37c6b8 | 2007-08-01 23:46:44 +0200 | [diff] [blame] | 476 | printk("%s: UltraDMA capable\n", name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | break; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 478 | case 0x03: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | default: |
Meelis Roos | b37c6b8 | 2007-08-01 23:46:44 +0200 | [diff] [blame] | 480 | printk("%s: MultiWord DMA force limited\n", name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | break; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 482 | case 0x01: |
| 483 | printk("%s: MultiWord DMA limited, " |
| 484 | "IRQ workaround enabled\n", name); |
| 485 | break; |
| 486 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | } |
| 488 | |
| 489 | /* Set a good latency timer and cache line size value. */ |
| 490 | (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
| 491 | /* FIXME: pci_set_master() to ensure a good latency timer value */ |
| 492 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 493 | /* |
| 494 | * Enable interrupts, select MEMORY READ LINE for reads. |
| 495 | * |
| 496 | * NOTE: although not mentioned in the PCI0646U specs, |
| 497 | * bits 0-1 are write only and won't be read back as |
| 498 | * set or not -- PCI0646U2 specs clarify this point. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 499 | */ |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 500 | (void) pci_read_config_byte (dev, MRDMODE, &mrdmode); |
| 501 | mrdmode &= ~0x30; |
| 502 | (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | |
Bartlomiej Zolnierkiewicz | ecfd80e | 2007-05-10 00:01:09 +0200 | [diff] [blame] | 504 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 505 | |
| 506 | cmd_devs[n_cmd_devs++] = dev; |
| 507 | |
| 508 | if (!cmd64x_proc) { |
| 509 | cmd64x_proc = 1; |
| 510 | ide_pci_create_host_proc("cmd64x", cmd64x_get_info); |
| 511 | } |
Bartlomiej Zolnierkiewicz | ecfd80e | 2007-05-10 00:01:09 +0200 | [diff] [blame] | 512 | #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | |
| 514 | return 0; |
| 515 | } |
| 516 | |
Bartlomiej Zolnierkiewicz | 49521f9 | 2007-07-09 23:17:58 +0200 | [diff] [blame] | 517 | static u8 __devinit ata66_cmd64x(ide_hwif_t *hwif) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 518 | { |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 519 | struct pci_dev *dev = hwif->pci_dev; |
| 520 | u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 521 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 522 | switch (dev->device) { |
| 523 | case PCI_DEVICE_ID_CMD_648: |
| 524 | case PCI_DEVICE_ID_CMD_649: |
| 525 | pci_read_config_byte(dev, BMIDECSR, &bmidecsr); |
Bartlomiej Zolnierkiewicz | 49521f9 | 2007-07-09 23:17:58 +0200 | [diff] [blame] | 526 | return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 527 | default: |
Bartlomiej Zolnierkiewicz | 49521f9 | 2007-07-09 23:17:58 +0200 | [diff] [blame] | 528 | return ATA_CBL_PATA40; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 529 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 530 | } |
| 531 | |
| 532 | static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif) |
| 533 | { |
| 534 | struct pci_dev *dev = hwif->pci_dev; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 535 | u8 rev = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 537 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 538 | |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 539 | hwif->tuneproc = &cmd64x_tune_drive; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 540 | hwif->speedproc = &cmd64x_tune_chipset; |
| 541 | |
Sergei Shtylyov | f92d50e6 | 2007-03-03 17:48:53 +0100 | [diff] [blame] | 542 | hwif->drives[0].autotune = hwif->drives[1].autotune = 1; |
| 543 | |
| 544 | if (!hwif->dma_base) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 546 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 547 | hwif->atapi_dma = 1; |
| 548 | hwif->mwdma_mask = 0x07; |
Bartlomiej Zolnierkiewicz | 1813720 | 2007-05-10 00:01:07 +0200 | [diff] [blame] | 549 | hwif->ultra_mask = hwif->cds->udma_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 550 | |
Bartlomiej Zolnierkiewicz | 2d5eaa6 | 2007-05-10 00:01:08 +0200 | [diff] [blame] | 551 | /* |
| 552 | * UltraDMA only supported on PCI646U and PCI646U2, which |
| 553 | * correspond to revisions 0x03, 0x05 and 0x07 respectively. |
| 554 | * Actually, although the CMD tech support people won't |
| 555 | * tell me the details, the 0x03 revision cannot support |
| 556 | * UDMA correctly without hardware modifications, and even |
| 557 | * then it only works with Quantum disks due to some |
| 558 | * hold time assumptions in the 646U part which are fixed |
| 559 | * in the 646U2. |
| 560 | * |
| 561 | * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. |
| 562 | */ |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 563 | if (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 5) |
Bartlomiej Zolnierkiewicz | 1813720 | 2007-05-10 00:01:07 +0200 | [diff] [blame] | 564 | hwif->ultra_mask = 0x00; |
| 565 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 566 | hwif->ide_dma_check = &cmd64x_config_drive_for_dma; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 567 | |
Bartlomiej Zolnierkiewicz | 49521f9 | 2007-07-09 23:17:58 +0200 | [diff] [blame] | 568 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
| 569 | hwif->cbl = ata66_cmd64x(hwif); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 570 | |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 571 | switch (dev->device) { |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 572 | case PCI_DEVICE_ID_CMD_648: |
| 573 | case PCI_DEVICE_ID_CMD_649: |
| 574 | alt_irq_bits: |
| 575 | hwif->ide_dma_end = &cmd648_ide_dma_end; |
| 576 | hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq; |
| 577 | break; |
| 578 | case PCI_DEVICE_ID_CMD_646: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 579 | hwif->chipset = ide_cmd646; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 580 | if (rev == 0x01) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 581 | hwif->ide_dma_end = &cmd646_1_ide_dma_end; |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 582 | break; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 583 | } else if (rev >= 0x03) |
Sergei Shtylyov | 66602c8 | 2007-05-05 22:03:50 +0200 | [diff] [blame] | 584 | goto alt_irq_bits; |
| 585 | /* fall thru */ |
| 586 | default: |
| 587 | hwif->ide_dma_end = &cmd64x_ide_dma_end; |
| 588 | hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq; |
| 589 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 590 | } |
| 591 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 592 | if (!noautodma) |
| 593 | hwif->autodma = 1; |
Sergei Shtylyov | 83a6d4a | 2007-07-09 23:17:55 +0200 | [diff] [blame] | 594 | hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 595 | } |
| 596 | |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 597 | static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d) |
| 598 | { |
| 599 | return ide_setup_pci_device(dev, d); |
| 600 | } |
| 601 | |
| 602 | static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d) |
| 603 | { |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 604 | /* |
| 605 | * The original PCI0646 didn't have the primary channel enable bit, |
| 606 | * it appeared starting with PCI0646U (i.e. revision ID 3). |
| 607 | */ |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 608 | if (dev->revision < 3) |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 609 | d->enablebits[0].reg = 0; |
| 610 | |
| 611 | return ide_setup_pci_device(dev, d); |
| 612 | } |
| 613 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | static ide_pci_device_t cmd64x_chipsets[] __devinitdata = { |
| 615 | { /* 0 */ |
| 616 | .name = "CMD643", |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 617 | .init_setup = init_setup_cmd64x, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | .init_chipset = init_chipset_cmd64x, |
| 619 | .init_hwif = init_hwif_cmd64x, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | .autodma = AUTODMA, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 621 | .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | .bootable = ON_BOARD, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 623 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 1813720 | 2007-05-10 00:01:07 +0200 | [diff] [blame] | 624 | .udma_mask = 0x00, /* no udma */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 625 | },{ /* 1 */ |
| 626 | .name = "CMD646", |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 627 | .init_setup = init_setup_cmd646, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 628 | .init_chipset = init_chipset_cmd64x, |
| 629 | .init_hwif = init_hwif_cmd64x, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 630 | .autodma = AUTODMA, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 631 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 632 | .bootable = ON_BOARD, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 633 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 1813720 | 2007-05-10 00:01:07 +0200 | [diff] [blame] | 634 | .udma_mask = 0x07, /* udma0-2 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 635 | },{ /* 2 */ |
| 636 | .name = "CMD648", |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 637 | .init_setup = init_setup_cmd64x, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 638 | .init_chipset = init_chipset_cmd64x, |
| 639 | .init_hwif = init_hwif_cmd64x, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | .autodma = AUTODMA, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 641 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 642 | .bootable = ON_BOARD, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 643 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 1813720 | 2007-05-10 00:01:07 +0200 | [diff] [blame] | 644 | .udma_mask = 0x1f, /* udma0-4 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 645 | },{ /* 3 */ |
| 646 | .name = "CMD649", |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 647 | .init_setup = init_setup_cmd64x, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 648 | .init_chipset = init_chipset_cmd64x, |
| 649 | .init_hwif = init_hwif_cmd64x, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | .autodma = AUTODMA, |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 651 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 652 | .bootable = ON_BOARD, |
Bartlomiej Zolnierkiewicz | 4099d14 | 2007-07-20 01:11:59 +0200 | [diff] [blame] | 653 | .pio_mask = ATA_PIO5, |
Bartlomiej Zolnierkiewicz | 1813720 | 2007-05-10 00:01:07 +0200 | [diff] [blame] | 654 | .udma_mask = 0x3f, /* udma0-5 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 655 | } |
| 656 | }; |
| 657 | |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 658 | /* |
| 659 | * We may have to modify enablebits for PCI0646, so we'd better pass |
| 660 | * a local copy of the ide_pci_device_t structure down the call chain... |
| 661 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 662 | static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
| 663 | { |
Sergei Shtylyov | 7accbff | 2007-05-05 22:03:49 +0200 | [diff] [blame] | 664 | ide_pci_device_t d = cmd64x_chipsets[id->driver_data]; |
| 665 | |
| 666 | return d.init_setup(dev, &d); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 667 | } |
| 668 | |
| 669 | static struct pci_device_id cmd64x_pci_tbl[] = { |
| 670 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
| 671 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, |
| 672 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, |
| 673 | { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, |
| 674 | { 0, }, |
| 675 | }; |
| 676 | MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl); |
| 677 | |
| 678 | static struct pci_driver driver = { |
| 679 | .name = "CMD64x_IDE", |
| 680 | .id_table = cmd64x_pci_tbl, |
| 681 | .probe = cmd64x_init_one, |
| 682 | }; |
| 683 | |
Bartlomiej Zolnierkiewicz | 82ab1ee | 2007-01-27 13:46:56 +0100 | [diff] [blame] | 684 | static int __init cmd64x_ide_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 685 | { |
| 686 | return ide_pci_register_driver(&driver); |
| 687 | } |
| 688 | |
| 689 | module_init(cmd64x_ide_init); |
| 690 | |
| 691 | MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); |
| 692 | MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); |
| 693 | MODULE_LICENSE("GPL"); |