blob: 55b50895503e0a41f3fc74948627a8103a05800a [file] [log] [blame]
Rajendra Nayak99e79382012-11-02 05:02:58 -06001/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
9 * With many device clock fixes by Kevin Hilman and Jouni Högander
10 * DPLL bypass clock support added by Roman Tereshonkov
11 *
12 */
13
14/*
15 * Virtual clocks are introduced as convenient tools.
16 * They are sources for other clocks and not supposed
17 * to be requested from drivers directly.
18 */
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/clk-private.h>
23#include <linux/list.h>
24#include <linux/io.h>
25
26#include "soc.h"
27#include "iomap.h"
28#include "clock.h"
29#include "clock3xxx.h"
30#include "clock34xx.h"
31#include "clock36xx.h"
32#include "clock3517.h"
33#include "cm3xxx.h"
34#include "cm-regbits-34xx.h"
35#include "prm3xxx.h"
36#include "prm-regbits-34xx.h"
37#include "control.h"
38
39/*
40 * clocks
41 */
42
43#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
44
45/* Maximum DPLL multiplier, divider values for OMAP3 */
46#define OMAP3_MAX_DPLL_MULT 2047
47#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
48#define OMAP3_MAX_DPLL_DIV 128
49
50DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
51
52DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
53
54DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
55
56DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
57
58DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
59
60DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
61
62DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
63
64DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
65
66DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
67
68DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
69
70DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
71
72DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
73
74DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
75
76static const char *osc_sys_ck_parent_names[] = {
77 "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
78 "virt_38_4m_ck", "virt_16_8m_ck",
79};
80
81DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
82 OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
83 OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
84
85DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
86 OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
87 OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
88
89static struct dpll_data dpll3_dd = {
90 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
91 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
92 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
93 .clk_bypass = &sys_ck,
94 .clk_ref = &sys_ck,
95 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
96 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
97 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
98 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
99 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
100 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
101 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
102 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
103 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
104 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
105 .max_multiplier = OMAP3_MAX_DPLL_MULT,
106 .min_divider = 1,
107 .max_divider = OMAP3_MAX_DPLL_DIV,
108};
109
110static struct clk dpll3_ck;
111
112static const char *dpll3_ck_parent_names[] = {
113 "sys_ck",
114};
115
116static const struct clk_ops dpll3_ck_ops = {
117 .init = &omap2_init_clk_clkdm,
118 .get_parent = &omap2_init_dpll_parent,
119 .recalc_rate = &omap3_dpll_recalc,
120 .round_rate = &omap2_dpll_round_rate,
121};
122
123static struct clk_hw_omap dpll3_ck_hw = {
124 .hw = {
125 .clk = &dpll3_ck,
126 },
127 .ops = &clkhwops_omap3_dpll,
128 .dpll_data = &dpll3_dd,
129 .clkdm_name = "dpll3_clkdm",
130};
131
132DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
133
134DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
135 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
136 OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
137 OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
138 CLK_DIVIDER_ONE_BASED, NULL);
139
140static struct clk core_ck;
141
142static const char *core_ck_parent_names[] = {
143 "dpll3_m2_ck",
144};
145
146static const struct clk_ops core_ck_ops = {};
147
148DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
149DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
150
151DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
153 OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
154 CLK_DIVIDER_ONE_BASED, NULL);
155
156DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
157 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
158 OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
159 CLK_DIVIDER_ONE_BASED, NULL);
160
161static struct clk security_l4_ick2;
162
163static const char *security_l4_ick2_parent_names[] = {
164 "l4_ick",
165};
166
167DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
168DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
169
170static struct clk aes1_ick;
171
172static const char *aes1_ick_parent_names[] = {
173 "security_l4_ick2",
174};
175
176static const struct clk_ops aes1_ick_ops = {
177 .enable = &omap2_dflt_clk_enable,
178 .disable = &omap2_dflt_clk_disable,
179 .is_enabled = &omap2_dflt_clk_is_enabled,
180};
181
182static struct clk_hw_omap aes1_ick_hw = {
183 .hw = {
184 .clk = &aes1_ick,
185 },
186 .ops = &clkhwops_iclk_wait,
187 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
188 .enable_bit = OMAP3430_EN_AES1_SHIFT,
189};
190
191DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
192
193static struct clk core_l4_ick;
194
195static const struct clk_ops core_l4_ick_ops = {
196 .init = &omap2_init_clk_clkdm,
197};
198
199DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
200DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
201
202static struct clk aes2_ick;
203
204static const char *aes2_ick_parent_names[] = {
205 "core_l4_ick",
206};
207
208static const struct clk_ops aes2_ick_ops = {
209 .init = &omap2_init_clk_clkdm,
210 .enable = &omap2_dflt_clk_enable,
211 .disable = &omap2_dflt_clk_disable,
212 .is_enabled = &omap2_dflt_clk_is_enabled,
213};
214
215static struct clk_hw_omap aes2_ick_hw = {
216 .hw = {
217 .clk = &aes2_ick,
218 },
219 .ops = &clkhwops_iclk_wait,
220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
221 .enable_bit = OMAP3430_EN_AES2_SHIFT,
222 .clkdm_name = "core_l4_clkdm",
223};
224
225DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
226
227static struct clk dpll1_fck;
228
229static struct dpll_data dpll1_dd = {
230 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
231 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
232 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
233 .clk_bypass = &dpll1_fck,
234 .clk_ref = &sys_ck,
235 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
236 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
237 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
238 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
239 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
240 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
241 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
242 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
243 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
244 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
245 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
246 .max_multiplier = OMAP3_MAX_DPLL_MULT,
247 .min_divider = 1,
248 .max_divider = OMAP3_MAX_DPLL_DIV,
249};
250
251static struct clk dpll1_ck;
252
253static const struct clk_ops dpll1_ck_ops = {
254 .init = &omap2_init_clk_clkdm,
255 .enable = &omap3_noncore_dpll_enable,
256 .disable = &omap3_noncore_dpll_disable,
257 .get_parent = &omap2_init_dpll_parent,
258 .recalc_rate = &omap3_dpll_recalc,
259 .set_rate = &omap3_noncore_dpll_set_rate,
260 .round_rate = &omap2_dpll_round_rate,
261};
262
263static struct clk_hw_omap dpll1_ck_hw = {
264 .hw = {
265 .clk = &dpll1_ck,
266 },
267 .ops = &clkhwops_omap3_dpll,
268 .dpll_data = &dpll1_dd,
269 .clkdm_name = "dpll1_clkdm",
270};
271
272DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
273
274DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
275
276DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
277 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
278 OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
279 OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
280 CLK_DIVIDER_ONE_BASED, NULL);
281
282static struct clk mpu_ck;
283
284static const char *mpu_ck_parent_names[] = {
285 "dpll1_x2m2_ck",
286};
287
288DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
289DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
290
291DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
292 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
293 OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
294 0x0, NULL);
295
296static struct clk cam_ick;
297
298static struct clk_hw_omap cam_ick_hw = {
299 .hw = {
300 .clk = &cam_ick,
301 },
302 .ops = &clkhwops_iclk,
303 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
304 .enable_bit = OMAP3430_EN_CAM_SHIFT,
305 .clkdm_name = "cam_clkdm",
306};
307
308DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
309
310/* DPLL4 */
311/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
312/* Type: DPLL */
313static struct dpll_data dpll4_dd;
314
315static struct dpll_data dpll4_dd_34xx __initdata = {
316 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
317 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
318 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
319 .clk_bypass = &sys_ck,
320 .clk_ref = &sys_ck,
321 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
322 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
323 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
324 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
325 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
326 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
327 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
328 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
329 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
330 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
331 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
332 .max_multiplier = OMAP3_MAX_DPLL_MULT,
333 .min_divider = 1,
334 .max_divider = OMAP3_MAX_DPLL_DIV,
335};
336
337static struct dpll_data dpll4_dd_3630 __initdata = {
338 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
339 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
340 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
341 .clk_bypass = &sys_ck,
342 .clk_ref = &sys_ck,
343 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
344 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
345 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
346 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
347 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
348 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
349 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
350 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
351 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
352 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
353 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
354 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
355 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
356 .min_divider = 1,
357 .max_divider = OMAP3_MAX_DPLL_DIV,
358 .flags = DPLL_J_TYPE
359};
360
361static struct clk dpll4_ck;
362
363static const struct clk_ops dpll4_ck_ops = {
364 .init = &omap2_init_clk_clkdm,
365 .enable = &omap3_noncore_dpll_enable,
366 .disable = &omap3_noncore_dpll_disable,
367 .get_parent = &omap2_init_dpll_parent,
368 .recalc_rate = &omap3_dpll_recalc,
369 .set_rate = &omap3_dpll4_set_rate,
370 .round_rate = &omap2_dpll_round_rate,
371};
372
373static struct clk_hw_omap dpll4_ck_hw = {
374 .hw = {
375 .clk = &dpll4_ck,
376 },
377 .dpll_data = &dpll4_dd,
378 .ops = &clkhwops_omap3_dpll,
379 .clkdm_name = "dpll4_clkdm",
380};
381
382DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
383
384DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
385 OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
386 OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
387 CLK_DIVIDER_ONE_BASED, NULL);
388
389static struct clk dpll4_m5x2_ck;
390
391static const char *dpll4_m5x2_ck_parent_names[] = {
392 "dpll4_m5_ck",
393};
394
395static const struct clk_ops dpll4_m5x2_ck_ops = {
396 .init = &omap2_init_clk_clkdm,
397 .enable = &omap2_dflt_clk_enable,
398 .disable = &omap2_dflt_clk_disable,
399 .is_enabled = &omap2_dflt_clk_is_enabled,
400 .recalc_rate = &omap3_clkoutx2_recalc,
401};
402
403static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
404 .init = &omap2_init_clk_clkdm,
405 .enable = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
406 .disable = &omap2_dflt_clk_disable,
407 .recalc_rate = &omap3_clkoutx2_recalc,
408};
409
410static struct clk_hw_omap dpll4_m5x2_ck_hw = {
411 .hw = {
412 .clk = &dpll4_m5x2_ck,
413 },
414 .ops = &clkhwops_wait,
415 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
416 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
417 .flags = INVERT_ENABLE,
418 .clkdm_name = "dpll4_clkdm",
419};
420
421DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops);
422
423static struct clk dpll4_m5x2_ck_3630 = {
424 .name = "dpll4_m5x2_ck",
425 .hw = &dpll4_m5x2_ck_hw.hw,
426 .parent_names = dpll4_m5x2_ck_parent_names,
427 .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
428 .ops = &dpll4_m5x2_ck_3630_ops,
Laurent Pinchart7b2e1272012-11-10 12:04:15 +0100429 .flags = CLK_SET_RATE_PARENT,
Rajendra Nayak99e79382012-11-02 05:02:58 -0600430};
431
432static struct clk cam_mclk;
433
434static const char *cam_mclk_parent_names[] = {
435 "dpll4_m5x2_ck",
436};
437
438static struct clk_hw_omap cam_mclk_hw = {
439 .hw = {
440 .clk = &cam_mclk,
441 },
442 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
443 .enable_bit = OMAP3430_EN_CAM_SHIFT,
444 .clkdm_name = "cam_clkdm",
445};
446
Laurent Pinchart7b2e1272012-11-10 12:04:15 +0100447static struct clk cam_mclk = {
448 .name = "cam_mclk",
449 .hw = &cam_mclk_hw.hw,
450 .parent_names = cam_mclk_parent_names,
451 .num_parents = ARRAY_SIZE(cam_mclk_parent_names),
452 .ops = &aes2_ick_ops,
453 .flags = CLK_SET_RATE_PARENT,
454};
Rajendra Nayak99e79382012-11-02 05:02:58 -0600455
456static const struct clksel_rate clkout2_src_core_rates[] = {
457 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
458 { .div = 0 }
459};
460
461static const struct clksel_rate clkout2_src_sys_rates[] = {
462 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
463 { .div = 0 }
464};
465
466static const struct clksel_rate clkout2_src_96m_rates[] = {
467 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
468 { .div = 0 }
469};
470
471DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
472 OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
473 OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
474 CLK_DIVIDER_ONE_BASED, NULL);
475
476static struct clk dpll4_m2x2_ck;
477
478static const char *dpll4_m2x2_ck_parent_names[] = {
479 "dpll4_m2_ck",
480};
481
482static struct clk_hw_omap dpll4_m2x2_ck_hw = {
483 .hw = {
484 .clk = &dpll4_m2x2_ck,
485 },
486 .ops = &clkhwops_wait,
487 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
488 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
489 .flags = INVERT_ENABLE,
490 .clkdm_name = "dpll4_clkdm",
491};
492
493DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
494
495static struct clk dpll4_m2x2_ck_3630 = {
496 .name = "dpll4_m2x2_ck",
497 .hw = &dpll4_m2x2_ck_hw.hw,
498 .parent_names = dpll4_m2x2_ck_parent_names,
499 .num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
500 .ops = &dpll4_m5x2_ck_3630_ops,
501};
502
503static struct clk omap_96m_alwon_fck;
504
505static const char *omap_96m_alwon_fck_parent_names[] = {
506 "dpll4_m2x2_ck",
507};
508
509DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
510DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
511 core_ck_ops);
512
513static struct clk cm_96m_fck;
514
515static const char *cm_96m_fck_parent_names[] = {
516 "omap_96m_alwon_fck",
517};
518
519DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
520DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
521
522static const struct clksel_rate clkout2_src_54m_rates[] = {
523 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
524 { .div = 0 }
525};
526
527DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
528 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
529 OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
530 CLK_DIVIDER_ONE_BASED, NULL);
531
532static struct clk dpll4_m3x2_ck;
533
534static const char *dpll4_m3x2_ck_parent_names[] = {
535 "dpll4_m3_ck",
536};
537
538static struct clk_hw_omap dpll4_m3x2_ck_hw = {
539 .hw = {
540 .clk = &dpll4_m3x2_ck,
541 },
542 .ops = &clkhwops_wait,
543 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
544 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
545 .flags = INVERT_ENABLE,
546 .clkdm_name = "dpll4_clkdm",
547};
548
549DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
550
551static struct clk dpll4_m3x2_ck_3630 = {
552 .name = "dpll4_m3x2_ck",
553 .hw = &dpll4_m3x2_ck_hw.hw,
554 .parent_names = dpll4_m3x2_ck_parent_names,
555 .num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
556 .ops = &dpll4_m5x2_ck_3630_ops,
557};
558
559static const char *omap_54m_fck_parent_names[] = {
560 "dpll4_m3x2_ck", "sys_altclk",
561};
562
563DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
564 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
565 OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
566
567static const struct clksel clkout2_src_clksel[] = {
568 { .parent = &core_ck, .rates = clkout2_src_core_rates },
569 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
570 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
571 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
572 { .parent = NULL },
573};
574
575static const char *clkout2_src_ck_parent_names[] = {
576 "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
577};
578
579static const struct clk_ops clkout2_src_ck_ops = {
580 .init = &omap2_init_clk_clkdm,
581 .enable = &omap2_dflt_clk_enable,
582 .disable = &omap2_dflt_clk_disable,
583 .is_enabled = &omap2_dflt_clk_is_enabled,
584 .recalc_rate = &omap2_clksel_recalc,
585 .get_parent = &omap2_clksel_find_parent_index,
586 .set_parent = &omap2_clksel_set_parent,
587};
588
589DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
590 clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
591 OMAP3430_CLKOUT2SOURCE_MASK,
592 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
593 NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
594
595static const struct clksel_rate omap_48m_cm96m_rates[] = {
596 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
597 { .div = 0 }
598};
599
600static const struct clksel_rate omap_48m_alt_rates[] = {
601 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
602 { .div = 0 }
603};
604
605static const struct clksel omap_48m_clksel[] = {
606 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
607 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
608 { .parent = NULL },
609};
610
611static const char *omap_48m_fck_parent_names[] = {
612 "cm_96m_fck", "sys_altclk",
613};
614
615static struct clk omap_48m_fck;
616
617static const struct clk_ops omap_48m_fck_ops = {
618 .recalc_rate = &omap2_clksel_recalc,
619 .get_parent = &omap2_clksel_find_parent_index,
620 .set_parent = &omap2_clksel_set_parent,
621};
622
623static struct clk_hw_omap omap_48m_fck_hw = {
624 .hw = {
625 .clk = &omap_48m_fck,
626 },
627 .clksel = omap_48m_clksel,
628 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
629 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
630};
631
632DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
633
634DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
635
636static struct clk core_12m_fck;
637
638static const char *core_12m_fck_parent_names[] = {
639 "omap_12m_fck",
640};
641
642DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
643DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
644
645static struct clk core_48m_fck;
646
647static const char *core_48m_fck_parent_names[] = {
648 "omap_48m_fck",
649};
650
651DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
652DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
653
654static const char *omap_96m_fck_parent_names[] = {
655 "cm_96m_fck", "sys_ck",
656};
657
658DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
659 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
660 OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
661
662static struct clk core_96m_fck;
663
664static const char *core_96m_fck_parent_names[] = {
665 "omap_96m_fck",
666};
667
668DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
669DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
670
671static struct clk core_l3_ick;
672
673static const char *core_l3_ick_parent_names[] = {
674 "l3_ick",
675};
676
677DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
678DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
679
680DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
681
682static struct clk corex2_fck;
683
684static const char *corex2_fck_parent_names[] = {
685 "dpll3_m2x2_ck",
686};
687
688DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
689DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
690
691static struct clk cpefuse_fck;
692
693static struct clk_hw_omap cpefuse_fck_hw = {
694 .hw = {
695 .clk = &cpefuse_fck,
696 },
697 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
698 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
699 .clkdm_name = "core_l4_clkdm",
700};
701
702DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
703
704static struct clk csi2_96m_fck;
705
706static const char *csi2_96m_fck_parent_names[] = {
707 "core_96m_fck",
708};
709
710static struct clk_hw_omap csi2_96m_fck_hw = {
711 .hw = {
712 .clk = &csi2_96m_fck,
713 },
714 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
715 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
716 .clkdm_name = "cam_clkdm",
717};
718
719DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
720
721static struct clk d2d_26m_fck;
722
723static struct clk_hw_omap d2d_26m_fck_hw = {
724 .hw = {
725 .clk = &d2d_26m_fck,
726 },
727 .ops = &clkhwops_wait,
728 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
729 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
730 .clkdm_name = "d2d_clkdm",
731};
732
733DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
734
735static struct clk des1_ick;
736
737static struct clk_hw_omap des1_ick_hw = {
738 .hw = {
739 .clk = &des1_ick,
740 },
741 .ops = &clkhwops_iclk_wait,
742 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
743 .enable_bit = OMAP3430_EN_DES1_SHIFT,
744};
745
746DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
747
748static struct clk des2_ick;
749
750static struct clk_hw_omap des2_ick_hw = {
751 .hw = {
752 .clk = &des2_ick,
753 },
754 .ops = &clkhwops_iclk_wait,
755 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
756 .enable_bit = OMAP3430_EN_DES2_SHIFT,
757 .clkdm_name = "core_l4_clkdm",
758};
759
760DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
761
762DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
763 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
764 OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
765 CLK_DIVIDER_ONE_BASED, NULL);
766
767static struct clk dpll2_fck;
768
769static struct dpll_data dpll2_dd = {
770 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
771 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
772 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
773 .clk_bypass = &dpll2_fck,
774 .clk_ref = &sys_ck,
775 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
776 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
777 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
778 .modes = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
779 (1 << DPLL_LOW_POWER_BYPASS)),
780 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
781 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
782 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
783 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
784 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
785 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
786 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
787 .max_multiplier = OMAP3_MAX_DPLL_MULT,
788 .min_divider = 1,
789 .max_divider = OMAP3_MAX_DPLL_DIV,
790};
791
792static struct clk dpll2_ck;
793
794static struct clk_hw_omap dpll2_ck_hw = {
795 .hw = {
796 .clk = &dpll2_ck,
797 },
798 .ops = &clkhwops_omap3_dpll,
799 .dpll_data = &dpll2_dd,
800 .clkdm_name = "dpll2_clkdm",
801};
802
803DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
804
805DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
806 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
807 OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
808 CLK_DIVIDER_ONE_BASED, NULL);
809
810DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
811 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
812 OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
813 OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
814 CLK_DIVIDER_ONE_BASED, NULL);
815
816DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
817 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
818 OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
819 CLK_DIVIDER_ONE_BASED, NULL);
820
821static struct clk dpll3_m3x2_ck;
822
823static const char *dpll3_m3x2_ck_parent_names[] = {
824 "dpll3_m3_ck",
825};
826
827static struct clk_hw_omap dpll3_m3x2_ck_hw = {
828 .hw = {
829 .clk = &dpll3_m3x2_ck,
830 },
831 .ops = &clkhwops_wait,
832 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
833 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
834 .flags = INVERT_ENABLE,
835 .clkdm_name = "dpll3_clkdm",
836};
837
838DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
839
840static struct clk dpll3_m3x2_ck_3630 = {
841 .name = "dpll3_m3x2_ck",
842 .hw = &dpll3_m3x2_ck_hw.hw,
843 .parent_names = dpll3_m3x2_ck_parent_names,
844 .num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
845 .ops = &dpll4_m5x2_ck_3630_ops,
846};
847
848DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
849
850DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
851 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
852 OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
853 CLK_DIVIDER_ONE_BASED, NULL);
854
855static struct clk dpll4_m4x2_ck;
856
857static const char *dpll4_m4x2_ck_parent_names[] = {
858 "dpll4_m4_ck",
859};
860
861static struct clk_hw_omap dpll4_m4x2_ck_hw = {
862 .hw = {
863 .clk = &dpll4_m4x2_ck,
864 },
865 .ops = &clkhwops_wait,
866 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
867 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
868 .flags = INVERT_ENABLE,
869 .clkdm_name = "dpll4_clkdm",
870};
871
872DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops);
873
874static struct clk dpll4_m4x2_ck_3630 = {
875 .name = "dpll4_m4x2_ck",
876 .hw = &dpll4_m4x2_ck_hw.hw,
877 .parent_names = dpll4_m4x2_ck_parent_names,
878 .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
879 .ops = &dpll4_m5x2_ck_3630_ops,
880};
881
882DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
883 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
884 OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
885 CLK_DIVIDER_ONE_BASED, NULL);
886
887static struct clk dpll4_m6x2_ck;
888
889static const char *dpll4_m6x2_ck_parent_names[] = {
890 "dpll4_m6_ck",
891};
892
893static struct clk_hw_omap dpll4_m6x2_ck_hw = {
894 .hw = {
895 .clk = &dpll4_m6x2_ck,
896 },
897 .ops = &clkhwops_wait,
898 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
899 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
900 .flags = INVERT_ENABLE,
901 .clkdm_name = "dpll4_clkdm",
902};
903
904DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
905
906static struct clk dpll4_m6x2_ck_3630 = {
907 .name = "dpll4_m6x2_ck",
908 .hw = &dpll4_m6x2_ck_hw.hw,
909 .parent_names = dpll4_m6x2_ck_parent_names,
910 .num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
911 .ops = &dpll4_m5x2_ck_3630_ops,
912};
913
914DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
915
916static struct dpll_data dpll5_dd = {
917 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
918 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
919 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
920 .clk_bypass = &sys_ck,
921 .clk_ref = &sys_ck,
922 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
923 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
924 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
925 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
926 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
927 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
928 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
929 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
930 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
931 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
932 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
933 .max_multiplier = OMAP3_MAX_DPLL_MULT,
934 .min_divider = 1,
935 .max_divider = OMAP3_MAX_DPLL_DIV,
936};
937
938static struct clk dpll5_ck;
939
940static struct clk_hw_omap dpll5_ck_hw = {
941 .hw = {
942 .clk = &dpll5_ck,
943 },
944 .ops = &clkhwops_omap3_dpll,
945 .dpll_data = &dpll5_dd,
946 .clkdm_name = "dpll5_clkdm",
947};
948
949DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
950
951DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
952 OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
953 OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
954 CLK_DIVIDER_ONE_BASED, NULL);
955
956static struct clk dss1_alwon_fck_3430es1;
957
958static const char *dss1_alwon_fck_3430es1_parent_names[] = {
959 "dpll4_m4x2_ck",
960};
961
962static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
963 .hw = {
964 .clk = &dss1_alwon_fck_3430es1,
965 },
966 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
967 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
968 .clkdm_name = "dss_clkdm",
969};
970
971DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names,
972 aes2_ick_ops);
973
974static struct clk dss1_alwon_fck_3430es2;
975
976static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
977 .hw = {
978 .clk = &dss1_alwon_fck_3430es2,
979 },
980 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
981 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
982 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
983 .clkdm_name = "dss_clkdm",
984};
985
986DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names,
987 aes2_ick_ops);
988
989static struct clk dss2_alwon_fck;
990
991static struct clk_hw_omap dss2_alwon_fck_hw = {
992 .hw = {
993 .clk = &dss2_alwon_fck,
994 },
995 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
996 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
997 .clkdm_name = "dss_clkdm",
998};
999
1000DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
1001
1002static struct clk dss_96m_fck;
1003
1004static struct clk_hw_omap dss_96m_fck_hw = {
1005 .hw = {
1006 .clk = &dss_96m_fck,
1007 },
1008 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1009 .enable_bit = OMAP3430_EN_TV_SHIFT,
1010 .clkdm_name = "dss_clkdm",
1011};
1012
1013DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
1014
1015static struct clk dss_ick_3430es1;
1016
1017static struct clk_hw_omap dss_ick_3430es1_hw = {
1018 .hw = {
1019 .clk = &dss_ick_3430es1,
1020 },
1021 .ops = &clkhwops_iclk,
1022 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1023 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1024 .clkdm_name = "dss_clkdm",
1025};
1026
1027DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
1028
1029static struct clk dss_ick_3430es2;
1030
1031static struct clk_hw_omap dss_ick_3430es2_hw = {
1032 .hw = {
1033 .clk = &dss_ick_3430es2,
1034 },
1035 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
1036 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1037 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1038 .clkdm_name = "dss_clkdm",
1039};
1040
1041DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
1042
1043static struct clk dss_tv_fck;
1044
1045static const char *dss_tv_fck_parent_names[] = {
1046 "omap_54m_fck",
1047};
1048
1049static struct clk_hw_omap dss_tv_fck_hw = {
1050 .hw = {
1051 .clk = &dss_tv_fck,
1052 },
1053 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1054 .enable_bit = OMAP3430_EN_TV_SHIFT,
1055 .clkdm_name = "dss_clkdm",
1056};
1057
1058DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
1059
1060static struct clk emac_fck;
1061
1062static const char *emac_fck_parent_names[] = {
1063 "rmii_ck",
1064};
1065
1066static struct clk_hw_omap emac_fck_hw = {
1067 .hw = {
1068 .clk = &emac_fck,
1069 },
1070 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1071 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
1072};
1073
1074DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
1075
1076static struct clk ipss_ick;
1077
1078static const char *ipss_ick_parent_names[] = {
1079 "core_l3_ick",
1080};
1081
1082static struct clk_hw_omap ipss_ick_hw = {
1083 .hw = {
1084 .clk = &ipss_ick,
1085 },
1086 .ops = &clkhwops_am35xx_ipss_wait,
1087 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1088 .enable_bit = AM35XX_EN_IPSS_SHIFT,
1089 .clkdm_name = "core_l3_clkdm",
1090};
1091
1092DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
1093
1094static struct clk emac_ick;
1095
1096static const char *emac_ick_parent_names[] = {
1097 "ipss_ick",
1098};
1099
1100static struct clk_hw_omap emac_ick_hw = {
1101 .hw = {
1102 .clk = &emac_ick,
1103 },
1104 .ops = &clkhwops_am35xx_ipss_module_wait,
1105 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1106 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
1107 .clkdm_name = "core_l3_clkdm",
1108};
1109
1110DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
1111
1112static struct clk emu_core_alwon_ck;
1113
1114static const char *emu_core_alwon_ck_parent_names[] = {
1115 "dpll3_m3x2_ck",
1116};
1117
1118DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
1119DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
1120 core_l4_ick_ops);
1121
1122static struct clk emu_mpu_alwon_ck;
1123
1124static const char *emu_mpu_alwon_ck_parent_names[] = {
1125 "mpu_ck",
1126};
1127
1128DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
1129DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
1130
1131static struct clk emu_per_alwon_ck;
1132
1133static const char *emu_per_alwon_ck_parent_names[] = {
1134 "dpll4_m6x2_ck",
1135};
1136
1137DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
1138DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
1139 core_l4_ick_ops);
1140
1141static const char *emu_src_ck_parent_names[] = {
1142 "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1143};
1144
1145static const struct clksel_rate emu_src_sys_rates[] = {
1146 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1147 { .div = 0 },
1148};
1149
1150static const struct clksel_rate emu_src_core_rates[] = {
1151 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1152 { .div = 0 },
1153};
1154
1155static const struct clksel_rate emu_src_per_rates[] = {
1156 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1157 { .div = 0 },
1158};
1159
1160static const struct clksel_rate emu_src_mpu_rates[] = {
1161 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1162 { .div = 0 },
1163};
1164
1165static const struct clksel emu_src_clksel[] = {
1166 { .parent = &sys_ck, .rates = emu_src_sys_rates },
1167 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1168 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
1169 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
1170 { .parent = NULL },
1171};
1172
1173static const struct clk_ops emu_src_ck_ops = {
1174 .init = &omap2_init_clk_clkdm,
1175 .recalc_rate = &omap2_clksel_recalc,
1176 .get_parent = &omap2_clksel_find_parent_index,
1177 .set_parent = &omap2_clksel_set_parent,
Jon Huntercfef4b22012-12-28 02:10:13 -07001178 .enable = &omap2_clkops_enable_clkdm,
1179 .disable = &omap2_clkops_disable_clkdm,
Rajendra Nayak99e79382012-11-02 05:02:58 -06001180};
1181
1182static struct clk emu_src_ck;
1183
1184static struct clk_hw_omap emu_src_ck_hw = {
1185 .hw = {
1186 .clk = &emu_src_ck,
1187 },
1188 .clksel = emu_src_clksel,
1189 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1190 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
1191 .clkdm_name = "emu_clkdm",
1192};
1193
1194DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
1195
1196DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
1197 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1198 OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
1199 CLK_DIVIDER_ONE_BASED, NULL);
1200
1201static struct clk fac_ick;
1202
1203static struct clk_hw_omap fac_ick_hw = {
1204 .hw = {
1205 .clk = &fac_ick,
1206 },
1207 .ops = &clkhwops_iclk_wait,
1208 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1209 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1210 .clkdm_name = "core_l4_clkdm",
1211};
1212
1213DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
1214
1215static struct clk fshostusb_fck;
1216
1217static const char *fshostusb_fck_parent_names[] = {
1218 "core_48m_fck",
1219};
1220
1221static struct clk_hw_omap fshostusb_fck_hw = {
1222 .hw = {
1223 .clk = &fshostusb_fck,
1224 },
1225 .ops = &clkhwops_wait,
1226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1227 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1228 .clkdm_name = "core_l4_clkdm",
1229};
1230
1231DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
1232
1233static struct clk gfx_l3_ck;
1234
1235static struct clk_hw_omap gfx_l3_ck_hw = {
1236 .hw = {
1237 .clk = &gfx_l3_ck,
1238 },
1239 .ops = &clkhwops_wait,
1240 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1241 .enable_bit = OMAP_EN_GFX_SHIFT,
1242 .clkdm_name = "gfx_3430es1_clkdm",
1243};
1244
1245DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
1246
1247DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
1248 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1249 OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
1250 CLK_DIVIDER_ONE_BASED, NULL);
1251
1252static struct clk gfx_cg1_ck;
1253
1254static const char *gfx_cg1_ck_parent_names[] = {
1255 "gfx_l3_fck",
1256};
1257
1258static struct clk_hw_omap gfx_cg1_ck_hw = {
1259 .hw = {
1260 .clk = &gfx_cg1_ck,
1261 },
1262 .ops = &clkhwops_wait,
1263 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1264 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1265 .clkdm_name = "gfx_3430es1_clkdm",
1266};
1267
1268DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1269
1270static struct clk gfx_cg2_ck;
1271
1272static struct clk_hw_omap gfx_cg2_ck_hw = {
1273 .hw = {
1274 .clk = &gfx_cg2_ck,
1275 },
1276 .ops = &clkhwops_wait,
1277 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1278 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1279 .clkdm_name = "gfx_3430es1_clkdm",
1280};
1281
1282DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1283
1284static struct clk gfx_l3_ick;
1285
1286static const char *gfx_l3_ick_parent_names[] = {
1287 "gfx_l3_ck",
1288};
1289
1290DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
1291DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
1292
1293static struct clk wkup_32k_fck;
1294
1295static const char *wkup_32k_fck_parent_names[] = {
1296 "omap_32k_fck",
1297};
1298
1299DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
1300DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
1301
1302static struct clk gpio1_dbck;
1303
1304static const char *gpio1_dbck_parent_names[] = {
1305 "wkup_32k_fck",
1306};
1307
1308static struct clk_hw_omap gpio1_dbck_hw = {
1309 .hw = {
1310 .clk = &gpio1_dbck,
1311 },
1312 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1313 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1314 .clkdm_name = "wkup_clkdm",
1315};
1316
1317DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1318
1319static struct clk wkup_l4_ick;
1320
1321DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1322DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
1323
1324static struct clk gpio1_ick;
1325
1326static const char *gpio1_ick_parent_names[] = {
1327 "wkup_l4_ick",
1328};
1329
1330static struct clk_hw_omap gpio1_ick_hw = {
1331 .hw = {
1332 .clk = &gpio1_ick,
1333 },
1334 .ops = &clkhwops_iclk_wait,
1335 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1336 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1337 .clkdm_name = "wkup_clkdm",
1338};
1339
1340DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1341
1342static struct clk per_32k_alwon_fck;
1343
1344DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
1345DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
1346 core_l4_ick_ops);
1347
1348static struct clk gpio2_dbck;
1349
1350static const char *gpio2_dbck_parent_names[] = {
1351 "per_32k_alwon_fck",
1352};
1353
1354static struct clk_hw_omap gpio2_dbck_hw = {
1355 .hw = {
1356 .clk = &gpio2_dbck,
1357 },
1358 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1359 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1360 .clkdm_name = "per_clkdm",
1361};
1362
1363DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1364
1365static struct clk per_l4_ick;
1366
1367DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
1368DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
1369
1370static struct clk gpio2_ick;
1371
1372static const char *gpio2_ick_parent_names[] = {
1373 "per_l4_ick",
1374};
1375
1376static struct clk_hw_omap gpio2_ick_hw = {
1377 .hw = {
1378 .clk = &gpio2_ick,
1379 },
1380 .ops = &clkhwops_iclk_wait,
1381 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1382 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1383 .clkdm_name = "per_clkdm",
1384};
1385
1386DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1387
1388static struct clk gpio3_dbck;
1389
1390static struct clk_hw_omap gpio3_dbck_hw = {
1391 .hw = {
1392 .clk = &gpio3_dbck,
1393 },
1394 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1395 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1396 .clkdm_name = "per_clkdm",
1397};
1398
1399DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1400
1401static struct clk gpio3_ick;
1402
1403static struct clk_hw_omap gpio3_ick_hw = {
1404 .hw = {
1405 .clk = &gpio3_ick,
1406 },
1407 .ops = &clkhwops_iclk_wait,
1408 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1409 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1410 .clkdm_name = "per_clkdm",
1411};
1412
1413DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1414
1415static struct clk gpio4_dbck;
1416
1417static struct clk_hw_omap gpio4_dbck_hw = {
1418 .hw = {
1419 .clk = &gpio4_dbck,
1420 },
1421 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1422 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1423 .clkdm_name = "per_clkdm",
1424};
1425
1426DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1427
1428static struct clk gpio4_ick;
1429
1430static struct clk_hw_omap gpio4_ick_hw = {
1431 .hw = {
1432 .clk = &gpio4_ick,
1433 },
1434 .ops = &clkhwops_iclk_wait,
1435 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1436 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1437 .clkdm_name = "per_clkdm",
1438};
1439
1440DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1441
1442static struct clk gpio5_dbck;
1443
1444static struct clk_hw_omap gpio5_dbck_hw = {
1445 .hw = {
1446 .clk = &gpio5_dbck,
1447 },
1448 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1449 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1450 .clkdm_name = "per_clkdm",
1451};
1452
1453DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1454
1455static struct clk gpio5_ick;
1456
1457static struct clk_hw_omap gpio5_ick_hw = {
1458 .hw = {
1459 .clk = &gpio5_ick,
1460 },
1461 .ops = &clkhwops_iclk_wait,
1462 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1463 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1464 .clkdm_name = "per_clkdm",
1465};
1466
1467DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1468
1469static struct clk gpio6_dbck;
1470
1471static struct clk_hw_omap gpio6_dbck_hw = {
1472 .hw = {
1473 .clk = &gpio6_dbck,
1474 },
1475 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1476 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1477 .clkdm_name = "per_clkdm",
1478};
1479
1480DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1481
1482static struct clk gpio6_ick;
1483
1484static struct clk_hw_omap gpio6_ick_hw = {
1485 .hw = {
1486 .clk = &gpio6_ick,
1487 },
1488 .ops = &clkhwops_iclk_wait,
1489 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1490 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1491 .clkdm_name = "per_clkdm",
1492};
1493
1494DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1495
1496static struct clk gpmc_fck;
1497
1498static struct clk_hw_omap gpmc_fck_hw = {
1499 .hw = {
1500 .clk = &gpmc_fck,
1501 },
1502 .flags = ENABLE_ON_INIT,
1503 .clkdm_name = "core_l3_clkdm",
1504};
1505
1506DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
1507
1508static const struct clksel omap343x_gpt_clksel[] = {
1509 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1510 { .parent = &sys_ck, .rates = gpt_sys_rates },
1511 { .parent = NULL },
1512};
1513
1514static const char *gpt10_fck_parent_names[] = {
1515 "omap_32k_fck", "sys_ck",
1516};
1517
1518DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1519 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1520 OMAP3430_CLKSEL_GPT10_MASK,
1521 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1522 OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
1523 gpt10_fck_parent_names, clkout2_src_ck_ops);
1524
1525static struct clk gpt10_ick;
1526
1527static struct clk_hw_omap gpt10_ick_hw = {
1528 .hw = {
1529 .clk = &gpt10_ick,
1530 },
1531 .ops = &clkhwops_iclk_wait,
1532 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1533 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1534 .clkdm_name = "core_l4_clkdm",
1535};
1536
1537DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
1538
1539DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1540 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1541 OMAP3430_CLKSEL_GPT11_MASK,
1542 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1543 OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
1544 gpt10_fck_parent_names, clkout2_src_ck_ops);
1545
1546static struct clk gpt11_ick;
1547
1548static struct clk_hw_omap gpt11_ick_hw = {
1549 .hw = {
1550 .clk = &gpt11_ick,
1551 },
1552 .ops = &clkhwops_iclk_wait,
1553 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1554 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1555 .clkdm_name = "core_l4_clkdm",
1556};
1557
1558DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
1559
1560static struct clk gpt12_fck;
1561
1562static const char *gpt12_fck_parent_names[] = {
1563 "secure_32k_fck",
1564};
1565
1566DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
1567DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
1568
1569static struct clk gpt12_ick;
1570
1571static struct clk_hw_omap gpt12_ick_hw = {
1572 .hw = {
1573 .clk = &gpt12_ick,
1574 },
1575 .ops = &clkhwops_iclk_wait,
1576 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1577 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
1578 .clkdm_name = "wkup_clkdm",
1579};
1580
1581DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
1582
1583DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
1584 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1585 OMAP3430_CLKSEL_GPT1_MASK,
1586 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1587 OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
1588 gpt10_fck_parent_names, clkout2_src_ck_ops);
1589
1590static struct clk gpt1_ick;
1591
1592static struct clk_hw_omap gpt1_ick_hw = {
1593 .hw = {
1594 .clk = &gpt1_ick,
1595 },
1596 .ops = &clkhwops_iclk_wait,
1597 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1598 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
1599 .clkdm_name = "wkup_clkdm",
1600};
1601
1602DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1603
1604DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
1605 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1606 OMAP3430_CLKSEL_GPT2_MASK,
1607 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1608 OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
1609 gpt10_fck_parent_names, clkout2_src_ck_ops);
1610
1611static struct clk gpt2_ick;
1612
1613static struct clk_hw_omap gpt2_ick_hw = {
1614 .hw = {
1615 .clk = &gpt2_ick,
1616 },
1617 .ops = &clkhwops_iclk_wait,
1618 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1619 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
1620 .clkdm_name = "per_clkdm",
1621};
1622
1623DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1624
1625DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
1626 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1627 OMAP3430_CLKSEL_GPT3_MASK,
1628 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1629 OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
1630 gpt10_fck_parent_names, clkout2_src_ck_ops);
1631
1632static struct clk gpt3_ick;
1633
1634static struct clk_hw_omap gpt3_ick_hw = {
1635 .hw = {
1636 .clk = &gpt3_ick,
1637 },
1638 .ops = &clkhwops_iclk_wait,
1639 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1640 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
1641 .clkdm_name = "per_clkdm",
1642};
1643
1644DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1645
1646DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
1647 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1648 OMAP3430_CLKSEL_GPT4_MASK,
1649 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1650 OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
1651 gpt10_fck_parent_names, clkout2_src_ck_ops);
1652
1653static struct clk gpt4_ick;
1654
1655static struct clk_hw_omap gpt4_ick_hw = {
1656 .hw = {
1657 .clk = &gpt4_ick,
1658 },
1659 .ops = &clkhwops_iclk_wait,
1660 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1661 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
1662 .clkdm_name = "per_clkdm",
1663};
1664
1665DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1666
1667DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
1668 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1669 OMAP3430_CLKSEL_GPT5_MASK,
1670 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1671 OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
1672 gpt10_fck_parent_names, clkout2_src_ck_ops);
1673
1674static struct clk gpt5_ick;
1675
1676static struct clk_hw_omap gpt5_ick_hw = {
1677 .hw = {
1678 .clk = &gpt5_ick,
1679 },
1680 .ops = &clkhwops_iclk_wait,
1681 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1682 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
1683 .clkdm_name = "per_clkdm",
1684};
1685
1686DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1687
1688DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
1689 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1690 OMAP3430_CLKSEL_GPT6_MASK,
1691 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1692 OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
1693 gpt10_fck_parent_names, clkout2_src_ck_ops);
1694
1695static struct clk gpt6_ick;
1696
1697static struct clk_hw_omap gpt6_ick_hw = {
1698 .hw = {
1699 .clk = &gpt6_ick,
1700 },
1701 .ops = &clkhwops_iclk_wait,
1702 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1703 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
1704 .clkdm_name = "per_clkdm",
1705};
1706
1707DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1708
1709DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
1710 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1711 OMAP3430_CLKSEL_GPT7_MASK,
1712 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1713 OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
1714 gpt10_fck_parent_names, clkout2_src_ck_ops);
1715
1716static struct clk gpt7_ick;
1717
1718static struct clk_hw_omap gpt7_ick_hw = {
1719 .hw = {
1720 .clk = &gpt7_ick,
1721 },
1722 .ops = &clkhwops_iclk_wait,
1723 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1724 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
1725 .clkdm_name = "per_clkdm",
1726};
1727
1728DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
1729
1730DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
1731 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1732 OMAP3430_CLKSEL_GPT8_MASK,
1733 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1734 OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
1735 gpt10_fck_parent_names, clkout2_src_ck_ops);
1736
1737static struct clk gpt8_ick;
1738
1739static struct clk_hw_omap gpt8_ick_hw = {
1740 .hw = {
1741 .clk = &gpt8_ick,
1742 },
1743 .ops = &clkhwops_iclk_wait,
1744 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1745 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
1746 .clkdm_name = "per_clkdm",
1747};
1748
1749DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
1750
1751DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
1752 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1753 OMAP3430_CLKSEL_GPT9_MASK,
1754 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1755 OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
1756 gpt10_fck_parent_names, clkout2_src_ck_ops);
1757
1758static struct clk gpt9_ick;
1759
1760static struct clk_hw_omap gpt9_ick_hw = {
1761 .hw = {
1762 .clk = &gpt9_ick,
1763 },
1764 .ops = &clkhwops_iclk_wait,
1765 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1766 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
1767 .clkdm_name = "per_clkdm",
1768};
1769
1770DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
1771
1772static struct clk hdq_fck;
1773
1774static const char *hdq_fck_parent_names[] = {
1775 "core_12m_fck",
1776};
1777
1778static struct clk_hw_omap hdq_fck_hw = {
1779 .hw = {
1780 .clk = &hdq_fck,
1781 },
1782 .ops = &clkhwops_wait,
1783 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1784 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1785 .clkdm_name = "core_l4_clkdm",
1786};
1787
1788DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
1789
1790static struct clk hdq_ick;
1791
1792static struct clk_hw_omap hdq_ick_hw = {
1793 .hw = {
1794 .clk = &hdq_ick,
1795 },
1796 .ops = &clkhwops_iclk_wait,
1797 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1798 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1799 .clkdm_name = "core_l4_clkdm",
1800};
1801
1802DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
1803
1804static struct clk hecc_ck;
1805
1806static struct clk_hw_omap hecc_ck_hw = {
1807 .hw = {
1808 .clk = &hecc_ck,
1809 },
1810 .ops = &clkhwops_am35xx_ipss_module_wait,
1811 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1812 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
1813 .clkdm_name = "core_l3_clkdm",
1814};
1815
1816DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
1817
1818static struct clk hsotgusb_fck_am35xx;
1819
1820static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1821 .hw = {
1822 .clk = &hsotgusb_fck_am35xx,
1823 },
1824 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1825 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
1826 .clkdm_name = "core_l3_clkdm",
1827};
1828
1829DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
1830
1831static struct clk hsotgusb_ick_3430es1;
1832
1833static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
1834 .hw = {
1835 .clk = &hsotgusb_ick_3430es1,
1836 },
1837 .ops = &clkhwops_iclk,
1838 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1839 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1840 .clkdm_name = "core_l3_clkdm",
1841};
1842
1843DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
1844
1845static struct clk hsotgusb_ick_3430es2;
1846
1847static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
1848 .hw = {
1849 .clk = &hsotgusb_ick_3430es2,
1850 },
1851 .ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
1852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1854 .clkdm_name = "core_l3_clkdm",
1855};
1856
1857DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
1858
1859static struct clk hsotgusb_ick_am35xx;
1860
1861static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
1862 .hw = {
1863 .clk = &hsotgusb_ick_am35xx,
1864 },
1865 .ops = &clkhwops_am35xx_ipss_module_wait,
1866 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1867 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
1868 .clkdm_name = "core_l3_clkdm",
1869};
1870
1871DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
1872
1873static struct clk i2c1_fck;
1874
1875static struct clk_hw_omap i2c1_fck_hw = {
1876 .hw = {
1877 .clk = &i2c1_fck,
1878 },
1879 .ops = &clkhwops_wait,
1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1881 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1882 .clkdm_name = "core_l4_clkdm",
1883};
1884
1885DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1886
1887static struct clk i2c1_ick;
1888
1889static struct clk_hw_omap i2c1_ick_hw = {
1890 .hw = {
1891 .clk = &i2c1_ick,
1892 },
1893 .ops = &clkhwops_iclk_wait,
1894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1895 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1896 .clkdm_name = "core_l4_clkdm",
1897};
1898
1899DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
1900
1901static struct clk i2c2_fck;
1902
1903static struct clk_hw_omap i2c2_fck_hw = {
1904 .hw = {
1905 .clk = &i2c2_fck,
1906 },
1907 .ops = &clkhwops_wait,
1908 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1909 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1910 .clkdm_name = "core_l4_clkdm",
1911};
1912
1913DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1914
1915static struct clk i2c2_ick;
1916
1917static struct clk_hw_omap i2c2_ick_hw = {
1918 .hw = {
1919 .clk = &i2c2_ick,
1920 },
1921 .ops = &clkhwops_iclk_wait,
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1924 .clkdm_name = "core_l4_clkdm",
1925};
1926
1927DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
1928
1929static struct clk i2c3_fck;
1930
1931static struct clk_hw_omap i2c3_fck_hw = {
1932 .hw = {
1933 .clk = &i2c3_fck,
1934 },
1935 .ops = &clkhwops_wait,
1936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1937 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1938 .clkdm_name = "core_l4_clkdm",
1939};
1940
1941DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1942
1943static struct clk i2c3_ick;
1944
1945static struct clk_hw_omap i2c3_ick_hw = {
1946 .hw = {
1947 .clk = &i2c3_ick,
1948 },
1949 .ops = &clkhwops_iclk_wait,
1950 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1951 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1952 .clkdm_name = "core_l4_clkdm",
1953};
1954
1955DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
1956
1957static struct clk icr_ick;
1958
1959static struct clk_hw_omap icr_ick_hw = {
1960 .hw = {
1961 .clk = &icr_ick,
1962 },
1963 .ops = &clkhwops_iclk_wait,
1964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1965 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1966 .clkdm_name = "core_l4_clkdm",
1967};
1968
1969DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
1970
1971static struct clk iva2_ck;
1972
1973static const char *iva2_ck_parent_names[] = {
1974 "dpll2_m2_ck",
1975};
1976
1977static struct clk_hw_omap iva2_ck_hw = {
1978 .hw = {
1979 .clk = &iva2_ck,
1980 },
1981 .ops = &clkhwops_wait,
1982 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1983 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1984 .clkdm_name = "iva2_clkdm",
1985};
1986
1987DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
1988
1989static struct clk mad2d_ick;
1990
1991static struct clk_hw_omap mad2d_ick_hw = {
1992 .hw = {
1993 .clk = &mad2d_ick,
1994 },
1995 .ops = &clkhwops_iclk_wait,
1996 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1997 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1998 .clkdm_name = "d2d_clkdm",
1999};
2000
2001DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2002
2003static struct clk mailboxes_ick;
2004
2005static struct clk_hw_omap mailboxes_ick_hw = {
2006 .hw = {
2007 .clk = &mailboxes_ick,
2008 },
2009 .ops = &clkhwops_iclk_wait,
2010 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2011 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2012 .clkdm_name = "core_l4_clkdm",
2013};
2014
2015DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
2016
2017static const struct clksel_rate common_mcbsp_96m_rates[] = {
2018 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2019 { .div = 0 }
2020};
2021
2022static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
2023 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2024 { .div = 0 }
2025};
2026
2027static const struct clksel mcbsp_15_clksel[] = {
2028 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2029 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2030 { .parent = NULL },
2031};
2032
2033static const char *mcbsp1_fck_parent_names[] = {
2034 "core_96m_fck", "mcbsp_clks",
2035};
2036
2037DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
2038 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2039 OMAP2_MCBSP1_CLKS_MASK,
2040 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2041 OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
2042 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2043
2044static struct clk mcbsp1_ick;
2045
2046static struct clk_hw_omap mcbsp1_ick_hw = {
2047 .hw = {
2048 .clk = &mcbsp1_ick,
2049 },
2050 .ops = &clkhwops_iclk_wait,
2051 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2052 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2053 .clkdm_name = "core_l4_clkdm",
2054};
2055
2056DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
2057
2058static struct clk per_96m_fck;
2059
2060DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
2061DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
2062
2063static const struct clksel mcbsp_234_clksel[] = {
2064 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2065 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2066 { .parent = NULL },
2067};
2068
2069static const char *mcbsp2_fck_parent_names[] = {
2070 "per_96m_fck", "mcbsp_clks",
2071};
2072
2073DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
2074 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2075 OMAP2_MCBSP2_CLKS_MASK,
2076 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2077 OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
2078 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2079
2080static struct clk mcbsp2_ick;
2081
2082static struct clk_hw_omap mcbsp2_ick_hw = {
2083 .hw = {
2084 .clk = &mcbsp2_ick,
2085 },
2086 .ops = &clkhwops_iclk_wait,
2087 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2088 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2089 .clkdm_name = "per_clkdm",
2090};
2091
2092DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
2093
2094DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
2095 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2096 OMAP2_MCBSP3_CLKS_MASK,
2097 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2098 OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
2099 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2100
2101static struct clk mcbsp3_ick;
2102
2103static struct clk_hw_omap mcbsp3_ick_hw = {
2104 .hw = {
2105 .clk = &mcbsp3_ick,
2106 },
2107 .ops = &clkhwops_iclk_wait,
2108 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2109 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2110 .clkdm_name = "per_clkdm",
2111};
2112
2113DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2114
2115DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
2116 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2117 OMAP2_MCBSP4_CLKS_MASK,
2118 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2119 OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
2120 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2121
2122static struct clk mcbsp4_ick;
2123
2124static struct clk_hw_omap mcbsp4_ick_hw = {
2125 .hw = {
2126 .clk = &mcbsp4_ick,
2127 },
2128 .ops = &clkhwops_iclk_wait,
2129 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2130 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2131 .clkdm_name = "per_clkdm",
2132};
2133
2134DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2135
2136DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
2137 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2138 OMAP2_MCBSP5_CLKS_MASK,
2139 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2140 OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
2141 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2142
2143static struct clk mcbsp5_ick;
2144
2145static struct clk_hw_omap mcbsp5_ick_hw = {
2146 .hw = {
2147 .clk = &mcbsp5_ick,
2148 },
2149 .ops = &clkhwops_iclk_wait,
2150 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2151 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2152 .clkdm_name = "core_l4_clkdm",
2153};
2154
2155DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
2156
2157static struct clk mcspi1_fck;
2158
2159static struct clk_hw_omap mcspi1_fck_hw = {
2160 .hw = {
2161 .clk = &mcspi1_fck,
2162 },
2163 .ops = &clkhwops_wait,
2164 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2165 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2166 .clkdm_name = "core_l4_clkdm",
2167};
2168
2169DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2170
2171static struct clk mcspi1_ick;
2172
2173static struct clk_hw_omap mcspi1_ick_hw = {
2174 .hw = {
2175 .clk = &mcspi1_ick,
2176 },
2177 .ops = &clkhwops_iclk_wait,
2178 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2179 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2180 .clkdm_name = "core_l4_clkdm",
2181};
2182
2183DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
2184
2185static struct clk mcspi2_fck;
2186
2187static struct clk_hw_omap mcspi2_fck_hw = {
2188 .hw = {
2189 .clk = &mcspi2_fck,
2190 },
2191 .ops = &clkhwops_wait,
2192 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2193 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2194 .clkdm_name = "core_l4_clkdm",
2195};
2196
2197DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2198
2199static struct clk mcspi2_ick;
2200
2201static struct clk_hw_omap mcspi2_ick_hw = {
2202 .hw = {
2203 .clk = &mcspi2_ick,
2204 },
2205 .ops = &clkhwops_iclk_wait,
2206 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2207 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2208 .clkdm_name = "core_l4_clkdm",
2209};
2210
2211DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
2212
2213static struct clk mcspi3_fck;
2214
2215static struct clk_hw_omap mcspi3_fck_hw = {
2216 .hw = {
2217 .clk = &mcspi3_fck,
2218 },
2219 .ops = &clkhwops_wait,
2220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2221 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2222 .clkdm_name = "core_l4_clkdm",
2223};
2224
2225DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2226
2227static struct clk mcspi3_ick;
2228
2229static struct clk_hw_omap mcspi3_ick_hw = {
2230 .hw = {
2231 .clk = &mcspi3_ick,
2232 },
2233 .ops = &clkhwops_iclk_wait,
2234 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2235 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2236 .clkdm_name = "core_l4_clkdm",
2237};
2238
2239DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
2240
2241static struct clk mcspi4_fck;
2242
2243static struct clk_hw_omap mcspi4_fck_hw = {
2244 .hw = {
2245 .clk = &mcspi4_fck,
2246 },
2247 .ops = &clkhwops_wait,
2248 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2249 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2250 .clkdm_name = "core_l4_clkdm",
2251};
2252
2253DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2254
2255static struct clk mcspi4_ick;
2256
2257static struct clk_hw_omap mcspi4_ick_hw = {
2258 .hw = {
2259 .clk = &mcspi4_ick,
2260 },
2261 .ops = &clkhwops_iclk_wait,
2262 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2263 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2264 .clkdm_name = "core_l4_clkdm",
2265};
2266
2267DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
2268
2269static struct clk mmchs1_fck;
2270
2271static struct clk_hw_omap mmchs1_fck_hw = {
2272 .hw = {
2273 .clk = &mmchs1_fck,
2274 },
2275 .ops = &clkhwops_wait,
2276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2277 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2278 .clkdm_name = "core_l4_clkdm",
2279};
2280
2281DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2282
2283static struct clk mmchs1_ick;
2284
2285static struct clk_hw_omap mmchs1_ick_hw = {
2286 .hw = {
2287 .clk = &mmchs1_ick,
2288 },
2289 .ops = &clkhwops_iclk_wait,
2290 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2291 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2292 .clkdm_name = "core_l4_clkdm",
2293};
2294
2295DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
2296
2297static struct clk mmchs2_fck;
2298
2299static struct clk_hw_omap mmchs2_fck_hw = {
2300 .hw = {
2301 .clk = &mmchs2_fck,
2302 },
2303 .ops = &clkhwops_wait,
2304 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2305 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2306 .clkdm_name = "core_l4_clkdm",
2307};
2308
2309DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2310
2311static struct clk mmchs2_ick;
2312
2313static struct clk_hw_omap mmchs2_ick_hw = {
2314 .hw = {
2315 .clk = &mmchs2_ick,
2316 },
2317 .ops = &clkhwops_iclk_wait,
2318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2319 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2320 .clkdm_name = "core_l4_clkdm",
2321};
2322
2323DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
2324
2325static struct clk mmchs3_fck;
2326
2327static struct clk_hw_omap mmchs3_fck_hw = {
2328 .hw = {
2329 .clk = &mmchs3_fck,
2330 },
2331 .ops = &clkhwops_wait,
2332 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2333 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2334 .clkdm_name = "core_l4_clkdm",
2335};
2336
2337DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2338
2339static struct clk mmchs3_ick;
2340
2341static struct clk_hw_omap mmchs3_ick_hw = {
2342 .hw = {
2343 .clk = &mmchs3_ick,
2344 },
2345 .ops = &clkhwops_iclk_wait,
2346 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2347 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2348 .clkdm_name = "core_l4_clkdm",
2349};
2350
2351DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
2352
2353static struct clk modem_fck;
2354
2355static struct clk_hw_omap modem_fck_hw = {
2356 .hw = {
2357 .clk = &modem_fck,
2358 },
2359 .ops = &clkhwops_iclk_wait,
2360 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2361 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
2362 .clkdm_name = "d2d_clkdm",
2363};
2364
2365DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
2366
2367static struct clk mspro_fck;
2368
2369static struct clk_hw_omap mspro_fck_hw = {
2370 .hw = {
2371 .clk = &mspro_fck,
2372 },
2373 .ops = &clkhwops_wait,
2374 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2375 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2376 .clkdm_name = "core_l4_clkdm",
2377};
2378
2379DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2380
2381static struct clk mspro_ick;
2382
2383static struct clk_hw_omap mspro_ick_hw = {
2384 .hw = {
2385 .clk = &mspro_ick,
2386 },
2387 .ops = &clkhwops_iclk_wait,
2388 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2389 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2390 .clkdm_name = "core_l4_clkdm",
2391};
2392
2393DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
2394
2395static struct clk omap_192m_alwon_fck;
2396
2397DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
2398DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
2399 core_ck_ops);
2400
2401static struct clk omap_32ksync_ick;
2402
2403static struct clk_hw_omap omap_32ksync_ick_hw = {
2404 .hw = {
2405 .clk = &omap_32ksync_ick,
2406 },
2407 .ops = &clkhwops_iclk_wait,
2408 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2409 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2410 .clkdm_name = "wkup_clkdm",
2411};
2412
2413DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
2414
2415static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
2416 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
2417 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
2418 { .div = 0 }
2419};
2420
2421static const struct clksel omap_96m_alwon_fck_clksel[] = {
2422 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
2423 { .parent = NULL }
2424};
2425
2426static struct clk omap_96m_alwon_fck_3630;
2427
2428static const char *omap_96m_alwon_fck_3630_parent_names[] = {
2429 "omap_192m_alwon_fck",
2430};
2431
2432static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
2433 .set_rate = &omap2_clksel_set_rate,
2434 .recalc_rate = &omap2_clksel_recalc,
2435 .round_rate = &omap2_clksel_round_rate,
2436};
2437
2438static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
2439 .hw = {
2440 .clk = &omap_96m_alwon_fck_3630,
2441 },
2442 .clksel = omap_96m_alwon_fck_clksel,
2443 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2444 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
2445};
2446
2447static struct clk omap_96m_alwon_fck_3630 = {
2448 .name = "omap_96m_alwon_fck",
2449 .hw = &omap_96m_alwon_fck_3630_hw.hw,
2450 .parent_names = omap_96m_alwon_fck_3630_parent_names,
2451 .num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
2452 .ops = &omap_96m_alwon_fck_3630_ops,
2453};
2454
2455static struct clk omapctrl_ick;
2456
2457static struct clk_hw_omap omapctrl_ick_hw = {
2458 .hw = {
2459 .clk = &omapctrl_ick,
2460 },
2461 .ops = &clkhwops_iclk_wait,
2462 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2463 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2464 .flags = ENABLE_ON_INIT,
2465 .clkdm_name = "core_l4_clkdm",
2466};
2467
2468DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
2469
2470DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
2471 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2472 OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
2473 CLK_DIVIDER_ONE_BASED, NULL);
2474
2475DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
2476 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2477 OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
2478 CLK_DIVIDER_ONE_BASED, NULL);
2479
2480static struct clk per_48m_fck;
2481
2482DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
2483DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
2484
2485static struct clk security_l3_ick;
2486
2487DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
2488DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
2489
2490static struct clk pka_ick;
2491
2492static const char *pka_ick_parent_names[] = {
2493 "security_l3_ick",
2494};
2495
2496static struct clk_hw_omap pka_ick_hw = {
2497 .hw = {
2498 .clk = &pka_ick,
2499 },
2500 .ops = &clkhwops_iclk_wait,
2501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2502 .enable_bit = OMAP3430_EN_PKA_SHIFT,
2503};
2504
2505DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
2506
2507DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
2508 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2509 OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
2510 CLK_DIVIDER_ONE_BASED, NULL);
2511
2512static struct clk rng_ick;
2513
2514static struct clk_hw_omap rng_ick_hw = {
2515 .hw = {
2516 .clk = &rng_ick,
2517 },
2518 .ops = &clkhwops_iclk_wait,
2519 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2520 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2521};
2522
2523DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
2524
2525static struct clk sad2d_ick;
2526
2527static struct clk_hw_omap sad2d_ick_hw = {
2528 .hw = {
2529 .clk = &sad2d_ick,
2530 },
2531 .ops = &clkhwops_iclk_wait,
2532 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2533 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
2534 .clkdm_name = "d2d_clkdm",
2535};
2536
2537DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2538
2539static struct clk sdrc_ick;
2540
2541static struct clk_hw_omap sdrc_ick_hw = {
2542 .hw = {
2543 .clk = &sdrc_ick,
2544 },
2545 .ops = &clkhwops_wait,
2546 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2547 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
2548 .flags = ENABLE_ON_INIT,
2549 .clkdm_name = "core_l3_clkdm",
2550};
2551
2552DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
2553
2554static const struct clksel_rate sgx_core_rates[] = {
2555 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
2556 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
2557 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
2558 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
2559 { .div = 0 }
2560};
2561
2562static const struct clksel_rate sgx_96m_rates[] = {
2563 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2564 { .div = 0 }
2565};
2566
2567static const struct clksel_rate sgx_192m_rates[] = {
2568 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
2569 { .div = 0 }
2570};
2571
2572static const struct clksel_rate sgx_corex2_rates[] = {
2573 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
2574 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
2575 { .div = 0 }
2576};
2577
2578static const struct clksel sgx_clksel[] = {
2579 { .parent = &core_ck, .rates = sgx_core_rates },
2580 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
2581 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
2582 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
2583 { .parent = NULL },
2584};
2585
2586static const char *sgx_fck_parent_names[] = {
2587 "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2588};
2589
2590static struct clk sgx_fck;
2591
2592static const struct clk_ops sgx_fck_ops = {
2593 .init = &omap2_init_clk_clkdm,
2594 .enable = &omap2_dflt_clk_enable,
2595 .disable = &omap2_dflt_clk_disable,
2596 .is_enabled = &omap2_dflt_clk_is_enabled,
2597 .recalc_rate = &omap2_clksel_recalc,
2598 .set_rate = &omap2_clksel_set_rate,
2599 .round_rate = &omap2_clksel_round_rate,
2600 .get_parent = &omap2_clksel_find_parent_index,
2601 .set_parent = &omap2_clksel_set_parent,
2602};
2603
2604DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
2605 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
2606 OMAP3430ES2_CLKSEL_SGX_MASK,
2607 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
2608 OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
2609 &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
2610
2611static struct clk sgx_ick;
2612
2613static struct clk_hw_omap sgx_ick_hw = {
2614 .hw = {
2615 .clk = &sgx_ick,
2616 },
2617 .ops = &clkhwops_wait,
2618 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
2619 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
2620 .clkdm_name = "sgx_clkdm",
2621};
2622
2623DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
2624
2625static struct clk sha11_ick;
2626
2627static struct clk_hw_omap sha11_ick_hw = {
2628 .hw = {
2629 .clk = &sha11_ick,
2630 },
2631 .ops = &clkhwops_iclk_wait,
2632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2633 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2634};
2635
2636DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
2637
2638static struct clk sha12_ick;
2639
2640static struct clk_hw_omap sha12_ick_hw = {
2641 .hw = {
2642 .clk = &sha12_ick,
2643 },
2644 .ops = &clkhwops_iclk_wait,
2645 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2646 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
2647 .clkdm_name = "core_l4_clkdm",
2648};
2649
2650DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
2651
2652static struct clk sr1_fck;
2653
2654static struct clk_hw_omap sr1_fck_hw = {
2655 .hw = {
2656 .clk = &sr1_fck,
2657 },
2658 .ops = &clkhwops_wait,
2659 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2660 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2661 .clkdm_name = "wkup_clkdm",
2662};
2663
2664DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
2665
2666static struct clk sr2_fck;
2667
2668static struct clk_hw_omap sr2_fck_hw = {
2669 .hw = {
2670 .clk = &sr2_fck,
2671 },
2672 .ops = &clkhwops_wait,
2673 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2674 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2675 .clkdm_name = "wkup_clkdm",
2676};
2677
2678DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
2679
2680static struct clk sr_l4_ick;
2681
2682DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
2683DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2684
2685static struct clk ssi_l4_ick;
2686
2687DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
2688DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2689
2690static struct clk ssi_ick_3430es1;
2691
2692static const char *ssi_ick_3430es1_parent_names[] = {
2693 "ssi_l4_ick",
2694};
2695
2696static struct clk_hw_omap ssi_ick_3430es1_hw = {
2697 .hw = {
2698 .clk = &ssi_ick_3430es1,
2699 },
2700 .ops = &clkhwops_iclk,
2701 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2702 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2703 .clkdm_name = "core_l4_clkdm",
2704};
2705
2706DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2707
2708static struct clk ssi_ick_3430es2;
2709
2710static struct clk_hw_omap ssi_ick_3430es2_hw = {
2711 .hw = {
2712 .clk = &ssi_ick_3430es2,
2713 },
2714 .ops = &clkhwops_omap3430es2_iclk_ssi_wait,
2715 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2716 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2717 .clkdm_name = "core_l4_clkdm",
2718};
2719
2720DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2721
2722static const struct clksel_rate ssi_ssr_corex2_rates[] = {
2723 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2724 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2725 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2726 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2727 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2728 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2729 { .div = 0 }
2730};
2731
2732static const struct clksel ssi_ssr_clksel[] = {
2733 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
2734 { .parent = NULL },
2735};
2736
2737static const char *ssi_ssr_fck_3430es1_parent_names[] = {
2738 "corex2_fck",
2739};
2740
2741static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
2742 .init = &omap2_init_clk_clkdm,
2743 .enable = &omap2_dflt_clk_enable,
2744 .disable = &omap2_dflt_clk_disable,
2745 .is_enabled = &omap2_dflt_clk_is_enabled,
2746 .recalc_rate = &omap2_clksel_recalc,
2747 .set_rate = &omap2_clksel_set_rate,
2748 .round_rate = &omap2_clksel_round_rate,
2749};
2750
2751DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
2752 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2753 OMAP3430_CLKSEL_SSI_MASK,
2754 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2755 OMAP3430_EN_SSI_SHIFT,
2756 NULL, ssi_ssr_fck_3430es1_parent_names,
2757 ssi_ssr_fck_3430es1_ops);
2758
2759DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
2760 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2761 OMAP3430_CLKSEL_SSI_MASK,
2762 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2763 OMAP3430_EN_SSI_SHIFT,
2764 NULL, ssi_ssr_fck_3430es1_parent_names,
2765 ssi_ssr_fck_3430es1_ops);
2766
2767DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2768 &ssi_ssr_fck_3430es1, 0x0, 1, 2);
2769
2770DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2771 &ssi_ssr_fck_3430es2, 0x0, 1, 2);
2772
2773static struct clk sys_clkout1;
2774
2775static const char *sys_clkout1_parent_names[] = {
2776 "osc_sys_ck",
2777};
2778
2779static struct clk_hw_omap sys_clkout1_hw = {
2780 .hw = {
2781 .clk = &sys_clkout1,
2782 },
2783 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
2784 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
2785};
2786
2787DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
2788
2789DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
2790 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
2791 OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
2792
2793DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
2794 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2795 OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
2796 0x0, NULL);
2797
2798DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
2799 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2800 OMAP3430_CLKSEL_TRACECLK_SHIFT,
2801 OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
2802
2803static struct clk ts_fck;
2804
2805static struct clk_hw_omap ts_fck_hw = {
2806 .hw = {
2807 .clk = &ts_fck,
2808 },
2809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
2810 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
2811 .clkdm_name = "core_l4_clkdm",
2812};
2813
2814DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
2815
2816static struct clk uart1_fck;
2817
2818static struct clk_hw_omap uart1_fck_hw = {
2819 .hw = {
2820 .clk = &uart1_fck,
2821 },
2822 .ops = &clkhwops_wait,
2823 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2824 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2825 .clkdm_name = "core_l4_clkdm",
2826};
2827
2828DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2829
2830static struct clk uart1_ick;
2831
2832static struct clk_hw_omap uart1_ick_hw = {
2833 .hw = {
2834 .clk = &uart1_ick,
2835 },
2836 .ops = &clkhwops_iclk_wait,
2837 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2838 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2839 .clkdm_name = "core_l4_clkdm",
2840};
2841
2842DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
2843
2844static struct clk uart2_fck;
2845
2846static struct clk_hw_omap uart2_fck_hw = {
2847 .hw = {
2848 .clk = &uart2_fck,
2849 },
2850 .ops = &clkhwops_wait,
2851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2852 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2853 .clkdm_name = "core_l4_clkdm",
2854};
2855
2856DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2857
2858static struct clk uart2_ick;
2859
2860static struct clk_hw_omap uart2_ick_hw = {
2861 .hw = {
2862 .clk = &uart2_ick,
2863 },
2864 .ops = &clkhwops_iclk_wait,
2865 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2866 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2867 .clkdm_name = "core_l4_clkdm",
2868};
2869
2870DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
2871
2872static struct clk uart3_fck;
2873
2874static const char *uart3_fck_parent_names[] = {
2875 "per_48m_fck",
2876};
2877
2878static struct clk_hw_omap uart3_fck_hw = {
2879 .hw = {
2880 .clk = &uart3_fck,
2881 },
2882 .ops = &clkhwops_wait,
2883 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2884 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2885 .clkdm_name = "per_clkdm",
2886};
2887
2888DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
2889
2890static struct clk uart3_ick;
2891
2892static struct clk_hw_omap uart3_ick_hw = {
2893 .hw = {
2894 .clk = &uart3_ick,
2895 },
2896 .ops = &clkhwops_iclk_wait,
2897 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2898 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2899 .clkdm_name = "per_clkdm",
2900};
2901
2902DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2903
2904static struct clk uart4_fck;
2905
2906static struct clk_hw_omap uart4_fck_hw = {
2907 .hw = {
2908 .clk = &uart4_fck,
2909 },
2910 .ops = &clkhwops_wait,
2911 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2912 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2913 .clkdm_name = "per_clkdm",
2914};
2915
2916DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
2917
2918static struct clk uart4_fck_am35xx;
2919
2920static struct clk_hw_omap uart4_fck_am35xx_hw = {
2921 .hw = {
2922 .clk = &uart4_fck_am35xx,
2923 },
2924 .ops = &clkhwops_wait,
2925 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2926 .enable_bit = AM35XX_EN_UART4_SHIFT,
2927 .clkdm_name = "core_l4_clkdm",
2928};
2929
2930DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
2931
2932static struct clk uart4_ick;
2933
2934static struct clk_hw_omap uart4_ick_hw = {
2935 .hw = {
2936 .clk = &uart4_ick,
2937 },
2938 .ops = &clkhwops_iclk_wait,
2939 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2940 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2941 .clkdm_name = "per_clkdm",
2942};
2943
2944DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2945
2946static struct clk uart4_ick_am35xx;
2947
2948static struct clk_hw_omap uart4_ick_am35xx_hw = {
2949 .hw = {
2950 .clk = &uart4_ick_am35xx,
2951 },
2952 .ops = &clkhwops_iclk_wait,
2953 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2954 .enable_bit = AM35XX_EN_UART4_SHIFT,
2955 .clkdm_name = "core_l4_clkdm",
2956};
2957
2958DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
2959
2960static const struct clksel_rate div2_rates[] = {
2961 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2962 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2963 { .div = 0 }
2964};
2965
2966static const struct clksel usb_l4_clksel[] = {
2967 { .parent = &l4_ick, .rates = div2_rates },
2968 { .parent = NULL },
2969};
2970
2971static const char *usb_l4_ick_parent_names[] = {
2972 "l4_ick",
2973};
2974
2975DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
2976 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2977 OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2978 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2979 OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2980 &clkhwops_iclk_wait, usb_l4_ick_parent_names,
2981 ssi_ssr_fck_3430es1_ops);
2982
2983static struct clk usbhost_120m_fck;
2984
2985static const char *usbhost_120m_fck_parent_names[] = {
2986 "dpll5_m2_ck",
2987};
2988
2989static struct clk_hw_omap usbhost_120m_fck_hw = {
2990 .hw = {
2991 .clk = &usbhost_120m_fck,
2992 },
2993 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2994 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2995 .clkdm_name = "usbhost_clkdm",
2996};
2997
2998DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
2999 aes2_ick_ops);
3000
3001static struct clk usbhost_48m_fck;
3002
3003static struct clk_hw_omap usbhost_48m_fck_hw = {
3004 .hw = {
3005 .clk = &usbhost_48m_fck,
3006 },
3007 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
3008 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3009 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3010 .clkdm_name = "usbhost_clkdm",
3011};
3012
3013DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
3014
3015static struct clk usbhost_ick;
3016
3017static struct clk_hw_omap usbhost_ick_hw = {
3018 .hw = {
3019 .clk = &usbhost_ick,
3020 },
3021 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
3022 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
3023 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
3024 .clkdm_name = "usbhost_clkdm",
3025};
3026
3027DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
3028
3029static struct clk usbtll_fck;
3030
3031static struct clk_hw_omap usbtll_fck_hw = {
3032 .hw = {
3033 .clk = &usbtll_fck,
3034 },
3035 .ops = &clkhwops_wait,
3036 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
3037 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3038 .clkdm_name = "core_l4_clkdm",
3039};
3040
3041DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
3042
3043static struct clk usbtll_ick;
3044
3045static struct clk_hw_omap usbtll_ick_hw = {
3046 .hw = {
3047 .clk = &usbtll_ick,
3048 },
3049 .ops = &clkhwops_iclk_wait,
3050 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
3051 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3052 .clkdm_name = "core_l4_clkdm",
3053};
3054
3055DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
3056
3057static const struct clksel_rate usim_96m_rates[] = {
3058 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
3059 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3060 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
3061 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
3062 { .div = 0 }
3063};
3064
3065static const struct clksel_rate usim_120m_rates[] = {
3066 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
3067 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
3068 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
3069 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
3070 { .div = 0 }
3071};
3072
3073static const struct clksel usim_clksel[] = {
3074 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
3075 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
3076 { .parent = &sys_ck, .rates = div2_rates },
3077 { .parent = NULL },
3078};
3079
3080static const char *usim_fck_parent_names[] = {
3081 "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3082};
3083
3084static struct clk usim_fck;
3085
3086static const struct clk_ops usim_fck_ops = {
3087 .enable = &omap2_dflt_clk_enable,
3088 .disable = &omap2_dflt_clk_disable,
3089 .is_enabled = &omap2_dflt_clk_is_enabled,
3090 .recalc_rate = &omap2_clksel_recalc,
3091 .get_parent = &omap2_clksel_find_parent_index,
3092 .set_parent = &omap2_clksel_set_parent,
3093};
3094
3095DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
3096 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
3097 OMAP3430ES2_CLKSEL_USIMOCP_MASK,
3098 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3099 OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
3100 usim_fck_parent_names, usim_fck_ops);
3101
3102static struct clk usim_ick;
3103
3104static struct clk_hw_omap usim_ick_hw = {
3105 .hw = {
3106 .clk = &usim_ick,
3107 },
3108 .ops = &clkhwops_iclk_wait,
3109 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3110 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
3111 .clkdm_name = "wkup_clkdm",
3112};
3113
3114DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
3115
3116static struct clk vpfe_fck;
3117
3118static const char *vpfe_fck_parent_names[] = {
3119 "pclk_ck",
3120};
3121
3122static struct clk_hw_omap vpfe_fck_hw = {
3123 .hw = {
3124 .clk = &vpfe_fck,
3125 },
3126 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3127 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3128};
3129
3130DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
3131
3132static struct clk vpfe_ick;
3133
3134static struct clk_hw_omap vpfe_ick_hw = {
3135 .hw = {
3136 .clk = &vpfe_ick,
3137 },
3138 .ops = &clkhwops_am35xx_ipss_module_wait,
3139 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3140 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3141 .clkdm_name = "core_l3_clkdm",
3142};
3143
3144DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
3145
3146static struct clk wdt1_fck;
3147
3148DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
3149DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
3150
3151static struct clk wdt1_ick;
3152
3153static struct clk_hw_omap wdt1_ick_hw = {
3154 .hw = {
3155 .clk = &wdt1_ick,
3156 },
3157 .ops = &clkhwops_iclk_wait,
3158 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3159 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
3160 .clkdm_name = "wkup_clkdm",
3161};
3162
3163DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
3164
3165static struct clk wdt2_fck;
3166
3167static struct clk_hw_omap wdt2_fck_hw = {
3168 .hw = {
3169 .clk = &wdt2_fck,
3170 },
3171 .ops = &clkhwops_wait,
3172 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3173 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3174 .clkdm_name = "wkup_clkdm",
3175};
3176
3177DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
3178
3179static struct clk wdt2_ick;
3180
3181static struct clk_hw_omap wdt2_ick_hw = {
3182 .hw = {
3183 .clk = &wdt2_ick,
3184 },
3185 .ops = &clkhwops_iclk_wait,
3186 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3187 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3188 .clkdm_name = "wkup_clkdm",
3189};
3190
3191DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
3192
3193static struct clk wdt3_fck;
3194
3195static struct clk_hw_omap wdt3_fck_hw = {
3196 .hw = {
3197 .clk = &wdt3_fck,
3198 },
3199 .ops = &clkhwops_wait,
3200 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3201 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3202 .clkdm_name = "per_clkdm",
3203};
3204
3205DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
3206
3207static struct clk wdt3_ick;
3208
3209static struct clk_hw_omap wdt3_ick_hw = {
3210 .hw = {
3211 .clk = &wdt3_ick,
3212 },
3213 .ops = &clkhwops_iclk_wait,
3214 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3215 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3216 .clkdm_name = "per_clkdm",
3217};
3218
3219DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3220
3221/*
J Keerthy78e52e02013-03-18 09:57:39 -06003222 * clocks specific to omap3430es1
3223 */
3224static struct omap_clk omap3430es1_clks[] = {
3225 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
3226 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
3227 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
3228 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
3229 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
3230 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
3231 CLK(NULL, "fshostusb_fck", &fshostusb_fck),
3232 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
3233 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
3234 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
3235 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
3236 CLK(NULL, "fac_ick", &fac_ick),
3237 CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
3238 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
3239 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
3240 CLK("omapdss_dss", "ick", &dss_ick_3430es1),
3241 CLK(NULL, "dss_ick", &dss_ick_3430es1),
3242};
3243
3244/*
3245 * clocks specific to am35xx
3246 */
3247static struct omap_clk am35xx_clks[] = {
3248 CLK(NULL, "ipss_ick", &ipss_ick),
3249 CLK(NULL, "rmii_ck", &rmii_ck),
3250 CLK(NULL, "pclk_ck", &pclk_ck),
3251 CLK(NULL, "emac_ick", &emac_ick),
3252 CLK(NULL, "emac_fck", &emac_fck),
3253 CLK("davinci_emac.0", NULL, &emac_ick),
3254 CLK("davinci_mdio.0", NULL, &emac_fck),
3255 CLK("vpfe-capture", "master", &vpfe_ick),
3256 CLK("vpfe-capture", "slave", &vpfe_fck),
3257 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
3258 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
3259 CLK(NULL, "hecc_ck", &hecc_ck),
3260 CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
3261 CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
3262};
3263
3264/*
3265 * clocks specific to omap36xx
3266 */
3267static struct omap_clk omap36xx_clks[] = {
3268 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
3269 CLK(NULL, "uart4_fck", &uart4_fck),
3270};
3271
3272/*
3273 * clocks common to omap36xx omap34xx
3274 */
3275static struct omap_clk omap34xx_omap36xx_clks[] = {
3276 CLK(NULL, "aes1_ick", &aes1_ick),
3277 CLK("omap_rng", "ick", &rng_ick),
3278 CLK(NULL, "sha11_ick", &sha11_ick),
3279 CLK(NULL, "des1_ick", &des1_ick),
3280 CLK(NULL, "cam_mclk", &cam_mclk),
3281 CLK(NULL, "cam_ick", &cam_ick),
3282 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
3283 CLK(NULL, "security_l3_ick", &security_l3_ick),
3284 CLK(NULL, "pka_ick", &pka_ick),
3285 CLK(NULL, "icr_ick", &icr_ick),
3286 CLK("omap-aes", "ick", &aes2_ick),
3287 CLK("omap-sham", "ick", &sha12_ick),
3288 CLK(NULL, "des2_ick", &des2_ick),
3289 CLK(NULL, "mspro_ick", &mspro_ick),
3290 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
3291 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
3292 CLK(NULL, "sr1_fck", &sr1_fck),
3293 CLK(NULL, "sr2_fck", &sr2_fck),
3294 CLK(NULL, "sr_l4_ick", &sr_l4_ick),
3295 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
3296 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
3297 CLK(NULL, "dpll2_fck", &dpll2_fck),
3298 CLK(NULL, "iva2_ck", &iva2_ck),
3299 CLK(NULL, "modem_fck", &modem_fck),
3300 CLK(NULL, "sad2d_ick", &sad2d_ick),
3301 CLK(NULL, "mad2d_ick", &mad2d_ick),
3302 CLK(NULL, "mspro_fck", &mspro_fck),
3303 CLK(NULL, "dpll2_ck", &dpll2_ck),
3304 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
3305};
3306
3307/*
3308 * clocks common to omap36xx and omap3430es2plus
3309 */
3310static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
3311 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
3312 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
3313 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
3314 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
3315 CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
3316 CLK(NULL, "usim_fck", &usim_fck),
3317 CLK(NULL, "usim_ick", &usim_ick),
3318};
3319
3320/*
3321 * clocks common to am35xx omap36xx and omap3430es2plus
3322 */
3323static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3324 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
3325 CLK(NULL, "dpll5_ck", &dpll5_ck),
3326 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
3327 CLK(NULL, "sgx_fck", &sgx_fck),
3328 CLK(NULL, "sgx_ick", &sgx_ick),
3329 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
3330 CLK(NULL, "ts_fck", &ts_fck),
3331 CLK(NULL, "usbtll_fck", &usbtll_fck),
3332 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck),
3333 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck),
3334 CLK(NULL, "usbtll_ick", &usbtll_ick),
3335 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick),
3336 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick),
3337 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
3338 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
3339 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
3340 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
3341 CLK("omapdss_dss", "ick", &dss_ick_3430es2),
3342 CLK(NULL, "dss_ick", &dss_ick_3430es2),
3343 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
3344 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
3345 CLK(NULL, "usbhost_ick", &usbhost_ick),
3346 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick),
3347};
3348
3349/*
3350 * common clocks
Rajendra Nayak99e79382012-11-02 05:02:58 -06003351 */
3352static struct omap_clk omap3xxx_clks[] = {
J Keerthy78e52e02013-03-18 09:57:39 -06003353 CLK(NULL, "apb_pclk", &dummy_apb_pclk),
3354 CLK(NULL, "omap_32k_fck", &omap_32k_fck),
3355 CLK(NULL, "virt_12m_ck", &virt_12m_ck),
3356 CLK(NULL, "virt_13m_ck", &virt_13m_ck),
3357 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
3358 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
3359 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
3360 CLK(NULL, "osc_sys_ck", &osc_sys_ck),
3361 CLK("twl", "fck", &osc_sys_ck),
3362 CLK(NULL, "sys_ck", &sys_ck),
3363 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
3364 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
3365 CLK(NULL, "sys_altclk", &sys_altclk),
3366 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
3367 CLK(NULL, "sys_clkout1", &sys_clkout1),
3368 CLK(NULL, "dpll1_ck", &dpll1_ck),
3369 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
3370 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
3371 CLK(NULL, "dpll3_ck", &dpll3_ck),
3372 CLK(NULL, "core_ck", &core_ck),
3373 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
3374 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
3375 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
3376 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
3377 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
3378 CLK(NULL, "dpll4_ck", &dpll4_ck),
3379 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
3380 CLK(NULL, "omap_96m_fck", &omap_96m_fck),
3381 CLK(NULL, "cm_96m_fck", &cm_96m_fck),
3382 CLK(NULL, "omap_54m_fck", &omap_54m_fck),
3383 CLK(NULL, "omap_48m_fck", &omap_48m_fck),
3384 CLK(NULL, "omap_12m_fck", &omap_12m_fck),
3385 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
3386 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
3387 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
3388 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
3389 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
3390 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
3391 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
3392 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
3393 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
3394 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
3395 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
3396 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
3397 CLK(NULL, "sys_clkout2", &sys_clkout2),
3398 CLK(NULL, "corex2_fck", &corex2_fck),
3399 CLK(NULL, "dpll1_fck", &dpll1_fck),
3400 CLK(NULL, "mpu_ck", &mpu_ck),
3401 CLK(NULL, "arm_fck", &arm_fck),
3402 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
3403 CLK(NULL, "l3_ick", &l3_ick),
3404 CLK(NULL, "l4_ick", &l4_ick),
3405 CLK(NULL, "rm_ick", &rm_ick),
3406 CLK(NULL, "gpt10_fck", &gpt10_fck),
3407 CLK(NULL, "gpt11_fck", &gpt11_fck),
3408 CLK(NULL, "core_96m_fck", &core_96m_fck),
3409 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
3410 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
3411 CLK(NULL, "i2c3_fck", &i2c3_fck),
3412 CLK(NULL, "i2c2_fck", &i2c2_fck),
3413 CLK(NULL, "i2c1_fck", &i2c1_fck),
3414 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
3415 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
3416 CLK(NULL, "core_48m_fck", &core_48m_fck),
3417 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
3418 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
3419 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
3420 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
3421 CLK(NULL, "uart2_fck", &uart2_fck),
3422 CLK(NULL, "uart1_fck", &uart1_fck),
3423 CLK(NULL, "core_12m_fck", &core_12m_fck),
3424 CLK("omap_hdq.0", "fck", &hdq_fck),
3425 CLK(NULL, "hdq_fck", &hdq_fck),
3426 CLK(NULL, "core_l3_ick", &core_l3_ick),
3427 CLK(NULL, "sdrc_ick", &sdrc_ick),
3428 CLK(NULL, "gpmc_fck", &gpmc_fck),
3429 CLK(NULL, "core_l4_ick", &core_l4_ick),
3430 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
3431 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
3432 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
3433 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
3434 CLK("omap_hdq.0", "ick", &hdq_ick),
3435 CLK(NULL, "hdq_ick", &hdq_ick),
3436 CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
3437 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
3438 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
3439 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
3440 CLK(NULL, "mcspi4_ick", &mcspi4_ick),
3441 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
3442 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
3443 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
3444 CLK("omap_i2c.3", "ick", &i2c3_ick),
3445 CLK("omap_i2c.2", "ick", &i2c2_ick),
3446 CLK("omap_i2c.1", "ick", &i2c1_ick),
3447 CLK(NULL, "i2c3_ick", &i2c3_ick),
3448 CLK(NULL, "i2c2_ick", &i2c2_ick),
3449 CLK(NULL, "i2c1_ick", &i2c1_ick),
3450 CLK(NULL, "uart2_ick", &uart2_ick),
3451 CLK(NULL, "uart1_ick", &uart1_ick),
3452 CLK(NULL, "gpt11_ick", &gpt11_ick),
3453 CLK(NULL, "gpt10_ick", &gpt10_ick),
3454 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
3455 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
3456 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
3457 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
3458 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
3459 CLK(NULL, "dss_tv_fck", &dss_tv_fck),
3460 CLK(NULL, "dss_96m_fck", &dss_96m_fck),
3461 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
3462 CLK(NULL, "utmi_p1_gfclk", &dummy_ck),
3463 CLK(NULL, "utmi_p2_gfclk", &dummy_ck),
3464 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck),
3465 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck),
3466 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck),
3467 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck),
3468 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
3469 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
3470 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
3471 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
3472 CLK(NULL, "init_60m_fclk", &dummy_ck),
3473 CLK(NULL, "gpt1_fck", &gpt1_fck),
3474 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
3475 CLK(NULL, "gpio1_dbck", &gpio1_dbck),
Mark A. Greer26f88e62013-03-18 10:06:32 -06003476 CLK(NULL, "sha12_ick", &sha12_ick),
J Keerthy78e52e02013-03-18 09:57:39 -06003477 CLK(NULL, "wdt2_fck", &wdt2_fck),
3478 CLK("omap_wdt", "ick", &wdt2_ick),
3479 CLK(NULL, "wdt2_ick", &wdt2_ick),
3480 CLK(NULL, "wdt1_ick", &wdt1_ick),
3481 CLK(NULL, "gpio1_ick", &gpio1_ick),
3482 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
3483 CLK(NULL, "gpt12_ick", &gpt12_ick),
3484 CLK(NULL, "gpt1_ick", &gpt1_ick),
3485 CLK(NULL, "per_96m_fck", &per_96m_fck),
3486 CLK(NULL, "per_48m_fck", &per_48m_fck),
3487 CLK(NULL, "uart3_fck", &uart3_fck),
3488 CLK(NULL, "gpt2_fck", &gpt2_fck),
3489 CLK(NULL, "gpt3_fck", &gpt3_fck),
3490 CLK(NULL, "gpt4_fck", &gpt4_fck),
3491 CLK(NULL, "gpt5_fck", &gpt5_fck),
3492 CLK(NULL, "gpt6_fck", &gpt6_fck),
3493 CLK(NULL, "gpt7_fck", &gpt7_fck),
3494 CLK(NULL, "gpt8_fck", &gpt8_fck),
3495 CLK(NULL, "gpt9_fck", &gpt9_fck),
3496 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
3497 CLK(NULL, "gpio6_dbck", &gpio6_dbck),
3498 CLK(NULL, "gpio5_dbck", &gpio5_dbck),
3499 CLK(NULL, "gpio4_dbck", &gpio4_dbck),
3500 CLK(NULL, "gpio3_dbck", &gpio3_dbck),
3501 CLK(NULL, "gpio2_dbck", &gpio2_dbck),
3502 CLK(NULL, "wdt3_fck", &wdt3_fck),
3503 CLK(NULL, "per_l4_ick", &per_l4_ick),
3504 CLK(NULL, "gpio6_ick", &gpio6_ick),
3505 CLK(NULL, "gpio5_ick", &gpio5_ick),
3506 CLK(NULL, "gpio4_ick", &gpio4_ick),
3507 CLK(NULL, "gpio3_ick", &gpio3_ick),
3508 CLK(NULL, "gpio2_ick", &gpio2_ick),
3509 CLK(NULL, "wdt3_ick", &wdt3_ick),
3510 CLK(NULL, "uart3_ick", &uart3_ick),
3511 CLK(NULL, "uart4_ick", &uart4_ick),
3512 CLK(NULL, "gpt9_ick", &gpt9_ick),
3513 CLK(NULL, "gpt8_ick", &gpt8_ick),
3514 CLK(NULL, "gpt7_ick", &gpt7_ick),
3515 CLK(NULL, "gpt6_ick", &gpt6_ick),
3516 CLK(NULL, "gpt5_ick", &gpt5_ick),
3517 CLK(NULL, "gpt4_ick", &gpt4_ick),
3518 CLK(NULL, "gpt3_ick", &gpt3_ick),
3519 CLK(NULL, "gpt2_ick", &gpt2_ick),
3520 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
3521 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
3522 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
3523 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
3524 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
3525 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
3526 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
3527 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
3528 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
3529 CLK("etb", "emu_src_ck", &emu_src_ck),
3530 CLK(NULL, "emu_src_ck", &emu_src_ck),
3531 CLK(NULL, "pclk_fck", &pclk_fck),
3532 CLK(NULL, "pclkx2_fck", &pclkx2_fck),
3533 CLK(NULL, "atclk_fck", &atclk_fck),
3534 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
3535 CLK(NULL, "traceclk_fck", &traceclk_fck),
3536 CLK(NULL, "secure_32k_fck", &secure_32k_fck),
3537 CLK(NULL, "gpt12_fck", &gpt12_fck),
3538 CLK(NULL, "wdt1_fck", &wdt1_fck),
3539 CLK(NULL, "timer_32k_ck", &omap_32k_fck),
3540 CLK(NULL, "timer_sys_ck", &sys_ck),
3541 CLK(NULL, "cpufreq_ck", &dpll1_ck),
Rajendra Nayak99e79382012-11-02 05:02:58 -06003542};
3543
3544static const char *enable_init_clks[] = {
3545 "sdrc_ick",
3546 "gpmc_fck",
3547 "omapctrl_ick",
3548};
3549
3550int __init omap3xxx_clk_init(void)
3551{
Rajendra Nayak99e79382012-11-02 05:02:58 -06003552 if (omap3_has_192mhz_clk())
3553 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3554
3555 if (cpu_is_omap3630()) {
3556 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3557 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3558 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3559 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3560 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3561 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3562 }
3563
3564 /*
3565 * XXX This type of dynamic rewriting of the clock tree is
3566 * deprecated and should be revised soon.
3567 */
3568 if (cpu_is_omap3630())
3569 dpll4_dd = dpll4_dd_3630;
3570 else
3571 dpll4_dd = dpll4_dd_34xx;
3572
Rajendra Nayak99e79382012-11-02 05:02:58 -06003573
J Keerthy78e52e02013-03-18 09:57:39 -06003574 /*
3575 * 3505 must be tested before 3517, since 3517 returns true
3576 * for both AM3517 chips and AM3517 family chips, which
3577 * includes 3505. Unfortunately there's no obvious family
3578 * test for 3517/3505 :-(
3579 */
3580 if (soc_is_am35xx()) {
3581 cpu_mask = RATE_IN_34XX;
3582 omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
3583 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3584 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3585 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3586 } else if (cpu_is_omap3630()) {
3587 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3588 omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
3589 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3590 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3591 omap_clocks_register(omap34xx_omap36xx_clks,
3592 ARRAY_SIZE(omap34xx_omap36xx_clks));
3593 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3594 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3595 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3596 } else if (soc_is_am33xx()) {
3597 cpu_mask = RATE_IN_AM33XX;
3598 } else if (cpu_is_ti814x()) {
3599 cpu_mask = RATE_IN_TI814X;
3600 } else if (cpu_is_omap34xx()) {
3601 if (omap_rev() == OMAP3430_REV_ES1_0) {
3602 cpu_mask = RATE_IN_3430ES1;
3603 omap_clocks_register(omap3430es1_clks,
3604 ARRAY_SIZE(omap3430es1_clks));
3605 omap_clocks_register(omap34xx_omap36xx_clks,
3606 ARRAY_SIZE(omap34xx_omap36xx_clks));
3607 omap_clocks_register(omap3xxx_clks,
3608 ARRAY_SIZE(omap3xxx_clks));
3609 } else {
3610 /*
3611 * Assume that anything that we haven't matched yet
3612 * has 3430ES2-type clocks.
3613 */
3614 cpu_mask = RATE_IN_3430ES2PLUS;
3615 omap_clocks_register(omap34xx_omap36xx_clks,
3616 ARRAY_SIZE(omap34xx_omap36xx_clks));
3617 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3618 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3619 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3620 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3621 omap_clocks_register(omap3xxx_clks,
3622 ARRAY_SIZE(omap3xxx_clks));
3623 }
3624 } else {
3625 WARN(1, "clock: could not identify OMAP3 variant\n");
3626 }
3627
3628 omap2_clk_disable_autoidle_all();
Rajendra Nayak99e79382012-11-02 05:02:58 -06003629
3630 omap2_clk_enable_init_clocks(enable_init_clks,
3631 ARRAY_SIZE(enable_init_clks));
3632
3633 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3634 (clk_get_rate(&osc_sys_ck) / 1000000),
3635 (clk_get_rate(&osc_sys_ck) / 100000) % 10,
3636 (clk_get_rate(&core_ck) / 1000000),
3637 (clk_get_rate(&arm_fck) / 1000000));
3638
3639 /*
3640 * Lock DPLL5 -- here only until other device init code can
3641 * handle this
3642 */
3643 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3644 omap3_clk_lock_dpll5();
3645
3646 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3647 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3648 arm_fck_p = clk_get(NULL, "arm_fck");
3649
3650 return 0;
3651}