Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 28 | #include <linux/slab.h> |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 29 | #include <linux/seq_file.h> |
| 30 | #include <linux/firmware.h> |
| 31 | #include <linux/platform_device.h> |
Paul Gortmaker | e0cd360 | 2011-08-30 11:04:30 -0400 | [diff] [blame] | 32 | #include <linux/module.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 33 | #include "drmP.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 34 | #include "radeon_drm.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 35 | #include "radeon.h" |
Daniel Vetter | e699037 | 2010-03-11 21:19:17 +0000 | [diff] [blame] | 36 | #include "radeon_asic.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 37 | #include "radeon_mode.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 38 | #include "r600d.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 39 | #include "atom.h" |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 40 | #include "avivod.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 42 | #define PFP_UCODE_SIZE 576 |
| 43 | #define PM4_UCODE_SIZE 1792 |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 44 | #define RLC_UCODE_SIZE 768 |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 45 | #define R700_PFP_UCODE_SIZE 848 |
| 46 | #define R700_PM4_UCODE_SIZE 1360 |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 47 | #define R700_RLC_UCODE_SIZE 1024 |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 48 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
| 49 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 50 | #define EVERGREEN_RLC_UCODE_SIZE 768 |
Alex Deucher | 1272780 | 2011-03-02 20:07:32 -0500 | [diff] [blame] | 51 | #define CAYMAN_RLC_UCODE_SIZE 1024 |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 52 | |
| 53 | /* Firmware Names */ |
| 54 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); |
| 55 | MODULE_FIRMWARE("radeon/R600_me.bin"); |
| 56 | MODULE_FIRMWARE("radeon/RV610_pfp.bin"); |
| 57 | MODULE_FIRMWARE("radeon/RV610_me.bin"); |
| 58 | MODULE_FIRMWARE("radeon/RV630_pfp.bin"); |
| 59 | MODULE_FIRMWARE("radeon/RV630_me.bin"); |
| 60 | MODULE_FIRMWARE("radeon/RV620_pfp.bin"); |
| 61 | MODULE_FIRMWARE("radeon/RV620_me.bin"); |
| 62 | MODULE_FIRMWARE("radeon/RV635_pfp.bin"); |
| 63 | MODULE_FIRMWARE("radeon/RV635_me.bin"); |
| 64 | MODULE_FIRMWARE("radeon/RV670_pfp.bin"); |
| 65 | MODULE_FIRMWARE("radeon/RV670_me.bin"); |
| 66 | MODULE_FIRMWARE("radeon/RS780_pfp.bin"); |
| 67 | MODULE_FIRMWARE("radeon/RS780_me.bin"); |
| 68 | MODULE_FIRMWARE("radeon/RV770_pfp.bin"); |
| 69 | MODULE_FIRMWARE("radeon/RV770_me.bin"); |
| 70 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); |
| 71 | MODULE_FIRMWARE("radeon/RV730_me.bin"); |
| 72 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); |
| 73 | MODULE_FIRMWARE("radeon/RV710_me.bin"); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 74 | MODULE_FIRMWARE("radeon/R600_rlc.bin"); |
| 75 | MODULE_FIRMWARE("radeon/R700_rlc.bin"); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 76 | MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); |
| 77 | MODULE_FIRMWARE("radeon/CEDAR_me.bin"); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 78 | MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 79 | MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); |
| 80 | MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 81 | MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 82 | MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); |
| 83 | MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 84 | MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); |
Dave Airlie | a743374 | 2010-04-09 15:31:09 +1000 | [diff] [blame] | 85 | MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 86 | MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 87 | MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); |
Alex Deucher | 439bd6c | 2010-11-22 17:56:31 -0500 | [diff] [blame] | 88 | MODULE_FIRMWARE("radeon/PALM_pfp.bin"); |
| 89 | MODULE_FIRMWARE("radeon/PALM_me.bin"); |
| 90 | MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); |
Alex Deucher | d5c5a72 | 2011-05-31 15:42:48 -0400 | [diff] [blame] | 91 | MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); |
| 92 | MODULE_FIRMWARE("radeon/SUMO_me.bin"); |
| 93 | MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); |
| 94 | MODULE_FIRMWARE("radeon/SUMO2_me.bin"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 95 | |
| 96 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 97 | |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 98 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 99 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
| 100 | void r600_gpu_init(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 101 | void r600_fini(struct radeon_device *rdev); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 102 | void r600_irq_disable(struct radeon_device *rdev); |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 103 | static void r600_pcie_gen2_enable(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 104 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 105 | /* get temperature in millidegrees */ |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 106 | int rv6xx_get_temp(struct radeon_device *rdev) |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 107 | { |
| 108 | u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> |
| 109 | ASIC_T_SHIFT; |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 110 | int actual_temp = temp & 0xff; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 111 | |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 112 | if (temp & 0x100) |
| 113 | actual_temp -= 256; |
| 114 | |
| 115 | return actual_temp * 1000; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 116 | } |
| 117 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 118 | void r600_pm_get_dynpm_state(struct radeon_device *rdev) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 119 | { |
| 120 | int i; |
| 121 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 122 | rdev->pm.dynpm_can_upclock = true; |
| 123 | rdev->pm.dynpm_can_downclock = true; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 124 | |
| 125 | /* power state array is low to high, default is first */ |
| 126 | if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { |
| 127 | int min_power_state_index = 0; |
| 128 | |
| 129 | if (rdev->pm.num_power_states > 2) |
| 130 | min_power_state_index = 1; |
| 131 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 132 | switch (rdev->pm.dynpm_planned_action) { |
| 133 | case DYNPM_ACTION_MINIMUM: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 134 | rdev->pm.requested_power_state_index = min_power_state_index; |
| 135 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 136 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 137 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 138 | case DYNPM_ACTION_DOWNCLOCK: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 139 | if (rdev->pm.current_power_state_index == min_power_state_index) { |
| 140 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 141 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 142 | } else { |
| 143 | if (rdev->pm.active_crtc_count > 1) { |
| 144 | for (i = 0; i < rdev->pm.num_power_states; i++) { |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 145 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 146 | continue; |
| 147 | else if (i >= rdev->pm.current_power_state_index) { |
| 148 | rdev->pm.requested_power_state_index = |
| 149 | rdev->pm.current_power_state_index; |
| 150 | break; |
| 151 | } else { |
| 152 | rdev->pm.requested_power_state_index = i; |
| 153 | break; |
| 154 | } |
| 155 | } |
Alex Deucher | 773c3fa | 2010-06-25 16:21:27 -0400 | [diff] [blame] | 156 | } else { |
| 157 | if (rdev->pm.current_power_state_index == 0) |
| 158 | rdev->pm.requested_power_state_index = |
| 159 | rdev->pm.num_power_states - 1; |
| 160 | else |
| 161 | rdev->pm.requested_power_state_index = |
| 162 | rdev->pm.current_power_state_index - 1; |
| 163 | } |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 164 | } |
| 165 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 166 | /* don't use the power state if crtcs are active and no display flag is set */ |
| 167 | if ((rdev->pm.active_crtc_count > 0) && |
| 168 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 169 | clock_info[rdev->pm.requested_clock_mode_index].flags & |
| 170 | RADEON_PM_MODE_NO_DISPLAY)) { |
| 171 | rdev->pm.requested_power_state_index++; |
| 172 | } |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 173 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 174 | case DYNPM_ACTION_UPCLOCK: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 175 | if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { |
| 176 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 177 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 178 | } else { |
| 179 | if (rdev->pm.active_crtc_count > 1) { |
| 180 | for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 181 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 182 | continue; |
| 183 | else if (i <= rdev->pm.current_power_state_index) { |
| 184 | rdev->pm.requested_power_state_index = |
| 185 | rdev->pm.current_power_state_index; |
| 186 | break; |
| 187 | } else { |
| 188 | rdev->pm.requested_power_state_index = i; |
| 189 | break; |
| 190 | } |
| 191 | } |
| 192 | } else |
| 193 | rdev->pm.requested_power_state_index = |
| 194 | rdev->pm.current_power_state_index + 1; |
| 195 | } |
| 196 | rdev->pm.requested_clock_mode_index = 0; |
| 197 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 198 | case DYNPM_ACTION_DEFAULT: |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 199 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
| 200 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 201 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 202 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 203 | case DYNPM_ACTION_NONE: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 204 | default: |
| 205 | DRM_ERROR("Requested mode for not defined action\n"); |
| 206 | return; |
| 207 | } |
| 208 | } else { |
| 209 | /* XXX select a power state based on AC/DC, single/dualhead, etc. */ |
| 210 | /* for now just select the first power state and switch between clock modes */ |
| 211 | /* power state array is low to high, default is first (0) */ |
| 212 | if (rdev->pm.active_crtc_count > 1) { |
| 213 | rdev->pm.requested_power_state_index = -1; |
| 214 | /* start at 1 as we don't want the default mode */ |
| 215 | for (i = 1; i < rdev->pm.num_power_states; i++) { |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 216 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 217 | continue; |
| 218 | else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || |
| 219 | (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { |
| 220 | rdev->pm.requested_power_state_index = i; |
| 221 | break; |
| 222 | } |
| 223 | } |
| 224 | /* if nothing selected, grab the default state. */ |
| 225 | if (rdev->pm.requested_power_state_index == -1) |
| 226 | rdev->pm.requested_power_state_index = 0; |
| 227 | } else |
| 228 | rdev->pm.requested_power_state_index = 1; |
| 229 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 230 | switch (rdev->pm.dynpm_planned_action) { |
| 231 | case DYNPM_ACTION_MINIMUM: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 232 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 233 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 234 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 235 | case DYNPM_ACTION_DOWNCLOCK: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 236 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
| 237 | if (rdev->pm.current_clock_mode_index == 0) { |
| 238 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 239 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 240 | } else |
| 241 | rdev->pm.requested_clock_mode_index = |
| 242 | rdev->pm.current_clock_mode_index - 1; |
| 243 | } else { |
| 244 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 245 | rdev->pm.dynpm_can_downclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 246 | } |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 247 | /* don't use the power state if crtcs are active and no display flag is set */ |
| 248 | if ((rdev->pm.active_crtc_count > 0) && |
| 249 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 250 | clock_info[rdev->pm.requested_clock_mode_index].flags & |
| 251 | RADEON_PM_MODE_NO_DISPLAY)) { |
| 252 | rdev->pm.requested_clock_mode_index++; |
| 253 | } |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 254 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 255 | case DYNPM_ACTION_UPCLOCK: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 256 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
| 257 | if (rdev->pm.current_clock_mode_index == |
| 258 | (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { |
| 259 | rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 260 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 261 | } else |
| 262 | rdev->pm.requested_clock_mode_index = |
| 263 | rdev->pm.current_clock_mode_index + 1; |
| 264 | } else { |
| 265 | rdev->pm.requested_clock_mode_index = |
| 266 | rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 267 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 268 | } |
| 269 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 270 | case DYNPM_ACTION_DEFAULT: |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 271 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
| 272 | rdev->pm.requested_clock_mode_index = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 273 | rdev->pm.dynpm_can_upclock = false; |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 274 | break; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 275 | case DYNPM_ACTION_NONE: |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 276 | default: |
| 277 | DRM_ERROR("Requested mode for not defined action\n"); |
| 278 | return; |
| 279 | } |
| 280 | } |
| 281 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 282 | DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", |
Alex Deucher | ce8a3eb | 2010-05-07 16:58:27 -0400 | [diff] [blame] | 283 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 284 | clock_info[rdev->pm.requested_clock_mode_index].sclk, |
| 285 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 286 | clock_info[rdev->pm.requested_clock_mode_index].mclk, |
| 287 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
| 288 | pcie_lanes); |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 289 | } |
| 290 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 291 | void rs780_pm_init_profile(struct radeon_device *rdev) |
| 292 | { |
| 293 | if (rdev->pm.num_power_states == 2) { |
| 294 | /* default */ |
| 295 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 296 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 297 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
| 298 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
| 299 | /* low sh */ |
| 300 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; |
| 301 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; |
| 302 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
| 303 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 304 | /* mid sh */ |
| 305 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; |
| 306 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; |
| 307 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 308 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 309 | /* high sh */ |
| 310 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; |
| 311 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; |
| 312 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
| 313 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
| 314 | /* low mh */ |
| 315 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; |
| 316 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; |
| 317 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
| 318 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 319 | /* mid mh */ |
| 320 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; |
| 321 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; |
| 322 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 323 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 324 | /* high mh */ |
| 325 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; |
| 326 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; |
| 327 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
| 328 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
| 329 | } else if (rdev->pm.num_power_states == 3) { |
| 330 | /* default */ |
| 331 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 332 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 333 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
| 334 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
| 335 | /* low sh */ |
| 336 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; |
| 337 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; |
| 338 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
| 339 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 340 | /* mid sh */ |
| 341 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; |
| 342 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; |
| 343 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 344 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 345 | /* high sh */ |
| 346 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; |
| 347 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; |
| 348 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
| 349 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
| 350 | /* low mh */ |
| 351 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; |
| 352 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; |
| 353 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
| 354 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 355 | /* mid mh */ |
| 356 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; |
| 357 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; |
| 358 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 359 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 360 | /* high mh */ |
| 361 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; |
| 362 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; |
| 363 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
| 364 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
| 365 | } else { |
| 366 | /* default */ |
| 367 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 368 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 369 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
| 370 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
| 371 | /* low sh */ |
| 372 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; |
| 373 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; |
| 374 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
| 375 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 376 | /* mid sh */ |
| 377 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; |
| 378 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; |
| 379 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 380 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 381 | /* high sh */ |
| 382 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; |
| 383 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; |
| 384 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
| 385 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
| 386 | /* low mh */ |
| 387 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; |
| 388 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; |
| 389 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
| 390 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 391 | /* mid mh */ |
| 392 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; |
| 393 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; |
| 394 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 395 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 396 | /* high mh */ |
| 397 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; |
| 398 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; |
| 399 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
| 400 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | void r600_pm_init_profile(struct radeon_device *rdev) |
| 405 | { |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 406 | int idx; |
| 407 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 408 | if (rdev->family == CHIP_R600) { |
| 409 | /* XXX */ |
| 410 | /* default */ |
| 411 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 412 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 413 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 414 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 415 | /* low sh */ |
| 416 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 417 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 418 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 419 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 420 | /* mid sh */ |
| 421 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 422 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 423 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 424 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 425 | /* high sh */ |
| 426 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 427 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 428 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 429 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 430 | /* low mh */ |
| 431 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 432 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 433 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 434 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 435 | /* mid mh */ |
| 436 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 437 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 438 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 439 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 440 | /* high mh */ |
| 441 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 442 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 443 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 444 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 445 | } else { |
| 446 | if (rdev->pm.num_power_states < 4) { |
| 447 | /* default */ |
| 448 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 449 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 450 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
| 451 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; |
| 452 | /* low sh */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 453 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; |
| 454 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; |
| 455 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 456 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
| 457 | /* mid sh */ |
| 458 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; |
| 459 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; |
| 460 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 461 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 462 | /* high sh */ |
| 463 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; |
| 464 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; |
| 465 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
| 466 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; |
| 467 | /* low mh */ |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 468 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; |
| 469 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 470 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 471 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
| 472 | /* low mh */ |
| 473 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; |
| 474 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; |
| 475 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 476 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 477 | /* high mh */ |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 478 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; |
| 479 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; |
| 480 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
| 481 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; |
| 482 | } else { |
| 483 | /* default */ |
| 484 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
| 485 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
| 486 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; |
| 487 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; |
| 488 | /* low sh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 489 | if (rdev->flags & RADEON_IS_MOBILITY) |
| 490 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); |
| 491 | else |
| 492 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); |
| 493 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; |
| 494 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; |
| 495 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
| 496 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 497 | /* mid sh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 498 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; |
| 499 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; |
| 500 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; |
| 501 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 502 | /* high sh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 503 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); |
| 504 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; |
| 505 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 506 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
| 507 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; |
| 508 | /* low mh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 509 | if (rdev->flags & RADEON_IS_MOBILITY) |
| 510 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); |
| 511 | else |
| 512 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); |
| 513 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; |
| 514 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; |
| 515 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
| 516 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 517 | /* mid mh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 518 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; |
| 519 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; |
| 520 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; |
| 521 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; |
Alex Deucher | 4bff517 | 2010-05-17 19:41:26 -0400 | [diff] [blame] | 522 | /* high mh */ |
Alex Deucher | bbe26ff | 2011-11-04 10:09:42 -0400 | [diff] [blame] | 523 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); |
| 524 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; |
| 525 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 526 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
| 527 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; |
| 528 | } |
| 529 | } |
Alex Deucher | bae6b562 | 2010-04-22 13:38:05 -0400 | [diff] [blame] | 530 | } |
| 531 | |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 532 | void r600_pm_misc(struct radeon_device *rdev) |
| 533 | { |
Rafał Miłecki | a081a9d | 2010-06-07 18:20:25 -0400 | [diff] [blame] | 534 | int req_ps_idx = rdev->pm.requested_power_state_index; |
| 535 | int req_cm_idx = rdev->pm.requested_clock_mode_index; |
| 536 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; |
| 537 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 538 | |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 539 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
Alex Deucher | a377e18 | 2011-06-20 13:00:31 -0400 | [diff] [blame] | 540 | /* 0xff01 is a flag rather then an actual voltage */ |
| 541 | if (voltage->voltage == 0xff01) |
| 542 | return; |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 543 | if (voltage->voltage != rdev->pm.current_vddc) { |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 544 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 545 | rdev->pm.current_vddc = voltage->voltage; |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 546 | DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); |
Alex Deucher | 4d60173 | 2010-06-07 18:15:18 -0400 | [diff] [blame] | 547 | } |
| 548 | } |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 549 | } |
| 550 | |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 551 | bool r600_gui_idle(struct radeon_device *rdev) |
| 552 | { |
| 553 | if (RREG32(GRBM_STATUS) & GUI_ACTIVE) |
| 554 | return false; |
| 555 | else |
| 556 | return true; |
| 557 | } |
| 558 | |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 559 | /* hpd for digital panel detect/disconnect */ |
| 560 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
| 561 | { |
| 562 | bool connected = false; |
| 563 | |
| 564 | if (ASIC_IS_DCE3(rdev)) { |
| 565 | switch (hpd) { |
| 566 | case RADEON_HPD_1: |
| 567 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) |
| 568 | connected = true; |
| 569 | break; |
| 570 | case RADEON_HPD_2: |
| 571 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) |
| 572 | connected = true; |
| 573 | break; |
| 574 | case RADEON_HPD_3: |
| 575 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) |
| 576 | connected = true; |
| 577 | break; |
| 578 | case RADEON_HPD_4: |
| 579 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) |
| 580 | connected = true; |
| 581 | break; |
| 582 | /* DCE 3.2 */ |
| 583 | case RADEON_HPD_5: |
| 584 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) |
| 585 | connected = true; |
| 586 | break; |
| 587 | case RADEON_HPD_6: |
| 588 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) |
| 589 | connected = true; |
| 590 | break; |
| 591 | default: |
| 592 | break; |
| 593 | } |
| 594 | } else { |
| 595 | switch (hpd) { |
| 596 | case RADEON_HPD_1: |
| 597 | if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) |
| 598 | connected = true; |
| 599 | break; |
| 600 | case RADEON_HPD_2: |
| 601 | if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) |
| 602 | connected = true; |
| 603 | break; |
| 604 | case RADEON_HPD_3: |
| 605 | if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) |
| 606 | connected = true; |
| 607 | break; |
| 608 | default: |
| 609 | break; |
| 610 | } |
| 611 | } |
| 612 | return connected; |
| 613 | } |
| 614 | |
| 615 | void r600_hpd_set_polarity(struct radeon_device *rdev, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 616 | enum radeon_hpd_id hpd) |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 617 | { |
| 618 | u32 tmp; |
| 619 | bool connected = r600_hpd_sense(rdev, hpd); |
| 620 | |
| 621 | if (ASIC_IS_DCE3(rdev)) { |
| 622 | switch (hpd) { |
| 623 | case RADEON_HPD_1: |
| 624 | tmp = RREG32(DC_HPD1_INT_CONTROL); |
| 625 | if (connected) |
| 626 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 627 | else |
| 628 | tmp |= DC_HPDx_INT_POLARITY; |
| 629 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
| 630 | break; |
| 631 | case RADEON_HPD_2: |
| 632 | tmp = RREG32(DC_HPD2_INT_CONTROL); |
| 633 | if (connected) |
| 634 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 635 | else |
| 636 | tmp |= DC_HPDx_INT_POLARITY; |
| 637 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
| 638 | break; |
| 639 | case RADEON_HPD_3: |
| 640 | tmp = RREG32(DC_HPD3_INT_CONTROL); |
| 641 | if (connected) |
| 642 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 643 | else |
| 644 | tmp |= DC_HPDx_INT_POLARITY; |
| 645 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
| 646 | break; |
| 647 | case RADEON_HPD_4: |
| 648 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
| 649 | if (connected) |
| 650 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 651 | else |
| 652 | tmp |= DC_HPDx_INT_POLARITY; |
| 653 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
| 654 | break; |
| 655 | case RADEON_HPD_5: |
| 656 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
| 657 | if (connected) |
| 658 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 659 | else |
| 660 | tmp |= DC_HPDx_INT_POLARITY; |
| 661 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
| 662 | break; |
| 663 | /* DCE 3.2 */ |
| 664 | case RADEON_HPD_6: |
| 665 | tmp = RREG32(DC_HPD6_INT_CONTROL); |
| 666 | if (connected) |
| 667 | tmp &= ~DC_HPDx_INT_POLARITY; |
| 668 | else |
| 669 | tmp |= DC_HPDx_INT_POLARITY; |
| 670 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
| 671 | break; |
| 672 | default: |
| 673 | break; |
| 674 | } |
| 675 | } else { |
| 676 | switch (hpd) { |
| 677 | case RADEON_HPD_1: |
| 678 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); |
| 679 | if (connected) |
| 680 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 681 | else |
| 682 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 683 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
| 684 | break; |
| 685 | case RADEON_HPD_2: |
| 686 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); |
| 687 | if (connected) |
| 688 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 689 | else |
| 690 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 691 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
| 692 | break; |
| 693 | case RADEON_HPD_3: |
| 694 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); |
| 695 | if (connected) |
| 696 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 697 | else |
| 698 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; |
| 699 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
| 700 | break; |
| 701 | default: |
| 702 | break; |
| 703 | } |
| 704 | } |
| 705 | } |
| 706 | |
| 707 | void r600_hpd_init(struct radeon_device *rdev) |
| 708 | { |
| 709 | struct drm_device *dev = rdev->ddev; |
| 710 | struct drm_connector *connector; |
| 711 | |
Alex Deucher | 64912e9 | 2011-11-03 11:21:39 -0400 | [diff] [blame] | 712 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 713 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 714 | |
Alex Deucher | 64912e9 | 2011-11-03 11:21:39 -0400 | [diff] [blame] | 715 | if (ASIC_IS_DCE3(rdev)) { |
| 716 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); |
| 717 | if (ASIC_IS_DCE32(rdev)) |
| 718 | tmp |= DC_HPDx_EN; |
| 719 | |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 720 | switch (radeon_connector->hpd.hpd) { |
| 721 | case RADEON_HPD_1: |
| 722 | WREG32(DC_HPD1_CONTROL, tmp); |
| 723 | rdev->irq.hpd[0] = true; |
| 724 | break; |
| 725 | case RADEON_HPD_2: |
| 726 | WREG32(DC_HPD2_CONTROL, tmp); |
| 727 | rdev->irq.hpd[1] = true; |
| 728 | break; |
| 729 | case RADEON_HPD_3: |
| 730 | WREG32(DC_HPD3_CONTROL, tmp); |
| 731 | rdev->irq.hpd[2] = true; |
| 732 | break; |
| 733 | case RADEON_HPD_4: |
| 734 | WREG32(DC_HPD4_CONTROL, tmp); |
| 735 | rdev->irq.hpd[3] = true; |
| 736 | break; |
| 737 | /* DCE 3.2 */ |
| 738 | case RADEON_HPD_5: |
| 739 | WREG32(DC_HPD5_CONTROL, tmp); |
| 740 | rdev->irq.hpd[4] = true; |
| 741 | break; |
| 742 | case RADEON_HPD_6: |
| 743 | WREG32(DC_HPD6_CONTROL, tmp); |
| 744 | rdev->irq.hpd[5] = true; |
| 745 | break; |
| 746 | default: |
| 747 | break; |
| 748 | } |
Alex Deucher | 64912e9 | 2011-11-03 11:21:39 -0400 | [diff] [blame] | 749 | } else { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 750 | switch (radeon_connector->hpd.hpd) { |
| 751 | case RADEON_HPD_1: |
| 752 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
| 753 | rdev->irq.hpd[0] = true; |
| 754 | break; |
| 755 | case RADEON_HPD_2: |
| 756 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
| 757 | rdev->irq.hpd[1] = true; |
| 758 | break; |
| 759 | case RADEON_HPD_3: |
| 760 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); |
| 761 | rdev->irq.hpd[2] = true; |
| 762 | break; |
| 763 | default: |
| 764 | break; |
| 765 | } |
| 766 | } |
Alex Deucher | 64912e9 | 2011-11-03 11:21:39 -0400 | [diff] [blame] | 767 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 768 | } |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 769 | if (rdev->irq.installed) |
| 770 | r600_irq_set(rdev); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 771 | } |
| 772 | |
| 773 | void r600_hpd_fini(struct radeon_device *rdev) |
| 774 | { |
| 775 | struct drm_device *dev = rdev->ddev; |
| 776 | struct drm_connector *connector; |
| 777 | |
| 778 | if (ASIC_IS_DCE3(rdev)) { |
| 779 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 780 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 781 | switch (radeon_connector->hpd.hpd) { |
| 782 | case RADEON_HPD_1: |
| 783 | WREG32(DC_HPD1_CONTROL, 0); |
| 784 | rdev->irq.hpd[0] = false; |
| 785 | break; |
| 786 | case RADEON_HPD_2: |
| 787 | WREG32(DC_HPD2_CONTROL, 0); |
| 788 | rdev->irq.hpd[1] = false; |
| 789 | break; |
| 790 | case RADEON_HPD_3: |
| 791 | WREG32(DC_HPD3_CONTROL, 0); |
| 792 | rdev->irq.hpd[2] = false; |
| 793 | break; |
| 794 | case RADEON_HPD_4: |
| 795 | WREG32(DC_HPD4_CONTROL, 0); |
| 796 | rdev->irq.hpd[3] = false; |
| 797 | break; |
| 798 | /* DCE 3.2 */ |
| 799 | case RADEON_HPD_5: |
| 800 | WREG32(DC_HPD5_CONTROL, 0); |
| 801 | rdev->irq.hpd[4] = false; |
| 802 | break; |
| 803 | case RADEON_HPD_6: |
| 804 | WREG32(DC_HPD6_CONTROL, 0); |
| 805 | rdev->irq.hpd[5] = false; |
| 806 | break; |
| 807 | default: |
| 808 | break; |
| 809 | } |
| 810 | } |
| 811 | } else { |
| 812 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 813 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 814 | switch (radeon_connector->hpd.hpd) { |
| 815 | case RADEON_HPD_1: |
| 816 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); |
| 817 | rdev->irq.hpd[0] = false; |
| 818 | break; |
| 819 | case RADEON_HPD_2: |
| 820 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); |
| 821 | rdev->irq.hpd[1] = false; |
| 822 | break; |
| 823 | case RADEON_HPD_3: |
| 824 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); |
| 825 | rdev->irq.hpd[2] = false; |
| 826 | break; |
| 827 | default: |
| 828 | break; |
| 829 | } |
| 830 | } |
| 831 | } |
| 832 | } |
| 833 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 834 | /* |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 835 | * R600 PCIE GART |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 836 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 837 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 838 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 839 | unsigned i; |
| 840 | u32 tmp; |
| 841 | |
Dave Airlie | 2e98f10 | 2010-02-15 15:54:45 +1000 | [diff] [blame] | 842 | /* flush hdp cache so updates hit vram */ |
Alex Deucher | f3886f8 | 2010-12-08 10:05:34 -0500 | [diff] [blame] | 843 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
| 844 | !(rdev->flags & RADEON_IS_AGP)) { |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 845 | void __iomem *ptr = (void *)rdev->gart.ptr; |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 846 | u32 tmp; |
| 847 | |
| 848 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read |
| 849 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL |
Alex Deucher | f3886f8 | 2010-12-08 10:05:34 -0500 | [diff] [blame] | 850 | * This seems to cause problems on some AGP cards. Just use the old |
| 851 | * method for them. |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 852 | */ |
| 853 | WREG32(HDP_DEBUG1, 0); |
| 854 | tmp = readl((void __iomem *)ptr); |
| 855 | } else |
| 856 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
Dave Airlie | 2e98f10 | 2010-02-15 15:54:45 +1000 | [diff] [blame] | 857 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 858 | WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); |
| 859 | WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); |
| 860 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); |
| 861 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 862 | /* read MC_STATUS */ |
| 863 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); |
| 864 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; |
| 865 | if (tmp == 2) { |
| 866 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); |
| 867 | return; |
| 868 | } |
| 869 | if (tmp) { |
| 870 | return; |
| 871 | } |
| 872 | udelay(1); |
| 873 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 874 | } |
| 875 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 876 | int r600_pcie_gart_init(struct radeon_device *rdev) |
| 877 | { |
| 878 | int r; |
| 879 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 880 | if (rdev->gart.robj) { |
Joe Perches | fce7d61 | 2010-10-30 21:08:30 +0000 | [diff] [blame] | 881 | WARN(1, "R600 PCIE GART already initialized\n"); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 882 | return 0; |
| 883 | } |
| 884 | /* Initialize common gart structure */ |
| 885 | r = radeon_gart_init(rdev); |
| 886 | if (r) |
| 887 | return r; |
| 888 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
| 889 | return radeon_gart_table_vram_alloc(rdev); |
| 890 | } |
| 891 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 892 | int r600_pcie_gart_enable(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 893 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 894 | u32 tmp; |
| 895 | int r, i; |
| 896 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 897 | if (rdev->gart.robj == NULL) { |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 898 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
| 899 | return -EINVAL; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 900 | } |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 901 | r = radeon_gart_table_vram_pin(rdev); |
| 902 | if (r) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 903 | return r; |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 904 | radeon_gart_restore(rdev); |
Dave Airlie | bc1a631 | 2009-09-15 11:07:52 +1000 | [diff] [blame] | 905 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 906 | /* Setup L2 cache */ |
| 907 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
| 908 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 909 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 910 | WREG32(VM_L2_CNTL2, 0); |
| 911 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); |
| 912 | /* Setup TLB control */ |
| 913 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
| 914 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| 915 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | |
| 916 | ENABLE_WAIT_L2_QUERY; |
| 917 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
| 918 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
| 919 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); |
| 920 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
| 921 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); |
| 922 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); |
| 923 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); |
| 924 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); |
| 925 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); |
| 926 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); |
| 927 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); |
| 928 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); |
| 929 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| 930 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| 931 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 932 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 933 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
| 934 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
| 935 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
| 936 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
| 937 | (u32)(rdev->dummy_page.addr >> 12)); |
| 938 | for (i = 1; i < 7; i++) |
| 939 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 940 | |
| 941 | r600_pcie_gart_tlb_flush(rdev); |
Tormod Volden | fcf4de5 | 2011-08-31 21:54:07 +0000 | [diff] [blame] | 942 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
| 943 | (unsigned)(rdev->mc.gtt_size >> 20), |
| 944 | (unsigned long long)rdev->gart.table_addr); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 945 | rdev->gart.ready = true; |
| 946 | return 0; |
| 947 | } |
| 948 | |
| 949 | void r600_pcie_gart_disable(struct radeon_device *rdev) |
| 950 | { |
| 951 | u32 tmp; |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 952 | int i; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 953 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 954 | /* Disable all tables */ |
| 955 | for (i = 0; i < 7; i++) |
| 956 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 957 | |
| 958 | /* Disable L2 cache */ |
| 959 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | |
| 960 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 961 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); |
| 962 | /* Setup L1 TLB control */ |
| 963 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | |
| 964 | ENABLE_WAIT_L2_QUERY; |
| 965 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); |
| 966 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); |
| 967 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); |
| 968 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); |
| 969 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); |
| 970 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); |
| 971 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); |
| 972 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); |
| 973 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); |
| 974 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); |
| 975 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
| 976 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
| 977 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); |
| 978 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 979 | radeon_gart_table_vram_unpin(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 980 | } |
| 981 | |
| 982 | void r600_pcie_gart_fini(struct radeon_device *rdev) |
| 983 | { |
Jerome Glisse | f927456 | 2010-03-17 14:44:29 +0000 | [diff] [blame] | 984 | radeon_gart_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 985 | r600_pcie_gart_disable(rdev); |
| 986 | radeon_gart_table_vram_free(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 987 | } |
| 988 | |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 989 | void r600_agp_enable(struct radeon_device *rdev) |
| 990 | { |
| 991 | u32 tmp; |
| 992 | int i; |
| 993 | |
| 994 | /* Setup L2 cache */ |
| 995 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
| 996 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| 997 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
| 998 | WREG32(VM_L2_CNTL2, 0); |
| 999 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); |
| 1000 | /* Setup TLB control */ |
| 1001 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
| 1002 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| 1003 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | |
| 1004 | ENABLE_WAIT_L2_QUERY; |
| 1005 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
| 1006 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
| 1007 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); |
| 1008 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
| 1009 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); |
| 1010 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); |
| 1011 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); |
| 1012 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); |
| 1013 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); |
| 1014 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); |
| 1015 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); |
| 1016 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); |
| 1017 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| 1018 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| 1019 | for (i = 0; i < 7; i++) |
| 1020 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| 1021 | } |
| 1022 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1023 | int r600_mc_wait_for_idle(struct radeon_device *rdev) |
| 1024 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1025 | unsigned i; |
| 1026 | u32 tmp; |
| 1027 | |
| 1028 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 1029 | /* read MC_STATUS */ |
| 1030 | tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; |
| 1031 | if (!tmp) |
| 1032 | return 0; |
| 1033 | udelay(1); |
| 1034 | } |
| 1035 | return -1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1036 | } |
| 1037 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1038 | static void r600_mc_program(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1039 | { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1040 | struct rv515_mc_save save; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1041 | u32 tmp; |
| 1042 | int i, j; |
| 1043 | |
| 1044 | /* Initialize HDP */ |
| 1045 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
| 1046 | WREG32((0x2c14 + j), 0x00000000); |
| 1047 | WREG32((0x2c18 + j), 0x00000000); |
| 1048 | WREG32((0x2c1c + j), 0x00000000); |
| 1049 | WREG32((0x2c20 + j), 0x00000000); |
| 1050 | WREG32((0x2c24 + j), 0x00000000); |
| 1051 | } |
| 1052 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); |
| 1053 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1054 | rv515_mc_stop(rdev, &save); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1055 | if (r600_mc_wait_for_idle(rdev)) { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1056 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1057 | } |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1058 | /* Lockout access through VGA aperture (doesn't exist before R600) */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1059 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1060 | /* Update configuration */ |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1061 | if (rdev->flags & RADEON_IS_AGP) { |
| 1062 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { |
| 1063 | /* VRAM before AGP */ |
| 1064 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 1065 | rdev->mc.vram_start >> 12); |
| 1066 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 1067 | rdev->mc.gtt_end >> 12); |
| 1068 | } else { |
| 1069 | /* VRAM after AGP */ |
| 1070 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 1071 | rdev->mc.gtt_start >> 12); |
| 1072 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 1073 | rdev->mc.vram_end >> 12); |
| 1074 | } |
| 1075 | } else { |
| 1076 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); |
| 1077 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); |
| 1078 | } |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1079 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1080 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1081 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
| 1082 | WREG32(MC_VM_FB_LOCATION, tmp); |
| 1083 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
| 1084 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
Jerome Glisse | 46fcd2b | 2010-06-03 19:34:48 +0200 | [diff] [blame] | 1085 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1086 | if (rdev->flags & RADEON_IS_AGP) { |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1087 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); |
| 1088 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1089 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
| 1090 | } else { |
| 1091 | WREG32(MC_VM_AGP_BASE, 0); |
| 1092 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
| 1093 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
| 1094 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1095 | if (r600_mc_wait_for_idle(rdev)) { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1096 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1097 | } |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1098 | rv515_mc_resume(rdev, &save); |
Dave Airlie | 698443d | 2009-09-18 14:16:38 +1000 | [diff] [blame] | 1099 | /* we need to own VRAM, so turn off the VGA renderer here |
| 1100 | * to stop it overwriting our objects */ |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1101 | rv515_vga_render_disable(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1102 | } |
| 1103 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1104 | /** |
| 1105 | * r600_vram_gtt_location - try to find VRAM & GTT location |
| 1106 | * @rdev: radeon device structure holding all necessary informations |
| 1107 | * @mc: memory controller structure holding memory informations |
| 1108 | * |
| 1109 | * Function will place try to place VRAM at same place as in CPU (PCI) |
| 1110 | * address space as some GPU seems to have issue when we reprogram at |
| 1111 | * different address space. |
| 1112 | * |
| 1113 | * If there is not enough space to fit the unvisible VRAM after the |
| 1114 | * aperture then we limit the VRAM size to the aperture. |
| 1115 | * |
| 1116 | * If we are using AGP then place VRAM adjacent to AGP aperture are we need |
| 1117 | * them to be in one from GPU point of view so that we can program GPU to |
| 1118 | * catch access outside them (weird GPU policy see ??). |
| 1119 | * |
| 1120 | * This function will never fails, worst case are limiting VRAM or GTT. |
| 1121 | * |
| 1122 | * Note: GTT start, end, size should be initialized before calling this |
| 1123 | * function on AGP platform. |
| 1124 | */ |
Alex Deucher | 0ef0c1f | 2010-11-22 17:56:26 -0500 | [diff] [blame] | 1125 | static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1126 | { |
| 1127 | u64 size_bf, size_af; |
| 1128 | |
| 1129 | if (mc->mc_vram_size > 0xE0000000) { |
| 1130 | /* leave room for at least 512M GTT */ |
| 1131 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1132 | mc->real_vram_size = 0xE0000000; |
| 1133 | mc->mc_vram_size = 0xE0000000; |
| 1134 | } |
| 1135 | if (rdev->flags & RADEON_IS_AGP) { |
| 1136 | size_bf = mc->gtt_start; |
| 1137 | size_af = 0xFFFFFFFF - mc->gtt_end + 1; |
| 1138 | if (size_bf > size_af) { |
| 1139 | if (mc->mc_vram_size > size_bf) { |
| 1140 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1141 | mc->real_vram_size = size_bf; |
| 1142 | mc->mc_vram_size = size_bf; |
| 1143 | } |
| 1144 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; |
| 1145 | } else { |
| 1146 | if (mc->mc_vram_size > size_af) { |
| 1147 | dev_warn(rdev->dev, "limiting VRAM\n"); |
| 1148 | mc->real_vram_size = size_af; |
| 1149 | mc->mc_vram_size = size_af; |
| 1150 | } |
| 1151 | mc->vram_start = mc->gtt_end; |
| 1152 | } |
| 1153 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
| 1154 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", |
| 1155 | mc->mc_vram_size >> 20, mc->vram_start, |
| 1156 | mc->vram_end, mc->real_vram_size >> 20); |
| 1157 | } else { |
| 1158 | u64 base = 0; |
Alex Deucher | 8961d52 | 2010-12-03 14:37:22 -0500 | [diff] [blame] | 1159 | if (rdev->flags & RADEON_IS_IGP) { |
| 1160 | base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; |
| 1161 | base <<= 24; |
| 1162 | } |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1163 | radeon_vram_location(rdev, &rdev->mc, base); |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 1164 | rdev->mc.gtt_base_align = 0; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1165 | radeon_gtt_location(rdev, mc); |
| 1166 | } |
| 1167 | } |
| 1168 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1169 | int r600_mc_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1170 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1171 | u32 tmp; |
Alex Deucher | 5885b7a | 2009-10-19 17:23:33 -0400 | [diff] [blame] | 1172 | int chansize, numchan; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1173 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1174 | /* Get VRAM informations */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1175 | rdev->mc.vram_is_ddr = true; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1176 | tmp = RREG32(RAMCFG); |
| 1177 | if (tmp & CHANSIZE_OVERRIDE) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1178 | chansize = 16; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1179 | } else if (tmp & CHANSIZE_MASK) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1180 | chansize = 64; |
| 1181 | } else { |
| 1182 | chansize = 32; |
| 1183 | } |
Alex Deucher | 5885b7a | 2009-10-19 17:23:33 -0400 | [diff] [blame] | 1184 | tmp = RREG32(CHMAP); |
| 1185 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
| 1186 | case 0: |
| 1187 | default: |
| 1188 | numchan = 1; |
| 1189 | break; |
| 1190 | case 1: |
| 1191 | numchan = 2; |
| 1192 | break; |
| 1193 | case 2: |
| 1194 | numchan = 4; |
| 1195 | break; |
| 1196 | case 3: |
| 1197 | numchan = 8; |
| 1198 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1199 | } |
Alex Deucher | 5885b7a | 2009-10-19 17:23:33 -0400 | [diff] [blame] | 1200 | rdev->mc.vram_width = numchan * chansize; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1201 | /* Could aper size report 0 ? */ |
Jordan Crouse | 01d73a6 | 2010-05-27 13:40:24 -0600 | [diff] [blame] | 1202 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
| 1203 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1204 | /* Setup GPU memory space */ |
| 1205 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
| 1206 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
Jerome Glisse | 51e5fcd | 2010-02-19 14:33:54 +0000 | [diff] [blame] | 1207 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1208 | r600_vram_gtt_location(rdev, &rdev->mc); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1209 | |
Alex Deucher | f892034 | 2010-06-30 12:02:03 -0400 | [diff] [blame] | 1210 | if (rdev->flags & RADEON_IS_IGP) { |
| 1211 | rs690_pm_info(rdev); |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 1212 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
Alex Deucher | f892034 | 2010-06-30 12:02:03 -0400 | [diff] [blame] | 1213 | } |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1214 | radeon_update_bandwidth_info(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1215 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1216 | } |
| 1217 | |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1218 | int r600_vram_scratch_init(struct radeon_device *rdev) |
| 1219 | { |
| 1220 | int r; |
| 1221 | |
| 1222 | if (rdev->vram_scratch.robj == NULL) { |
| 1223 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, |
| 1224 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
| 1225 | &rdev->vram_scratch.robj); |
| 1226 | if (r) { |
| 1227 | return r; |
| 1228 | } |
| 1229 | } |
| 1230 | |
| 1231 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); |
| 1232 | if (unlikely(r != 0)) |
| 1233 | return r; |
| 1234 | r = radeon_bo_pin(rdev->vram_scratch.robj, |
| 1235 | RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); |
| 1236 | if (r) { |
| 1237 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
| 1238 | return r; |
| 1239 | } |
| 1240 | r = radeon_bo_kmap(rdev->vram_scratch.robj, |
| 1241 | (void **)&rdev->vram_scratch.ptr); |
| 1242 | if (r) |
| 1243 | radeon_bo_unpin(rdev->vram_scratch.robj); |
| 1244 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
| 1245 | |
| 1246 | return r; |
| 1247 | } |
| 1248 | |
| 1249 | void r600_vram_scratch_fini(struct radeon_device *rdev) |
| 1250 | { |
| 1251 | int r; |
| 1252 | |
| 1253 | if (rdev->vram_scratch.robj == NULL) { |
| 1254 | return; |
| 1255 | } |
| 1256 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); |
| 1257 | if (likely(r == 0)) { |
| 1258 | radeon_bo_kunmap(rdev->vram_scratch.robj); |
| 1259 | radeon_bo_unpin(rdev->vram_scratch.robj); |
| 1260 | radeon_bo_unreserve(rdev->vram_scratch.robj); |
| 1261 | } |
| 1262 | radeon_bo_unref(&rdev->vram_scratch.robj); |
| 1263 | } |
| 1264 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1265 | /* We doesn't check that the GPU really needs a reset we simply do the |
| 1266 | * reset, it's up to the caller to determine if the GPU needs one. We |
| 1267 | * might add an helper function to check that. |
| 1268 | */ |
| 1269 | int r600_gpu_soft_reset(struct radeon_device *rdev) |
| 1270 | { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1271 | struct rv515_mc_save save; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1272 | u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | |
| 1273 | S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | |
| 1274 | S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | |
| 1275 | S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | |
| 1276 | S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | |
| 1277 | S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | |
| 1278 | S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | |
| 1279 | S_008010_GUI_ACTIVE(1); |
| 1280 | u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | |
| 1281 | S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | |
| 1282 | S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | |
| 1283 | S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | |
| 1284 | S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | |
| 1285 | S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | |
| 1286 | S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | |
| 1287 | S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1288 | u32 tmp; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1289 | |
Alex Deucher | 8d96fe9 | 2011-01-21 15:38:22 +0000 | [diff] [blame] | 1290 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) |
| 1291 | return 0; |
| 1292 | |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1293 | dev_info(rdev->dev, "GPU softreset \n"); |
| 1294 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", |
| 1295 | RREG32(R_008010_GRBM_STATUS)); |
| 1296 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1297 | RREG32(R_008014_GRBM_STATUS2)); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1298 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
| 1299 | RREG32(R_000E50_SRBM_STATUS)); |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1300 | rv515_mc_stop(rdev, &save); |
| 1301 | if (r600_mc_wait_for_idle(rdev)) { |
| 1302 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
| 1303 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1304 | /* Disable CP parsing/prefetching */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1305 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1306 | /* Check if any of the rendering block is busy and reset it */ |
| 1307 | if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || |
| 1308 | (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1309 | tmp = S_008020_SOFT_RESET_CR(1) | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1310 | S_008020_SOFT_RESET_DB(1) | |
| 1311 | S_008020_SOFT_RESET_CB(1) | |
| 1312 | S_008020_SOFT_RESET_PA(1) | |
| 1313 | S_008020_SOFT_RESET_SC(1) | |
| 1314 | S_008020_SOFT_RESET_SMX(1) | |
| 1315 | S_008020_SOFT_RESET_SPI(1) | |
| 1316 | S_008020_SOFT_RESET_SX(1) | |
| 1317 | S_008020_SOFT_RESET_SH(1) | |
| 1318 | S_008020_SOFT_RESET_TC(1) | |
| 1319 | S_008020_SOFT_RESET_TA(1) | |
| 1320 | S_008020_SOFT_RESET_VC(1) | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1321 | S_008020_SOFT_RESET_VGT(1); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1322 | dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1323 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1324 | RREG32(R_008020_GRBM_SOFT_RESET); |
| 1325 | mdelay(15); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1326 | WREG32(R_008020_GRBM_SOFT_RESET, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1327 | } |
| 1328 | /* Reset CP (we always reset CP) */ |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1329 | tmp = S_008020_SOFT_RESET_CP(1); |
| 1330 | dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); |
| 1331 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1332 | RREG32(R_008020_GRBM_SOFT_RESET); |
| 1333 | mdelay(15); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1334 | WREG32(R_008020_GRBM_SOFT_RESET, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1335 | /* Wait a little for things to settle down */ |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1336 | mdelay(1); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 1337 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", |
| 1338 | RREG32(R_008010_GRBM_STATUS)); |
| 1339 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", |
| 1340 | RREG32(R_008014_GRBM_STATUS2)); |
| 1341 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
| 1342 | RREG32(R_000E50_SRBM_STATUS)); |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 1343 | rv515_mc_resume(rdev, &save); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1344 | return 0; |
| 1345 | } |
| 1346 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1347 | bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1348 | { |
| 1349 | u32 srbm_status; |
| 1350 | u32 grbm_status; |
| 1351 | u32 grbm_status2; |
Alex Deucher | e29ff72 | 2010-12-21 16:05:38 -0500 | [diff] [blame] | 1352 | struct r100_gpu_lockup *lockup; |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1353 | int r; |
| 1354 | |
Alex Deucher | e29ff72 | 2010-12-21 16:05:38 -0500 | [diff] [blame] | 1355 | if (rdev->family >= CHIP_RV770) |
| 1356 | lockup = &rdev->config.rv770.lockup; |
| 1357 | else |
| 1358 | lockup = &rdev->config.r600.lockup; |
| 1359 | |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1360 | srbm_status = RREG32(R_000E50_SRBM_STATUS); |
| 1361 | grbm_status = RREG32(R_008010_GRBM_STATUS); |
| 1362 | grbm_status2 = RREG32(R_008014_GRBM_STATUS2); |
| 1363 | if (!G_008010_GUI_ACTIVE(grbm_status)) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1364 | r100_gpu_lockup_update(lockup, ring); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1365 | return false; |
| 1366 | } |
| 1367 | /* force CP activities */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1368 | r = radeon_ring_lock(rdev, ring, 2); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1369 | if (!r) { |
| 1370 | /* PACKET2 NOP */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1371 | radeon_ring_write(ring, 0x80000000); |
| 1372 | radeon_ring_write(ring, 0x80000000); |
| 1373 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1374 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1375 | ring->rptr = RREG32(ring->rptr_reg); |
| 1376 | return r100_gpu_cp_is_lockup(rdev, lockup, ring); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1377 | } |
| 1378 | |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1379 | int r600_asic_reset(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1380 | { |
| 1381 | return r600_gpu_soft_reset(rdev); |
| 1382 | } |
| 1383 | |
| 1384 | static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, |
| 1385 | u32 num_backends, |
| 1386 | u32 backend_disable_mask) |
| 1387 | { |
| 1388 | u32 backend_map = 0; |
| 1389 | u32 enabled_backends_mask; |
| 1390 | u32 enabled_backends_count; |
| 1391 | u32 cur_pipe; |
| 1392 | u32 swizzle_pipe[R6XX_MAX_PIPES]; |
| 1393 | u32 cur_backend; |
| 1394 | u32 i; |
| 1395 | |
| 1396 | if (num_tile_pipes > R6XX_MAX_PIPES) |
| 1397 | num_tile_pipes = R6XX_MAX_PIPES; |
| 1398 | if (num_tile_pipes < 1) |
| 1399 | num_tile_pipes = 1; |
| 1400 | if (num_backends > R6XX_MAX_BACKENDS) |
| 1401 | num_backends = R6XX_MAX_BACKENDS; |
| 1402 | if (num_backends < 1) |
| 1403 | num_backends = 1; |
| 1404 | |
| 1405 | enabled_backends_mask = 0; |
| 1406 | enabled_backends_count = 0; |
| 1407 | for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { |
| 1408 | if (((backend_disable_mask >> i) & 1) == 0) { |
| 1409 | enabled_backends_mask |= (1 << i); |
| 1410 | ++enabled_backends_count; |
| 1411 | } |
| 1412 | if (enabled_backends_count == num_backends) |
| 1413 | break; |
| 1414 | } |
| 1415 | |
| 1416 | if (enabled_backends_count == 0) { |
| 1417 | enabled_backends_mask = 1; |
| 1418 | enabled_backends_count = 1; |
| 1419 | } |
| 1420 | |
| 1421 | if (enabled_backends_count != num_backends) |
| 1422 | num_backends = enabled_backends_count; |
| 1423 | |
| 1424 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); |
| 1425 | switch (num_tile_pipes) { |
| 1426 | case 1: |
| 1427 | swizzle_pipe[0] = 0; |
| 1428 | break; |
| 1429 | case 2: |
| 1430 | swizzle_pipe[0] = 0; |
| 1431 | swizzle_pipe[1] = 1; |
| 1432 | break; |
| 1433 | case 3: |
| 1434 | swizzle_pipe[0] = 0; |
| 1435 | swizzle_pipe[1] = 1; |
| 1436 | swizzle_pipe[2] = 2; |
| 1437 | break; |
| 1438 | case 4: |
| 1439 | swizzle_pipe[0] = 0; |
| 1440 | swizzle_pipe[1] = 1; |
| 1441 | swizzle_pipe[2] = 2; |
| 1442 | swizzle_pipe[3] = 3; |
| 1443 | break; |
| 1444 | case 5: |
| 1445 | swizzle_pipe[0] = 0; |
| 1446 | swizzle_pipe[1] = 1; |
| 1447 | swizzle_pipe[2] = 2; |
| 1448 | swizzle_pipe[3] = 3; |
| 1449 | swizzle_pipe[4] = 4; |
| 1450 | break; |
| 1451 | case 6: |
| 1452 | swizzle_pipe[0] = 0; |
| 1453 | swizzle_pipe[1] = 2; |
| 1454 | swizzle_pipe[2] = 4; |
| 1455 | swizzle_pipe[3] = 5; |
| 1456 | swizzle_pipe[4] = 1; |
| 1457 | swizzle_pipe[5] = 3; |
| 1458 | break; |
| 1459 | case 7: |
| 1460 | swizzle_pipe[0] = 0; |
| 1461 | swizzle_pipe[1] = 2; |
| 1462 | swizzle_pipe[2] = 4; |
| 1463 | swizzle_pipe[3] = 6; |
| 1464 | swizzle_pipe[4] = 1; |
| 1465 | swizzle_pipe[5] = 3; |
| 1466 | swizzle_pipe[6] = 5; |
| 1467 | break; |
| 1468 | case 8: |
| 1469 | swizzle_pipe[0] = 0; |
| 1470 | swizzle_pipe[1] = 2; |
| 1471 | swizzle_pipe[2] = 4; |
| 1472 | swizzle_pipe[3] = 6; |
| 1473 | swizzle_pipe[4] = 1; |
| 1474 | swizzle_pipe[5] = 3; |
| 1475 | swizzle_pipe[6] = 5; |
| 1476 | swizzle_pipe[7] = 7; |
| 1477 | break; |
| 1478 | } |
| 1479 | |
| 1480 | cur_backend = 0; |
| 1481 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { |
| 1482 | while (((1 << cur_backend) & enabled_backends_mask) == 0) |
| 1483 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; |
| 1484 | |
| 1485 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); |
| 1486 | |
| 1487 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; |
| 1488 | } |
| 1489 | |
| 1490 | return backend_map; |
| 1491 | } |
| 1492 | |
| 1493 | int r600_count_pipe_bits(uint32_t val) |
| 1494 | { |
| 1495 | int i, ret = 0; |
| 1496 | |
| 1497 | for (i = 0; i < 32; i++) { |
| 1498 | ret += val & 1; |
| 1499 | val >>= 1; |
| 1500 | } |
| 1501 | return ret; |
| 1502 | } |
| 1503 | |
| 1504 | void r600_gpu_init(struct radeon_device *rdev) |
| 1505 | { |
| 1506 | u32 tiling_config; |
| 1507 | u32 ramcfg; |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1508 | u32 backend_map; |
| 1509 | u32 cc_rb_backend_disable; |
| 1510 | u32 cc_gc_shader_pipe_config; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1511 | u32 tmp; |
| 1512 | int i, j; |
| 1513 | u32 sq_config; |
| 1514 | u32 sq_gpr_resource_mgmt_1 = 0; |
| 1515 | u32 sq_gpr_resource_mgmt_2 = 0; |
| 1516 | u32 sq_thread_resource_mgmt = 0; |
| 1517 | u32 sq_stack_resource_mgmt_1 = 0; |
| 1518 | u32 sq_stack_resource_mgmt_2 = 0; |
| 1519 | |
| 1520 | /* FIXME: implement */ |
| 1521 | switch (rdev->family) { |
| 1522 | case CHIP_R600: |
| 1523 | rdev->config.r600.max_pipes = 4; |
| 1524 | rdev->config.r600.max_tile_pipes = 8; |
| 1525 | rdev->config.r600.max_simds = 4; |
| 1526 | rdev->config.r600.max_backends = 4; |
| 1527 | rdev->config.r600.max_gprs = 256; |
| 1528 | rdev->config.r600.max_threads = 192; |
| 1529 | rdev->config.r600.max_stack_entries = 256; |
| 1530 | rdev->config.r600.max_hw_contexts = 8; |
| 1531 | rdev->config.r600.max_gs_threads = 16; |
| 1532 | rdev->config.r600.sx_max_export_size = 128; |
| 1533 | rdev->config.r600.sx_max_export_pos_size = 16; |
| 1534 | rdev->config.r600.sx_max_export_smx_size = 128; |
| 1535 | rdev->config.r600.sq_num_cf_insts = 2; |
| 1536 | break; |
| 1537 | case CHIP_RV630: |
| 1538 | case CHIP_RV635: |
| 1539 | rdev->config.r600.max_pipes = 2; |
| 1540 | rdev->config.r600.max_tile_pipes = 2; |
| 1541 | rdev->config.r600.max_simds = 3; |
| 1542 | rdev->config.r600.max_backends = 1; |
| 1543 | rdev->config.r600.max_gprs = 128; |
| 1544 | rdev->config.r600.max_threads = 192; |
| 1545 | rdev->config.r600.max_stack_entries = 128; |
| 1546 | rdev->config.r600.max_hw_contexts = 8; |
| 1547 | rdev->config.r600.max_gs_threads = 4; |
| 1548 | rdev->config.r600.sx_max_export_size = 128; |
| 1549 | rdev->config.r600.sx_max_export_pos_size = 16; |
| 1550 | rdev->config.r600.sx_max_export_smx_size = 128; |
| 1551 | rdev->config.r600.sq_num_cf_insts = 2; |
| 1552 | break; |
| 1553 | case CHIP_RV610: |
| 1554 | case CHIP_RV620: |
| 1555 | case CHIP_RS780: |
| 1556 | case CHIP_RS880: |
| 1557 | rdev->config.r600.max_pipes = 1; |
| 1558 | rdev->config.r600.max_tile_pipes = 1; |
| 1559 | rdev->config.r600.max_simds = 2; |
| 1560 | rdev->config.r600.max_backends = 1; |
| 1561 | rdev->config.r600.max_gprs = 128; |
| 1562 | rdev->config.r600.max_threads = 192; |
| 1563 | rdev->config.r600.max_stack_entries = 128; |
| 1564 | rdev->config.r600.max_hw_contexts = 4; |
| 1565 | rdev->config.r600.max_gs_threads = 4; |
| 1566 | rdev->config.r600.sx_max_export_size = 128; |
| 1567 | rdev->config.r600.sx_max_export_pos_size = 16; |
| 1568 | rdev->config.r600.sx_max_export_smx_size = 128; |
| 1569 | rdev->config.r600.sq_num_cf_insts = 1; |
| 1570 | break; |
| 1571 | case CHIP_RV670: |
| 1572 | rdev->config.r600.max_pipes = 4; |
| 1573 | rdev->config.r600.max_tile_pipes = 4; |
| 1574 | rdev->config.r600.max_simds = 4; |
| 1575 | rdev->config.r600.max_backends = 4; |
| 1576 | rdev->config.r600.max_gprs = 192; |
| 1577 | rdev->config.r600.max_threads = 192; |
| 1578 | rdev->config.r600.max_stack_entries = 256; |
| 1579 | rdev->config.r600.max_hw_contexts = 8; |
| 1580 | rdev->config.r600.max_gs_threads = 16; |
| 1581 | rdev->config.r600.sx_max_export_size = 128; |
| 1582 | rdev->config.r600.sx_max_export_pos_size = 16; |
| 1583 | rdev->config.r600.sx_max_export_smx_size = 128; |
| 1584 | rdev->config.r600.sq_num_cf_insts = 2; |
| 1585 | break; |
| 1586 | default: |
| 1587 | break; |
| 1588 | } |
| 1589 | |
| 1590 | /* Initialize HDP */ |
| 1591 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
| 1592 | WREG32((0x2c14 + j), 0x00000000); |
| 1593 | WREG32((0x2c18 + j), 0x00000000); |
| 1594 | WREG32((0x2c1c + j), 0x00000000); |
| 1595 | WREG32((0x2c20 + j), 0x00000000); |
| 1596 | WREG32((0x2c24 + j), 0x00000000); |
| 1597 | } |
| 1598 | |
| 1599 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
| 1600 | |
| 1601 | /* Setup tiling */ |
| 1602 | tiling_config = 0; |
| 1603 | ramcfg = RREG32(RAMCFG); |
| 1604 | switch (rdev->config.r600.max_tile_pipes) { |
| 1605 | case 1: |
| 1606 | tiling_config |= PIPE_TILING(0); |
| 1607 | break; |
| 1608 | case 2: |
| 1609 | tiling_config |= PIPE_TILING(1); |
| 1610 | break; |
| 1611 | case 4: |
| 1612 | tiling_config |= PIPE_TILING(2); |
| 1613 | break; |
| 1614 | case 8: |
| 1615 | tiling_config |= PIPE_TILING(3); |
| 1616 | break; |
| 1617 | default: |
| 1618 | break; |
| 1619 | } |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1620 | rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; |
Jerome Glisse | 961fb59 | 2010-02-10 22:30:05 +0000 | [diff] [blame] | 1621 | rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1622 | tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
Alex Deucher | 881fe6c | 2010-10-18 23:54:56 -0400 | [diff] [blame] | 1623 | tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
| 1624 | if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) |
| 1625 | rdev->config.r600.tiling_group_size = 512; |
| 1626 | else |
| 1627 | rdev->config.r600.tiling_group_size = 256; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1628 | tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
| 1629 | if (tmp > 3) { |
| 1630 | tiling_config |= ROW_TILING(3); |
| 1631 | tiling_config |= SAMPLE_SPLIT(3); |
| 1632 | } else { |
| 1633 | tiling_config |= ROW_TILING(tmp); |
| 1634 | tiling_config |= SAMPLE_SPLIT(tmp); |
| 1635 | } |
| 1636 | tiling_config |= BANK_SWAPS(1); |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1637 | |
| 1638 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; |
| 1639 | cc_rb_backend_disable |= |
| 1640 | BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); |
| 1641 | |
| 1642 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; |
| 1643 | cc_gc_shader_pipe_config |= |
| 1644 | INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); |
| 1645 | cc_gc_shader_pipe_config |= |
| 1646 | INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); |
| 1647 | |
| 1648 | backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, |
| 1649 | (R6XX_MAX_BACKENDS - |
| 1650 | r600_count_pipe_bits((cc_rb_backend_disable & |
| 1651 | R6XX_MAX_BACKENDS_MASK) >> 16)), |
| 1652 | (cc_rb_backend_disable >> 16)); |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1653 | rdev->config.r600.tile_config = tiling_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1654 | rdev->config.r600.backend_map = backend_map; |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1655 | tiling_config |= BACKEND_MAP(backend_map); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1656 | WREG32(GB_TILING_CONFIG, tiling_config); |
| 1657 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); |
| 1658 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); |
| 1659 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1660 | /* Setup pipes */ |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1661 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
| 1662 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
Alex Deucher | f867c60d | 2010-03-05 14:50:37 -0500 | [diff] [blame] | 1663 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1664 | |
Alex Deucher | d03f5d5 | 2010-02-19 16:22:31 -0500 | [diff] [blame] | 1665 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1666 | WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); |
| 1667 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
| 1668 | |
| 1669 | /* Setup some CP states */ |
| 1670 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); |
| 1671 | WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); |
| 1672 | |
| 1673 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | |
| 1674 | SYNC_WALKER | SYNC_ALIGNER)); |
| 1675 | /* Setup various GPU states */ |
| 1676 | if (rdev->family == CHIP_RV670) |
| 1677 | WREG32(ARB_GDEC_RD_CNTL, 0x00000021); |
| 1678 | |
| 1679 | tmp = RREG32(SX_DEBUG_1); |
| 1680 | tmp |= SMX_EVENT_RELEASE; |
| 1681 | if ((rdev->family > CHIP_R600)) |
| 1682 | tmp |= ENABLE_NEW_SMX_ADDRESS; |
| 1683 | WREG32(SX_DEBUG_1, tmp); |
| 1684 | |
| 1685 | if (((rdev->family) == CHIP_R600) || |
| 1686 | ((rdev->family) == CHIP_RV630) || |
| 1687 | ((rdev->family) == CHIP_RV610) || |
| 1688 | ((rdev->family) == CHIP_RV620) || |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1689 | ((rdev->family) == CHIP_RS780) || |
| 1690 | ((rdev->family) == CHIP_RS880)) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1691 | WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); |
| 1692 | } else { |
| 1693 | WREG32(DB_DEBUG, 0); |
| 1694 | } |
| 1695 | WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | |
| 1696 | DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); |
| 1697 | |
| 1698 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
| 1699 | WREG32(VGT_NUM_INSTANCES, 0); |
| 1700 | |
| 1701 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); |
| 1702 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); |
| 1703 | |
| 1704 | tmp = RREG32(SQ_MS_FIFO_SIZES); |
| 1705 | if (((rdev->family) == CHIP_RV610) || |
| 1706 | ((rdev->family) == CHIP_RV620) || |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1707 | ((rdev->family) == CHIP_RS780) || |
| 1708 | ((rdev->family) == CHIP_RS880)) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1709 | tmp = (CACHE_FIFO_SIZE(0xa) | |
| 1710 | FETCH_FIFO_HIWATER(0xa) | |
| 1711 | DONE_FIFO_HIWATER(0xe0) | |
| 1712 | ALU_UPDATE_FIFO_HIWATER(0x8)); |
| 1713 | } else if (((rdev->family) == CHIP_R600) || |
| 1714 | ((rdev->family) == CHIP_RV630)) { |
| 1715 | tmp &= ~DONE_FIFO_HIWATER(0xff); |
| 1716 | tmp |= DONE_FIFO_HIWATER(0x4); |
| 1717 | } |
| 1718 | WREG32(SQ_MS_FIFO_SIZES, tmp); |
| 1719 | |
| 1720 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT |
| 1721 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values |
| 1722 | */ |
| 1723 | sq_config = RREG32(SQ_CONFIG); |
| 1724 | sq_config &= ~(PS_PRIO(3) | |
| 1725 | VS_PRIO(3) | |
| 1726 | GS_PRIO(3) | |
| 1727 | ES_PRIO(3)); |
| 1728 | sq_config |= (DX9_CONSTS | |
| 1729 | VC_ENABLE | |
| 1730 | PS_PRIO(0) | |
| 1731 | VS_PRIO(1) | |
| 1732 | GS_PRIO(2) | |
| 1733 | ES_PRIO(3)); |
| 1734 | |
| 1735 | if ((rdev->family) == CHIP_R600) { |
| 1736 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | |
| 1737 | NUM_VS_GPRS(124) | |
| 1738 | NUM_CLAUSE_TEMP_GPRS(4)); |
| 1739 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | |
| 1740 | NUM_ES_GPRS(0)); |
| 1741 | sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | |
| 1742 | NUM_VS_THREADS(48) | |
| 1743 | NUM_GS_THREADS(4) | |
| 1744 | NUM_ES_THREADS(4)); |
| 1745 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | |
| 1746 | NUM_VS_STACK_ENTRIES(128)); |
| 1747 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | |
| 1748 | NUM_ES_STACK_ENTRIES(0)); |
| 1749 | } else if (((rdev->family) == CHIP_RV610) || |
| 1750 | ((rdev->family) == CHIP_RV620) || |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1751 | ((rdev->family) == CHIP_RS780) || |
| 1752 | ((rdev->family) == CHIP_RS880)) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1753 | /* no vertex cache */ |
| 1754 | sq_config &= ~VC_ENABLE; |
| 1755 | |
| 1756 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | |
| 1757 | NUM_VS_GPRS(44) | |
| 1758 | NUM_CLAUSE_TEMP_GPRS(2)); |
| 1759 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | |
| 1760 | NUM_ES_GPRS(17)); |
| 1761 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | |
| 1762 | NUM_VS_THREADS(78) | |
| 1763 | NUM_GS_THREADS(4) | |
| 1764 | NUM_ES_THREADS(31)); |
| 1765 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | |
| 1766 | NUM_VS_STACK_ENTRIES(40)); |
| 1767 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | |
| 1768 | NUM_ES_STACK_ENTRIES(16)); |
| 1769 | } else if (((rdev->family) == CHIP_RV630) || |
| 1770 | ((rdev->family) == CHIP_RV635)) { |
| 1771 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | |
| 1772 | NUM_VS_GPRS(44) | |
| 1773 | NUM_CLAUSE_TEMP_GPRS(2)); |
| 1774 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | |
| 1775 | NUM_ES_GPRS(18)); |
| 1776 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | |
| 1777 | NUM_VS_THREADS(78) | |
| 1778 | NUM_GS_THREADS(4) | |
| 1779 | NUM_ES_THREADS(31)); |
| 1780 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | |
| 1781 | NUM_VS_STACK_ENTRIES(40)); |
| 1782 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | |
| 1783 | NUM_ES_STACK_ENTRIES(16)); |
| 1784 | } else if ((rdev->family) == CHIP_RV670) { |
| 1785 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | |
| 1786 | NUM_VS_GPRS(44) | |
| 1787 | NUM_CLAUSE_TEMP_GPRS(2)); |
| 1788 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | |
| 1789 | NUM_ES_GPRS(17)); |
| 1790 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | |
| 1791 | NUM_VS_THREADS(78) | |
| 1792 | NUM_GS_THREADS(4) | |
| 1793 | NUM_ES_THREADS(31)); |
| 1794 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | |
| 1795 | NUM_VS_STACK_ENTRIES(64)); |
| 1796 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | |
| 1797 | NUM_ES_STACK_ENTRIES(64)); |
| 1798 | } |
| 1799 | |
| 1800 | WREG32(SQ_CONFIG, sq_config); |
| 1801 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); |
| 1802 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); |
| 1803 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); |
| 1804 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); |
| 1805 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); |
| 1806 | |
| 1807 | if (((rdev->family) == CHIP_RV610) || |
| 1808 | ((rdev->family) == CHIP_RV620) || |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1809 | ((rdev->family) == CHIP_RS780) || |
| 1810 | ((rdev->family) == CHIP_RS880)) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1811 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); |
| 1812 | } else { |
| 1813 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); |
| 1814 | } |
| 1815 | |
| 1816 | /* More default values. 2D/3D driver should adjust as needed */ |
| 1817 | WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | |
| 1818 | S1_X(0x4) | S1_Y(0xc))); |
| 1819 | WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | |
| 1820 | S1_X(0x2) | S1_Y(0x2) | |
| 1821 | S2_X(0xa) | S2_Y(0x6) | |
| 1822 | S3_X(0x6) | S3_Y(0xa))); |
| 1823 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | |
| 1824 | S1_X(0x4) | S1_Y(0xc) | |
| 1825 | S2_X(0x1) | S2_Y(0x6) | |
| 1826 | S3_X(0xa) | S3_Y(0xe))); |
| 1827 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | |
| 1828 | S5_X(0x0) | S5_Y(0x0) | |
| 1829 | S6_X(0xb) | S6_Y(0x4) | |
| 1830 | S7_X(0x7) | S7_Y(0x8))); |
| 1831 | |
| 1832 | WREG32(VGT_STRMOUT_EN, 0); |
| 1833 | tmp = rdev->config.r600.max_pipes * 16; |
| 1834 | switch (rdev->family) { |
| 1835 | case CHIP_RV610: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1836 | case CHIP_RV620: |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1837 | case CHIP_RS780: |
| 1838 | case CHIP_RS880: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1839 | tmp += 32; |
| 1840 | break; |
| 1841 | case CHIP_RV670: |
| 1842 | tmp += 128; |
| 1843 | break; |
| 1844 | default: |
| 1845 | break; |
| 1846 | } |
| 1847 | if (tmp > 256) { |
| 1848 | tmp = 256; |
| 1849 | } |
| 1850 | WREG32(VGT_ES_PER_GS, 128); |
| 1851 | WREG32(VGT_GS_PER_ES, tmp); |
| 1852 | WREG32(VGT_GS_PER_VS, 2); |
| 1853 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
| 1854 | |
| 1855 | /* more default values. 2D/3D driver should adjust as needed */ |
| 1856 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
| 1857 | WREG32(VGT_STRMOUT_EN, 0); |
| 1858 | WREG32(SX_MISC, 0); |
| 1859 | WREG32(PA_SC_MODE_CNTL, 0); |
| 1860 | WREG32(PA_SC_AA_CONFIG, 0); |
| 1861 | WREG32(PA_SC_LINE_STIPPLE, 0); |
| 1862 | WREG32(SPI_INPUT_Z, 0); |
| 1863 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); |
| 1864 | WREG32(CB_COLOR7_FRAG, 0); |
| 1865 | |
| 1866 | /* Clear render buffer base addresses */ |
| 1867 | WREG32(CB_COLOR0_BASE, 0); |
| 1868 | WREG32(CB_COLOR1_BASE, 0); |
| 1869 | WREG32(CB_COLOR2_BASE, 0); |
| 1870 | WREG32(CB_COLOR3_BASE, 0); |
| 1871 | WREG32(CB_COLOR4_BASE, 0); |
| 1872 | WREG32(CB_COLOR5_BASE, 0); |
| 1873 | WREG32(CB_COLOR6_BASE, 0); |
| 1874 | WREG32(CB_COLOR7_BASE, 0); |
| 1875 | WREG32(CB_COLOR7_FRAG, 0); |
| 1876 | |
| 1877 | switch (rdev->family) { |
| 1878 | case CHIP_RV610: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1879 | case CHIP_RV620: |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 1880 | case CHIP_RS780: |
| 1881 | case CHIP_RS880: |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1882 | tmp = TC_L2_SIZE(8); |
| 1883 | break; |
| 1884 | case CHIP_RV630: |
| 1885 | case CHIP_RV635: |
| 1886 | tmp = TC_L2_SIZE(4); |
| 1887 | break; |
| 1888 | case CHIP_R600: |
| 1889 | tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; |
| 1890 | break; |
| 1891 | default: |
| 1892 | tmp = TC_L2_SIZE(0); |
| 1893 | break; |
| 1894 | } |
| 1895 | WREG32(TC_CNTL, tmp); |
| 1896 | |
| 1897 | tmp = RREG32(HDP_HOST_PATH_CNTL); |
| 1898 | WREG32(HDP_HOST_PATH_CNTL, tmp); |
| 1899 | |
| 1900 | tmp = RREG32(ARB_POP); |
| 1901 | tmp |= ENABLE_TC128; |
| 1902 | WREG32(ARB_POP, tmp); |
| 1903 | |
| 1904 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
| 1905 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
| 1906 | NUM_CLIP_SEQ(3))); |
| 1907 | WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); |
| 1908 | } |
| 1909 | |
| 1910 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1911 | /* |
| 1912 | * Indirect registers accessor |
| 1913 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1914 | u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1915 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1916 | u32 r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1917 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1918 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); |
| 1919 | (void)RREG32(PCIE_PORT_INDEX); |
| 1920 | r = RREG32(PCIE_PORT_DATA); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1921 | return r; |
| 1922 | } |
| 1923 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1924 | void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1925 | { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1926 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); |
| 1927 | (void)RREG32(PCIE_PORT_INDEX); |
| 1928 | WREG32(PCIE_PORT_DATA, (v)); |
| 1929 | (void)RREG32(PCIE_PORT_DATA); |
| 1930 | } |
| 1931 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1932 | /* |
| 1933 | * CP & Ring |
| 1934 | */ |
| 1935 | void r600_cp_stop(struct radeon_device *rdev) |
| 1936 | { |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 1937 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1938 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1939 | WREG32(SCRATCH_UMSK, 0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1940 | } |
| 1941 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1942 | int r600_init_microcode(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1943 | { |
| 1944 | struct platform_device *pdev; |
| 1945 | const char *chip_name; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1946 | const char *rlc_chip_name; |
| 1947 | size_t pfp_req_size, me_req_size, rlc_req_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1948 | char fw_name[30]; |
| 1949 | int err; |
| 1950 | |
| 1951 | DRM_DEBUG("\n"); |
| 1952 | |
| 1953 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
| 1954 | err = IS_ERR(pdev); |
| 1955 | if (err) { |
| 1956 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
| 1957 | return -EINVAL; |
| 1958 | } |
| 1959 | |
| 1960 | switch (rdev->family) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1961 | case CHIP_R600: |
| 1962 | chip_name = "R600"; |
| 1963 | rlc_chip_name = "R600"; |
| 1964 | break; |
| 1965 | case CHIP_RV610: |
| 1966 | chip_name = "RV610"; |
| 1967 | rlc_chip_name = "R600"; |
| 1968 | break; |
| 1969 | case CHIP_RV630: |
| 1970 | chip_name = "RV630"; |
| 1971 | rlc_chip_name = "R600"; |
| 1972 | break; |
| 1973 | case CHIP_RV620: |
| 1974 | chip_name = "RV620"; |
| 1975 | rlc_chip_name = "R600"; |
| 1976 | break; |
| 1977 | case CHIP_RV635: |
| 1978 | chip_name = "RV635"; |
| 1979 | rlc_chip_name = "R600"; |
| 1980 | break; |
| 1981 | case CHIP_RV670: |
| 1982 | chip_name = "RV670"; |
| 1983 | rlc_chip_name = "R600"; |
| 1984 | break; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1985 | case CHIP_RS780: |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1986 | case CHIP_RS880: |
| 1987 | chip_name = "RS780"; |
| 1988 | rlc_chip_name = "R600"; |
| 1989 | break; |
| 1990 | case CHIP_RV770: |
| 1991 | chip_name = "RV770"; |
| 1992 | rlc_chip_name = "R700"; |
| 1993 | break; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1994 | case CHIP_RV730: |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1995 | case CHIP_RV740: |
| 1996 | chip_name = "RV730"; |
| 1997 | rlc_chip_name = "R700"; |
| 1998 | break; |
| 1999 | case CHIP_RV710: |
| 2000 | chip_name = "RV710"; |
| 2001 | rlc_chip_name = "R700"; |
| 2002 | break; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2003 | case CHIP_CEDAR: |
| 2004 | chip_name = "CEDAR"; |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2005 | rlc_chip_name = "CEDAR"; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2006 | break; |
| 2007 | case CHIP_REDWOOD: |
| 2008 | chip_name = "REDWOOD"; |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2009 | rlc_chip_name = "REDWOOD"; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2010 | break; |
| 2011 | case CHIP_JUNIPER: |
| 2012 | chip_name = "JUNIPER"; |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2013 | rlc_chip_name = "JUNIPER"; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2014 | break; |
| 2015 | case CHIP_CYPRESS: |
| 2016 | case CHIP_HEMLOCK: |
| 2017 | chip_name = "CYPRESS"; |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2018 | rlc_chip_name = "CYPRESS"; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2019 | break; |
Alex Deucher | 439bd6c | 2010-11-22 17:56:31 -0500 | [diff] [blame] | 2020 | case CHIP_PALM: |
| 2021 | chip_name = "PALM"; |
| 2022 | rlc_chip_name = "SUMO"; |
| 2023 | break; |
Alex Deucher | d5c5a72 | 2011-05-31 15:42:48 -0400 | [diff] [blame] | 2024 | case CHIP_SUMO: |
| 2025 | chip_name = "SUMO"; |
| 2026 | rlc_chip_name = "SUMO"; |
| 2027 | break; |
| 2028 | case CHIP_SUMO2: |
| 2029 | chip_name = "SUMO2"; |
| 2030 | rlc_chip_name = "SUMO"; |
| 2031 | break; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2032 | default: BUG(); |
| 2033 | } |
| 2034 | |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2035 | if (rdev->family >= CHIP_CEDAR) { |
| 2036 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; |
| 2037 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2038 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2039 | } else if (rdev->family >= CHIP_RV770) { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2040 | pfp_req_size = R700_PFP_UCODE_SIZE * 4; |
| 2041 | me_req_size = R700_PM4_UCODE_SIZE * 4; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2042 | rlc_req_size = R700_RLC_UCODE_SIZE * 4; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2043 | } else { |
| 2044 | pfp_req_size = PFP_UCODE_SIZE * 4; |
| 2045 | me_req_size = PM4_UCODE_SIZE * 12; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2046 | rlc_req_size = RLC_UCODE_SIZE * 4; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2047 | } |
| 2048 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2049 | DRM_INFO("Loading %s Microcode\n", chip_name); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2050 | |
| 2051 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); |
| 2052 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); |
| 2053 | if (err) |
| 2054 | goto out; |
| 2055 | if (rdev->pfp_fw->size != pfp_req_size) { |
| 2056 | printk(KERN_ERR |
| 2057 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", |
| 2058 | rdev->pfp_fw->size, fw_name); |
| 2059 | err = -EINVAL; |
| 2060 | goto out; |
| 2061 | } |
| 2062 | |
| 2063 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); |
| 2064 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
| 2065 | if (err) |
| 2066 | goto out; |
| 2067 | if (rdev->me_fw->size != me_req_size) { |
| 2068 | printk(KERN_ERR |
| 2069 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", |
| 2070 | rdev->me_fw->size, fw_name); |
| 2071 | err = -EINVAL; |
| 2072 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2073 | |
| 2074 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); |
| 2075 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); |
| 2076 | if (err) |
| 2077 | goto out; |
| 2078 | if (rdev->rlc_fw->size != rlc_req_size) { |
| 2079 | printk(KERN_ERR |
| 2080 | "r600_rlc: Bogus length %zu in firmware \"%s\"\n", |
| 2081 | rdev->rlc_fw->size, fw_name); |
| 2082 | err = -EINVAL; |
| 2083 | } |
| 2084 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2085 | out: |
| 2086 | platform_device_unregister(pdev); |
| 2087 | |
| 2088 | if (err) { |
| 2089 | if (err != -EINVAL) |
| 2090 | printk(KERN_ERR |
| 2091 | "r600_cp: Failed to load firmware \"%s\"\n", |
| 2092 | fw_name); |
| 2093 | release_firmware(rdev->pfp_fw); |
| 2094 | rdev->pfp_fw = NULL; |
| 2095 | release_firmware(rdev->me_fw); |
| 2096 | rdev->me_fw = NULL; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2097 | release_firmware(rdev->rlc_fw); |
| 2098 | rdev->rlc_fw = NULL; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2099 | } |
| 2100 | return err; |
| 2101 | } |
| 2102 | |
| 2103 | static int r600_cp_load_microcode(struct radeon_device *rdev) |
| 2104 | { |
| 2105 | const __be32 *fw_data; |
| 2106 | int i; |
| 2107 | |
| 2108 | if (!rdev->me_fw || !rdev->pfp_fw) |
| 2109 | return -EINVAL; |
| 2110 | |
| 2111 | r600_cp_stop(rdev); |
| 2112 | |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 2113 | WREG32(CP_RB_CNTL, |
| 2114 | #ifdef __BIG_ENDIAN |
| 2115 | BUF_SWAP_32BIT | |
| 2116 | #endif |
| 2117 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2118 | |
| 2119 | /* Reset cp */ |
| 2120 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
| 2121 | RREG32(GRBM_SOFT_RESET); |
| 2122 | mdelay(15); |
| 2123 | WREG32(GRBM_SOFT_RESET, 0); |
| 2124 | |
| 2125 | WREG32(CP_ME_RAM_WADDR, 0); |
| 2126 | |
| 2127 | fw_data = (const __be32 *)rdev->me_fw->data; |
| 2128 | WREG32(CP_ME_RAM_WADDR, 0); |
| 2129 | for (i = 0; i < PM4_UCODE_SIZE * 3; i++) |
| 2130 | WREG32(CP_ME_RAM_DATA, |
| 2131 | be32_to_cpup(fw_data++)); |
| 2132 | |
| 2133 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
| 2134 | WREG32(CP_PFP_UCODE_ADDR, 0); |
| 2135 | for (i = 0; i < PFP_UCODE_SIZE; i++) |
| 2136 | WREG32(CP_PFP_UCODE_DATA, |
| 2137 | be32_to_cpup(fw_data++)); |
| 2138 | |
| 2139 | WREG32(CP_PFP_UCODE_ADDR, 0); |
| 2140 | WREG32(CP_ME_RAM_WADDR, 0); |
| 2141 | WREG32(CP_ME_RAM_RADDR, 0); |
| 2142 | return 0; |
| 2143 | } |
| 2144 | |
| 2145 | int r600_cp_start(struct radeon_device *rdev) |
| 2146 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2147 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2148 | int r; |
| 2149 | uint32_t cp_me; |
| 2150 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2151 | r = radeon_ring_lock(rdev, ring, 7); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2152 | if (r) { |
| 2153 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
| 2154 | return r; |
| 2155 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2156 | radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
| 2157 | radeon_ring_write(ring, 0x1); |
Alex Deucher | 7e7b41d | 2010-09-02 21:32:32 -0400 | [diff] [blame] | 2158 | if (rdev->family >= CHIP_RV770) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2159 | radeon_ring_write(ring, 0x0); |
| 2160 | radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2161 | } else { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2162 | radeon_ring_write(ring, 0x3); |
| 2163 | radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2164 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2165 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
| 2166 | radeon_ring_write(ring, 0); |
| 2167 | radeon_ring_write(ring, 0); |
| 2168 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2169 | |
| 2170 | cp_me = 0xff; |
| 2171 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); |
| 2172 | return 0; |
| 2173 | } |
| 2174 | |
| 2175 | int r600_cp_resume(struct radeon_device *rdev) |
| 2176 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2177 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2178 | u32 tmp; |
| 2179 | u32 rb_bufsz; |
| 2180 | int r; |
| 2181 | |
| 2182 | /* Reset cp */ |
| 2183 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
| 2184 | RREG32(GRBM_SOFT_RESET); |
| 2185 | mdelay(15); |
| 2186 | WREG32(GRBM_SOFT_RESET, 0); |
| 2187 | |
| 2188 | /* Set ring buffer size */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2189 | rb_bufsz = drm_order(ring->ring_size / 8); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2190 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2191 | #ifdef __BIG_ENDIAN |
Alex Deucher | d6f2893 | 2009-11-02 16:01:27 -0500 | [diff] [blame] | 2192 | tmp |= BUF_SWAP_32BIT; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2193 | #endif |
Alex Deucher | d6f2893 | 2009-11-02 16:01:27 -0500 | [diff] [blame] | 2194 | WREG32(CP_RB_CNTL, tmp); |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 2195 | WREG32(CP_SEM_WAIT_TIMER, 0x0); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2196 | |
| 2197 | /* Set the write pointer delay */ |
| 2198 | WREG32(CP_RB_WPTR_DELAY, 0); |
| 2199 | |
| 2200 | /* Initialize the ring buffer's read and write pointers */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2201 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
| 2202 | WREG32(CP_RB_RPTR_WR, 0); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2203 | ring->wptr = 0; |
| 2204 | WREG32(CP_RB_WPTR, ring->wptr); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2205 | |
| 2206 | /* set the wb address whether it's enabled or not */ |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 2207 | WREG32(CP_RB_RPTR_ADDR, |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 2208 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2209 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
| 2210 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
| 2211 | |
| 2212 | if (rdev->wb.enabled) |
| 2213 | WREG32(SCRATCH_UMSK, 0xff); |
| 2214 | else { |
| 2215 | tmp |= RB_NO_UPDATE; |
| 2216 | WREG32(SCRATCH_UMSK, 0); |
| 2217 | } |
| 2218 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2219 | mdelay(1); |
| 2220 | WREG32(CP_RB_CNTL, tmp); |
| 2221 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2222 | WREG32(CP_RB_BASE, ring->gpu_addr >> 8); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2223 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
| 2224 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2225 | ring->rptr = RREG32(CP_RB_RPTR); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2226 | |
| 2227 | r600_cp_start(rdev); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2228 | ring->ready = true; |
| 2229 | r = radeon_ring_test(rdev, ring); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2230 | if (r) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2231 | ring->ready = false; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2232 | return r; |
| 2233 | } |
| 2234 | return 0; |
| 2235 | } |
| 2236 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2237 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2238 | { |
| 2239 | u32 rb_bufsz; |
| 2240 | |
| 2241 | /* Align ring size */ |
| 2242 | rb_bufsz = drm_order(ring_size / 8); |
| 2243 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2244 | ring->ring_size = ring_size; |
| 2245 | ring->align_mask = 16 - 1; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2246 | } |
| 2247 | |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2248 | void r600_cp_fini(struct radeon_device *rdev) |
| 2249 | { |
| 2250 | r600_cp_stop(rdev); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2251 | radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2252 | } |
| 2253 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2254 | |
| 2255 | /* |
| 2256 | * GPU scratch registers helpers function. |
| 2257 | */ |
| 2258 | void r600_scratch_init(struct radeon_device *rdev) |
| 2259 | { |
| 2260 | int i; |
| 2261 | |
| 2262 | rdev->scratch.num_reg = 7; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2263 | rdev->scratch.reg_base = SCRATCH_REG0; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2264 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
| 2265 | rdev->scratch.free[i] = true; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2266 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2267 | } |
| 2268 | } |
| 2269 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2270 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2271 | { |
| 2272 | uint32_t scratch; |
| 2273 | uint32_t tmp = 0; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2274 | unsigned i, ridx = radeon_ring_index(rdev, ring); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2275 | int r; |
| 2276 | |
| 2277 | r = radeon_scratch_get(rdev, &scratch); |
| 2278 | if (r) { |
| 2279 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); |
| 2280 | return r; |
| 2281 | } |
| 2282 | WREG32(scratch, 0xCAFEDEAD); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2283 | r = radeon_ring_lock(rdev, ring, 3); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2284 | if (r) { |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 2285 | DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ridx, r); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2286 | radeon_scratch_free(rdev, scratch); |
| 2287 | return r; |
| 2288 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2289 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 2290 | radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
| 2291 | radeon_ring_write(ring, 0xDEADBEEF); |
| 2292 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2293 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 2294 | tmp = RREG32(scratch); |
| 2295 | if (tmp == 0xDEADBEEF) |
| 2296 | break; |
| 2297 | DRM_UDELAY(1); |
| 2298 | } |
| 2299 | if (i < rdev->usec_timeout) { |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 2300 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ridx, i); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2301 | } else { |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 2302 | DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", |
| 2303 | ridx, scratch, tmp); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2304 | r = -EINVAL; |
| 2305 | } |
| 2306 | radeon_scratch_free(rdev, scratch); |
| 2307 | return r; |
| 2308 | } |
| 2309 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2310 | void r600_fence_ring_emit(struct radeon_device *rdev, |
| 2311 | struct radeon_fence *fence) |
| 2312 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2313 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 2314 | |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2315 | if (rdev->wb.use_event) { |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 2316 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
Jerome Glisse | 77b1bad | 2011-10-26 11:41:22 -0400 | [diff] [blame] | 2317 | /* flush read cache over gart */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2318 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| 2319 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | |
| 2320 | PACKET3_VC_ACTION_ENA | |
| 2321 | PACKET3_SH_ACTION_ENA); |
| 2322 | radeon_ring_write(ring, 0xFFFFFFFF); |
| 2323 | radeon_ring_write(ring, 0); |
| 2324 | radeon_ring_write(ring, 10); /* poll interval */ |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2325 | /* EVENT_WRITE_EOP - flush caches, send int */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2326 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
| 2327 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); |
| 2328 | radeon_ring_write(ring, addr & 0xffffffff); |
| 2329 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); |
| 2330 | radeon_ring_write(ring, fence->seq); |
| 2331 | radeon_ring_write(ring, 0); |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2332 | } else { |
Jerome Glisse | 77b1bad | 2011-10-26 11:41:22 -0400 | [diff] [blame] | 2333 | /* flush read cache over gart */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2334 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| 2335 | radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | |
| 2336 | PACKET3_VC_ACTION_ENA | |
| 2337 | PACKET3_SH_ACTION_ENA); |
| 2338 | radeon_ring_write(ring, 0xFFFFFFFF); |
| 2339 | radeon_ring_write(ring, 0); |
| 2340 | radeon_ring_write(ring, 10); /* poll interval */ |
| 2341 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); |
| 2342 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2343 | /* wait for 3D idle clean */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2344 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 2345 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| 2346 | radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2347 | /* Emit fence sequence & fire IRQ */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2348 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 2349 | radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
| 2350 | radeon_ring_write(ring, fence->seq); |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2351 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2352 | radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); |
| 2353 | radeon_ring_write(ring, RB_INT_STAT); |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 2354 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2355 | } |
| 2356 | |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 2357 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2358 | struct radeon_ring *ring, |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 2359 | struct radeon_semaphore *semaphore, |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 2360 | bool emit_wait) |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 2361 | { |
| 2362 | uint64_t addr = semaphore->gpu_addr; |
| 2363 | unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; |
| 2364 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2365 | radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); |
| 2366 | radeon_ring_write(ring, addr & 0xffffffff); |
| 2367 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 2368 | } |
| 2369 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2370 | int r600_copy_blit(struct radeon_device *rdev, |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 2371 | uint64_t src_offset, |
| 2372 | uint64_t dst_offset, |
| 2373 | unsigned num_gpu_pages, |
| 2374 | struct radeon_fence *fence) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2375 | { |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 2376 | int r; |
| 2377 | |
| 2378 | mutex_lock(&rdev->r600_blit.mutex); |
| 2379 | rdev->r600_blit.vb_ib = NULL; |
Dave Airlie | 017ed80 | 2011-10-18 10:54:30 +0100 | [diff] [blame] | 2380 | r = r600_blit_prepare_copy(rdev, num_gpu_pages); |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 2381 | if (r) { |
| 2382 | if (rdev->r600_blit.vb_ib) |
| 2383 | radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
| 2384 | mutex_unlock(&rdev->r600_blit.mutex); |
| 2385 | return r; |
| 2386 | } |
Dave Airlie | 017ed80 | 2011-10-18 10:54:30 +0100 | [diff] [blame] | 2387 | r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2388 | r600_blit_done_copy(rdev, fence); |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 2389 | mutex_unlock(&rdev->r600_blit.mutex); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2390 | return 0; |
| 2391 | } |
| 2392 | |
Alex Deucher | 6ddddfe | 2011-10-14 10:51:22 -0400 | [diff] [blame] | 2393 | void r600_blit_suspend(struct radeon_device *rdev) |
| 2394 | { |
| 2395 | int r; |
| 2396 | |
| 2397 | /* unpin shaders bo */ |
| 2398 | if (rdev->r600_blit.shader_obj) { |
| 2399 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| 2400 | if (!r) { |
| 2401 | radeon_bo_unpin(rdev->r600_blit.shader_obj); |
| 2402 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| 2403 | } |
| 2404 | } |
| 2405 | } |
| 2406 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2407 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 2408 | uint32_t tiling_flags, uint32_t pitch, |
| 2409 | uint32_t offset, uint32_t obj_size) |
| 2410 | { |
| 2411 | /* FIXME: implement */ |
| 2412 | return 0; |
| 2413 | } |
| 2414 | |
| 2415 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg) |
| 2416 | { |
| 2417 | /* FIXME: implement */ |
| 2418 | } |
| 2419 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2420 | int r600_startup(struct radeon_device *rdev) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2421 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2422 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2423 | int r; |
| 2424 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 2425 | /* enable pcie gen2 link */ |
| 2426 | r600_pcie_gen2_enable(rdev); |
| 2427 | |
Alex Deucher | 779720a | 2009-12-09 19:31:44 -0500 | [diff] [blame] | 2428 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
| 2429 | r = r600_init_microcode(rdev); |
| 2430 | if (r) { |
| 2431 | DRM_ERROR("Failed to load firmware!\n"); |
| 2432 | return r; |
| 2433 | } |
| 2434 | } |
| 2435 | |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2436 | r = r600_vram_scratch_init(rdev); |
| 2437 | if (r) |
| 2438 | return r; |
| 2439 | |
Jerome Glisse | a3c1945 | 2009-10-01 18:02:13 +0200 | [diff] [blame] | 2440 | r600_mc_program(rdev); |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 2441 | if (rdev->flags & RADEON_IS_AGP) { |
| 2442 | r600_agp_enable(rdev); |
| 2443 | } else { |
| 2444 | r = r600_pcie_gart_enable(rdev); |
| 2445 | if (r) |
| 2446 | return r; |
| 2447 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2448 | r600_gpu_init(rdev); |
Jerome Glisse | c38c7b6 | 2010-02-04 17:27:27 +0100 | [diff] [blame] | 2449 | r = r600_blit_init(rdev); |
| 2450 | if (r) { |
| 2451 | r600_blit_fini(rdev); |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame^] | 2452 | rdev->asic->copy.copy = NULL; |
Jerome Glisse | c38c7b6 | 2010-02-04 17:27:27 +0100 | [diff] [blame] | 2453 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
| 2454 | } |
Alex Deucher | b70d6bb | 2010-08-06 21:36:58 -0400 | [diff] [blame] | 2455 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2456 | /* allocate wb buffer */ |
| 2457 | r = radeon_wb_init(rdev); |
| 2458 | if (r) |
| 2459 | return r; |
| 2460 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 2461 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
| 2462 | if (r) { |
| 2463 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
| 2464 | return r; |
| 2465 | } |
| 2466 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2467 | /* Enable IRQ */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2468 | r = r600_irq_init(rdev); |
| 2469 | if (r) { |
| 2470 | DRM_ERROR("radeon: IH init failed (%d).\n", r); |
| 2471 | radeon_irq_kms_fini(rdev); |
| 2472 | return r; |
| 2473 | } |
| 2474 | r600_irq_set(rdev); |
| 2475 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2476 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 2477 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
| 2478 | 0, 0xfffff, RADEON_CP_PACKET2); |
Christian König | 5596a9d | 2011-10-13 12:48:45 +0200 | [diff] [blame] | 2479 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2480 | if (r) |
| 2481 | return r; |
| 2482 | r = r600_cp_load_microcode(rdev); |
| 2483 | if (r) |
| 2484 | return r; |
| 2485 | r = r600_cp_resume(rdev); |
| 2486 | if (r) |
| 2487 | return r; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2488 | |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 2489 | r = radeon_ib_pool_start(rdev); |
| 2490 | if (r) |
| 2491 | return r; |
| 2492 | |
| 2493 | r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX); |
| 2494 | if (r) { |
| 2495 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
| 2496 | rdev->accel_working = false; |
| 2497 | return r; |
| 2498 | } |
| 2499 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2500 | return 0; |
| 2501 | } |
| 2502 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2503 | void r600_vga_set_state(struct radeon_device *rdev, bool state) |
| 2504 | { |
| 2505 | uint32_t temp; |
| 2506 | |
| 2507 | temp = RREG32(CONFIG_CNTL); |
| 2508 | if (state == false) { |
| 2509 | temp &= ~(1<<0); |
| 2510 | temp |= (1<<1); |
| 2511 | } else { |
| 2512 | temp &= ~(1<<1); |
| 2513 | } |
| 2514 | WREG32(CONFIG_CNTL, temp); |
| 2515 | } |
| 2516 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2517 | int r600_resume(struct radeon_device *rdev) |
| 2518 | { |
| 2519 | int r; |
| 2520 | |
Jerome Glisse | 1a029b7 | 2009-10-06 19:04:30 +0200 | [diff] [blame] | 2521 | /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, |
| 2522 | * posting will perform necessary task to bring back GPU into good |
| 2523 | * shape. |
| 2524 | */ |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2525 | /* post card */ |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 2526 | atom_asic_init(rdev->mode_info.atom_context); |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2527 | |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 2528 | rdev->accel_working = true; |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2529 | r = r600_startup(rdev); |
| 2530 | if (r) { |
| 2531 | DRM_ERROR("r600 startup failed on resume\n"); |
| 2532 | return r; |
| 2533 | } |
| 2534 | |
Rafał Miłecki | 38fd2c6 | 2010-01-28 18:16:30 +0100 | [diff] [blame] | 2535 | r = r600_audio_init(rdev); |
| 2536 | if (r) { |
| 2537 | DRM_ERROR("radeon: audio resume failed\n"); |
| 2538 | return r; |
| 2539 | } |
| 2540 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2541 | return r; |
| 2542 | } |
| 2543 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2544 | int r600_suspend(struct radeon_device *rdev) |
| 2545 | { |
Rafał Miłecki | 38fd2c6 | 2010-01-28 18:16:30 +0100 | [diff] [blame] | 2546 | r600_audio_fini(rdev); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 2547 | radeon_ib_pool_suspend(rdev); |
| 2548 | r600_blit_suspend(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2549 | /* FIXME: we should wait for ring to be empty */ |
| 2550 | r600_cp_stop(rdev); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2551 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 2552 | r600_irq_suspend(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2553 | radeon_wb_disable(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 2554 | r600_pcie_gart_disable(rdev); |
Alex Deucher | 6ddddfe | 2011-10-14 10:51:22 -0400 | [diff] [blame] | 2555 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2556 | return 0; |
| 2557 | } |
| 2558 | |
| 2559 | /* Plan is to move initialization in that function and use |
| 2560 | * helper function so that radeon_device_init pretty much |
| 2561 | * do nothing more than calling asic specific function. This |
| 2562 | * should also allow to remove a bunch of callback function |
| 2563 | * like vram_info. |
| 2564 | */ |
| 2565 | int r600_init(struct radeon_device *rdev) |
| 2566 | { |
| 2567 | int r; |
| 2568 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2569 | if (r600_debugfs_mc_info_init(rdev)) { |
| 2570 | DRM_ERROR("Failed to register debugfs file for mc !\n"); |
| 2571 | } |
| 2572 | /* This don't do much */ |
| 2573 | r = radeon_gem_init(rdev); |
| 2574 | if (r) |
| 2575 | return r; |
| 2576 | /* Read BIOS */ |
| 2577 | if (!radeon_get_bios(rdev)) { |
| 2578 | if (ASIC_IS_AVIVO(rdev)) |
| 2579 | return -EINVAL; |
| 2580 | } |
| 2581 | /* Must be an ATOMBIOS */ |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 2582 | if (!rdev->is_atom_bios) { |
| 2583 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2584 | return -EINVAL; |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 2585 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2586 | r = radeon_atombios_init(rdev); |
| 2587 | if (r) |
| 2588 | return r; |
| 2589 | /* Post card if necessary */ |
Alex Deucher | fd909c3 | 2011-01-11 18:08:59 -0500 | [diff] [blame] | 2590 | if (!radeon_card_posted(rdev)) { |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 2591 | if (!rdev->bios) { |
| 2592 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
| 2593 | return -EINVAL; |
| 2594 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2595 | DRM_INFO("GPU not posted. posting now...\n"); |
| 2596 | atom_asic_init(rdev->mode_info.atom_context); |
| 2597 | } |
| 2598 | /* Initialize scratch registers */ |
| 2599 | r600_scratch_init(rdev); |
| 2600 | /* Initialize surface registers */ |
| 2601 | radeon_surface_init(rdev); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 2602 | /* Initialize clocks */ |
Michel Dänzer | 5e6dde7 | 2009-09-17 09:42:28 +0200 | [diff] [blame] | 2603 | radeon_get_clock_info(rdev->ddev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2604 | /* Fence driver */ |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 2605 | r = radeon_fence_driver_init(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2606 | if (r) |
| 2607 | return r; |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 2608 | if (rdev->flags & RADEON_IS_AGP) { |
| 2609 | r = radeon_agp_init(rdev); |
| 2610 | if (r) |
| 2611 | radeon_agp_disable(rdev); |
| 2612 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2613 | r = r600_mc_init(rdev); |
Jerome Glisse | b574f25 | 2009-10-06 19:04:29 +0200 | [diff] [blame] | 2614 | if (r) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2615 | return r; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2616 | /* Memory manager */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2617 | r = radeon_bo_init(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2618 | if (r) |
| 2619 | return r; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2620 | |
| 2621 | r = radeon_irq_kms_init(rdev); |
| 2622 | if (r) |
| 2623 | return r; |
| 2624 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2625 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
| 2626 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2627 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2628 | rdev->ih.ring_obj = NULL; |
| 2629 | r600_ih_ring_init(rdev, 64 * 1024); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2630 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 2631 | r = r600_pcie_gart_init(rdev); |
| 2632 | if (r) |
| 2633 | return r; |
| 2634 | |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 2635 | r = radeon_ib_pool_init(rdev); |
Alex Deucher | 779720a | 2009-12-09 19:31:44 -0500 | [diff] [blame] | 2636 | rdev->accel_working = true; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 2637 | if (r) { |
| 2638 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| 2639 | rdev->accel_working = false; |
| 2640 | } |
| 2641 | |
Dave Airlie | fc30b8e | 2009-09-18 15:19:37 +1000 | [diff] [blame] | 2642 | r = r600_startup(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2643 | if (r) { |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2644 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
| 2645 | r600_cp_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2646 | r600_irq_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2647 | radeon_wb_fini(rdev); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 2648 | r100_ib_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2649 | radeon_irq_kms_fini(rdev); |
Jerome Glisse | 75c8129 | 2009-10-01 18:02:14 +0200 | [diff] [blame] | 2650 | r600_pcie_gart_fini(rdev); |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 2651 | rdev->accel_working = false; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2652 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 2653 | |
| 2654 | r = r600_audio_init(rdev); |
| 2655 | if (r) |
| 2656 | return r; /* TODO error handling */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2657 | return 0; |
| 2658 | } |
| 2659 | |
| 2660 | void r600_fini(struct radeon_device *rdev) |
| 2661 | { |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 2662 | r600_audio_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2663 | r600_blit_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2664 | r600_cp_fini(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2665 | r600_irq_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2666 | radeon_wb_fini(rdev); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 2667 | r100_ib_fini(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2668 | radeon_irq_kms_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 2669 | r600_pcie_gart_fini(rdev); |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2670 | r600_vram_scratch_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 2671 | radeon_agp_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2672 | radeon_gem_fini(rdev); |
Christian König | 15d3332 | 2011-09-15 19:02:22 +0200 | [diff] [blame] | 2673 | radeon_semaphore_driver_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2674 | radeon_fence_driver_fini(rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2675 | radeon_bo_fini(rdev); |
Jerome Glisse | e7d40b9 | 2009-10-01 18:02:15 +0200 | [diff] [blame] | 2676 | radeon_atombios_fini(rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2677 | kfree(rdev->bios); |
| 2678 | rdev->bios = NULL; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2679 | } |
| 2680 | |
| 2681 | |
| 2682 | /* |
| 2683 | * CS stuff |
| 2684 | */ |
| 2685 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
| 2686 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2687 | struct radeon_ring *ring = &rdev->ring[ib->fence->ring]; |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 2688 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2689 | /* FIXME: implement */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2690 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
| 2691 | radeon_ring_write(ring, |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 2692 | #ifdef __BIG_ENDIAN |
| 2693 | (2 << 0) | |
| 2694 | #endif |
| 2695 | (ib->gpu_addr & 0xFFFFFFFC)); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2696 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
| 2697 | radeon_ring_write(ring, ib->length_dw); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2698 | } |
| 2699 | |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 2700 | int r600_ib_test(struct radeon_device *rdev, int ring) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2701 | { |
| 2702 | struct radeon_ib *ib; |
| 2703 | uint32_t scratch; |
| 2704 | uint32_t tmp = 0; |
| 2705 | unsigned i; |
| 2706 | int r; |
| 2707 | |
| 2708 | r = radeon_scratch_get(rdev, &scratch); |
| 2709 | if (r) { |
| 2710 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); |
| 2711 | return r; |
| 2712 | } |
| 2713 | WREG32(scratch, 0xCAFEDEAD); |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 2714 | r = radeon_ib_get(rdev, ring, &ib, 256); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2715 | if (r) { |
| 2716 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
| 2717 | return r; |
| 2718 | } |
| 2719 | ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); |
| 2720 | ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| 2721 | ib->ptr[2] = 0xDEADBEEF; |
Christian König | 442f7cf | 2012-02-23 15:18:43 +0100 | [diff] [blame] | 2722 | ib->length_dw = 3; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2723 | r = radeon_ib_schedule(rdev, ib); |
| 2724 | if (r) { |
| 2725 | radeon_scratch_free(rdev, scratch); |
| 2726 | radeon_ib_free(rdev, &ib); |
| 2727 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
| 2728 | return r; |
| 2729 | } |
| 2730 | r = radeon_fence_wait(ib->fence, false); |
| 2731 | if (r) { |
| 2732 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
| 2733 | return r; |
| 2734 | } |
| 2735 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 2736 | tmp = RREG32(scratch); |
| 2737 | if (tmp == 0xDEADBEEF) |
| 2738 | break; |
| 2739 | DRM_UDELAY(1); |
| 2740 | } |
| 2741 | if (i < rdev->usec_timeout) { |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 2742 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib->fence->ring, i); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2743 | } else { |
Daniel J Blueman | 4417d7f | 2010-09-22 17:57:19 +0100 | [diff] [blame] | 2744 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2745 | scratch, tmp); |
| 2746 | r = -EINVAL; |
| 2747 | } |
| 2748 | radeon_scratch_free(rdev, scratch); |
| 2749 | radeon_ib_free(rdev, &ib); |
| 2750 | return r; |
| 2751 | } |
| 2752 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2753 | /* |
| 2754 | * Interrupts |
| 2755 | * |
| 2756 | * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty |
| 2757 | * the same as the CP ring buffer, but in reverse. Rather than the CPU |
| 2758 | * writing to the ring and the GPU consuming, the GPU writes to the ring |
| 2759 | * and host consumes. As the host irq handler processes interrupts, it |
| 2760 | * increments the rptr. When the rptr catches up with the wptr, all the |
| 2761 | * current interrupts have been processed. |
| 2762 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2763 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2764 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) |
| 2765 | { |
| 2766 | u32 rb_bufsz; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2767 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2768 | /* Align ring size */ |
| 2769 | rb_bufsz = drm_order(ring_size / 4); |
| 2770 | ring_size = (1 << rb_bufsz) * 4; |
| 2771 | rdev->ih.ring_size = ring_size; |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 2772 | rdev->ih.ptr_mask = rdev->ih.ring_size - 1; |
| 2773 | rdev->ih.rptr = 0; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2774 | } |
| 2775 | |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 2776 | static int r600_ih_ring_alloc(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2777 | { |
| 2778 | int r; |
| 2779 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2780 | /* Allocate ring buffer */ |
| 2781 | if (rdev->ih.ring_obj == NULL) { |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 2782 | r = radeon_bo_create(rdev, rdev->ih.ring_size, |
Alex Deucher | 268b251 | 2010-11-17 19:00:26 -0500 | [diff] [blame] | 2783 | PAGE_SIZE, true, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2784 | RADEON_GEM_DOMAIN_GTT, |
| 2785 | &rdev->ih.ring_obj); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2786 | if (r) { |
| 2787 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); |
| 2788 | return r; |
| 2789 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2790 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
| 2791 | if (unlikely(r != 0)) |
| 2792 | return r; |
| 2793 | r = radeon_bo_pin(rdev->ih.ring_obj, |
| 2794 | RADEON_GEM_DOMAIN_GTT, |
| 2795 | &rdev->ih.gpu_addr); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2796 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2797 | radeon_bo_unreserve(rdev->ih.ring_obj); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2798 | DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); |
| 2799 | return r; |
| 2800 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2801 | r = radeon_bo_kmap(rdev->ih.ring_obj, |
| 2802 | (void **)&rdev->ih.ring); |
| 2803 | radeon_bo_unreserve(rdev->ih.ring_obj); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2804 | if (r) { |
| 2805 | DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); |
| 2806 | return r; |
| 2807 | } |
| 2808 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2809 | return 0; |
| 2810 | } |
| 2811 | |
| 2812 | static void r600_ih_ring_fini(struct radeon_device *rdev) |
| 2813 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2814 | int r; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2815 | if (rdev->ih.ring_obj) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2816 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
| 2817 | if (likely(r == 0)) { |
| 2818 | radeon_bo_kunmap(rdev->ih.ring_obj); |
| 2819 | radeon_bo_unpin(rdev->ih.ring_obj); |
| 2820 | radeon_bo_unreserve(rdev->ih.ring_obj); |
| 2821 | } |
| 2822 | radeon_bo_unref(&rdev->ih.ring_obj); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2823 | rdev->ih.ring = NULL; |
| 2824 | rdev->ih.ring_obj = NULL; |
| 2825 | } |
| 2826 | } |
| 2827 | |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2828 | void r600_rlc_stop(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2829 | { |
| 2830 | |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2831 | if ((rdev->family >= CHIP_RV770) && |
| 2832 | (rdev->family <= CHIP_RV740)) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2833 | /* r7xx asics need to soft reset RLC before halting */ |
| 2834 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); |
| 2835 | RREG32(SRBM_SOFT_RESET); |
| 2836 | udelay(15000); |
| 2837 | WREG32(SRBM_SOFT_RESET, 0); |
| 2838 | RREG32(SRBM_SOFT_RESET); |
| 2839 | } |
| 2840 | |
| 2841 | WREG32(RLC_CNTL, 0); |
| 2842 | } |
| 2843 | |
| 2844 | static void r600_rlc_start(struct radeon_device *rdev) |
| 2845 | { |
| 2846 | WREG32(RLC_CNTL, RLC_ENABLE); |
| 2847 | } |
| 2848 | |
| 2849 | static int r600_rlc_init(struct radeon_device *rdev) |
| 2850 | { |
| 2851 | u32 i; |
| 2852 | const __be32 *fw_data; |
| 2853 | |
| 2854 | if (!rdev->rlc_fw) |
| 2855 | return -EINVAL; |
| 2856 | |
| 2857 | r600_rlc_stop(rdev); |
| 2858 | |
| 2859 | WREG32(RLC_HB_BASE, 0); |
| 2860 | WREG32(RLC_HB_CNTL, 0); |
| 2861 | WREG32(RLC_HB_RPTR, 0); |
| 2862 | WREG32(RLC_HB_WPTR, 0); |
Alex Deucher | 1272780 | 2011-03-02 20:07:32 -0500 | [diff] [blame] | 2863 | if (rdev->family <= CHIP_CAICOS) { |
| 2864 | WREG32(RLC_HB_WPTR_LSB_ADDR, 0); |
| 2865 | WREG32(RLC_HB_WPTR_MSB_ADDR, 0); |
| 2866 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2867 | WREG32(RLC_MC_CNTL, 0); |
| 2868 | WREG32(RLC_UCODE_CNTL, 0); |
| 2869 | |
| 2870 | fw_data = (const __be32 *)rdev->rlc_fw->data; |
Alex Deucher | 1272780 | 2011-03-02 20:07:32 -0500 | [diff] [blame] | 2871 | if (rdev->family >= CHIP_CAYMAN) { |
| 2872 | for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { |
| 2873 | WREG32(RLC_UCODE_ADDR, i); |
| 2874 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); |
| 2875 | } |
| 2876 | } else if (rdev->family >= CHIP_CEDAR) { |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2877 | for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { |
| 2878 | WREG32(RLC_UCODE_ADDR, i); |
| 2879 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); |
| 2880 | } |
| 2881 | } else if (rdev->family >= CHIP_RV770) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2882 | for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { |
| 2883 | WREG32(RLC_UCODE_ADDR, i); |
| 2884 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); |
| 2885 | } |
| 2886 | } else { |
| 2887 | for (i = 0; i < RLC_UCODE_SIZE; i++) { |
| 2888 | WREG32(RLC_UCODE_ADDR, i); |
| 2889 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); |
| 2890 | } |
| 2891 | } |
| 2892 | WREG32(RLC_UCODE_ADDR, 0); |
| 2893 | |
| 2894 | r600_rlc_start(rdev); |
| 2895 | |
| 2896 | return 0; |
| 2897 | } |
| 2898 | |
| 2899 | static void r600_enable_interrupts(struct radeon_device *rdev) |
| 2900 | { |
| 2901 | u32 ih_cntl = RREG32(IH_CNTL); |
| 2902 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); |
| 2903 | |
| 2904 | ih_cntl |= ENABLE_INTR; |
| 2905 | ih_rb_cntl |= IH_RB_ENABLE; |
| 2906 | WREG32(IH_CNTL, ih_cntl); |
| 2907 | WREG32(IH_RB_CNTL, ih_rb_cntl); |
| 2908 | rdev->ih.enabled = true; |
| 2909 | } |
| 2910 | |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 2911 | void r600_disable_interrupts(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2912 | { |
| 2913 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); |
| 2914 | u32 ih_cntl = RREG32(IH_CNTL); |
| 2915 | |
| 2916 | ih_rb_cntl &= ~IH_RB_ENABLE; |
| 2917 | ih_cntl &= ~ENABLE_INTR; |
| 2918 | WREG32(IH_RB_CNTL, ih_rb_cntl); |
| 2919 | WREG32(IH_CNTL, ih_cntl); |
| 2920 | /* set rptr, wptr to 0 */ |
| 2921 | WREG32(IH_RB_RPTR, 0); |
| 2922 | WREG32(IH_RB_WPTR, 0); |
| 2923 | rdev->ih.enabled = false; |
| 2924 | rdev->ih.wptr = 0; |
| 2925 | rdev->ih.rptr = 0; |
| 2926 | } |
| 2927 | |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 2928 | static void r600_disable_interrupt_state(struct radeon_device *rdev) |
| 2929 | { |
| 2930 | u32 tmp; |
| 2931 | |
Alex Deucher | 3555e53 | 2010-10-08 12:09:12 -0400 | [diff] [blame] | 2932 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 2933 | WREG32(GRBM_INT_CNTL, 0); |
| 2934 | WREG32(DxMODE_INT_MASK, 0); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 2935 | WREG32(D1GRPH_INTERRUPT_CONTROL, 0); |
| 2936 | WREG32(D2GRPH_INTERRUPT_CONTROL, 0); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 2937 | if (ASIC_IS_DCE3(rdev)) { |
| 2938 | WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); |
| 2939 | WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); |
| 2940 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
| 2941 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
| 2942 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
| 2943 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
| 2944 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
| 2945 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
| 2946 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
| 2947 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
| 2948 | if (ASIC_IS_DCE32(rdev)) { |
| 2949 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
Alex Deucher | 5898b1f | 2010-03-24 13:57:29 -0400 | [diff] [blame] | 2950 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 2951 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
Alex Deucher | 5898b1f | 2010-03-24 13:57:29 -0400 | [diff] [blame] | 2952 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 2953 | } |
| 2954 | } else { |
| 2955 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); |
| 2956 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); |
| 2957 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
Alex Deucher | 5898b1f | 2010-03-24 13:57:29 -0400 | [diff] [blame] | 2958 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 2959 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
Alex Deucher | 5898b1f | 2010-03-24 13:57:29 -0400 | [diff] [blame] | 2960 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 2961 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
Alex Deucher | 5898b1f | 2010-03-24 13:57:29 -0400 | [diff] [blame] | 2962 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 2963 | } |
| 2964 | } |
| 2965 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2966 | int r600_irq_init(struct radeon_device *rdev) |
| 2967 | { |
| 2968 | int ret = 0; |
| 2969 | int rb_bufsz; |
| 2970 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; |
| 2971 | |
| 2972 | /* allocate ring */ |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 2973 | ret = r600_ih_ring_alloc(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2974 | if (ret) |
| 2975 | return ret; |
| 2976 | |
| 2977 | /* disable irqs */ |
| 2978 | r600_disable_interrupts(rdev); |
| 2979 | |
| 2980 | /* init rlc */ |
| 2981 | ret = r600_rlc_init(rdev); |
| 2982 | if (ret) { |
| 2983 | r600_ih_ring_fini(rdev); |
| 2984 | return ret; |
| 2985 | } |
| 2986 | |
| 2987 | /* setup interrupt control */ |
| 2988 | /* set dummy read address to ring address */ |
| 2989 | WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); |
| 2990 | interrupt_cntl = RREG32(INTERRUPT_CNTL); |
| 2991 | /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi |
| 2992 | * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN |
| 2993 | */ |
| 2994 | interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; |
| 2995 | /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ |
| 2996 | interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; |
| 2997 | WREG32(INTERRUPT_CNTL, interrupt_cntl); |
| 2998 | |
| 2999 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); |
| 3000 | rb_bufsz = drm_order(rdev->ih.ring_size / 4); |
| 3001 | |
| 3002 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | |
| 3003 | IH_WPTR_OVERFLOW_CLEAR | |
| 3004 | (rb_bufsz << 1)); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 3005 | |
| 3006 | if (rdev->wb.enabled) |
| 3007 | ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; |
| 3008 | |
| 3009 | /* set the writeback address whether it's enabled or not */ |
| 3010 | WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); |
| 3011 | WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3012 | |
| 3013 | WREG32(IH_RB_CNTL, ih_rb_cntl); |
| 3014 | |
| 3015 | /* set rptr, wptr to 0 */ |
| 3016 | WREG32(IH_RB_RPTR, 0); |
| 3017 | WREG32(IH_RB_WPTR, 0); |
| 3018 | |
| 3019 | /* Default settings for IH_CNTL (disabled at first) */ |
| 3020 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); |
| 3021 | /* RPTR_REARM only works if msi's are enabled */ |
| 3022 | if (rdev->msi_enabled) |
| 3023 | ih_cntl |= RPTR_REARM; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3024 | WREG32(IH_CNTL, ih_cntl); |
| 3025 | |
| 3026 | /* force the active interrupt state to all disabled */ |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 3027 | if (rdev->family >= CHIP_CEDAR) |
| 3028 | evergreen_disable_interrupt_state(rdev); |
| 3029 | else |
| 3030 | r600_disable_interrupt_state(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3031 | |
| 3032 | /* enable irqs */ |
| 3033 | r600_enable_interrupts(rdev); |
| 3034 | |
| 3035 | return ret; |
| 3036 | } |
| 3037 | |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 3038 | void r600_irq_suspend(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3039 | { |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 3040 | r600_irq_disable(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3041 | r600_rlc_stop(rdev); |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 3042 | } |
| 3043 | |
| 3044 | void r600_irq_fini(struct radeon_device *rdev) |
| 3045 | { |
| 3046 | r600_irq_suspend(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3047 | r600_ih_ring_fini(rdev); |
| 3048 | } |
| 3049 | |
| 3050 | int r600_irq_set(struct radeon_device *rdev) |
| 3051 | { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3052 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
| 3053 | u32 mode_int = 0; |
| 3054 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 3055 | u32 grbm_int_cntl = 0; |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3056 | u32 hdmi1, hdmi2; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3057 | u32 d1grph = 0, d2grph = 0; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3058 | |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 3059 | if (!rdev->irq.installed) { |
Joe Perches | fce7d61 | 2010-10-30 21:08:30 +0000 | [diff] [blame] | 3060 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 3061 | return -EINVAL; |
| 3062 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3063 | /* don't enable anything if the ih is disabled */ |
Jerome Glisse | 79c2bbc | 2010-01-15 14:44:38 +0100 | [diff] [blame] | 3064 | if (!rdev->ih.enabled) { |
| 3065 | r600_disable_interrupts(rdev); |
| 3066 | /* force the active interrupt state to all disabled */ |
| 3067 | r600_disable_interrupt_state(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3068 | return 0; |
Jerome Glisse | 79c2bbc | 2010-01-15 14:44:38 +0100 | [diff] [blame] | 3069 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3070 | |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3071 | hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3072 | if (ASIC_IS_DCE3(rdev)) { |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3073 | hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3074 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3075 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3076 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3077 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3078 | if (ASIC_IS_DCE32(rdev)) { |
| 3079 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3080 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3081 | } |
| 3082 | } else { |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3083 | hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3084 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3085 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3086 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| 3087 | } |
| 3088 | |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 3089 | if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3090 | DRM_DEBUG("r600_irq_set: sw int\n"); |
| 3091 | cp_int_cntl |= RB_INT_ENABLE; |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 3092 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3093 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3094 | if (rdev->irq.crtc_vblank_int[0] || |
| 3095 | rdev->irq.pflip[0]) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3096 | DRM_DEBUG("r600_irq_set: vblank 0\n"); |
| 3097 | mode_int |= D1MODE_VBLANK_INT_MASK; |
| 3098 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3099 | if (rdev->irq.crtc_vblank_int[1] || |
| 3100 | rdev->irq.pflip[1]) { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3101 | DRM_DEBUG("r600_irq_set: vblank 1\n"); |
| 3102 | mode_int |= D2MODE_VBLANK_INT_MASK; |
| 3103 | } |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3104 | if (rdev->irq.hpd[0]) { |
| 3105 | DRM_DEBUG("r600_irq_set: hpd 1\n"); |
| 3106 | hpd1 |= DC_HPDx_INT_EN; |
| 3107 | } |
| 3108 | if (rdev->irq.hpd[1]) { |
| 3109 | DRM_DEBUG("r600_irq_set: hpd 2\n"); |
| 3110 | hpd2 |= DC_HPDx_INT_EN; |
| 3111 | } |
| 3112 | if (rdev->irq.hpd[2]) { |
| 3113 | DRM_DEBUG("r600_irq_set: hpd 3\n"); |
| 3114 | hpd3 |= DC_HPDx_INT_EN; |
| 3115 | } |
| 3116 | if (rdev->irq.hpd[3]) { |
| 3117 | DRM_DEBUG("r600_irq_set: hpd 4\n"); |
| 3118 | hpd4 |= DC_HPDx_INT_EN; |
| 3119 | } |
| 3120 | if (rdev->irq.hpd[4]) { |
| 3121 | DRM_DEBUG("r600_irq_set: hpd 5\n"); |
| 3122 | hpd5 |= DC_HPDx_INT_EN; |
| 3123 | } |
| 3124 | if (rdev->irq.hpd[5]) { |
| 3125 | DRM_DEBUG("r600_irq_set: hpd 6\n"); |
| 3126 | hpd6 |= DC_HPDx_INT_EN; |
| 3127 | } |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3128 | if (rdev->irq.hdmi[0]) { |
| 3129 | DRM_DEBUG("r600_irq_set: hdmi 1\n"); |
| 3130 | hdmi1 |= R600_HDMI_INT_EN; |
| 3131 | } |
| 3132 | if (rdev->irq.hdmi[1]) { |
| 3133 | DRM_DEBUG("r600_irq_set: hdmi 2\n"); |
| 3134 | hdmi2 |= R600_HDMI_INT_EN; |
| 3135 | } |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 3136 | if (rdev->irq.gui_idle) { |
| 3137 | DRM_DEBUG("gui idle\n"); |
| 3138 | grbm_int_cntl |= GUI_IDLE_INT_ENABLE; |
| 3139 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3140 | |
| 3141 | WREG32(CP_INT_CNTL, cp_int_cntl); |
| 3142 | WREG32(DxMODE_INT_MASK, mode_int); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3143 | WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); |
| 3144 | WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 3145 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3146 | WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3147 | if (ASIC_IS_DCE3(rdev)) { |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3148 | WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3149 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
| 3150 | WREG32(DC_HPD2_INT_CONTROL, hpd2); |
| 3151 | WREG32(DC_HPD3_INT_CONTROL, hpd3); |
| 3152 | WREG32(DC_HPD4_INT_CONTROL, hpd4); |
| 3153 | if (ASIC_IS_DCE32(rdev)) { |
| 3154 | WREG32(DC_HPD5_INT_CONTROL, hpd5); |
| 3155 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
| 3156 | } |
| 3157 | } else { |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3158 | WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3159 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
| 3160 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
| 3161 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); |
| 3162 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3163 | |
| 3164 | return 0; |
| 3165 | } |
| 3166 | |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 3167 | static void r600_irq_ack(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3168 | { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3169 | u32 tmp; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3170 | |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3171 | if (ASIC_IS_DCE3(rdev)) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3172 | rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); |
| 3173 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); |
| 3174 | rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3175 | } else { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3176 | rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
| 3177 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); |
| 3178 | rdev->irq.stat_regs.r600.disp_int_cont2 = 0; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3179 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3180 | rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); |
| 3181 | rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3182 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3183 | if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) |
| 3184 | WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); |
| 3185 | if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) |
| 3186 | WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); |
| 3187 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3188 | WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3189 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3190 | WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3191 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3192 | WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3193 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3194 | WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3195 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3196 | if (ASIC_IS_DCE3(rdev)) { |
| 3197 | tmp = RREG32(DC_HPD1_INT_CONTROL); |
| 3198 | tmp |= DC_HPDx_INT_ACK; |
| 3199 | WREG32(DC_HPD1_INT_CONTROL, tmp); |
| 3200 | } else { |
| 3201 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); |
| 3202 | tmp |= DC_HPDx_INT_ACK; |
| 3203 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
| 3204 | } |
| 3205 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3206 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3207 | if (ASIC_IS_DCE3(rdev)) { |
| 3208 | tmp = RREG32(DC_HPD2_INT_CONTROL); |
| 3209 | tmp |= DC_HPDx_INT_ACK; |
| 3210 | WREG32(DC_HPD2_INT_CONTROL, tmp); |
| 3211 | } else { |
| 3212 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); |
| 3213 | tmp |= DC_HPDx_INT_ACK; |
| 3214 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
| 3215 | } |
| 3216 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3217 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3218 | if (ASIC_IS_DCE3(rdev)) { |
| 3219 | tmp = RREG32(DC_HPD3_INT_CONTROL); |
| 3220 | tmp |= DC_HPDx_INT_ACK; |
| 3221 | WREG32(DC_HPD3_INT_CONTROL, tmp); |
| 3222 | } else { |
| 3223 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); |
| 3224 | tmp |= DC_HPDx_INT_ACK; |
| 3225 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
| 3226 | } |
| 3227 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3228 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3229 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
| 3230 | tmp |= DC_HPDx_INT_ACK; |
| 3231 | WREG32(DC_HPD4_INT_CONTROL, tmp); |
| 3232 | } |
| 3233 | if (ASIC_IS_DCE32(rdev)) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3234 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3235 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
| 3236 | tmp |= DC_HPDx_INT_ACK; |
| 3237 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
| 3238 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3239 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3240 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
| 3241 | tmp |= DC_HPDx_INT_ACK; |
| 3242 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
| 3243 | } |
| 3244 | } |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3245 | if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { |
| 3246 | WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); |
| 3247 | } |
| 3248 | if (ASIC_IS_DCE3(rdev)) { |
| 3249 | if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { |
| 3250 | WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); |
| 3251 | } |
| 3252 | } else { |
| 3253 | if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { |
| 3254 | WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); |
| 3255 | } |
| 3256 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3257 | } |
| 3258 | |
| 3259 | void r600_irq_disable(struct radeon_device *rdev) |
| 3260 | { |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3261 | r600_disable_interrupts(rdev); |
| 3262 | /* Wait and acknowledge irq */ |
| 3263 | mdelay(1); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3264 | r600_irq_ack(rdev); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3265 | r600_disable_interrupt_state(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3266 | } |
| 3267 | |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 3268 | static u32 r600_get_ih_wptr(struct radeon_device *rdev) |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3269 | { |
| 3270 | u32 wptr, tmp; |
| 3271 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 3272 | if (rdev->wb.enabled) |
Cédric Cano | 204ae24 | 2011-04-19 11:07:13 -0400 | [diff] [blame] | 3273 | wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 3274 | else |
| 3275 | wptr = RREG32(IH_RB_WPTR); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3276 | |
| 3277 | if (wptr & RB_OVERFLOW) { |
Jerome Glisse | 7924e5e | 2010-01-15 14:44:39 +0100 | [diff] [blame] | 3278 | /* When a ring buffer overflow happen start parsing interrupt |
| 3279 | * from the last not overwritten vector (wptr + 16). Hopefully |
| 3280 | * this should allow us to catchup. |
| 3281 | */ |
| 3282 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", |
| 3283 | wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); |
| 3284 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3285 | tmp = RREG32(IH_RB_CNTL); |
| 3286 | tmp |= IH_WPTR_OVERFLOW_CLEAR; |
| 3287 | WREG32(IH_RB_CNTL, tmp); |
| 3288 | } |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 3289 | return (wptr & rdev->ih.ptr_mask); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3290 | } |
| 3291 | |
| 3292 | /* r600 IV Ring |
| 3293 | * Each IV ring entry is 128 bits: |
| 3294 | * [7:0] - interrupt source id |
| 3295 | * [31:8] - reserved |
| 3296 | * [59:32] - interrupt source data |
| 3297 | * [127:60] - reserved |
| 3298 | * |
| 3299 | * The basic interrupt vector entries |
| 3300 | * are decoded as follows: |
| 3301 | * src_id src_data description |
| 3302 | * 1 0 D1 Vblank |
| 3303 | * 1 1 D1 Vline |
| 3304 | * 5 0 D2 Vblank |
| 3305 | * 5 1 D2 Vline |
| 3306 | * 19 0 FP Hot plug detection A |
| 3307 | * 19 1 FP Hot plug detection B |
| 3308 | * 19 2 DAC A auto-detection |
| 3309 | * 19 3 DAC B auto-detection |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3310 | * 21 4 HDMI block A |
| 3311 | * 21 5 HDMI block B |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3312 | * 176 - CP_INT RB |
| 3313 | * 177 - CP_INT IB1 |
| 3314 | * 178 - CP_INT IB2 |
| 3315 | * 181 - EOP Interrupt |
| 3316 | * 233 - GUI Idle |
| 3317 | * |
| 3318 | * Note, these are based on r600 and may need to be |
| 3319 | * adjusted or added to on newer asics |
| 3320 | */ |
| 3321 | |
| 3322 | int r600_irq_process(struct radeon_device *rdev) |
| 3323 | { |
Dave Airlie | 682f1a5 | 2011-06-18 03:59:51 +0000 | [diff] [blame] | 3324 | u32 wptr; |
| 3325 | u32 rptr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3326 | u32 src_id, src_data; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3327 | u32 ring_index; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3328 | unsigned long flags; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3329 | bool queue_hotplug = false; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3330 | |
Dave Airlie | 682f1a5 | 2011-06-18 03:59:51 +0000 | [diff] [blame] | 3331 | if (!rdev->ih.enabled || rdev->shutdown) |
Jerome Glisse | 79c2bbc | 2010-01-15 14:44:38 +0100 | [diff] [blame] | 3332 | return IRQ_NONE; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3333 | |
Benjamin Herrenschmidt | f6a5693 | 2011-07-13 06:28:22 +0000 | [diff] [blame] | 3334 | /* No MSIs, need a dummy read to flush PCI DMAs */ |
| 3335 | if (!rdev->msi_enabled) |
| 3336 | RREG32(IH_RB_WPTR); |
| 3337 | |
Dave Airlie | 682f1a5 | 2011-06-18 03:59:51 +0000 | [diff] [blame] | 3338 | wptr = r600_get_ih_wptr(rdev); |
| 3339 | rptr = rdev->ih.rptr; |
| 3340 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); |
| 3341 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3342 | spin_lock_irqsave(&rdev->ih.lock, flags); |
| 3343 | |
| 3344 | if (rptr == wptr) { |
| 3345 | spin_unlock_irqrestore(&rdev->ih.lock, flags); |
| 3346 | return IRQ_NONE; |
| 3347 | } |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3348 | |
| 3349 | restart_ih: |
Benjamin Herrenschmidt | 964f664 | 2011-07-13 16:28:19 +1000 | [diff] [blame] | 3350 | /* Order reading of wptr vs. reading of IH ring data */ |
| 3351 | rmb(); |
| 3352 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3353 | /* display interrupts */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3354 | r600_irq_ack(rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3355 | |
| 3356 | rdev->ih.wptr = wptr; |
| 3357 | while (rptr != wptr) { |
| 3358 | /* wptr/rptr are in bytes! */ |
| 3359 | ring_index = rptr / 4; |
Cédric Cano | 4eace7f | 2011-02-11 19:45:38 -0500 | [diff] [blame] | 3360 | src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; |
| 3361 | src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3362 | |
| 3363 | switch (src_id) { |
| 3364 | case 1: /* D1 vblank/vline */ |
| 3365 | switch (src_data) { |
| 3366 | case 0: /* D1 vblank */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3367 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3368 | if (rdev->irq.crtc_vblank_int[0]) { |
| 3369 | drm_handle_vblank(rdev->ddev, 0); |
| 3370 | rdev->pm.vblank_sync = true; |
| 3371 | wake_up(&rdev->irq.vblank_queue); |
| 3372 | } |
Mario Kleiner | 3e4ea74 | 2010-11-21 10:59:02 -0500 | [diff] [blame] | 3373 | if (rdev->irq.pflip[0]) |
| 3374 | radeon_crtc_handle_flip(rdev, 0); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3375 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3376 | DRM_DEBUG("IH: D1 vblank\n"); |
| 3377 | } |
| 3378 | break; |
| 3379 | case 1: /* D1 vline */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3380 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { |
| 3381 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3382 | DRM_DEBUG("IH: D1 vline\n"); |
| 3383 | } |
| 3384 | break; |
| 3385 | default: |
Alex Deucher | b042589 | 2010-01-11 19:47:38 -0500 | [diff] [blame] | 3386 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3387 | break; |
| 3388 | } |
| 3389 | break; |
| 3390 | case 5: /* D2 vblank/vline */ |
| 3391 | switch (src_data) { |
| 3392 | case 0: /* D2 vblank */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3393 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3394 | if (rdev->irq.crtc_vblank_int[1]) { |
| 3395 | drm_handle_vblank(rdev->ddev, 1); |
| 3396 | rdev->pm.vblank_sync = true; |
| 3397 | wake_up(&rdev->irq.vblank_queue); |
| 3398 | } |
Mario Kleiner | 3e4ea74 | 2010-11-21 10:59:02 -0500 | [diff] [blame] | 3399 | if (rdev->irq.pflip[1]) |
| 3400 | radeon_crtc_handle_flip(rdev, 1); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3401 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3402 | DRM_DEBUG("IH: D2 vblank\n"); |
| 3403 | } |
| 3404 | break; |
| 3405 | case 1: /* D1 vline */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3406 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { |
| 3407 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3408 | DRM_DEBUG("IH: D2 vline\n"); |
| 3409 | } |
| 3410 | break; |
| 3411 | default: |
Alex Deucher | b042589 | 2010-01-11 19:47:38 -0500 | [diff] [blame] | 3412 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3413 | break; |
| 3414 | } |
| 3415 | break; |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3416 | case 19: /* HPD/DAC hotplug */ |
| 3417 | switch (src_data) { |
| 3418 | case 0: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3419 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { |
| 3420 | rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3421 | queue_hotplug = true; |
| 3422 | DRM_DEBUG("IH: HPD1\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3423 | } |
| 3424 | break; |
| 3425 | case 1: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3426 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { |
| 3427 | rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3428 | queue_hotplug = true; |
| 3429 | DRM_DEBUG("IH: HPD2\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3430 | } |
| 3431 | break; |
| 3432 | case 4: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3433 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { |
| 3434 | rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3435 | queue_hotplug = true; |
| 3436 | DRM_DEBUG("IH: HPD3\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3437 | } |
| 3438 | break; |
| 3439 | case 5: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3440 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { |
| 3441 | rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3442 | queue_hotplug = true; |
| 3443 | DRM_DEBUG("IH: HPD4\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3444 | } |
| 3445 | break; |
| 3446 | case 10: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3447 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { |
| 3448 | rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3449 | queue_hotplug = true; |
| 3450 | DRM_DEBUG("IH: HPD5\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3451 | } |
| 3452 | break; |
| 3453 | case 12: |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 3454 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
| 3455 | rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3456 | queue_hotplug = true; |
| 3457 | DRM_DEBUG("IH: HPD6\n"); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3458 | } |
| 3459 | break; |
| 3460 | default: |
Alex Deucher | b042589 | 2010-01-11 19:47:38 -0500 | [diff] [blame] | 3461 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
Alex Deucher | e0df1ac | 2009-12-04 15:12:21 -0500 | [diff] [blame] | 3462 | break; |
| 3463 | } |
| 3464 | break; |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 3465 | case 21: /* HDMI */ |
| 3466 | DRM_DEBUG("IH: HDMI: 0x%x\n", src_data); |
| 3467 | r600_audio_schedule_polling(rdev); |
| 3468 | break; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3469 | case 176: /* CP_INT in ring buffer */ |
| 3470 | case 177: /* CP_INT in IB1 */ |
| 3471 | case 178: /* CP_INT in IB2 */ |
| 3472 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 3473 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3474 | break; |
| 3475 | case 181: /* CP EOP event */ |
| 3476 | DRM_DEBUG("IH: CP EOP\n"); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 3477 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3478 | break; |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 3479 | case 233: /* GUI IDLE */ |
Ilija Hadzic | 303c805 | 2011-06-07 14:54:48 -0400 | [diff] [blame] | 3480 | DRM_DEBUG("IH: GUI idle\n"); |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 3481 | rdev->pm.gui_idle = true; |
| 3482 | wake_up(&rdev->irq.idle_queue); |
| 3483 | break; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3484 | default: |
Alex Deucher | b042589 | 2010-01-11 19:47:38 -0500 | [diff] [blame] | 3485 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3486 | break; |
| 3487 | } |
| 3488 | |
| 3489 | /* wptr/rptr are in bytes! */ |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 3490 | rptr += 16; |
| 3491 | rptr &= rdev->ih.ptr_mask; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3492 | } |
| 3493 | /* make sure wptr hasn't changed while processing */ |
| 3494 | wptr = r600_get_ih_wptr(rdev); |
| 3495 | if (wptr != rdev->ih.wptr) |
| 3496 | goto restart_ih; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 3497 | if (queue_hotplug) |
Tejun Heo | 32c87fc | 2011-01-03 14:49:32 +0100 | [diff] [blame] | 3498 | schedule_work(&rdev->hotplug_work); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 3499 | rdev->ih.rptr = rptr; |
| 3500 | WREG32(IH_RB_RPTR, rdev->ih.rptr); |
| 3501 | spin_unlock_irqrestore(&rdev->ih.lock, flags); |
| 3502 | return IRQ_HANDLED; |
| 3503 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3504 | |
| 3505 | /* |
| 3506 | * Debugfs info |
| 3507 | */ |
| 3508 | #if defined(CONFIG_DEBUG_FS) |
| 3509 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3510 | static int r600_debugfs_mc_info(struct seq_file *m, void *data) |
| 3511 | { |
| 3512 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 3513 | struct drm_device *dev = node->minor->dev; |
| 3514 | struct radeon_device *rdev = dev->dev_private; |
| 3515 | |
| 3516 | DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); |
| 3517 | DREG32_SYS(m, rdev, VM_L2_STATUS); |
| 3518 | return 0; |
| 3519 | } |
| 3520 | |
| 3521 | static struct drm_info_list r600_mc_info_list[] = { |
| 3522 | {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3523 | }; |
| 3524 | #endif |
| 3525 | |
| 3526 | int r600_debugfs_mc_info_init(struct radeon_device *rdev) |
| 3527 | { |
| 3528 | #if defined(CONFIG_DEBUG_FS) |
| 3529 | return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); |
| 3530 | #else |
| 3531 | return 0; |
| 3532 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3533 | } |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 3534 | |
| 3535 | /** |
| 3536 | * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl |
| 3537 | * rdev: radeon device structure |
| 3538 | * bo: buffer object struct which userspace is waiting for idle |
| 3539 | * |
| 3540 | * Some R6XX/R7XX doesn't seems to take into account HDP flush performed |
| 3541 | * through ring buffer, this leads to corruption in rendering, see |
| 3542 | * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we |
| 3543 | * directly perform HDP flush by writing register through MMIO. |
| 3544 | */ |
| 3545 | void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) |
| 3546 | { |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 3547 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read |
Alex Deucher | f3886f8 | 2010-12-08 10:05:34 -0500 | [diff] [blame] | 3548 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. |
| 3549 | * This seems to cause problems on some AGP cards. Just use the old |
| 3550 | * method for them. |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 3551 | */ |
Alex Deucher | e488459 | 2010-09-27 10:57:10 -0400 | [diff] [blame] | 3552 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
Alex Deucher | f3886f8 | 2010-12-08 10:05:34 -0500 | [diff] [blame] | 3553 | rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 3554 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
Alex Deucher | 812d046 | 2010-07-26 18:51:53 -0400 | [diff] [blame] | 3555 | u32 tmp; |
| 3556 | |
| 3557 | WREG32(HDP_DEBUG1, 0); |
| 3558 | tmp = readl((void __iomem *)ptr); |
| 3559 | } else |
| 3560 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 3561 | } |
Alex Deucher | 3313e3d | 2011-01-06 18:49:34 -0500 | [diff] [blame] | 3562 | |
| 3563 | void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
| 3564 | { |
| 3565 | u32 link_width_cntl, mask, target_reg; |
| 3566 | |
| 3567 | if (rdev->flags & RADEON_IS_IGP) |
| 3568 | return; |
| 3569 | |
| 3570 | if (!(rdev->flags & RADEON_IS_PCIE)) |
| 3571 | return; |
| 3572 | |
| 3573 | /* x2 cards have a special sequence */ |
| 3574 | if (ASIC_IS_X2(rdev)) |
| 3575 | return; |
| 3576 | |
| 3577 | /* FIXME wait for idle */ |
| 3578 | |
| 3579 | switch (lanes) { |
| 3580 | case 0: |
| 3581 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; |
| 3582 | break; |
| 3583 | case 1: |
| 3584 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; |
| 3585 | break; |
| 3586 | case 2: |
| 3587 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; |
| 3588 | break; |
| 3589 | case 4: |
| 3590 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; |
| 3591 | break; |
| 3592 | case 8: |
| 3593 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; |
| 3594 | break; |
| 3595 | case 12: |
| 3596 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; |
| 3597 | break; |
| 3598 | case 16: |
| 3599 | default: |
| 3600 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; |
| 3601 | break; |
| 3602 | } |
| 3603 | |
| 3604 | link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
| 3605 | |
| 3606 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == |
| 3607 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) |
| 3608 | return; |
| 3609 | |
| 3610 | if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS) |
| 3611 | return; |
| 3612 | |
| 3613 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | |
| 3614 | RADEON_PCIE_LC_RECONFIG_NOW | |
| 3615 | R600_PCIE_LC_RENEGOTIATE_EN | |
| 3616 | R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); |
| 3617 | link_width_cntl |= mask; |
| 3618 | |
| 3619 | WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 3620 | |
| 3621 | /* some northbridges can renegotiate the link rather than requiring |
| 3622 | * a complete re-config. |
| 3623 | * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) |
| 3624 | */ |
| 3625 | if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT) |
| 3626 | link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT; |
| 3627 | else |
| 3628 | link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; |
| 3629 | |
| 3630 | WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | |
| 3631 | RADEON_PCIE_LC_RECONFIG_NOW)); |
| 3632 | |
| 3633 | if (rdev->family >= CHIP_RV770) |
| 3634 | target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; |
| 3635 | else |
| 3636 | target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; |
| 3637 | |
| 3638 | /* wait for lane set to complete */ |
| 3639 | link_width_cntl = RREG32(target_reg); |
| 3640 | while (link_width_cntl == 0xffffffff) |
| 3641 | link_width_cntl = RREG32(target_reg); |
| 3642 | |
| 3643 | } |
| 3644 | |
| 3645 | int r600_get_pcie_lanes(struct radeon_device *rdev) |
| 3646 | { |
| 3647 | u32 link_width_cntl; |
| 3648 | |
| 3649 | if (rdev->flags & RADEON_IS_IGP) |
| 3650 | return 0; |
| 3651 | |
| 3652 | if (!(rdev->flags & RADEON_IS_PCIE)) |
| 3653 | return 0; |
| 3654 | |
| 3655 | /* x2 cards have a special sequence */ |
| 3656 | if (ASIC_IS_X2(rdev)) |
| 3657 | return 0; |
| 3658 | |
| 3659 | /* FIXME wait for idle */ |
| 3660 | |
| 3661 | link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
| 3662 | |
| 3663 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { |
| 3664 | case RADEON_PCIE_LC_LINK_WIDTH_X0: |
| 3665 | return 0; |
| 3666 | case RADEON_PCIE_LC_LINK_WIDTH_X1: |
| 3667 | return 1; |
| 3668 | case RADEON_PCIE_LC_LINK_WIDTH_X2: |
| 3669 | return 2; |
| 3670 | case RADEON_PCIE_LC_LINK_WIDTH_X4: |
| 3671 | return 4; |
| 3672 | case RADEON_PCIE_LC_LINK_WIDTH_X8: |
| 3673 | return 8; |
| 3674 | case RADEON_PCIE_LC_LINK_WIDTH_X16: |
| 3675 | default: |
| 3676 | return 16; |
| 3677 | } |
| 3678 | } |
| 3679 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 3680 | static void r600_pcie_gen2_enable(struct radeon_device *rdev) |
| 3681 | { |
| 3682 | u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; |
| 3683 | u16 link_cntl2; |
| 3684 | |
Alex Deucher | d42dd57 | 2011-01-12 20:05:11 -0500 | [diff] [blame] | 3685 | if (radeon_pcie_gen2 == 0) |
| 3686 | return; |
| 3687 | |
Alex Deucher | 9e46a48 | 2011-01-06 18:49:35 -0500 | [diff] [blame] | 3688 | if (rdev->flags & RADEON_IS_IGP) |
| 3689 | return; |
| 3690 | |
| 3691 | if (!(rdev->flags & RADEON_IS_PCIE)) |
| 3692 | return; |
| 3693 | |
| 3694 | /* x2 cards have a special sequence */ |
| 3695 | if (ASIC_IS_X2(rdev)) |
| 3696 | return; |
| 3697 | |
| 3698 | /* only RV6xx+ chips are supported */ |
| 3699 | if (rdev->family <= CHIP_R600) |
| 3700 | return; |
| 3701 | |
| 3702 | /* 55 nm r6xx asics */ |
| 3703 | if ((rdev->family == CHIP_RV670) || |
| 3704 | (rdev->family == CHIP_RV620) || |
| 3705 | (rdev->family == CHIP_RV635)) { |
| 3706 | /* advertise upconfig capability */ |
| 3707 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
| 3708 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
| 3709 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 3710 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
| 3711 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { |
| 3712 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; |
| 3713 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | |
| 3714 | LC_RECONFIG_ARC_MISSING_ESCAPE); |
| 3715 | link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; |
| 3716 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 3717 | } else { |
| 3718 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
| 3719 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 3720 | } |
| 3721 | } |
| 3722 | |
| 3723 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 3724 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && |
| 3725 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |
| 3726 | |
| 3727 | /* 55 nm r6xx asics */ |
| 3728 | if ((rdev->family == CHIP_RV670) || |
| 3729 | (rdev->family == CHIP_RV620) || |
| 3730 | (rdev->family == CHIP_RV635)) { |
| 3731 | WREG32(MM_CFGREGS_CNTL, 0x8); |
| 3732 | link_cntl2 = RREG32(0x4088); |
| 3733 | WREG32(MM_CFGREGS_CNTL, 0); |
| 3734 | /* not supported yet */ |
| 3735 | if (link_cntl2 & SELECTABLE_DEEMPHASIS) |
| 3736 | return; |
| 3737 | } |
| 3738 | |
| 3739 | speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; |
| 3740 | speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); |
| 3741 | speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; |
| 3742 | speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; |
| 3743 | speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; |
| 3744 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
| 3745 | |
| 3746 | tmp = RREG32(0x541c); |
| 3747 | WREG32(0x541c, tmp | 0x8); |
| 3748 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); |
| 3749 | link_cntl2 = RREG16(0x4088); |
| 3750 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; |
| 3751 | link_cntl2 |= 0x2; |
| 3752 | WREG16(0x4088, link_cntl2); |
| 3753 | WREG32(MM_CFGREGS_CNTL, 0); |
| 3754 | |
| 3755 | if ((rdev->family == CHIP_RV670) || |
| 3756 | (rdev->family == CHIP_RV620) || |
| 3757 | (rdev->family == CHIP_RV635)) { |
| 3758 | training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); |
| 3759 | training_cntl &= ~LC_POINT_7_PLUS_EN; |
| 3760 | WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); |
| 3761 | } else { |
| 3762 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 3763 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; |
| 3764 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
| 3765 | } |
| 3766 | |
| 3767 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
| 3768 | speed_cntl |= LC_GEN2_EN_STRAP; |
| 3769 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
| 3770 | |
| 3771 | } else { |
| 3772 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
| 3773 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ |
| 3774 | if (1) |
| 3775 | link_width_cntl |= LC_UPCONFIGURE_DIS; |
| 3776 | else |
| 3777 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
| 3778 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
| 3779 | } |
| 3780 | } |