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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020043#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050044#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
Jeff Garzik7bdd7202005-11-16 11:06:59 -050051#define DRV_VERSION "1.2"
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
Jeff Garzika0ea7322005-06-04 01:13:15 -040062 AHCI_CMD_TBL_CDB = 0x40,
Linus Torvalds1da177e2005-04-16 15:20:36 -070063 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69
70 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
71
72 board_ahci = 0,
73
74 /* global controller registers */
75 HOST_CAP = 0x00, /* host capabilities */
76 HOST_CTL = 0x04, /* global host control */
77 HOST_IRQ_STAT = 0x08, /* interrupt status */
78 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
79 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
80
81 /* HOST_CTL bits */
82 HOST_RESET = (1 << 0), /* reset controller; self-clear */
83 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
84 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
85
86 /* HOST_CAP bits */
87 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
88
89 /* registers for each SATA port */
90 PORT_LST_ADDR = 0x00, /* command list DMA addr */
91 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
92 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
93 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
94 PORT_IRQ_STAT = 0x10, /* interrupt status */
95 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
96 PORT_CMD = 0x18, /* port command */
97 PORT_TFDATA = 0x20, /* taskfile data */
98 PORT_SIG = 0x24, /* device TF signature */
99 PORT_CMD_ISSUE = 0x38, /* command issue */
100 PORT_SCR = 0x28, /* SATA phy register block */
101 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
102 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
103 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
104 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
105
106 /* PORT_IRQ_{STAT,MASK} bits */
107 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
108 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
109 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
110 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
111 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
112 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
113 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
114 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
115
116 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
117 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
118 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
119 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
120 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
121 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
122 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
123 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
124 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
125
126 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
127 PORT_IRQ_HBUS_ERR |
128 PORT_IRQ_HBUS_DATA_ERR |
129 PORT_IRQ_IF_ERR,
130 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
131 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
132 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
133 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
134 PORT_IRQ_D2H_REG_FIS,
135
136 /* PORT_CMD bits */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500137 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
139 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
140 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
141 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
142 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
143 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
144
145 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
146 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
147 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400148
149 /* hpriv->flags bits */
150 AHCI_FLAG_MSI = (1 << 0),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151};
152
153struct ahci_cmd_hdr {
154 u32 opts;
155 u32 status;
156 u32 tbl_addr;
157 u32 tbl_addr_hi;
158 u32 reserved[4];
159};
160
161struct ahci_sg {
162 u32 addr;
163 u32 addr_hi;
164 u32 reserved;
165 u32 flags_size;
166};
167
168struct ahci_host_priv {
169 unsigned long flags;
170 u32 cap; /* cache of HOST_CAP register */
171 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
172};
173
174struct ahci_port_priv {
175 struct ahci_cmd_hdr *cmd_slot;
176 dma_addr_t cmd_slot_dma;
177 void *cmd_tbl;
178 dma_addr_t cmd_tbl_dma;
179 struct ahci_sg *cmd_tbl_sg;
180 void *rx_fis;
181 dma_addr_t rx_fis_dma;
182};
183
184static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
185static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
186static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
187static int ahci_qc_issue(struct ata_queued_cmd *qc);
188static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
189static void ahci_phy_reset(struct ata_port *ap);
190static void ahci_irq_clear(struct ata_port *ap);
191static void ahci_eng_timeout(struct ata_port *ap);
192static int ahci_port_start(struct ata_port *ap);
193static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
195static void ahci_qc_prep(struct ata_queued_cmd *qc);
196static u8 ahci_check_status(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
Jeff Garzik907f4672005-05-12 15:03:42 -0400198static void ahci_remove_one (struct pci_dev *pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199
Jeff Garzik193515d2005-11-07 00:59:37 -0500200static struct scsi_host_template ahci_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 .module = THIS_MODULE,
202 .name = DRV_NAME,
203 .ioctl = ata_scsi_ioctl,
204 .queuecommand = ata_scsi_queuecmd,
205 .eh_strategy_handler = ata_scsi_error,
206 .can_queue = ATA_DEF_QUEUE,
207 .this_id = ATA_SHT_THIS_ID,
208 .sg_tablesize = AHCI_MAX_SG,
209 .max_sectors = ATA_MAX_SECTORS,
210 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
211 .emulated = ATA_SHT_EMULATED,
212 .use_clustering = AHCI_USE_CLUSTERING,
213 .proc_name = DRV_NAME,
214 .dma_boundary = AHCI_DMA_BOUNDARY,
215 .slave_configure = ata_scsi_slave_config,
216 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217};
218
Jeff Garzik057ace52005-10-22 14:27:05 -0400219static const struct ata_port_operations ahci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 .port_disable = ata_port_disable,
221
222 .check_status = ahci_check_status,
223 .check_altstatus = ahci_check_status,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 .dev_select = ata_noop_dev_select,
225
226 .tf_read = ahci_tf_read,
227
228 .phy_reset = ahci_phy_reset,
229
230 .qc_prep = ahci_qc_prep,
231 .qc_issue = ahci_qc_issue,
232
233 .eng_timeout = ahci_eng_timeout,
234
235 .irq_handler = ahci_interrupt,
236 .irq_clear = ahci_irq_clear,
237
238 .scr_read = ahci_scr_read,
239 .scr_write = ahci_scr_write,
240
241 .port_start = ahci_port_start,
242 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243};
244
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100245static const struct ata_port_info ahci_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 /* board_ahci */
247 {
248 .sht = &ahci_sht,
249 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
250 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
251 ATA_FLAG_PIO_DMA,
Brett Russ7da79312005-09-01 21:53:34 -0400252 .pio_mask = 0x1f, /* pio0-4 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
254 .port_ops = &ahci_ops,
255 },
256};
257
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500258static const struct pci_device_id ahci_pci_tbl[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
260 board_ahci }, /* ICH6 */
261 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 board_ahci }, /* ICH6M */
263 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_ahci }, /* ICH7 */
265 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_ahci }, /* ICH7M */
267 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_ahci }, /* ICH7R */
269 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_ahci }, /* ULi M5288 */
Jason Gaston680d3232005-04-16 15:24:45 -0700271 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
272 board_ahci }, /* ESB2 */
273 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
274 board_ahci }, /* ESB2 */
275 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
276 board_ahci }, /* ESB2 */
Jason Gaston3db368f2005-08-10 06:18:43 -0700277 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
278 board_ahci }, /* ICH7-M DH */
Jason Gastonf2857572006-01-09 11:09:13 -0800279 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
280 board_ahci }, /* ICH8 */
281 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
282 board_ahci }, /* ICH8 */
283 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
284 board_ahci }, /* ICH8 */
285 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
286 board_ahci }, /* ICH8M */
287 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
288 board_ahci }, /* ICH8M */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 { } /* terminate list */
290};
291
292
293static struct pci_driver ahci_pci_driver = {
294 .name = DRV_NAME,
295 .id_table = ahci_pci_tbl,
296 .probe = ahci_init_one,
Jeff Garzik907f4672005-05-12 15:03:42 -0400297 .remove = ahci_remove_one,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298};
299
300
301static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
302{
303 return base + 0x100 + (port * 0x80);
304}
305
Jeff Garzikea6ba102005-08-30 05:18:18 -0400306static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400308 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309}
310
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311static int ahci_port_start(struct ata_port *ap)
312{
313 struct device *dev = ap->host_set->dev;
314 struct ahci_host_priv *hpriv = ap->host_set->private_data;
315 struct ahci_port_priv *pp;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400316 void __iomem *mmio = ap->host_set->mmio_base;
317 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
318 void *mem;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 dma_addr_t mem_dma;
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500320 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
Tejun Heo0a139e72005-06-26 23:52:50 +0900323 if (!pp)
324 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 memset(pp, 0, sizeof(*pp));
326
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500327 rc = ata_pad_alloc(ap, dev);
328 if (rc) {
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400329 kfree(pp);
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500330 return rc;
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400331 }
332
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
334 if (!mem) {
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500335 ata_pad_free(ap, dev);
Tejun Heo0a139e72005-06-26 23:52:50 +0900336 kfree(pp);
337 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338 }
339 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
340
341 /*
342 * First item in chunk of DMA memory: 32-slot command table,
343 * 32 bytes each in size
344 */
345 pp->cmd_slot = mem;
346 pp->cmd_slot_dma = mem_dma;
347
348 mem += AHCI_CMD_SLOT_SZ;
349 mem_dma += AHCI_CMD_SLOT_SZ;
350
351 /*
352 * Second item: Received-FIS area
353 */
354 pp->rx_fis = mem;
355 pp->rx_fis_dma = mem_dma;
356
357 mem += AHCI_RX_FIS_SZ;
358 mem_dma += AHCI_RX_FIS_SZ;
359
360 /*
361 * Third item: data area for storing a single command
362 * and its scatter-gather table
363 */
364 pp->cmd_tbl = mem;
365 pp->cmd_tbl_dma = mem_dma;
366
367 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
368
369 ap->private_data = pp;
370
371 if (hpriv->cap & HOST_CAP_64)
372 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
373 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
374 readl(port_mmio + PORT_LST_ADDR); /* flush */
375
376 if (hpriv->cap & HOST_CAP_64)
377 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
378 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
379 readl(port_mmio + PORT_FIS_ADDR); /* flush */
380
381 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
382 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
383 PORT_CMD_START, port_mmio + PORT_CMD);
384 readl(port_mmio + PORT_CMD); /* flush */
385
386 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387}
388
389
390static void ahci_port_stop(struct ata_port *ap)
391{
392 struct device *dev = ap->host_set->dev;
393 struct ahci_port_priv *pp = ap->private_data;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400394 void __iomem *mmio = ap->host_set->mmio_base;
395 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 u32 tmp;
397
398 tmp = readl(port_mmio + PORT_CMD);
399 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
400 writel(tmp, port_mmio + PORT_CMD);
401 readl(port_mmio + PORT_CMD); /* flush */
402
403 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
404 * this is slightly incorrect.
405 */
406 msleep(500);
407
408 ap->private_data = NULL;
409 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
410 pp->cmd_slot, pp->cmd_slot_dma);
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500411 ata_pad_free(ap, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 kfree(pp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413}
414
415static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
416{
417 unsigned int sc_reg;
418
419 switch (sc_reg_in) {
420 case SCR_STATUS: sc_reg = 0; break;
421 case SCR_CONTROL: sc_reg = 1; break;
422 case SCR_ERROR: sc_reg = 2; break;
423 case SCR_ACTIVE: sc_reg = 3; break;
424 default:
425 return 0xffffffffU;
426 }
427
Al Viro1e4f2a92005-10-21 06:46:02 +0100428 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429}
430
431
432static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
433 u32 val)
434{
435 unsigned int sc_reg;
436
437 switch (sc_reg_in) {
438 case SCR_STATUS: sc_reg = 0; break;
439 case SCR_CONTROL: sc_reg = 1; break;
440 case SCR_ERROR: sc_reg = 2; break;
441 case SCR_ACTIVE: sc_reg = 3; break;
442 default:
443 return;
444 }
445
Al Viro1e4f2a92005-10-21 06:46:02 +0100446 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447}
448
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900449static int ahci_stop_engine(struct ata_port *ap)
450{
451 void __iomem *mmio = ap->host_set->mmio_base;
452 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
453 int work;
454 u32 tmp;
455
456 tmp = readl(port_mmio + PORT_CMD);
457 tmp &= ~PORT_CMD_START;
458 writel(tmp, port_mmio + PORT_CMD);
459
460 /* wait for engine to stop. TODO: this could be
461 * as long as 500 msec
462 */
463 work = 1000;
464 while (work-- > 0) {
465 tmp = readl(port_mmio + PORT_CMD);
466 if ((tmp & PORT_CMD_LIST_ON) == 0)
467 return 0;
468 udelay(10);
469 }
470
471 return -EIO;
472}
473
474static void ahci_start_engine(struct ata_port *ap)
475{
476 void __iomem *mmio = ap->host_set->mmio_base;
477 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
478 u32 tmp;
479
480 tmp = readl(port_mmio + PORT_CMD);
481 tmp |= PORT_CMD_START;
482 writel(tmp, port_mmio + PORT_CMD);
483 readl(port_mmio + PORT_CMD); /* flush */
484}
485
Tejun Heo422b7592005-12-19 22:37:17 +0900486static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487{
488 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
489 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +0900490 u32 tmp;
491
492 tmp = readl(port_mmio + PORT_SIG);
493 tf.lbah = (tmp >> 24) & 0xff;
494 tf.lbam = (tmp >> 16) & 0xff;
495 tf.lbal = (tmp >> 8) & 0xff;
496 tf.nsect = (tmp) & 0xff;
497
498 return ata_dev_classify(&tf);
499}
500
501static void ahci_phy_reset(struct ata_port *ap)
502{
503 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504 struct ata_device *dev = &ap->device[0];
Jeff Garzik02eaa662005-11-12 01:32:19 -0500505 u32 new_tmp, tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506
507 __sata_phy_reset(ap);
508
509 if (ap->flags & ATA_FLAG_PORT_DISABLED)
510 return;
511
Tejun Heo422b7592005-12-19 22:37:17 +0900512 dev->class = ahci_dev_classify(ap);
Jeff Garzik02eaa662005-11-12 01:32:19 -0500513 if (!ata_dev_present(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514 ata_port_disable(ap);
Jeff Garzik02eaa662005-11-12 01:32:19 -0500515 return;
516 }
517
518 /* Make sure port's ATAPI bit is set appropriately */
519 new_tmp = tmp = readl(port_mmio + PORT_CMD);
520 if (dev->class == ATA_DEV_ATAPI)
521 new_tmp |= PORT_CMD_ATAPI;
522 else
523 new_tmp &= ~PORT_CMD_ATAPI;
524 if (new_tmp != tmp) {
525 writel(new_tmp, port_mmio + PORT_CMD);
526 readl(port_mmio + PORT_CMD); /* flush */
527 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528}
529
530static u8 ahci_check_status(struct ata_port *ap)
531{
Al Viro1e4f2a92005-10-21 06:46:02 +0100532 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533
534 return readl(mmio + PORT_TFDATA) & 0xFF;
535}
536
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
538{
539 struct ahci_port_priv *pp = ap->private_data;
540 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
541
542 ata_tf_from_fis(d2h_fis, tf);
543}
544
Jeff Garzik828d09d2005-11-12 01:27:07 -0500545static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546{
547 struct ahci_port_priv *pp = qc->ap->private_data;
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400548 struct scatterlist *sg;
549 struct ahci_sg *ahci_sg;
Jeff Garzik828d09d2005-11-12 01:27:07 -0500550 unsigned int n_sg = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551
552 VPRINTK("ENTER\n");
553
554 /*
555 * Next, the S/G list.
556 */
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400557 ahci_sg = pp->cmd_tbl_sg;
558 ata_for_each_sg(sg, qc) {
559 dma_addr_t addr = sg_dma_address(sg);
560 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400562 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
563 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
564 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
Jeff Garzik828d09d2005-11-12 01:27:07 -0500565
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400566 ahci_sg++;
Jeff Garzik828d09d2005-11-12 01:27:07 -0500567 n_sg++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568 }
Jeff Garzik828d09d2005-11-12 01:27:07 -0500569
570 return n_sg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571}
572
573static void ahci_qc_prep(struct ata_queued_cmd *qc)
574{
Jeff Garzika0ea7322005-06-04 01:13:15 -0400575 struct ata_port *ap = qc->ap;
576 struct ahci_port_priv *pp = ap->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577 u32 opts;
578 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -0500579 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580
581 /*
582 * Fill in command slot information (currently only one slot,
583 * slot 0, is currently since we don't do queueing)
584 */
585
Jeff Garzik828d09d2005-11-12 01:27:07 -0500586 opts = cmd_fis_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700587 if (qc->tf.flags & ATA_TFLAG_WRITE)
588 opts |= AHCI_CMD_WRITE;
Jeff Garzika0ea7322005-06-04 01:13:15 -0400589 if (is_atapi_taskfile(&qc->tf))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590 opts |= AHCI_CMD_ATAPI;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591
592 pp->cmd_slot[0].opts = cpu_to_le32(opts);
593 pp->cmd_slot[0].status = 0;
594 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
595 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
596
597 /*
598 * Fill in command table information. First, the header,
599 * a SATA Register - Host to Device command FIS.
600 */
601 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
Jeff Garzika0ea7322005-06-04 01:13:15 -0400602 if (opts & AHCI_CMD_ATAPI) {
603 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
604 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
605 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606
607 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
608 return;
609
Jeff Garzik828d09d2005-11-12 01:27:07 -0500610 n_elem = ahci_fill_sg(qc);
611
612 pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700613}
614
Jeff Garzikc2cd76f2005-11-16 09:23:30 -0500615static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400617 void __iomem *mmio = ap->host_set->mmio_base;
618 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619 u32 tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620
Jeff Garzikc2cd76f2005-11-16 09:23:30 -0500621 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
622 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
623 printk(KERN_WARNING "ata%u: port reset, "
624 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
625 ap->id,
626 irq_stat,
627 readl(mmio + HOST_IRQ_STAT),
628 readl(port_mmio + PORT_IRQ_STAT),
629 readl(port_mmio + PORT_CMD),
630 readl(port_mmio + PORT_TFDATA),
631 readl(port_mmio + PORT_SCR_STAT),
632 readl(port_mmio + PORT_SCR_ERR));
Jeff Garzik9f68a242005-11-15 14:03:47 -0500633
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 /* stop DMA */
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900635 ahci_stop_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636
637 /* clear SATA phy error, if any */
638 tmp = readl(port_mmio + PORT_SCR_ERR);
639 writel(tmp, port_mmio + PORT_SCR_ERR);
640
641 /* if DRQ/BSY is set, device needs to be reset.
642 * if so, issue COMRESET
643 */
644 tmp = readl(port_mmio + PORT_TFDATA);
645 if (tmp & (ATA_BUSY | ATA_DRQ)) {
646 writel(0x301, port_mmio + PORT_SCR_CTL);
647 readl(port_mmio + PORT_SCR_CTL); /* flush */
648 udelay(10);
649 writel(0x300, port_mmio + PORT_SCR_CTL);
650 readl(port_mmio + PORT_SCR_CTL); /* flush */
651 }
652
653 /* re-start DMA */
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900654 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655}
656
657static void ahci_eng_timeout(struct ata_port *ap)
658{
Jeff Garzikb8f61532005-08-25 22:01:20 -0400659 struct ata_host_set *host_set = ap->host_set;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400660 void __iomem *mmio = host_set->mmio_base;
661 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662 struct ata_queued_cmd *qc;
Jeff Garzikb8f61532005-08-25 22:01:20 -0400663 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664
Jeff Garzik9f68a242005-11-15 14:03:47 -0500665 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666
Jeff Garzikb8f61532005-08-25 22:01:20 -0400667 spin_lock_irqsave(&host_set->lock, flags);
668
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 qc = ata_qc_from_tag(ap, ap->active_tag);
670 if (!qc) {
671 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
672 ap->id);
673 } else {
Jeff Garzikc2cd76f2005-11-16 09:23:30 -0500674 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
Jeff Garzikad36d1a2005-11-14 13:56:37 -0500675
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676 /* hack alert! We cannot use the supplied completion
677 * function from inside the ->eh_strategy_handler() thread.
678 * libata is the only user of ->eh_strategy_handler() in
679 * any kernel, so the default scsi_done() assumes it is
680 * not being called from the SCSI EH.
681 */
682 qc->scsidone = scsi_finish_command;
Albert Leea22e2eb2005-12-05 15:38:02 +0800683 qc->err_mask |= AC_ERR_OTHER;
684 ata_qc_complete(qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700685 }
686
Jeff Garzikb8f61532005-08-25 22:01:20 -0400687 spin_unlock_irqrestore(&host_set->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688}
689
690static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
691{
Jeff Garzikea6ba102005-08-30 05:18:18 -0400692 void __iomem *mmio = ap->host_set->mmio_base;
693 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694 u32 status, serr, ci;
695
696 serr = readl(port_mmio + PORT_SCR_ERR);
697 writel(serr, port_mmio + PORT_SCR_ERR);
698
699 status = readl(port_mmio + PORT_IRQ_STAT);
700 writel(status, port_mmio + PORT_IRQ_STAT);
701
702 ci = readl(port_mmio + PORT_CMD_ISSUE);
703 if (likely((ci & 0x1) == 0)) {
704 if (qc) {
Albert Leea22e2eb2005-12-05 15:38:02 +0800705 assert(qc->err_mask == 0);
706 ata_qc_complete(qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707 qc = NULL;
708 }
709 }
710
711 if (status & PORT_IRQ_FATAL) {
Jeff Garzikad36d1a2005-11-14 13:56:37 -0500712 unsigned int err_mask;
713 if (status & PORT_IRQ_TF_ERR)
714 err_mask = AC_ERR_DEV;
715 else if (status & PORT_IRQ_IF_ERR)
716 err_mask = AC_ERR_ATA_BUS;
717 else
718 err_mask = AC_ERR_HOST_BUS;
719
Jeff Garzik9f68a242005-11-15 14:03:47 -0500720 /* command processing has stopped due to error; restart */
Jeff Garzikc2cd76f2005-11-16 09:23:30 -0500721 ahci_restart_port(ap, status);
Jeff Garzik9f68a242005-11-15 14:03:47 -0500722
Albert Leea22e2eb2005-12-05 15:38:02 +0800723 if (qc) {
Tejun Heo284b6482006-01-23 13:09:36 +0900724 qc->err_mask |= err_mask;
Albert Leea22e2eb2005-12-05 15:38:02 +0800725 ata_qc_complete(qc);
726 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727 }
728
729 return 1;
730}
731
732static void ahci_irq_clear(struct ata_port *ap)
733{
734 /* TODO */
735}
736
737static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
738{
739 struct ata_host_set *host_set = dev_instance;
740 struct ahci_host_priv *hpriv;
741 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400742 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743 u32 irq_stat, irq_ack = 0;
744
745 VPRINTK("ENTER\n");
746
747 hpriv = host_set->private_data;
748 mmio = host_set->mmio_base;
749
750 /* sigh. 0xffffffff is a valid return from h/w */
751 irq_stat = readl(mmio + HOST_IRQ_STAT);
752 irq_stat &= hpriv->port_map;
753 if (!irq_stat)
754 return IRQ_NONE;
755
756 spin_lock(&host_set->lock);
757
758 for (i = 0; i < host_set->n_ports; i++) {
759 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760
Jeff Garzik67846b32005-10-05 02:58:32 -0400761 if (!(irq_stat & (1 << i)))
762 continue;
763
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764 ap = host_set->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -0400765 if (ap) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766 struct ata_queued_cmd *qc;
767 qc = ata_qc_from_tag(ap, ap->active_tag);
Jeff Garzik67846b32005-10-05 02:58:32 -0400768 if (!ahci_host_intr(ap, qc))
769 if (ata_ratelimit()) {
770 struct pci_dev *pdev =
Jeff Garzika9524a72005-10-30 14:39:11 -0500771 to_pci_dev(ap->host_set->dev);
772 dev_printk(KERN_WARNING, &pdev->dev,
773 "unhandled interrupt on port %u\n",
774 i);
Jeff Garzik67846b32005-10-05 02:58:32 -0400775 }
776
777 VPRINTK("port %u\n", i);
778 } else {
779 VPRINTK("port %u (no irq)\n", i);
780 if (ata_ratelimit()) {
781 struct pci_dev *pdev =
Jeff Garzika9524a72005-10-30 14:39:11 -0500782 to_pci_dev(ap->host_set->dev);
783 dev_printk(KERN_WARNING, &pdev->dev,
784 "interrupt on disabled port %u\n", i);
Jeff Garzik67846b32005-10-05 02:58:32 -0400785 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786 }
Jeff Garzik67846b32005-10-05 02:58:32 -0400787
788 irq_ack |= (1 << i);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789 }
790
791 if (irq_ack) {
792 writel(irq_ack, mmio + HOST_IRQ_STAT);
793 handled = 1;
794 }
795
796 spin_unlock(&host_set->lock);
797
798 VPRINTK("EXIT\n");
799
800 return IRQ_RETVAL(handled);
801}
802
803static int ahci_qc_issue(struct ata_queued_cmd *qc)
804{
805 struct ata_port *ap = qc->ap;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400806 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808 writel(1, port_mmio + PORT_CMD_ISSUE);
809 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
810
811 return 0;
812}
813
814static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
815 unsigned int port_idx)
816{
817 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
818 base = ahci_port_base_ul(base, port_idx);
819 VPRINTK("base now==0x%lx\n", base);
820
821 port->cmd_addr = base;
822 port->scr_addr = base + PORT_SCR;
823
824 VPRINTK("EXIT\n");
825}
826
827static int ahci_host_init(struct ata_probe_ent *probe_ent)
828{
829 struct ahci_host_priv *hpriv = probe_ent->private_data;
830 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
831 void __iomem *mmio = probe_ent->mmio_base;
832 u32 tmp, cap_save;
833 u16 tmp16;
834 unsigned int i, j, using_dac;
835 int rc;
836 void __iomem *port_mmio;
837
838 cap_save = readl(mmio + HOST_CAP);
839 cap_save &= ( (1<<28) | (1<<17) );
840 cap_save |= (1 << 27);
841
842 /* global controller reset */
843 tmp = readl(mmio + HOST_CTL);
844 if ((tmp & HOST_RESET) == 0) {
845 writel(tmp | HOST_RESET, mmio + HOST_CTL);
846 readl(mmio + HOST_CTL); /* flush */
847 }
848
849 /* reset must complete within 1 second, or
850 * the hardware should be considered fried.
851 */
852 ssleep(1);
853
854 tmp = readl(mmio + HOST_CTL);
855 if (tmp & HOST_RESET) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500856 dev_printk(KERN_ERR, &pdev->dev,
857 "controller reset failed (0x%x)\n", tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 return -EIO;
859 }
860
861 writel(HOST_AHCI_EN, mmio + HOST_CTL);
862 (void) readl(mmio + HOST_CTL); /* flush */
863 writel(cap_save, mmio + HOST_CAP);
864 writel(0xf, mmio + HOST_PORTS_IMPL);
865 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
866
867 pci_read_config_word(pdev, 0x92, &tmp16);
868 tmp16 |= 0xf;
869 pci_write_config_word(pdev, 0x92, tmp16);
870
871 hpriv->cap = readl(mmio + HOST_CAP);
872 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
873 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
874
875 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
876 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
877
878 using_dac = hpriv->cap & HOST_CAP_64;
879 if (using_dac &&
880 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
881 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
882 if (rc) {
883 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
884 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500885 dev_printk(KERN_ERR, &pdev->dev,
886 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700887 return rc;
888 }
889 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 } else {
891 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
892 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500893 dev_printk(KERN_ERR, &pdev->dev,
894 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895 return rc;
896 }
897 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
898 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500899 dev_printk(KERN_ERR, &pdev->dev,
900 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 return rc;
902 }
903 }
904
905 for (i = 0; i < probe_ent->n_ports; i++) {
906#if 0 /* BIOSen initialize this incorrectly */
907 if (!(hpriv->port_map & (1 << i)))
908 continue;
909#endif
910
911 port_mmio = ahci_port_base(mmio, i);
912 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
913
914 ahci_setup_port(&probe_ent->port[i],
915 (unsigned long) mmio, i);
916
917 /* make sure port is not active */
918 tmp = readl(port_mmio + PORT_CMD);
919 VPRINTK("PORT_CMD 0x%x\n", tmp);
920 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
921 PORT_CMD_FIS_RX | PORT_CMD_START)) {
922 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
923 PORT_CMD_FIS_RX | PORT_CMD_START);
924 writel(tmp, port_mmio + PORT_CMD);
925 readl(port_mmio + PORT_CMD); /* flush */
926
927 /* spec says 500 msecs for each bit, so
928 * this is slightly incorrect.
929 */
930 msleep(500);
931 }
932
933 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
934
935 j = 0;
936 while (j < 100) {
937 msleep(10);
938 tmp = readl(port_mmio + PORT_SCR_STAT);
939 if ((tmp & 0xf) == 0x3)
940 break;
941 j++;
942 }
943
944 tmp = readl(port_mmio + PORT_SCR_ERR);
945 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
946 writel(tmp, port_mmio + PORT_SCR_ERR);
947
948 /* ack any pending irq events for this port */
949 tmp = readl(port_mmio + PORT_IRQ_STAT);
950 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
951 if (tmp)
952 writel(tmp, port_mmio + PORT_IRQ_STAT);
953
954 writel(1 << i, mmio + HOST_IRQ_STAT);
955
956 /* set irq mask (enables interrupts) */
957 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
958 }
959
960 tmp = readl(mmio + HOST_CTL);
961 VPRINTK("HOST_CTL 0x%x\n", tmp);
962 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
963 tmp = readl(mmio + HOST_CTL);
964 VPRINTK("HOST_CTL 0x%x\n", tmp);
965
966 pci_set_master(pdev);
967
968 return 0;
969}
970
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971static void ahci_print_info(struct ata_probe_ent *probe_ent)
972{
973 struct ahci_host_priv *hpriv = probe_ent->private_data;
974 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
Jeff Garzikea6ba102005-08-30 05:18:18 -0400975 void __iomem *mmio = probe_ent->mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976 u32 vers, cap, impl, speed;
977 const char *speed_s;
978 u16 cc;
979 const char *scc_s;
980
981 vers = readl(mmio + HOST_VERSION);
982 cap = hpriv->cap;
983 impl = hpriv->port_map;
984
985 speed = (cap >> 20) & 0xf;
986 if (speed == 1)
987 speed_s = "1.5";
988 else if (speed == 2)
989 speed_s = "3";
990 else
991 speed_s = "?";
992
993 pci_read_config_word(pdev, 0x0a, &cc);
994 if (cc == 0x0101)
995 scc_s = "IDE";
996 else if (cc == 0x0106)
997 scc_s = "SATA";
998 else if (cc == 0x0104)
999 scc_s = "RAID";
1000 else
1001 scc_s = "unknown";
1002
Jeff Garzika9524a72005-10-30 14:39:11 -05001003 dev_printk(KERN_INFO, &pdev->dev,
1004 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1006 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007
1008 (vers >> 24) & 0xff,
1009 (vers >> 16) & 0xff,
1010 (vers >> 8) & 0xff,
1011 vers & 0xff,
1012
1013 ((cap >> 8) & 0x1f) + 1,
1014 (cap & 0x1f) + 1,
1015 speed_s,
1016 impl,
1017 scc_s);
1018
Jeff Garzika9524a72005-10-30 14:39:11 -05001019 dev_printk(KERN_INFO, &pdev->dev,
1020 "flags: "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021 "%s%s%s%s%s%s"
1022 "%s%s%s%s%s%s%s\n"
1023 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024
1025 cap & (1 << 31) ? "64bit " : "",
1026 cap & (1 << 30) ? "ncq " : "",
1027 cap & (1 << 28) ? "ilck " : "",
1028 cap & (1 << 27) ? "stag " : "",
1029 cap & (1 << 26) ? "pm " : "",
1030 cap & (1 << 25) ? "led " : "",
1031
1032 cap & (1 << 24) ? "clo " : "",
1033 cap & (1 << 19) ? "nz " : "",
1034 cap & (1 << 18) ? "only " : "",
1035 cap & (1 << 17) ? "pmp " : "",
1036 cap & (1 << 15) ? "pio " : "",
1037 cap & (1 << 14) ? "slum " : "",
1038 cap & (1 << 13) ? "part " : ""
1039 );
1040}
1041
1042static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1043{
1044 static int printed_version;
1045 struct ata_probe_ent *probe_ent = NULL;
1046 struct ahci_host_priv *hpriv;
1047 unsigned long base;
Jeff Garzikea6ba102005-08-30 05:18:18 -04001048 void __iomem *mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049 unsigned int board_idx = (unsigned int) ent->driver_data;
Jeff Garzik907f4672005-05-12 15:03:42 -04001050 int have_msi, pci_dev_busy = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051 int rc;
1052
1053 VPRINTK("ENTER\n");
1054
1055 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05001056 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057
1058 rc = pci_enable_device(pdev);
1059 if (rc)
1060 return rc;
1061
1062 rc = pci_request_regions(pdev, DRV_NAME);
1063 if (rc) {
1064 pci_dev_busy = 1;
1065 goto err_out;
1066 }
1067
Jeff Garzik907f4672005-05-12 15:03:42 -04001068 if (pci_enable_msi(pdev) == 0)
1069 have_msi = 1;
1070 else {
1071 pci_intx(pdev, 1);
1072 have_msi = 0;
1073 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074
1075 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1076 if (probe_ent == NULL) {
1077 rc = -ENOMEM;
Jeff Garzik907f4672005-05-12 15:03:42 -04001078 goto err_out_msi;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001079 }
1080
1081 memset(probe_ent, 0, sizeof(*probe_ent));
1082 probe_ent->dev = pci_dev_to_dev(pdev);
1083 INIT_LIST_HEAD(&probe_ent->node);
1084
Jeff Garzik374b1872005-08-30 05:42:52 -04001085 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001086 if (mmio_base == NULL) {
1087 rc = -ENOMEM;
1088 goto err_out_free_ent;
1089 }
1090 base = (unsigned long) mmio_base;
1091
1092 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1093 if (!hpriv) {
1094 rc = -ENOMEM;
1095 goto err_out_iounmap;
1096 }
1097 memset(hpriv, 0, sizeof(*hpriv));
1098
1099 probe_ent->sht = ahci_port_info[board_idx].sht;
1100 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1101 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1102 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1103 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1104
1105 probe_ent->irq = pdev->irq;
1106 probe_ent->irq_flags = SA_SHIRQ;
1107 probe_ent->mmio_base = mmio_base;
1108 probe_ent->private_data = hpriv;
1109
Jeff Garzik4b0060f2005-06-04 00:50:22 -04001110 if (have_msi)
1111 hpriv->flags |= AHCI_FLAG_MSI;
Jeff Garzik907f4672005-05-12 15:03:42 -04001112
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113 /* initialize adapter */
1114 rc = ahci_host_init(probe_ent);
1115 if (rc)
1116 goto err_out_hpriv;
1117
1118 ahci_print_info(probe_ent);
1119
1120 /* FIXME: check ata_device_add return value */
1121 ata_device_add(probe_ent);
1122 kfree(probe_ent);
1123
1124 return 0;
1125
1126err_out_hpriv:
1127 kfree(hpriv);
1128err_out_iounmap:
Jeff Garzik374b1872005-08-30 05:42:52 -04001129 pci_iounmap(pdev, mmio_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001130err_out_free_ent:
1131 kfree(probe_ent);
Jeff Garzik907f4672005-05-12 15:03:42 -04001132err_out_msi:
1133 if (have_msi)
1134 pci_disable_msi(pdev);
1135 else
1136 pci_intx(pdev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001137 pci_release_regions(pdev);
1138err_out:
1139 if (!pci_dev_busy)
1140 pci_disable_device(pdev);
1141 return rc;
1142}
1143
Jeff Garzik907f4672005-05-12 15:03:42 -04001144static void ahci_remove_one (struct pci_dev *pdev)
1145{
1146 struct device *dev = pci_dev_to_dev(pdev);
1147 struct ata_host_set *host_set = dev_get_drvdata(dev);
1148 struct ahci_host_priv *hpriv = host_set->private_data;
1149 struct ata_port *ap;
1150 unsigned int i;
1151 int have_msi;
1152
1153 for (i = 0; i < host_set->n_ports; i++) {
1154 ap = host_set->ports[i];
1155
1156 scsi_remove_host(ap->host);
1157 }
1158
Jeff Garzik4b0060f2005-06-04 00:50:22 -04001159 have_msi = hpriv->flags & AHCI_FLAG_MSI;
Jeff Garzik907f4672005-05-12 15:03:42 -04001160 free_irq(host_set->irq, host_set);
Jeff Garzik907f4672005-05-12 15:03:42 -04001161
1162 for (i = 0; i < host_set->n_ports; i++) {
1163 ap = host_set->ports[i];
1164
1165 ata_scsi_release(ap->host);
1166 scsi_host_put(ap->host);
1167 }
1168
Jeff Garzike005f012005-08-30 04:18:28 -04001169 kfree(hpriv);
Jeff Garzik374b1872005-08-30 05:42:52 -04001170 pci_iounmap(pdev, host_set->mmio_base);
Jeff Garzikead5de92005-05-31 11:53:57 -04001171 kfree(host_set);
1172
Jeff Garzik907f4672005-05-12 15:03:42 -04001173 if (have_msi)
1174 pci_disable_msi(pdev);
1175 else
1176 pci_intx(pdev, 0);
1177 pci_release_regions(pdev);
Jeff Garzik907f4672005-05-12 15:03:42 -04001178 pci_disable_device(pdev);
1179 dev_set_drvdata(dev, NULL);
1180}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181
1182static int __init ahci_init(void)
1183{
1184 return pci_module_init(&ahci_pci_driver);
1185}
1186
Linus Torvalds1da177e2005-04-16 15:20:36 -07001187static void __exit ahci_exit(void)
1188{
1189 pci_unregister_driver(&ahci_pci_driver);
1190}
1191
1192
1193MODULE_AUTHOR("Jeff Garzik");
1194MODULE_DESCRIPTION("AHCI SATA low-level driver");
1195MODULE_LICENSE("GPL");
1196MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001197MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001198
1199module_init(ahci_init);
1200module_exit(ahci_exit);