Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * core.c - DesignWare HS OTG Controller common routines |
| 3 | * |
| 4 | * Copyright (C) 2004-2013 Synopsys, Inc. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions, and the following disclaimer, |
| 11 | * without modification. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. The names of the above-listed copyright holders may not be used |
| 16 | * to endorse or promote products derived from this software without |
| 17 | * specific prior written permission. |
| 18 | * |
| 19 | * ALTERNATIVELY, this software may be distributed under the terms of the |
| 20 | * GNU General Public License ("GPL") as published by the Free Software |
| 21 | * Foundation; either version 2 of the License, or (at your option) any |
| 22 | * later version. |
| 23 | * |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
| 25 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| 26 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 27 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 28 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 29 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 30 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 31 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 32 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 33 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 34 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 35 | */ |
| 36 | |
| 37 | /* |
| 38 | * The Core code provides basic services for accessing and managing the |
| 39 | * DWC_otg hardware. These services are used by both the Host Controller |
| 40 | * Driver and the Peripheral Controller Driver. |
| 41 | */ |
| 42 | #include <linux/kernel.h> |
| 43 | #include <linux/module.h> |
| 44 | #include <linux/moduleparam.h> |
| 45 | #include <linux/spinlock.h> |
| 46 | #include <linux/interrupt.h> |
| 47 | #include <linux/dma-mapping.h> |
| 48 | #include <linux/delay.h> |
| 49 | #include <linux/io.h> |
| 50 | #include <linux/slab.h> |
| 51 | #include <linux/usb.h> |
| 52 | |
| 53 | #include <linux/usb/hcd.h> |
| 54 | #include <linux/usb/ch11.h> |
| 55 | |
| 56 | #include "core.h" |
| 57 | #include "hcd.h" |
| 58 | |
Gregory Herrero | d17ee77 | 2015-04-29 22:09:01 +0200 | [diff] [blame] | 59 | #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
| 60 | /** |
| 61 | * dwc2_backup_host_registers() - Backup controller host registers. |
| 62 | * When suspending usb bus, registers needs to be backuped |
| 63 | * if controller power is disabled once suspended. |
| 64 | * |
| 65 | * @hsotg: Programming view of the DWC_otg controller |
| 66 | */ |
| 67 | static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) |
| 68 | { |
| 69 | struct dwc2_hregs_backup *hr; |
| 70 | int i; |
| 71 | |
| 72 | dev_dbg(hsotg->dev, "%s\n", __func__); |
| 73 | |
| 74 | /* Backup Host regs */ |
| 75 | hr = hsotg->hr_backup; |
| 76 | if (!hr) { |
| 77 | hr = devm_kzalloc(hsotg->dev, sizeof(*hr), GFP_KERNEL); |
| 78 | if (!hr) { |
| 79 | dev_err(hsotg->dev, "%s: can't allocate host regs\n", |
| 80 | __func__); |
| 81 | return -ENOMEM; |
| 82 | } |
| 83 | |
| 84 | hsotg->hr_backup = hr; |
| 85 | } |
| 86 | hr->hcfg = readl(hsotg->regs + HCFG); |
| 87 | hr->haintmsk = readl(hsotg->regs + HAINTMSK); |
| 88 | for (i = 0; i < hsotg->core_params->host_channels; ++i) |
| 89 | hr->hcintmsk[i] = readl(hsotg->regs + HCINTMSK(i)); |
| 90 | |
| 91 | hr->hprt0 = readl(hsotg->regs + HPRT0); |
| 92 | hr->hfir = readl(hsotg->regs + HFIR); |
| 93 | |
| 94 | return 0; |
| 95 | } |
| 96 | |
| 97 | /** |
| 98 | * dwc2_restore_host_registers() - Restore controller host registers. |
| 99 | * When resuming usb bus, device registers needs to be restored |
| 100 | * if controller power were disabled. |
| 101 | * |
| 102 | * @hsotg: Programming view of the DWC_otg controller |
| 103 | */ |
| 104 | static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) |
| 105 | { |
| 106 | struct dwc2_hregs_backup *hr; |
| 107 | int i; |
| 108 | |
| 109 | dev_dbg(hsotg->dev, "%s\n", __func__); |
| 110 | |
| 111 | /* Restore host regs */ |
| 112 | hr = hsotg->hr_backup; |
| 113 | if (!hr) { |
| 114 | dev_err(hsotg->dev, "%s: no host registers to restore\n", |
| 115 | __func__); |
| 116 | return -EINVAL; |
| 117 | } |
| 118 | |
| 119 | writel(hr->hcfg, hsotg->regs + HCFG); |
| 120 | writel(hr->haintmsk, hsotg->regs + HAINTMSK); |
| 121 | |
| 122 | for (i = 0; i < hsotg->core_params->host_channels; ++i) |
| 123 | writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); |
| 124 | |
| 125 | writel(hr->hprt0, hsotg->regs + HPRT0); |
| 126 | writel(hr->hfir, hsotg->regs + HFIR); |
| 127 | |
| 128 | return 0; |
| 129 | } |
| 130 | #else |
| 131 | static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) |
| 132 | { return 0; } |
| 133 | |
| 134 | static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) |
| 135 | { return 0; } |
| 136 | #endif |
| 137 | |
| 138 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ |
| 139 | IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
| 140 | /** |
| 141 | * dwc2_backup_device_registers() - Backup controller device registers. |
| 142 | * When suspending usb bus, registers needs to be backuped |
| 143 | * if controller power is disabled once suspended. |
| 144 | * |
| 145 | * @hsotg: Programming view of the DWC_otg controller |
| 146 | */ |
| 147 | static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) |
| 148 | { |
| 149 | struct dwc2_dregs_backup *dr; |
| 150 | int i; |
| 151 | |
| 152 | dev_dbg(hsotg->dev, "%s\n", __func__); |
| 153 | |
| 154 | /* Backup dev regs */ |
| 155 | dr = hsotg->dr_backup; |
| 156 | if (!dr) { |
| 157 | dr = devm_kzalloc(hsotg->dev, sizeof(*dr), GFP_KERNEL); |
| 158 | if (!dr) { |
| 159 | dev_err(hsotg->dev, "%s: can't allocate device regs\n", |
| 160 | __func__); |
| 161 | return -ENOMEM; |
| 162 | } |
| 163 | |
| 164 | hsotg->dr_backup = dr; |
| 165 | } |
| 166 | |
| 167 | dr->dcfg = readl(hsotg->regs + DCFG); |
| 168 | dr->dctl = readl(hsotg->regs + DCTL); |
| 169 | dr->daintmsk = readl(hsotg->regs + DAINTMSK); |
| 170 | dr->diepmsk = readl(hsotg->regs + DIEPMSK); |
| 171 | dr->doepmsk = readl(hsotg->regs + DOEPMSK); |
| 172 | |
| 173 | for (i = 0; i < hsotg->num_of_eps; i++) { |
| 174 | /* Backup IN EPs */ |
| 175 | dr->diepctl[i] = readl(hsotg->regs + DIEPCTL(i)); |
| 176 | |
| 177 | /* Ensure DATA PID is correctly configured */ |
| 178 | if (dr->diepctl[i] & DXEPCTL_DPID) |
| 179 | dr->diepctl[i] |= DXEPCTL_SETD1PID; |
| 180 | else |
| 181 | dr->diepctl[i] |= DXEPCTL_SETD0PID; |
| 182 | |
| 183 | dr->dieptsiz[i] = readl(hsotg->regs + DIEPTSIZ(i)); |
| 184 | dr->diepdma[i] = readl(hsotg->regs + DIEPDMA(i)); |
| 185 | |
| 186 | /* Backup OUT EPs */ |
| 187 | dr->doepctl[i] = readl(hsotg->regs + DOEPCTL(i)); |
| 188 | |
| 189 | /* Ensure DATA PID is correctly configured */ |
| 190 | if (dr->doepctl[i] & DXEPCTL_DPID) |
| 191 | dr->doepctl[i] |= DXEPCTL_SETD1PID; |
| 192 | else |
| 193 | dr->doepctl[i] |= DXEPCTL_SETD0PID; |
| 194 | |
| 195 | dr->doeptsiz[i] = readl(hsotg->regs + DOEPTSIZ(i)); |
| 196 | dr->doepdma[i] = readl(hsotg->regs + DOEPDMA(i)); |
| 197 | } |
| 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | /** |
| 203 | * dwc2_restore_device_registers() - Restore controller device registers. |
| 204 | * When resuming usb bus, device registers needs to be restored |
| 205 | * if controller power were disabled. |
| 206 | * |
| 207 | * @hsotg: Programming view of the DWC_otg controller |
| 208 | */ |
| 209 | static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) |
| 210 | { |
| 211 | struct dwc2_dregs_backup *dr; |
| 212 | u32 dctl; |
| 213 | int i; |
| 214 | |
| 215 | dev_dbg(hsotg->dev, "%s\n", __func__); |
| 216 | |
| 217 | /* Restore dev regs */ |
| 218 | dr = hsotg->dr_backup; |
| 219 | if (!dr) { |
| 220 | dev_err(hsotg->dev, "%s: no device registers to restore\n", |
| 221 | __func__); |
| 222 | return -EINVAL; |
| 223 | } |
| 224 | |
| 225 | writel(dr->dcfg, hsotg->regs + DCFG); |
| 226 | writel(dr->dctl, hsotg->regs + DCTL); |
| 227 | writel(dr->daintmsk, hsotg->regs + DAINTMSK); |
| 228 | writel(dr->diepmsk, hsotg->regs + DIEPMSK); |
| 229 | writel(dr->doepmsk, hsotg->regs + DOEPMSK); |
| 230 | |
| 231 | for (i = 0; i < hsotg->num_of_eps; i++) { |
| 232 | /* Restore IN EPs */ |
| 233 | writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); |
| 234 | writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); |
| 235 | writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); |
| 236 | |
| 237 | /* Restore OUT EPs */ |
| 238 | writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); |
| 239 | writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); |
| 240 | writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); |
| 241 | } |
| 242 | |
| 243 | /* Set the Power-On Programming done bit */ |
| 244 | dctl = readl(hsotg->regs + DCTL); |
| 245 | dctl |= DCTL_PWRONPRGDONE; |
| 246 | writel(dctl, hsotg->regs + DCTL); |
| 247 | |
| 248 | return 0; |
| 249 | } |
| 250 | #else |
| 251 | static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) |
| 252 | { return 0; } |
| 253 | |
| 254 | static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) |
| 255 | { return 0; } |
| 256 | #endif |
| 257 | |
| 258 | /** |
| 259 | * dwc2_backup_global_registers() - Backup global controller registers. |
| 260 | * When suspending usb bus, registers needs to be backuped |
| 261 | * if controller power is disabled once suspended. |
| 262 | * |
| 263 | * @hsotg: Programming view of the DWC_otg controller |
| 264 | */ |
| 265 | static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) |
| 266 | { |
| 267 | struct dwc2_gregs_backup *gr; |
| 268 | int i; |
| 269 | |
| 270 | /* Backup global regs */ |
| 271 | gr = hsotg->gr_backup; |
| 272 | if (!gr) { |
| 273 | gr = devm_kzalloc(hsotg->dev, sizeof(*gr), GFP_KERNEL); |
| 274 | if (!gr) { |
| 275 | dev_err(hsotg->dev, "%s: can't allocate global regs\n", |
| 276 | __func__); |
| 277 | return -ENOMEM; |
| 278 | } |
| 279 | |
| 280 | hsotg->gr_backup = gr; |
| 281 | } |
| 282 | |
| 283 | gr->gotgctl = readl(hsotg->regs + GOTGCTL); |
| 284 | gr->gintmsk = readl(hsotg->regs + GINTMSK); |
| 285 | gr->gahbcfg = readl(hsotg->regs + GAHBCFG); |
| 286 | gr->gusbcfg = readl(hsotg->regs + GUSBCFG); |
| 287 | gr->grxfsiz = readl(hsotg->regs + GRXFSIZ); |
| 288 | gr->gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ); |
| 289 | gr->hptxfsiz = readl(hsotg->regs + HPTXFSIZ); |
| 290 | gr->gdfifocfg = readl(hsotg->regs + GDFIFOCFG); |
| 291 | for (i = 0; i < MAX_EPS_CHANNELS; i++) |
| 292 | gr->dtxfsiz[i] = readl(hsotg->regs + DPTXFSIZN(i)); |
| 293 | |
| 294 | return 0; |
| 295 | } |
| 296 | |
| 297 | /** |
| 298 | * dwc2_restore_global_registers() - Restore controller global registers. |
| 299 | * When resuming usb bus, device registers needs to be restored |
| 300 | * if controller power were disabled. |
| 301 | * |
| 302 | * @hsotg: Programming view of the DWC_otg controller |
| 303 | */ |
| 304 | static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) |
| 305 | { |
| 306 | struct dwc2_gregs_backup *gr; |
| 307 | int i; |
| 308 | |
| 309 | dev_dbg(hsotg->dev, "%s\n", __func__); |
| 310 | |
| 311 | /* Restore global regs */ |
| 312 | gr = hsotg->gr_backup; |
| 313 | if (!gr) { |
| 314 | dev_err(hsotg->dev, "%s: no global registers to restore\n", |
| 315 | __func__); |
| 316 | return -EINVAL; |
| 317 | } |
| 318 | |
| 319 | writel(0xffffffff, hsotg->regs + GINTSTS); |
| 320 | writel(gr->gotgctl, hsotg->regs + GOTGCTL); |
| 321 | writel(gr->gintmsk, hsotg->regs + GINTMSK); |
| 322 | writel(gr->gusbcfg, hsotg->regs + GUSBCFG); |
| 323 | writel(gr->gahbcfg, hsotg->regs + GAHBCFG); |
| 324 | writel(gr->grxfsiz, hsotg->regs + GRXFSIZ); |
| 325 | writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ); |
| 326 | writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ); |
| 327 | writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG); |
| 328 | for (i = 0; i < MAX_EPS_CHANNELS; i++) |
| 329 | writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); |
| 330 | |
| 331 | return 0; |
| 332 | } |
| 333 | |
| 334 | /** |
| 335 | * dwc2_exit_hibernation() - Exit controller from Partial Power Down. |
| 336 | * |
| 337 | * @hsotg: Programming view of the DWC_otg controller |
| 338 | * @restore: Controller registers need to be restored |
| 339 | */ |
| 340 | int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore) |
| 341 | { |
| 342 | u32 pcgcctl; |
| 343 | int ret = 0; |
| 344 | |
| 345 | pcgcctl = readl(hsotg->regs + PCGCTL); |
| 346 | pcgcctl &= ~PCGCTL_STOPPCLK; |
| 347 | writel(pcgcctl, hsotg->regs + PCGCTL); |
| 348 | |
| 349 | pcgcctl = readl(hsotg->regs + PCGCTL); |
| 350 | pcgcctl &= ~PCGCTL_PWRCLMP; |
| 351 | writel(pcgcctl, hsotg->regs + PCGCTL); |
| 352 | |
| 353 | pcgcctl = readl(hsotg->regs + PCGCTL); |
| 354 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; |
| 355 | writel(pcgcctl, hsotg->regs + PCGCTL); |
| 356 | |
| 357 | udelay(100); |
| 358 | if (restore) { |
| 359 | ret = dwc2_restore_global_registers(hsotg); |
| 360 | if (ret) { |
| 361 | dev_err(hsotg->dev, "%s: failed to restore registers\n", |
| 362 | __func__); |
| 363 | return ret; |
| 364 | } |
| 365 | if (dwc2_is_host_mode(hsotg)) { |
| 366 | ret = dwc2_restore_host_registers(hsotg); |
| 367 | if (ret) { |
| 368 | dev_err(hsotg->dev, "%s: failed to restore host registers\n", |
| 369 | __func__); |
| 370 | return ret; |
| 371 | } |
| 372 | } else { |
| 373 | ret = dwc2_restore_device_registers(hsotg); |
| 374 | if (ret) { |
| 375 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", |
| 376 | __func__); |
| 377 | return ret; |
| 378 | } |
| 379 | } |
| 380 | } |
| 381 | |
| 382 | return ret; |
| 383 | } |
| 384 | |
| 385 | /** |
| 386 | * dwc2_enter_hibernation() - Put controller in Partial Power Down. |
| 387 | * |
| 388 | * @hsotg: Programming view of the DWC_otg controller |
| 389 | */ |
| 390 | int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg) |
| 391 | { |
| 392 | u32 pcgcctl; |
| 393 | int ret = 0; |
| 394 | |
| 395 | /* Backup all registers */ |
| 396 | ret = dwc2_backup_global_registers(hsotg); |
| 397 | if (ret) { |
| 398 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", |
| 399 | __func__); |
| 400 | return ret; |
| 401 | } |
| 402 | |
| 403 | if (dwc2_is_host_mode(hsotg)) { |
| 404 | ret = dwc2_backup_host_registers(hsotg); |
| 405 | if (ret) { |
| 406 | dev_err(hsotg->dev, "%s: failed to backup host registers\n", |
| 407 | __func__); |
| 408 | return ret; |
| 409 | } |
| 410 | } else { |
| 411 | ret = dwc2_backup_device_registers(hsotg); |
| 412 | if (ret) { |
| 413 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", |
| 414 | __func__); |
| 415 | return ret; |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | /* Put the controller in low power state */ |
| 420 | pcgcctl = readl(hsotg->regs + PCGCTL); |
| 421 | |
| 422 | pcgcctl |= PCGCTL_PWRCLMP; |
| 423 | writel(pcgcctl, hsotg->regs + PCGCTL); |
| 424 | ndelay(20); |
| 425 | |
| 426 | pcgcctl |= PCGCTL_RSTPDWNMODULE; |
| 427 | writel(pcgcctl, hsotg->regs + PCGCTL); |
| 428 | ndelay(20); |
| 429 | |
| 430 | pcgcctl |= PCGCTL_STOPPCLK; |
| 431 | writel(pcgcctl, hsotg->regs + PCGCTL); |
| 432 | |
| 433 | return ret; |
| 434 | } |
| 435 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 436 | /** |
| 437 | * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, |
| 438 | * used in both device and host modes |
| 439 | * |
| 440 | * @hsotg: Programming view of the DWC_otg controller |
| 441 | */ |
| 442 | static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) |
| 443 | { |
| 444 | u32 intmsk; |
| 445 | |
| 446 | /* Clear any pending OTG Interrupts */ |
| 447 | writel(0xffffffff, hsotg->regs + GOTGINT); |
| 448 | |
| 449 | /* Clear any pending interrupts */ |
| 450 | writel(0xffffffff, hsotg->regs + GINTSTS); |
| 451 | |
| 452 | /* Enable the interrupts in the GINTMSK */ |
| 453 | intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; |
| 454 | |
| 455 | if (hsotg->core_params->dma_enable <= 0) |
| 456 | intmsk |= GINTSTS_RXFLVL; |
Gregory Herrero | a6d249d | 2015-04-29 22:09:04 +0200 | [diff] [blame] | 457 | if (hsotg->core_params->external_id_pin_ctl <= 0) |
| 458 | intmsk |= GINTSTS_CONIDSTSCHNG; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 459 | |
Gregory Herrero | a6d249d | 2015-04-29 22:09:04 +0200 | [diff] [blame] | 460 | intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 461 | GINTSTS_SESSREQINT; |
| 462 | |
| 463 | writel(intmsk, hsotg->regs + GINTMSK); |
| 464 | } |
| 465 | |
| 466 | /* |
| 467 | * Initializes the FSLSPClkSel field of the HCFG register depending on the |
| 468 | * PHY type |
| 469 | */ |
| 470 | static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) |
| 471 | { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 472 | u32 hcfg, val; |
| 473 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 474 | if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && |
| 475 | hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 476 | hsotg->core_params->ulpi_fs_ls > 0) || |
| 477 | hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { |
| 478 | /* Full speed PHY */ |
| 479 | val = HCFG_FSLSPCLKSEL_48_MHZ; |
| 480 | } else { |
| 481 | /* High speed PHY running at full speed or high speed */ |
| 482 | val = HCFG_FSLSPCLKSEL_30_60_MHZ; |
| 483 | } |
| 484 | |
| 485 | dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); |
| 486 | hcfg = readl(hsotg->regs + HCFG); |
| 487 | hcfg &= ~HCFG_FSLSPCLKSEL_MASK; |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 488 | hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 489 | writel(hcfg, hsotg->regs + HCFG); |
| 490 | } |
| 491 | |
| 492 | /* |
| 493 | * Do core a soft reset of the core. Be careful with this because it |
| 494 | * resets all the internal state machines of the core. |
| 495 | */ |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 496 | static int dwc2_core_reset(struct dwc2_hsotg *hsotg) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 497 | { |
| 498 | u32 greset; |
| 499 | int count = 0; |
Kever Yang | c0155b9 | 2014-08-06 09:01:50 +0800 | [diff] [blame] | 500 | u32 gusbcfg; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 501 | |
| 502 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
| 503 | |
| 504 | /* Wait for AHB master IDLE state */ |
| 505 | do { |
| 506 | usleep_range(20000, 40000); |
| 507 | greset = readl(hsotg->regs + GRSTCTL); |
| 508 | if (++count > 50) { |
| 509 | dev_warn(hsotg->dev, |
| 510 | "%s() HANG! AHB Idle GRSTCTL=%0x\n", |
| 511 | __func__, greset); |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 512 | return -EBUSY; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 513 | } |
| 514 | } while (!(greset & GRSTCTL_AHBIDLE)); |
| 515 | |
| 516 | /* Core Soft Reset */ |
| 517 | count = 0; |
| 518 | greset |= GRSTCTL_CSFTRST; |
| 519 | writel(greset, hsotg->regs + GRSTCTL); |
| 520 | do { |
| 521 | usleep_range(20000, 40000); |
| 522 | greset = readl(hsotg->regs + GRSTCTL); |
| 523 | if (++count > 50) { |
| 524 | dev_warn(hsotg->dev, |
| 525 | "%s() HANG! Soft Reset GRSTCTL=%0x\n", |
| 526 | __func__, greset); |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 527 | return -EBUSY; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 528 | } |
| 529 | } while (greset & GRSTCTL_CSFTRST); |
| 530 | |
Kever Yang | c0155b9 | 2014-08-06 09:01:50 +0800 | [diff] [blame] | 531 | if (hsotg->dr_mode == USB_DR_MODE_HOST) { |
| 532 | gusbcfg = readl(hsotg->regs + GUSBCFG); |
| 533 | gusbcfg &= ~GUSBCFG_FORCEDEVMODE; |
| 534 | gusbcfg |= GUSBCFG_FORCEHOSTMODE; |
| 535 | writel(gusbcfg, hsotg->regs + GUSBCFG); |
| 536 | } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
| 537 | gusbcfg = readl(hsotg->regs + GUSBCFG); |
| 538 | gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; |
| 539 | gusbcfg |= GUSBCFG_FORCEDEVMODE; |
| 540 | writel(gusbcfg, hsotg->regs + GUSBCFG); |
| 541 | } else if (hsotg->dr_mode == USB_DR_MODE_OTG) { |
| 542 | gusbcfg = readl(hsotg->regs + GUSBCFG); |
| 543 | gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; |
| 544 | gusbcfg &= ~GUSBCFG_FORCEDEVMODE; |
| 545 | writel(gusbcfg, hsotg->regs + GUSBCFG); |
| 546 | } |
| 547 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 548 | /* |
| 549 | * NOTE: This long sleep is _very_ important, otherwise the core will |
| 550 | * not stay in host mode after a connector ID change! |
| 551 | */ |
| 552 | usleep_range(150000, 200000); |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 553 | |
| 554 | return 0; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 555 | } |
| 556 | |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 557 | static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 558 | { |
| 559 | u32 usbcfg, i2cctl; |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 560 | int retval = 0; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 561 | |
| 562 | /* |
| 563 | * core_init() is now called on every switch so only call the |
| 564 | * following for the first time through |
| 565 | */ |
| 566 | if (select_phy) { |
| 567 | dev_dbg(hsotg->dev, "FS PHY selected\n"); |
| 568 | usbcfg = readl(hsotg->regs + GUSBCFG); |
| 569 | usbcfg |= GUSBCFG_PHYSEL; |
| 570 | writel(usbcfg, hsotg->regs + GUSBCFG); |
| 571 | |
| 572 | /* Reset after a PHY select */ |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 573 | retval = dwc2_core_reset(hsotg); |
| 574 | if (retval) { |
| 575 | dev_err(hsotg->dev, "%s() Reset failed, aborting", |
| 576 | __func__); |
| 577 | return retval; |
| 578 | } |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 579 | } |
| 580 | |
| 581 | /* |
| 582 | * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also |
| 583 | * do this on HNP Dev/Host mode switches (done in dev_init and |
| 584 | * host_init). |
| 585 | */ |
| 586 | if (dwc2_is_host_mode(hsotg)) |
| 587 | dwc2_init_fs_ls_pclk_sel(hsotg); |
| 588 | |
| 589 | if (hsotg->core_params->i2c_enable > 0) { |
| 590 | dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); |
| 591 | |
| 592 | /* Program GUSBCFG.OtgUtmiFsSel to I2C */ |
| 593 | usbcfg = readl(hsotg->regs + GUSBCFG); |
| 594 | usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; |
| 595 | writel(usbcfg, hsotg->regs + GUSBCFG); |
| 596 | |
| 597 | /* Program GI2CCTL.I2CEn */ |
| 598 | i2cctl = readl(hsotg->regs + GI2CCTL); |
| 599 | i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; |
| 600 | i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; |
| 601 | i2cctl &= ~GI2CCTL_I2CEN; |
| 602 | writel(i2cctl, hsotg->regs + GI2CCTL); |
| 603 | i2cctl |= GI2CCTL_I2CEN; |
| 604 | writel(i2cctl, hsotg->regs + GI2CCTL); |
| 605 | } |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 606 | |
| 607 | return retval; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 608 | } |
| 609 | |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 610 | static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 611 | { |
| 612 | u32 usbcfg; |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 613 | int retval = 0; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 614 | |
| 615 | if (!select_phy) |
Paul Zimmerman | a23666c | 2014-02-04 11:42:15 -0800 | [diff] [blame] | 616 | return 0; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 617 | |
| 618 | usbcfg = readl(hsotg->regs + GUSBCFG); |
| 619 | |
| 620 | /* |
| 621 | * HS PHY parameters. These parameters are preserved during soft reset |
| 622 | * so only program the first time. Do a soft reset immediately after |
| 623 | * setting phyif. |
| 624 | */ |
| 625 | switch (hsotg->core_params->phy_type) { |
| 626 | case DWC2_PHY_TYPE_PARAM_ULPI: |
| 627 | /* ULPI interface */ |
| 628 | dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); |
| 629 | usbcfg |= GUSBCFG_ULPI_UTMI_SEL; |
| 630 | usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); |
| 631 | if (hsotg->core_params->phy_ulpi_ddr > 0) |
| 632 | usbcfg |= GUSBCFG_DDRSEL; |
| 633 | break; |
| 634 | case DWC2_PHY_TYPE_PARAM_UTMI: |
| 635 | /* UTMI+ interface */ |
| 636 | dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); |
| 637 | usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); |
| 638 | if (hsotg->core_params->phy_utmi_width == 16) |
| 639 | usbcfg |= GUSBCFG_PHYIF16; |
| 640 | break; |
| 641 | default: |
| 642 | dev_err(hsotg->dev, "FS PHY selected at HS!\n"); |
| 643 | break; |
| 644 | } |
| 645 | |
| 646 | writel(usbcfg, hsotg->regs + GUSBCFG); |
| 647 | |
| 648 | /* Reset after setting the PHY parameters */ |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 649 | retval = dwc2_core_reset(hsotg); |
| 650 | if (retval) { |
| 651 | dev_err(hsotg->dev, "%s() Reset failed, aborting", |
| 652 | __func__); |
| 653 | return retval; |
| 654 | } |
| 655 | |
| 656 | return retval; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 657 | } |
| 658 | |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 659 | static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 660 | { |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 661 | u32 usbcfg; |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 662 | int retval = 0; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 663 | |
| 664 | if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL && |
| 665 | hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { |
| 666 | /* If FS mode with FS PHY */ |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 667 | retval = dwc2_fs_phy_init(hsotg, select_phy); |
| 668 | if (retval) |
| 669 | return retval; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 670 | } else { |
| 671 | /* High speed PHY */ |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 672 | retval = dwc2_hs_phy_init(hsotg, select_phy); |
| 673 | if (retval) |
| 674 | return retval; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 675 | } |
| 676 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 677 | if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && |
| 678 | hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 679 | hsotg->core_params->ulpi_fs_ls > 0) { |
| 680 | dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); |
| 681 | usbcfg = readl(hsotg->regs + GUSBCFG); |
| 682 | usbcfg |= GUSBCFG_ULPI_FS_LS; |
| 683 | usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; |
| 684 | writel(usbcfg, hsotg->regs + GUSBCFG); |
| 685 | } else { |
| 686 | usbcfg = readl(hsotg->regs + GUSBCFG); |
| 687 | usbcfg &= ~GUSBCFG_ULPI_FS_LS; |
| 688 | usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; |
| 689 | writel(usbcfg, hsotg->regs + GUSBCFG); |
| 690 | } |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 691 | |
| 692 | return retval; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 693 | } |
| 694 | |
| 695 | static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) |
| 696 | { |
Paul Zimmerman | 4d3190e | 2013-07-16 12:22:12 -0700 | [diff] [blame] | 697 | u32 ahbcfg = readl(hsotg->regs + GAHBCFG); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 698 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 699 | switch (hsotg->hw_params.arch) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 700 | case GHWCFG2_EXT_DMA_ARCH: |
| 701 | dev_err(hsotg->dev, "External DMA Mode not supported\n"); |
| 702 | return -EINVAL; |
| 703 | |
| 704 | case GHWCFG2_INT_DMA_ARCH: |
| 705 | dev_dbg(hsotg->dev, "Internal DMA Mode\n"); |
Paul Zimmerman | 4d3190e | 2013-07-16 12:22:12 -0700 | [diff] [blame] | 706 | if (hsotg->core_params->ahbcfg != -1) { |
| 707 | ahbcfg &= GAHBCFG_CTRL_MASK; |
| 708 | ahbcfg |= hsotg->core_params->ahbcfg & |
| 709 | ~GAHBCFG_CTRL_MASK; |
| 710 | } |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 711 | break; |
| 712 | |
| 713 | case GHWCFG2_SLAVE_ONLY_ARCH: |
| 714 | default: |
| 715 | dev_dbg(hsotg->dev, "Slave Only Mode\n"); |
| 716 | break; |
| 717 | } |
| 718 | |
| 719 | dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n", |
| 720 | hsotg->core_params->dma_enable, |
| 721 | hsotg->core_params->dma_desc_enable); |
| 722 | |
| 723 | if (hsotg->core_params->dma_enable > 0) { |
| 724 | if (hsotg->core_params->dma_desc_enable > 0) |
| 725 | dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); |
| 726 | else |
| 727 | dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); |
| 728 | } else { |
| 729 | dev_dbg(hsotg->dev, "Using Slave mode\n"); |
| 730 | hsotg->core_params->dma_desc_enable = 0; |
| 731 | } |
| 732 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 733 | if (hsotg->core_params->dma_enable > 0) |
| 734 | ahbcfg |= GAHBCFG_DMA_EN; |
| 735 | |
| 736 | writel(ahbcfg, hsotg->regs + GAHBCFG); |
| 737 | |
| 738 | return 0; |
| 739 | } |
| 740 | |
| 741 | static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) |
| 742 | { |
| 743 | u32 usbcfg; |
| 744 | |
| 745 | usbcfg = readl(hsotg->regs + GUSBCFG); |
| 746 | usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); |
| 747 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 748 | switch (hsotg->hw_params.op_mode) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 749 | case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: |
| 750 | if (hsotg->core_params->otg_cap == |
| 751 | DWC2_CAP_PARAM_HNP_SRP_CAPABLE) |
| 752 | usbcfg |= GUSBCFG_HNPCAP; |
| 753 | if (hsotg->core_params->otg_cap != |
| 754 | DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) |
| 755 | usbcfg |= GUSBCFG_SRPCAP; |
| 756 | break; |
| 757 | |
| 758 | case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: |
| 759 | case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: |
| 760 | case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: |
| 761 | if (hsotg->core_params->otg_cap != |
| 762 | DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) |
| 763 | usbcfg |= GUSBCFG_SRPCAP; |
| 764 | break; |
| 765 | |
| 766 | case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: |
| 767 | case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: |
| 768 | case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: |
| 769 | default: |
| 770 | break; |
| 771 | } |
| 772 | |
| 773 | writel(usbcfg, hsotg->regs + GUSBCFG); |
| 774 | } |
| 775 | |
| 776 | /** |
| 777 | * dwc2_core_init() - Initializes the DWC_otg controller registers and |
| 778 | * prepares the core for device mode or host mode operation |
| 779 | * |
| 780 | * @hsotg: Programming view of the DWC_otg controller |
| 781 | * @select_phy: If true then also set the Phy type |
Matthijs Kooijman | 6706c72 | 2013-04-11 17:52:41 +0200 | [diff] [blame] | 782 | * @irq: If >= 0, the irq to register |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 783 | */ |
Matthijs Kooijman | 6706c72 | 2013-04-11 17:52:41 +0200 | [diff] [blame] | 784 | int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 785 | { |
| 786 | u32 usbcfg, otgctl; |
| 787 | int retval; |
| 788 | |
| 789 | dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); |
| 790 | |
| 791 | usbcfg = readl(hsotg->regs + GUSBCFG); |
| 792 | |
| 793 | /* Set ULPI External VBUS bit if needed */ |
| 794 | usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; |
| 795 | if (hsotg->core_params->phy_ulpi_ext_vbus == |
| 796 | DWC2_PHY_ULPI_EXTERNAL_VBUS) |
| 797 | usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; |
| 798 | |
| 799 | /* Set external TS Dline pulsing bit if needed */ |
| 800 | usbcfg &= ~GUSBCFG_TERMSELDLPULSE; |
| 801 | if (hsotg->core_params->ts_dline > 0) |
| 802 | usbcfg |= GUSBCFG_TERMSELDLPULSE; |
| 803 | |
| 804 | writel(usbcfg, hsotg->regs + GUSBCFG); |
| 805 | |
| 806 | /* Reset the Controller */ |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 807 | retval = dwc2_core_reset(hsotg); |
| 808 | if (retval) { |
| 809 | dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", |
| 810 | __func__); |
| 811 | return retval; |
| 812 | } |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 813 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 814 | /* |
| 815 | * This needs to happen in FS mode before any other programming occurs |
| 816 | */ |
Julien DELACOU | beb7e59 | 2013-11-20 17:29:49 +0100 | [diff] [blame] | 817 | retval = dwc2_phy_init(hsotg, select_phy); |
| 818 | if (retval) |
| 819 | return retval; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 820 | |
| 821 | /* Program the GAHBCFG Register */ |
| 822 | retval = dwc2_gahbcfg_init(hsotg); |
| 823 | if (retval) |
| 824 | return retval; |
| 825 | |
| 826 | /* Program the GUSBCFG register */ |
| 827 | dwc2_gusbcfg_init(hsotg); |
| 828 | |
| 829 | /* Program the GOTGCTL register */ |
| 830 | otgctl = readl(hsotg->regs + GOTGCTL); |
| 831 | otgctl &= ~GOTGCTL_OTGVER; |
| 832 | if (hsotg->core_params->otg_ver > 0) |
| 833 | otgctl |= GOTGCTL_OTGVER; |
| 834 | writel(otgctl, hsotg->regs + GOTGCTL); |
| 835 | dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); |
| 836 | |
| 837 | /* Clear the SRP success bit for FS-I2c */ |
| 838 | hsotg->srp_success = 0; |
| 839 | |
| 840 | /* Enable common interrupts */ |
| 841 | dwc2_enable_common_interrupts(hsotg); |
| 842 | |
| 843 | /* |
Mickael Maison | 997f4f8 | 2014-12-23 17:39:45 +0100 | [diff] [blame] | 844 | * Do device or host initialization based on mode during PCD and |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 845 | * HCD initialization |
| 846 | */ |
| 847 | if (dwc2_is_host_mode(hsotg)) { |
| 848 | dev_dbg(hsotg->dev, "Host Mode\n"); |
| 849 | hsotg->op_state = OTG_STATE_A_HOST; |
| 850 | } else { |
| 851 | dev_dbg(hsotg->dev, "Device Mode\n"); |
| 852 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
| 853 | } |
| 854 | |
| 855 | return 0; |
| 856 | } |
| 857 | |
| 858 | /** |
| 859 | * dwc2_enable_host_interrupts() - Enables the Host mode interrupts |
| 860 | * |
| 861 | * @hsotg: Programming view of DWC_otg controller |
| 862 | */ |
| 863 | void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) |
| 864 | { |
| 865 | u32 intmsk; |
| 866 | |
| 867 | dev_dbg(hsotg->dev, "%s()\n", __func__); |
| 868 | |
| 869 | /* Disable all interrupts */ |
| 870 | writel(0, hsotg->regs + GINTMSK); |
| 871 | writel(0, hsotg->regs + HAINTMSK); |
| 872 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 873 | /* Enable the common interrupts */ |
| 874 | dwc2_enable_common_interrupts(hsotg); |
| 875 | |
| 876 | /* Enable host mode interrupts without disturbing common interrupts */ |
| 877 | intmsk = readl(hsotg->regs + GINTMSK); |
| 878 | intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; |
| 879 | writel(intmsk, hsotg->regs + GINTMSK); |
| 880 | } |
| 881 | |
| 882 | /** |
| 883 | * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts |
| 884 | * |
| 885 | * @hsotg: Programming view of DWC_otg controller |
| 886 | */ |
| 887 | void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) |
| 888 | { |
| 889 | u32 intmsk = readl(hsotg->regs + GINTMSK); |
| 890 | |
| 891 | /* Disable host mode interrupts without disturbing common interrupts */ |
| 892 | intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | |
| 893 | GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); |
| 894 | writel(intmsk, hsotg->regs + GINTMSK); |
| 895 | } |
| 896 | |
Dinh Nguyen | 112fe8e | 2014-05-07 08:31:29 -0500 | [diff] [blame] | 897 | /* |
| 898 | * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size |
| 899 | * For system that have a total fifo depth that is smaller than the default |
| 900 | * RX + TX fifo size. |
| 901 | * |
| 902 | * @hsotg: Programming view of DWC_otg controller |
| 903 | */ |
| 904 | static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) |
| 905 | { |
| 906 | struct dwc2_core_params *params = hsotg->core_params; |
| 907 | struct dwc2_hw_params *hw = &hsotg->hw_params; |
| 908 | u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; |
| 909 | |
| 910 | total_fifo_size = hw->total_fifo_size; |
| 911 | rxfsiz = params->host_rx_fifo_size; |
| 912 | nptxfsiz = params->host_nperio_tx_fifo_size; |
| 913 | ptxfsiz = params->host_perio_tx_fifo_size; |
| 914 | |
| 915 | /* |
| 916 | * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth |
| 917 | * allocation with support for high bandwidth endpoints. Synopsys |
| 918 | * defines MPS(Max Packet size) for a periodic EP=1024, and for |
| 919 | * non-periodic as 512. |
| 920 | */ |
| 921 | if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { |
| 922 | /* |
| 923 | * For Buffer DMA mode/Scatter Gather DMA mode |
| 924 | * 2 * ((Largest Packet size / 4) + 1 + 1) + n |
| 925 | * with n = number of host channel. |
| 926 | * 2 * ((1024/4) + 2) = 516 |
| 927 | */ |
| 928 | rxfsiz = 516 + hw->host_channels; |
| 929 | |
| 930 | /* |
| 931 | * min non-periodic tx fifo depth |
| 932 | * 2 * (largest non-periodic USB packet used / 4) |
| 933 | * 2 * (512/4) = 256 |
| 934 | */ |
| 935 | nptxfsiz = 256; |
| 936 | |
| 937 | /* |
| 938 | * min periodic tx fifo depth |
| 939 | * (largest packet size*MC)/4 |
| 940 | * (1024 * 3)/4 = 768 |
| 941 | */ |
| 942 | ptxfsiz = 768; |
| 943 | |
| 944 | params->host_rx_fifo_size = rxfsiz; |
| 945 | params->host_nperio_tx_fifo_size = nptxfsiz; |
| 946 | params->host_perio_tx_fifo_size = ptxfsiz; |
| 947 | } |
| 948 | |
| 949 | /* |
| 950 | * If the summation of RX, NPTX and PTX fifo sizes is still |
| 951 | * bigger than the total_fifo_size, then we have a problem. |
| 952 | * |
| 953 | * We won't be able to allocate as many endpoints. Right now, |
| 954 | * we're just printing an error message, but ideally this FIFO |
| 955 | * allocation algorithm would be improved in the future. |
| 956 | * |
| 957 | * FIXME improve this FIFO allocation algorithm. |
| 958 | */ |
| 959 | if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) |
| 960 | dev_err(hsotg->dev, "invalid fifo sizes\n"); |
| 961 | } |
| 962 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 963 | static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) |
| 964 | { |
| 965 | struct dwc2_core_params *params = hsotg->core_params; |
Matthijs Kooijman | a1fc524 | 2013-08-30 18:45:20 +0200 | [diff] [blame] | 966 | u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 967 | |
Matthijs Kooijman | 1208605 | 2013-04-29 19:46:35 +0000 | [diff] [blame] | 968 | if (!params->enable_dynamic_fifo) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 969 | return; |
| 970 | |
Dinh Nguyen | 112fe8e | 2014-05-07 08:31:29 -0500 | [diff] [blame] | 971 | dwc2_calculate_dynamic_fifo(hsotg); |
| 972 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 973 | /* Rx FIFO */ |
Matthijs Kooijman | a1fc524 | 2013-08-30 18:45:20 +0200 | [diff] [blame] | 974 | grxfsiz = readl(hsotg->regs + GRXFSIZ); |
| 975 | dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); |
| 976 | grxfsiz &= ~GRXFSIZ_DEPTH_MASK; |
| 977 | grxfsiz |= params->host_rx_fifo_size << |
| 978 | GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; |
| 979 | writel(grxfsiz, hsotg->regs + GRXFSIZ); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 980 | dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ)); |
| 981 | |
| 982 | /* Non-periodic Tx FIFO */ |
| 983 | dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", |
| 984 | readl(hsotg->regs + GNPTXFSIZ)); |
| 985 | nptxfsiz = params->host_nperio_tx_fifo_size << |
| 986 | FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; |
| 987 | nptxfsiz |= params->host_rx_fifo_size << |
| 988 | FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; |
| 989 | writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); |
| 990 | dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", |
| 991 | readl(hsotg->regs + GNPTXFSIZ)); |
| 992 | |
| 993 | /* Periodic Tx FIFO */ |
| 994 | dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", |
| 995 | readl(hsotg->regs + HPTXFSIZ)); |
Matthijs Kooijman | c35205a | 2013-08-30 18:45:18 +0200 | [diff] [blame] | 996 | hptxfsiz = params->host_perio_tx_fifo_size << |
| 997 | FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; |
| 998 | hptxfsiz |= (params->host_rx_fifo_size + |
| 999 | params->host_nperio_tx_fifo_size) << |
| 1000 | FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; |
| 1001 | writel(hptxfsiz, hsotg->regs + HPTXFSIZ); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1002 | dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", |
| 1003 | readl(hsotg->regs + HPTXFSIZ)); |
| 1004 | |
| 1005 | if (hsotg->core_params->en_multiple_tx_fifo > 0 && |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 1006 | hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1007 | /* |
| 1008 | * Global DFIFOCFG calculation for Host mode - |
| 1009 | * include RxFIFO, NPTXFIFO and HPTXFIFO |
| 1010 | */ |
| 1011 | dfifocfg = readl(hsotg->regs + GDFIFOCFG); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1012 | dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; |
Matthijs Kooijman | 08b9f9d | 2013-08-30 18:45:19 +0200 | [diff] [blame] | 1013 | dfifocfg |= (params->host_rx_fifo_size + |
| 1014 | params->host_nperio_tx_fifo_size + |
| 1015 | params->host_perio_tx_fifo_size) << |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1016 | GDFIFOCFG_EPINFOBASE_SHIFT & |
| 1017 | GDFIFOCFG_EPINFOBASE_MASK; |
| 1018 | writel(dfifocfg, hsotg->regs + GDFIFOCFG); |
| 1019 | } |
| 1020 | } |
| 1021 | |
| 1022 | /** |
| 1023 | * dwc2_core_host_init() - Initializes the DWC_otg controller registers for |
| 1024 | * Host mode |
| 1025 | * |
| 1026 | * @hsotg: Programming view of DWC_otg controller |
| 1027 | * |
| 1028 | * This function flushes the Tx and Rx FIFOs and flushes any entries in the |
| 1029 | * request queues. Host channels are reset to ensure that they are ready for |
| 1030 | * performing transfers. |
| 1031 | */ |
| 1032 | void dwc2_core_host_init(struct dwc2_hsotg *hsotg) |
| 1033 | { |
| 1034 | u32 hcfg, hfir, otgctl; |
| 1035 | |
| 1036 | dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); |
| 1037 | |
| 1038 | /* Restart the Phy Clock */ |
| 1039 | writel(0, hsotg->regs + PCGCTL); |
| 1040 | |
| 1041 | /* Initialize Host Configuration Register */ |
| 1042 | dwc2_init_fs_ls_pclk_sel(hsotg); |
| 1043 | if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { |
| 1044 | hcfg = readl(hsotg->regs + HCFG); |
| 1045 | hcfg |= HCFG_FSLSSUPP; |
| 1046 | writel(hcfg, hsotg->regs + HCFG); |
| 1047 | } |
| 1048 | |
| 1049 | /* |
| 1050 | * This bit allows dynamic reloading of the HFIR register during |
Masanari Iida | 0dcde508 | 2013-09-13 23:34:36 +0900 | [diff] [blame] | 1051 | * runtime. This bit needs to be programmed during initial configuration |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1052 | * and its value must not be changed during runtime. |
| 1053 | */ |
| 1054 | if (hsotg->core_params->reload_ctl > 0) { |
| 1055 | hfir = readl(hsotg->regs + HFIR); |
| 1056 | hfir |= HFIR_RLDCTRL; |
| 1057 | writel(hfir, hsotg->regs + HFIR); |
| 1058 | } |
| 1059 | |
| 1060 | if (hsotg->core_params->dma_desc_enable > 0) { |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 1061 | u32 op_mode = hsotg->hw_params.op_mode; |
| 1062 | if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || |
| 1063 | !hsotg->hw_params.dma_desc_enable || |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1064 | op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || |
| 1065 | op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || |
| 1066 | op_mode == GHWCFG2_OP_MODE_UNDEFINED) { |
| 1067 | dev_err(hsotg->dev, |
| 1068 | "Hardware does not support descriptor DMA mode -\n"); |
| 1069 | dev_err(hsotg->dev, |
| 1070 | "falling back to buffer DMA mode.\n"); |
| 1071 | hsotg->core_params->dma_desc_enable = 0; |
| 1072 | } else { |
| 1073 | hcfg = readl(hsotg->regs + HCFG); |
| 1074 | hcfg |= HCFG_DESCDMA; |
| 1075 | writel(hcfg, hsotg->regs + HCFG); |
| 1076 | } |
| 1077 | } |
| 1078 | |
| 1079 | /* Configure data FIFO sizes */ |
| 1080 | dwc2_config_fifos(hsotg); |
| 1081 | |
| 1082 | /* TODO - check this */ |
| 1083 | /* Clear Host Set HNP Enable in the OTG Control Register */ |
| 1084 | otgctl = readl(hsotg->regs + GOTGCTL); |
| 1085 | otgctl &= ~GOTGCTL_HSTSETHNPEN; |
| 1086 | writel(otgctl, hsotg->regs + GOTGCTL); |
| 1087 | |
| 1088 | /* Make sure the FIFOs are flushed */ |
| 1089 | dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); |
| 1090 | dwc2_flush_rx_fifo(hsotg); |
| 1091 | |
| 1092 | /* Clear Host Set HNP Enable in the OTG Control Register */ |
| 1093 | otgctl = readl(hsotg->regs + GOTGCTL); |
| 1094 | otgctl &= ~GOTGCTL_HSTSETHNPEN; |
| 1095 | writel(otgctl, hsotg->regs + GOTGCTL); |
| 1096 | |
| 1097 | if (hsotg->core_params->dma_desc_enable <= 0) { |
| 1098 | int num_channels, i; |
| 1099 | u32 hcchar; |
| 1100 | |
| 1101 | /* Flush out any leftover queued requests */ |
| 1102 | num_channels = hsotg->core_params->host_channels; |
| 1103 | for (i = 0; i < num_channels; i++) { |
| 1104 | hcchar = readl(hsotg->regs + HCCHAR(i)); |
| 1105 | hcchar &= ~HCCHAR_CHENA; |
| 1106 | hcchar |= HCCHAR_CHDIS; |
| 1107 | hcchar &= ~HCCHAR_EPDIR; |
| 1108 | writel(hcchar, hsotg->regs + HCCHAR(i)); |
| 1109 | } |
| 1110 | |
| 1111 | /* Halt all channels to put them into a known state */ |
| 1112 | for (i = 0; i < num_channels; i++) { |
| 1113 | int count = 0; |
| 1114 | |
| 1115 | hcchar = readl(hsotg->regs + HCCHAR(i)); |
| 1116 | hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; |
| 1117 | hcchar &= ~HCCHAR_EPDIR; |
| 1118 | writel(hcchar, hsotg->regs + HCCHAR(i)); |
| 1119 | dev_dbg(hsotg->dev, "%s: Halt channel %d\n", |
| 1120 | __func__, i); |
| 1121 | do { |
| 1122 | hcchar = readl(hsotg->regs + HCCHAR(i)); |
| 1123 | if (++count > 1000) { |
| 1124 | dev_err(hsotg->dev, |
| 1125 | "Unable to clear enable on channel %d\n", |
| 1126 | i); |
| 1127 | break; |
| 1128 | } |
| 1129 | udelay(1); |
| 1130 | } while (hcchar & HCCHAR_CHENA); |
| 1131 | } |
| 1132 | } |
| 1133 | |
| 1134 | /* Turn on the vbus power */ |
| 1135 | dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); |
| 1136 | if (hsotg->op_state == OTG_STATE_A_HOST) { |
| 1137 | u32 hprt0 = dwc2_read_hprt0(hsotg); |
| 1138 | |
| 1139 | dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", |
| 1140 | !!(hprt0 & HPRT0_PWR)); |
| 1141 | if (!(hprt0 & HPRT0_PWR)) { |
| 1142 | hprt0 |= HPRT0_PWR; |
| 1143 | writel(hprt0, hsotg->regs + HPRT0); |
| 1144 | } |
| 1145 | } |
| 1146 | |
| 1147 | dwc2_enable_host_interrupts(hsotg); |
| 1148 | } |
| 1149 | |
| 1150 | static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, |
| 1151 | struct dwc2_host_chan *chan) |
| 1152 | { |
| 1153 | u32 hcintmsk = HCINTMSK_CHHLTD; |
| 1154 | |
| 1155 | switch (chan->ep_type) { |
| 1156 | case USB_ENDPOINT_XFER_CONTROL: |
| 1157 | case USB_ENDPOINT_XFER_BULK: |
| 1158 | dev_vdbg(hsotg->dev, "control/bulk\n"); |
| 1159 | hcintmsk |= HCINTMSK_XFERCOMPL; |
| 1160 | hcintmsk |= HCINTMSK_STALL; |
| 1161 | hcintmsk |= HCINTMSK_XACTERR; |
| 1162 | hcintmsk |= HCINTMSK_DATATGLERR; |
| 1163 | if (chan->ep_is_in) { |
| 1164 | hcintmsk |= HCINTMSK_BBLERR; |
| 1165 | } else { |
| 1166 | hcintmsk |= HCINTMSK_NAK; |
| 1167 | hcintmsk |= HCINTMSK_NYET; |
| 1168 | if (chan->do_ping) |
| 1169 | hcintmsk |= HCINTMSK_ACK; |
| 1170 | } |
| 1171 | |
| 1172 | if (chan->do_split) { |
| 1173 | hcintmsk |= HCINTMSK_NAK; |
| 1174 | if (chan->complete_split) |
| 1175 | hcintmsk |= HCINTMSK_NYET; |
| 1176 | else |
| 1177 | hcintmsk |= HCINTMSK_ACK; |
| 1178 | } |
| 1179 | |
| 1180 | if (chan->error_state) |
| 1181 | hcintmsk |= HCINTMSK_ACK; |
| 1182 | break; |
| 1183 | |
| 1184 | case USB_ENDPOINT_XFER_INT: |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1185 | if (dbg_perio()) |
| 1186 | dev_vdbg(hsotg->dev, "intr\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1187 | hcintmsk |= HCINTMSK_XFERCOMPL; |
| 1188 | hcintmsk |= HCINTMSK_NAK; |
| 1189 | hcintmsk |= HCINTMSK_STALL; |
| 1190 | hcintmsk |= HCINTMSK_XACTERR; |
| 1191 | hcintmsk |= HCINTMSK_DATATGLERR; |
| 1192 | hcintmsk |= HCINTMSK_FRMOVRUN; |
| 1193 | |
| 1194 | if (chan->ep_is_in) |
| 1195 | hcintmsk |= HCINTMSK_BBLERR; |
| 1196 | if (chan->error_state) |
| 1197 | hcintmsk |= HCINTMSK_ACK; |
| 1198 | if (chan->do_split) { |
| 1199 | if (chan->complete_split) |
| 1200 | hcintmsk |= HCINTMSK_NYET; |
| 1201 | else |
| 1202 | hcintmsk |= HCINTMSK_ACK; |
| 1203 | } |
| 1204 | break; |
| 1205 | |
| 1206 | case USB_ENDPOINT_XFER_ISOC: |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1207 | if (dbg_perio()) |
| 1208 | dev_vdbg(hsotg->dev, "isoc\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1209 | hcintmsk |= HCINTMSK_XFERCOMPL; |
| 1210 | hcintmsk |= HCINTMSK_FRMOVRUN; |
| 1211 | hcintmsk |= HCINTMSK_ACK; |
| 1212 | |
| 1213 | if (chan->ep_is_in) { |
| 1214 | hcintmsk |= HCINTMSK_XACTERR; |
| 1215 | hcintmsk |= HCINTMSK_BBLERR; |
| 1216 | } |
| 1217 | break; |
| 1218 | default: |
| 1219 | dev_err(hsotg->dev, "## Unknown EP type ##\n"); |
| 1220 | break; |
| 1221 | } |
| 1222 | |
| 1223 | writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1224 | if (dbg_hc(chan)) |
| 1225 | dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1226 | } |
| 1227 | |
| 1228 | static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, |
| 1229 | struct dwc2_host_chan *chan) |
| 1230 | { |
| 1231 | u32 hcintmsk = HCINTMSK_CHHLTD; |
| 1232 | |
| 1233 | /* |
| 1234 | * For Descriptor DMA mode core halts the channel on AHB error. |
| 1235 | * Interrupt is not required. |
| 1236 | */ |
| 1237 | if (hsotg->core_params->dma_desc_enable <= 0) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1238 | if (dbg_hc(chan)) |
| 1239 | dev_vdbg(hsotg->dev, "desc DMA disabled\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1240 | hcintmsk |= HCINTMSK_AHBERR; |
| 1241 | } else { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1242 | if (dbg_hc(chan)) |
| 1243 | dev_vdbg(hsotg->dev, "desc DMA enabled\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1244 | if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) |
| 1245 | hcintmsk |= HCINTMSK_XFERCOMPL; |
| 1246 | } |
| 1247 | |
| 1248 | if (chan->error_state && !chan->do_split && |
| 1249 | chan->ep_type != USB_ENDPOINT_XFER_ISOC) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1250 | if (dbg_hc(chan)) |
| 1251 | dev_vdbg(hsotg->dev, "setting ACK\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1252 | hcintmsk |= HCINTMSK_ACK; |
| 1253 | if (chan->ep_is_in) { |
| 1254 | hcintmsk |= HCINTMSK_DATATGLERR; |
| 1255 | if (chan->ep_type != USB_ENDPOINT_XFER_INT) |
| 1256 | hcintmsk |= HCINTMSK_NAK; |
| 1257 | } |
| 1258 | } |
| 1259 | |
| 1260 | writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1261 | if (dbg_hc(chan)) |
| 1262 | dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1263 | } |
| 1264 | |
| 1265 | static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, |
| 1266 | struct dwc2_host_chan *chan) |
| 1267 | { |
| 1268 | u32 intmsk; |
| 1269 | |
| 1270 | if (hsotg->core_params->dma_enable > 0) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1271 | if (dbg_hc(chan)) |
| 1272 | dev_vdbg(hsotg->dev, "DMA enabled\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1273 | dwc2_hc_enable_dma_ints(hsotg, chan); |
| 1274 | } else { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1275 | if (dbg_hc(chan)) |
| 1276 | dev_vdbg(hsotg->dev, "DMA disabled\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1277 | dwc2_hc_enable_slave_ints(hsotg, chan); |
| 1278 | } |
| 1279 | |
| 1280 | /* Enable the top level host channel interrupt */ |
| 1281 | intmsk = readl(hsotg->regs + HAINTMSK); |
| 1282 | intmsk |= 1 << chan->hc_num; |
| 1283 | writel(intmsk, hsotg->regs + HAINTMSK); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1284 | if (dbg_hc(chan)) |
| 1285 | dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1286 | |
| 1287 | /* Make sure host channel interrupts are enabled */ |
| 1288 | intmsk = readl(hsotg->regs + GINTMSK); |
| 1289 | intmsk |= GINTSTS_HCHINT; |
| 1290 | writel(intmsk, hsotg->regs + GINTMSK); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1291 | if (dbg_hc(chan)) |
| 1292 | dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1293 | } |
| 1294 | |
| 1295 | /** |
| 1296 | * dwc2_hc_init() - Prepares a host channel for transferring packets to/from |
| 1297 | * a specific endpoint |
| 1298 | * |
| 1299 | * @hsotg: Programming view of DWC_otg controller |
| 1300 | * @chan: Information needed to initialize the host channel |
| 1301 | * |
| 1302 | * The HCCHARn register is set up with the characteristics specified in chan. |
| 1303 | * Host channel interrupts that may need to be serviced while this transfer is |
| 1304 | * in progress are enabled. |
| 1305 | */ |
| 1306 | void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) |
| 1307 | { |
| 1308 | u8 hc_num = chan->hc_num; |
| 1309 | u32 hcintmsk; |
| 1310 | u32 hcchar; |
| 1311 | u32 hcsplt = 0; |
| 1312 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1313 | if (dbg_hc(chan)) |
| 1314 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1315 | |
| 1316 | /* Clear old interrupt conditions for this host channel */ |
| 1317 | hcintmsk = 0xffffffff; |
| 1318 | hcintmsk &= ~HCINTMSK_RESERVED14_31; |
| 1319 | writel(hcintmsk, hsotg->regs + HCINT(hc_num)); |
| 1320 | |
| 1321 | /* Enable channel interrupts required for this transfer */ |
| 1322 | dwc2_hc_enable_ints(hsotg, chan); |
| 1323 | |
| 1324 | /* |
| 1325 | * Program the HCCHARn register with the endpoint characteristics for |
| 1326 | * the current transfer |
| 1327 | */ |
| 1328 | hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; |
| 1329 | hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; |
| 1330 | if (chan->ep_is_in) |
| 1331 | hcchar |= HCCHAR_EPDIR; |
| 1332 | if (chan->speed == USB_SPEED_LOW) |
| 1333 | hcchar |= HCCHAR_LSPDDEV; |
| 1334 | hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; |
| 1335 | hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; |
| 1336 | writel(hcchar, hsotg->regs + HCCHAR(hc_num)); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1337 | if (dbg_hc(chan)) { |
| 1338 | dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", |
| 1339 | hc_num, hcchar); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1340 | |
Matthijs Kooijman | 57bb8ae | 2013-08-30 18:45:17 +0200 | [diff] [blame] | 1341 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", |
| 1342 | __func__, hc_num); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1343 | dev_vdbg(hsotg->dev, " Dev Addr: %d\n", |
Matthijs Kooijman | 57bb8ae | 2013-08-30 18:45:17 +0200 | [diff] [blame] | 1344 | chan->dev_addr); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1345 | dev_vdbg(hsotg->dev, " Ep Num: %d\n", |
Matthijs Kooijman | 57bb8ae | 2013-08-30 18:45:17 +0200 | [diff] [blame] | 1346 | chan->ep_num); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1347 | dev_vdbg(hsotg->dev, " Is In: %d\n", |
Matthijs Kooijman | 57bb8ae | 2013-08-30 18:45:17 +0200 | [diff] [blame] | 1348 | chan->ep_is_in); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1349 | dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", |
Matthijs Kooijman | 57bb8ae | 2013-08-30 18:45:17 +0200 | [diff] [blame] | 1350 | chan->speed == USB_SPEED_LOW); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1351 | dev_vdbg(hsotg->dev, " Ep Type: %d\n", |
Matthijs Kooijman | 57bb8ae | 2013-08-30 18:45:17 +0200 | [diff] [blame] | 1352 | chan->ep_type); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1353 | dev_vdbg(hsotg->dev, " Max Pkt: %d\n", |
Matthijs Kooijman | 57bb8ae | 2013-08-30 18:45:17 +0200 | [diff] [blame] | 1354 | chan->max_packet); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1355 | } |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1356 | |
| 1357 | /* Program the HCSPLT register for SPLITs */ |
| 1358 | if (chan->do_split) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1359 | if (dbg_hc(chan)) |
| 1360 | dev_vdbg(hsotg->dev, |
| 1361 | "Programming HC %d with split --> %s\n", |
| 1362 | hc_num, |
| 1363 | chan->complete_split ? "CSPLIT" : "SSPLIT"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1364 | if (chan->complete_split) |
| 1365 | hcsplt |= HCSPLT_COMPSPLT; |
| 1366 | hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & |
| 1367 | HCSPLT_XACTPOS_MASK; |
| 1368 | hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & |
| 1369 | HCSPLT_HUBADDR_MASK; |
| 1370 | hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & |
| 1371 | HCSPLT_PRTADDR_MASK; |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1372 | if (dbg_hc(chan)) { |
| 1373 | dev_vdbg(hsotg->dev, " comp split %d\n", |
| 1374 | chan->complete_split); |
| 1375 | dev_vdbg(hsotg->dev, " xact pos %d\n", |
| 1376 | chan->xact_pos); |
| 1377 | dev_vdbg(hsotg->dev, " hub addr %d\n", |
| 1378 | chan->hub_addr); |
| 1379 | dev_vdbg(hsotg->dev, " hub port %d\n", |
| 1380 | chan->hub_port); |
| 1381 | dev_vdbg(hsotg->dev, " is_in %d\n", |
| 1382 | chan->ep_is_in); |
| 1383 | dev_vdbg(hsotg->dev, " Max Pkt %d\n", |
Matthijs Kooijman | 57bb8ae | 2013-08-30 18:45:17 +0200 | [diff] [blame] | 1384 | chan->max_packet); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1385 | dev_vdbg(hsotg->dev, " xferlen %d\n", |
| 1386 | chan->xfer_len); |
| 1387 | } |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1388 | } |
| 1389 | |
| 1390 | writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); |
| 1391 | } |
| 1392 | |
| 1393 | /** |
| 1394 | * dwc2_hc_halt() - Attempts to halt a host channel |
| 1395 | * |
| 1396 | * @hsotg: Controller register interface |
| 1397 | * @chan: Host channel to halt |
| 1398 | * @halt_status: Reason for halting the channel |
| 1399 | * |
| 1400 | * This function should only be called in Slave mode or to abort a transfer in |
| 1401 | * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the |
| 1402 | * controller halts the channel when the transfer is complete or a condition |
| 1403 | * occurs that requires application intervention. |
| 1404 | * |
| 1405 | * In slave mode, checks for a free request queue entry, then sets the Channel |
| 1406 | * Enable and Channel Disable bits of the Host Channel Characteristics |
| 1407 | * register of the specified channel to intiate the halt. If there is no free |
| 1408 | * request queue entry, sets only the Channel Disable bit of the HCCHARn |
| 1409 | * register to flush requests for this channel. In the latter case, sets a |
| 1410 | * flag to indicate that the host channel needs to be halted when a request |
| 1411 | * queue slot is open. |
| 1412 | * |
| 1413 | * In DMA mode, always sets the Channel Enable and Channel Disable bits of the |
| 1414 | * HCCHARn register. The controller ensures there is space in the request |
| 1415 | * queue before submitting the halt request. |
| 1416 | * |
| 1417 | * Some time may elapse before the core flushes any posted requests for this |
| 1418 | * host channel and halts. The Channel Halted interrupt handler completes the |
| 1419 | * deactivation of the host channel. |
| 1420 | */ |
| 1421 | void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, |
| 1422 | enum dwc2_halt_status halt_status) |
| 1423 | { |
| 1424 | u32 nptxsts, hptxsts, hcchar; |
| 1425 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1426 | if (dbg_hc(chan)) |
| 1427 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1428 | if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) |
| 1429 | dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); |
| 1430 | |
| 1431 | if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || |
| 1432 | halt_status == DWC2_HC_XFER_AHB_ERR) { |
| 1433 | /* |
| 1434 | * Disable all channel interrupts except Ch Halted. The QTD |
| 1435 | * and QH state associated with this transfer has been cleared |
| 1436 | * (in the case of URB_DEQUEUE), so the channel needs to be |
| 1437 | * shut down carefully to prevent crashes. |
| 1438 | */ |
| 1439 | u32 hcintmsk = HCINTMSK_CHHLTD; |
| 1440 | |
| 1441 | dev_vdbg(hsotg->dev, "dequeue/error\n"); |
| 1442 | writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); |
| 1443 | |
| 1444 | /* |
| 1445 | * Make sure no other interrupts besides halt are currently |
| 1446 | * pending. Handling another interrupt could cause a crash due |
| 1447 | * to the QTD and QH state. |
| 1448 | */ |
| 1449 | writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); |
| 1450 | |
| 1451 | /* |
| 1452 | * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR |
| 1453 | * even if the channel was already halted for some other |
| 1454 | * reason |
| 1455 | */ |
| 1456 | chan->halt_status = halt_status; |
| 1457 | |
| 1458 | hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); |
| 1459 | if (!(hcchar & HCCHAR_CHENA)) { |
| 1460 | /* |
| 1461 | * The channel is either already halted or it hasn't |
| 1462 | * started yet. In DMA mode, the transfer may halt if |
| 1463 | * it finishes normally or a condition occurs that |
| 1464 | * requires driver intervention. Don't want to halt |
| 1465 | * the channel again. In either Slave or DMA mode, |
| 1466 | * it's possible that the transfer has been assigned |
| 1467 | * to a channel, but not started yet when an URB is |
| 1468 | * dequeued. Don't want to halt a channel that hasn't |
| 1469 | * started yet. |
| 1470 | */ |
| 1471 | return; |
| 1472 | } |
| 1473 | } |
| 1474 | if (chan->halt_pending) { |
| 1475 | /* |
| 1476 | * A halt has already been issued for this channel. This might |
| 1477 | * happen when a transfer is aborted by a higher level in |
| 1478 | * the stack. |
| 1479 | */ |
| 1480 | dev_vdbg(hsotg->dev, |
| 1481 | "*** %s: Channel %d, chan->halt_pending already set ***\n", |
| 1482 | __func__, chan->hc_num); |
| 1483 | return; |
| 1484 | } |
| 1485 | |
| 1486 | hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); |
| 1487 | |
| 1488 | /* No need to set the bit in DDMA for disabling the channel */ |
| 1489 | /* TODO check it everywhere channel is disabled */ |
| 1490 | if (hsotg->core_params->dma_desc_enable <= 0) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1491 | if (dbg_hc(chan)) |
| 1492 | dev_vdbg(hsotg->dev, "desc DMA disabled\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1493 | hcchar |= HCCHAR_CHENA; |
| 1494 | } else { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1495 | if (dbg_hc(chan)) |
| 1496 | dev_dbg(hsotg->dev, "desc DMA enabled\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1497 | } |
| 1498 | hcchar |= HCCHAR_CHDIS; |
| 1499 | |
| 1500 | if (hsotg->core_params->dma_enable <= 0) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1501 | if (dbg_hc(chan)) |
| 1502 | dev_vdbg(hsotg->dev, "DMA not enabled\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1503 | hcchar |= HCCHAR_CHENA; |
| 1504 | |
| 1505 | /* Check for space in the request queue to issue the halt */ |
| 1506 | if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || |
| 1507 | chan->ep_type == USB_ENDPOINT_XFER_BULK) { |
| 1508 | dev_vdbg(hsotg->dev, "control/bulk\n"); |
| 1509 | nptxsts = readl(hsotg->regs + GNPTXSTS); |
| 1510 | if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { |
| 1511 | dev_vdbg(hsotg->dev, "Disabling channel\n"); |
| 1512 | hcchar &= ~HCCHAR_CHENA; |
| 1513 | } |
| 1514 | } else { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1515 | if (dbg_perio()) |
| 1516 | dev_vdbg(hsotg->dev, "isoc/intr\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1517 | hptxsts = readl(hsotg->regs + HPTXSTS); |
| 1518 | if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || |
| 1519 | hsotg->queuing_high_bandwidth) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1520 | if (dbg_perio()) |
| 1521 | dev_vdbg(hsotg->dev, "Disabling channel\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1522 | hcchar &= ~HCCHAR_CHENA; |
| 1523 | } |
| 1524 | } |
| 1525 | } else { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1526 | if (dbg_hc(chan)) |
| 1527 | dev_vdbg(hsotg->dev, "DMA enabled\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1528 | } |
| 1529 | |
| 1530 | writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); |
| 1531 | chan->halt_status = halt_status; |
| 1532 | |
| 1533 | if (hcchar & HCCHAR_CHENA) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1534 | if (dbg_hc(chan)) |
| 1535 | dev_vdbg(hsotg->dev, "Channel enabled\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1536 | chan->halt_pending = 1; |
| 1537 | chan->halt_on_queue = 0; |
| 1538 | } else { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1539 | if (dbg_hc(chan)) |
| 1540 | dev_vdbg(hsotg->dev, "Channel disabled\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1541 | chan->halt_on_queue = 1; |
| 1542 | } |
| 1543 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1544 | if (dbg_hc(chan)) { |
| 1545 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, |
| 1546 | chan->hc_num); |
| 1547 | dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", |
| 1548 | hcchar); |
| 1549 | dev_vdbg(hsotg->dev, " halt_pending: %d\n", |
| 1550 | chan->halt_pending); |
| 1551 | dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", |
| 1552 | chan->halt_on_queue); |
| 1553 | dev_vdbg(hsotg->dev, " halt_status: %d\n", |
| 1554 | chan->halt_status); |
| 1555 | } |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1556 | } |
| 1557 | |
| 1558 | /** |
| 1559 | * dwc2_hc_cleanup() - Clears the transfer state for a host channel |
| 1560 | * |
| 1561 | * @hsotg: Programming view of DWC_otg controller |
| 1562 | * @chan: Identifies the host channel to clean up |
| 1563 | * |
| 1564 | * This function is normally called after a transfer is done and the host |
| 1565 | * channel is being released |
| 1566 | */ |
| 1567 | void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) |
| 1568 | { |
| 1569 | u32 hcintmsk; |
| 1570 | |
| 1571 | chan->xfer_started = 0; |
| 1572 | |
| 1573 | /* |
| 1574 | * Clear channel interrupt enables and any unhandled channel interrupt |
| 1575 | * conditions |
| 1576 | */ |
| 1577 | writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); |
| 1578 | hcintmsk = 0xffffffff; |
| 1579 | hcintmsk &= ~HCINTMSK_RESERVED14_31; |
| 1580 | writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); |
| 1581 | } |
| 1582 | |
| 1583 | /** |
| 1584 | * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in |
| 1585 | * which frame a periodic transfer should occur |
| 1586 | * |
| 1587 | * @hsotg: Programming view of DWC_otg controller |
| 1588 | * @chan: Identifies the host channel to set up and its properties |
| 1589 | * @hcchar: Current value of the HCCHAR register for the specified host channel |
| 1590 | * |
| 1591 | * This function has no effect on non-periodic transfers |
| 1592 | */ |
| 1593 | static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, |
| 1594 | struct dwc2_host_chan *chan, u32 *hcchar) |
| 1595 | { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1596 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || |
| 1597 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1598 | /* 1 if _next_ frame is odd, 0 if it's even */ |
Paul Zimmerman | 81a5895 | 2013-06-24 11:34:23 -0700 | [diff] [blame] | 1599 | if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1)) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1600 | *hcchar |= HCCHAR_ODDFRM; |
| 1601 | } |
| 1602 | } |
| 1603 | |
| 1604 | static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) |
| 1605 | { |
| 1606 | /* Set up the initial PID for the transfer */ |
| 1607 | if (chan->speed == USB_SPEED_HIGH) { |
| 1608 | if (chan->ep_is_in) { |
| 1609 | if (chan->multi_count == 1) |
| 1610 | chan->data_pid_start = DWC2_HC_PID_DATA0; |
| 1611 | else if (chan->multi_count == 2) |
| 1612 | chan->data_pid_start = DWC2_HC_PID_DATA1; |
| 1613 | else |
| 1614 | chan->data_pid_start = DWC2_HC_PID_DATA2; |
| 1615 | } else { |
| 1616 | if (chan->multi_count == 1) |
| 1617 | chan->data_pid_start = DWC2_HC_PID_DATA0; |
| 1618 | else |
| 1619 | chan->data_pid_start = DWC2_HC_PID_MDATA; |
| 1620 | } |
| 1621 | } else { |
| 1622 | chan->data_pid_start = DWC2_HC_PID_DATA0; |
| 1623 | } |
| 1624 | } |
| 1625 | |
| 1626 | /** |
| 1627 | * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with |
| 1628 | * the Host Channel |
| 1629 | * |
| 1630 | * @hsotg: Programming view of DWC_otg controller |
| 1631 | * @chan: Information needed to initialize the host channel |
| 1632 | * |
| 1633 | * This function should only be called in Slave mode. For a channel associated |
| 1634 | * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel |
| 1635 | * associated with a periodic EP, the periodic Tx FIFO is written. |
| 1636 | * |
| 1637 | * Upon return the xfer_buf and xfer_count fields in chan are incremented by |
| 1638 | * the number of bytes written to the Tx FIFO. |
| 1639 | */ |
| 1640 | static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, |
| 1641 | struct dwc2_host_chan *chan) |
| 1642 | { |
| 1643 | u32 i; |
| 1644 | u32 remaining_count; |
| 1645 | u32 byte_count; |
| 1646 | u32 dword_count; |
| 1647 | u32 __iomem *data_fifo; |
| 1648 | u32 *data_buf = (u32 *)chan->xfer_buf; |
| 1649 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1650 | if (dbg_hc(chan)) |
| 1651 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1652 | |
| 1653 | data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); |
| 1654 | |
| 1655 | remaining_count = chan->xfer_len - chan->xfer_count; |
| 1656 | if (remaining_count > chan->max_packet) |
| 1657 | byte_count = chan->max_packet; |
| 1658 | else |
| 1659 | byte_count = remaining_count; |
| 1660 | |
| 1661 | dword_count = (byte_count + 3) / 4; |
| 1662 | |
| 1663 | if (((unsigned long)data_buf & 0x3) == 0) { |
| 1664 | /* xfer_buf is DWORD aligned */ |
| 1665 | for (i = 0; i < dword_count; i++, data_buf++) |
| 1666 | writel(*data_buf, data_fifo); |
| 1667 | } else { |
| 1668 | /* xfer_buf is not DWORD aligned */ |
| 1669 | for (i = 0; i < dword_count; i++, data_buf++) { |
| 1670 | u32 data = data_buf[0] | data_buf[1] << 8 | |
| 1671 | data_buf[2] << 16 | data_buf[3] << 24; |
| 1672 | writel(data, data_fifo); |
| 1673 | } |
| 1674 | } |
| 1675 | |
| 1676 | chan->xfer_count += byte_count; |
| 1677 | chan->xfer_buf += byte_count; |
| 1678 | } |
| 1679 | |
| 1680 | /** |
| 1681 | * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host |
| 1682 | * channel and starts the transfer |
| 1683 | * |
| 1684 | * @hsotg: Programming view of DWC_otg controller |
| 1685 | * @chan: Information needed to initialize the host channel. The xfer_len value |
| 1686 | * may be reduced to accommodate the max widths of the XferSize and |
| 1687 | * PktCnt fields in the HCTSIZn register. The multi_count value may be |
| 1688 | * changed to reflect the final xfer_len value. |
| 1689 | * |
| 1690 | * This function may be called in either Slave mode or DMA mode. In Slave mode, |
| 1691 | * the caller must ensure that there is sufficient space in the request queue |
| 1692 | * and Tx Data FIFO. |
| 1693 | * |
| 1694 | * For an OUT transfer in Slave mode, it loads a data packet into the |
| 1695 | * appropriate FIFO. If necessary, additional data packets are loaded in the |
| 1696 | * Host ISR. |
| 1697 | * |
| 1698 | * For an IN transfer in Slave mode, a data packet is requested. The data |
| 1699 | * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, |
| 1700 | * additional data packets are requested in the Host ISR. |
| 1701 | * |
| 1702 | * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ |
| 1703 | * register along with a packet count of 1 and the channel is enabled. This |
| 1704 | * causes a single PING transaction to occur. Other fields in HCTSIZ are |
| 1705 | * simply set to 0 since no data transfer occurs in this case. |
| 1706 | * |
| 1707 | * For a PING transfer in DMA mode, the HCTSIZ register is initialized with |
| 1708 | * all the information required to perform the subsequent data transfer. In |
| 1709 | * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the |
| 1710 | * controller performs the entire PING protocol, then starts the data |
| 1711 | * transfer. |
| 1712 | */ |
| 1713 | void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, |
| 1714 | struct dwc2_host_chan *chan) |
| 1715 | { |
| 1716 | u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size; |
| 1717 | u16 max_hc_pkt_count = hsotg->core_params->max_packet_count; |
| 1718 | u32 hcchar; |
| 1719 | u32 hctsiz = 0; |
| 1720 | u16 num_packets; |
| 1721 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1722 | if (dbg_hc(chan)) |
| 1723 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1724 | |
| 1725 | if (chan->do_ping) { |
| 1726 | if (hsotg->core_params->dma_enable <= 0) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1727 | if (dbg_hc(chan)) |
| 1728 | dev_vdbg(hsotg->dev, "ping, no DMA\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1729 | dwc2_hc_do_ping(hsotg, chan); |
| 1730 | chan->xfer_started = 1; |
| 1731 | return; |
| 1732 | } else { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1733 | if (dbg_hc(chan)) |
| 1734 | dev_vdbg(hsotg->dev, "ping, DMA\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1735 | hctsiz |= TSIZ_DOPNG; |
| 1736 | } |
| 1737 | } |
| 1738 | |
| 1739 | if (chan->do_split) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1740 | if (dbg_hc(chan)) |
| 1741 | dev_vdbg(hsotg->dev, "split\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1742 | num_packets = 1; |
| 1743 | |
| 1744 | if (chan->complete_split && !chan->ep_is_in) |
| 1745 | /* |
| 1746 | * For CSPLIT OUT Transfer, set the size to 0 so the |
| 1747 | * core doesn't expect any data written to the FIFO |
| 1748 | */ |
| 1749 | chan->xfer_len = 0; |
| 1750 | else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) |
| 1751 | chan->xfer_len = chan->max_packet; |
| 1752 | else if (!chan->ep_is_in && chan->xfer_len > 188) |
| 1753 | chan->xfer_len = 188; |
| 1754 | |
| 1755 | hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & |
| 1756 | TSIZ_XFERSIZE_MASK; |
| 1757 | } else { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1758 | if (dbg_hc(chan)) |
| 1759 | dev_vdbg(hsotg->dev, "no split\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1760 | /* |
| 1761 | * Ensure that the transfer length and packet count will fit |
| 1762 | * in the widths allocated for them in the HCTSIZn register |
| 1763 | */ |
| 1764 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || |
| 1765 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) { |
| 1766 | /* |
| 1767 | * Make sure the transfer size is no larger than one |
| 1768 | * (micro)frame's worth of data. (A check was done |
| 1769 | * when the periodic transfer was accepted to ensure |
| 1770 | * that a (micro)frame's worth of data can be |
| 1771 | * programmed into a channel.) |
| 1772 | */ |
| 1773 | u32 max_periodic_len = |
| 1774 | chan->multi_count * chan->max_packet; |
| 1775 | |
| 1776 | if (chan->xfer_len > max_periodic_len) |
| 1777 | chan->xfer_len = max_periodic_len; |
| 1778 | } else if (chan->xfer_len > max_hc_xfer_size) { |
| 1779 | /* |
| 1780 | * Make sure that xfer_len is a multiple of max packet |
| 1781 | * size |
| 1782 | */ |
| 1783 | chan->xfer_len = |
| 1784 | max_hc_xfer_size - chan->max_packet + 1; |
| 1785 | } |
| 1786 | |
| 1787 | if (chan->xfer_len > 0) { |
| 1788 | num_packets = (chan->xfer_len + chan->max_packet - 1) / |
| 1789 | chan->max_packet; |
| 1790 | if (num_packets > max_hc_pkt_count) { |
| 1791 | num_packets = max_hc_pkt_count; |
| 1792 | chan->xfer_len = num_packets * chan->max_packet; |
| 1793 | } |
| 1794 | } else { |
| 1795 | /* Need 1 packet for transfer length of 0 */ |
| 1796 | num_packets = 1; |
| 1797 | } |
| 1798 | |
| 1799 | if (chan->ep_is_in) |
| 1800 | /* |
| 1801 | * Always program an integral # of max packets for IN |
| 1802 | * transfers |
| 1803 | */ |
| 1804 | chan->xfer_len = num_packets * chan->max_packet; |
| 1805 | |
| 1806 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || |
| 1807 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) |
| 1808 | /* |
| 1809 | * Make sure that the multi_count field matches the |
| 1810 | * actual transfer length |
| 1811 | */ |
| 1812 | chan->multi_count = num_packets; |
| 1813 | |
| 1814 | if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) |
| 1815 | dwc2_set_pid_isoc(chan); |
| 1816 | |
| 1817 | hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & |
| 1818 | TSIZ_XFERSIZE_MASK; |
| 1819 | } |
| 1820 | |
| 1821 | chan->start_pkt_count = num_packets; |
| 1822 | hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; |
| 1823 | hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & |
| 1824 | TSIZ_SC_MC_PID_MASK; |
| 1825 | writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1826 | if (dbg_hc(chan)) { |
| 1827 | dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", |
| 1828 | hctsiz, chan->hc_num); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1829 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1830 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, |
| 1831 | chan->hc_num); |
| 1832 | dev_vdbg(hsotg->dev, " Xfer Size: %d\n", |
Matthijs Kooijman | d6ec53e | 2013-08-30 18:45:15 +0200 | [diff] [blame] | 1833 | (hctsiz & TSIZ_XFERSIZE_MASK) >> |
| 1834 | TSIZ_XFERSIZE_SHIFT); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1835 | dev_vdbg(hsotg->dev, " Num Pkts: %d\n", |
Matthijs Kooijman | d6ec53e | 2013-08-30 18:45:15 +0200 | [diff] [blame] | 1836 | (hctsiz & TSIZ_PKTCNT_MASK) >> |
| 1837 | TSIZ_PKTCNT_SHIFT); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1838 | dev_vdbg(hsotg->dev, " Start PID: %d\n", |
Matthijs Kooijman | d6ec53e | 2013-08-30 18:45:15 +0200 | [diff] [blame] | 1839 | (hctsiz & TSIZ_SC_MC_PID_MASK) >> |
| 1840 | TSIZ_SC_MC_PID_SHIFT); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1841 | } |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1842 | |
| 1843 | if (hsotg->core_params->dma_enable > 0) { |
| 1844 | dma_addr_t dma_addr; |
| 1845 | |
| 1846 | if (chan->align_buf) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1847 | if (dbg_hc(chan)) |
| 1848 | dev_vdbg(hsotg->dev, "align_buf\n"); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1849 | dma_addr = chan->align_buf; |
| 1850 | } else { |
| 1851 | dma_addr = chan->xfer_dma; |
| 1852 | } |
| 1853 | writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1854 | if (dbg_hc(chan)) |
| 1855 | dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", |
| 1856 | (unsigned long)dma_addr, chan->hc_num); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1857 | } |
| 1858 | |
| 1859 | /* Start the split */ |
| 1860 | if (chan->do_split) { |
| 1861 | u32 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); |
| 1862 | |
| 1863 | hcsplt |= HCSPLT_SPLTENA; |
| 1864 | writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); |
| 1865 | } |
| 1866 | |
| 1867 | hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); |
| 1868 | hcchar &= ~HCCHAR_MULTICNT_MASK; |
| 1869 | hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & |
| 1870 | HCCHAR_MULTICNT_MASK; |
| 1871 | dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); |
| 1872 | |
| 1873 | if (hcchar & HCCHAR_CHDIS) |
| 1874 | dev_warn(hsotg->dev, |
| 1875 | "%s: chdis set, channel %d, hcchar 0x%08x\n", |
| 1876 | __func__, chan->hc_num, hcchar); |
| 1877 | |
| 1878 | /* Set host channel enable after all other setup is complete */ |
| 1879 | hcchar |= HCCHAR_CHENA; |
| 1880 | hcchar &= ~HCCHAR_CHDIS; |
| 1881 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1882 | if (dbg_hc(chan)) |
| 1883 | dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", |
Matthijs Kooijman | d6ec53e | 2013-08-30 18:45:15 +0200 | [diff] [blame] | 1884 | (hcchar & HCCHAR_MULTICNT_MASK) >> |
| 1885 | HCCHAR_MULTICNT_SHIFT); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1886 | |
| 1887 | writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1888 | if (dbg_hc(chan)) |
| 1889 | dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, |
| 1890 | chan->hc_num); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1891 | |
| 1892 | chan->xfer_started = 1; |
| 1893 | chan->requests++; |
| 1894 | |
| 1895 | if (hsotg->core_params->dma_enable <= 0 && |
| 1896 | !chan->ep_is_in && chan->xfer_len > 0) |
| 1897 | /* Load OUT packet into the appropriate Tx FIFO */ |
| 1898 | dwc2_hc_write_packet(hsotg, chan); |
| 1899 | } |
| 1900 | |
| 1901 | /** |
| 1902 | * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a |
| 1903 | * host channel and starts the transfer in Descriptor DMA mode |
| 1904 | * |
| 1905 | * @hsotg: Programming view of DWC_otg controller |
| 1906 | * @chan: Information needed to initialize the host channel |
| 1907 | * |
| 1908 | * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. |
| 1909 | * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field |
| 1910 | * with micro-frame bitmap. |
| 1911 | * |
| 1912 | * Initializes HCDMA register with descriptor list address and CTD value then |
| 1913 | * starts the transfer via enabling the channel. |
| 1914 | */ |
| 1915 | void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, |
| 1916 | struct dwc2_host_chan *chan) |
| 1917 | { |
| 1918 | u32 hcchar; |
| 1919 | u32 hc_dma; |
| 1920 | u32 hctsiz = 0; |
| 1921 | |
| 1922 | if (chan->do_ping) |
| 1923 | hctsiz |= TSIZ_DOPNG; |
| 1924 | |
| 1925 | if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) |
| 1926 | dwc2_set_pid_isoc(chan); |
| 1927 | |
| 1928 | /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ |
| 1929 | hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & |
| 1930 | TSIZ_SC_MC_PID_MASK; |
| 1931 | |
| 1932 | /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ |
| 1933 | hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; |
| 1934 | |
| 1935 | /* Non-zero only for high-speed interrupt endpoints */ |
| 1936 | hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; |
| 1937 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1938 | if (dbg_hc(chan)) { |
| 1939 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, |
| 1940 | chan->hc_num); |
| 1941 | dev_vdbg(hsotg->dev, " Start PID: %d\n", |
| 1942 | chan->data_pid_start); |
| 1943 | dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); |
| 1944 | } |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1945 | |
| 1946 | writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); |
| 1947 | |
| 1948 | hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK; |
| 1949 | |
| 1950 | /* Always start from first descriptor */ |
| 1951 | hc_dma &= ~HCDMA_CTD_MASK; |
| 1952 | writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num)); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1953 | if (dbg_hc(chan)) |
| 1954 | dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n", |
| 1955 | hc_dma, chan->hc_num); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1956 | |
| 1957 | hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); |
| 1958 | hcchar &= ~HCCHAR_MULTICNT_MASK; |
| 1959 | hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & |
| 1960 | HCCHAR_MULTICNT_MASK; |
| 1961 | |
| 1962 | if (hcchar & HCCHAR_CHDIS) |
| 1963 | dev_warn(hsotg->dev, |
| 1964 | "%s: chdis set, channel %d, hcchar 0x%08x\n", |
| 1965 | __func__, chan->hc_num, hcchar); |
| 1966 | |
| 1967 | /* Set host channel enable after all other setup is complete */ |
| 1968 | hcchar |= HCCHAR_CHENA; |
| 1969 | hcchar &= ~HCCHAR_CHDIS; |
| 1970 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1971 | if (dbg_hc(chan)) |
| 1972 | dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", |
Matthijs Kooijman | d6ec53e | 2013-08-30 18:45:15 +0200 | [diff] [blame] | 1973 | (hcchar & HCCHAR_MULTICNT_MASK) >> |
| 1974 | HCCHAR_MULTICNT_SHIFT); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1975 | |
| 1976 | writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1977 | if (dbg_hc(chan)) |
| 1978 | dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, |
| 1979 | chan->hc_num); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 1980 | |
| 1981 | chan->xfer_started = 1; |
| 1982 | chan->requests++; |
| 1983 | } |
| 1984 | |
| 1985 | /** |
| 1986 | * dwc2_hc_continue_transfer() - Continues a data transfer that was started by |
| 1987 | * a previous call to dwc2_hc_start_transfer() |
| 1988 | * |
| 1989 | * @hsotg: Programming view of DWC_otg controller |
| 1990 | * @chan: Information needed to initialize the host channel |
| 1991 | * |
| 1992 | * The caller must ensure there is sufficient space in the request queue and Tx |
| 1993 | * Data FIFO. This function should only be called in Slave mode. In DMA mode, |
| 1994 | * the controller acts autonomously to complete transfers programmed to a host |
| 1995 | * channel. |
| 1996 | * |
| 1997 | * For an OUT transfer, a new data packet is loaded into the appropriate FIFO |
| 1998 | * if there is any data remaining to be queued. For an IN transfer, another |
| 1999 | * data packet is always requested. For the SETUP phase of a control transfer, |
| 2000 | * this function does nothing. |
| 2001 | * |
| 2002 | * Return: 1 if a new request is queued, 0 if no more requests are required |
| 2003 | * for this transfer |
| 2004 | */ |
| 2005 | int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, |
| 2006 | struct dwc2_host_chan *chan) |
| 2007 | { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 2008 | if (dbg_hc(chan)) |
| 2009 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, |
| 2010 | chan->hc_num); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2011 | |
| 2012 | if (chan->do_split) |
| 2013 | /* SPLITs always queue just once per channel */ |
| 2014 | return 0; |
| 2015 | |
| 2016 | if (chan->data_pid_start == DWC2_HC_PID_SETUP) |
| 2017 | /* SETUPs are queued only once since they can't be NAK'd */ |
| 2018 | return 0; |
| 2019 | |
| 2020 | if (chan->ep_is_in) { |
| 2021 | /* |
| 2022 | * Always queue another request for other IN transfers. If |
| 2023 | * back-to-back INs are issued and NAKs are received for both, |
| 2024 | * the driver may still be processing the first NAK when the |
| 2025 | * second NAK is received. When the interrupt handler clears |
| 2026 | * the NAK interrupt for the first NAK, the second NAK will |
| 2027 | * not be seen. So we can't depend on the NAK interrupt |
| 2028 | * handler to requeue a NAK'd request. Instead, IN requests |
| 2029 | * are issued each time this function is called. When the |
| 2030 | * transfer completes, the extra requests for the channel will |
| 2031 | * be flushed. |
| 2032 | */ |
| 2033 | u32 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); |
| 2034 | |
| 2035 | dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); |
| 2036 | hcchar |= HCCHAR_CHENA; |
| 2037 | hcchar &= ~HCCHAR_CHDIS; |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 2038 | if (dbg_hc(chan)) |
| 2039 | dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", |
| 2040 | hcchar); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2041 | writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); |
| 2042 | chan->requests++; |
| 2043 | return 1; |
| 2044 | } |
| 2045 | |
| 2046 | /* OUT transfers */ |
| 2047 | |
| 2048 | if (chan->xfer_count < chan->xfer_len) { |
| 2049 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || |
| 2050 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) { |
| 2051 | u32 hcchar = readl(hsotg->regs + |
| 2052 | HCCHAR(chan->hc_num)); |
| 2053 | |
| 2054 | dwc2_hc_set_even_odd_frame(hsotg, chan, |
| 2055 | &hcchar); |
| 2056 | } |
| 2057 | |
| 2058 | /* Load OUT packet into the appropriate Tx FIFO */ |
| 2059 | dwc2_hc_write_packet(hsotg, chan); |
| 2060 | chan->requests++; |
| 2061 | return 1; |
| 2062 | } |
| 2063 | |
| 2064 | return 0; |
| 2065 | } |
| 2066 | |
| 2067 | /** |
| 2068 | * dwc2_hc_do_ping() - Starts a PING transfer |
| 2069 | * |
| 2070 | * @hsotg: Programming view of DWC_otg controller |
| 2071 | * @chan: Information needed to initialize the host channel |
| 2072 | * |
| 2073 | * This function should only be called in Slave mode. The Do Ping bit is set in |
| 2074 | * the HCTSIZ register, then the channel is enabled. |
| 2075 | */ |
| 2076 | void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) |
| 2077 | { |
| 2078 | u32 hcchar; |
| 2079 | u32 hctsiz; |
| 2080 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 2081 | if (dbg_hc(chan)) |
| 2082 | dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, |
| 2083 | chan->hc_num); |
| 2084 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2085 | |
| 2086 | hctsiz = TSIZ_DOPNG; |
| 2087 | hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; |
| 2088 | writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); |
| 2089 | |
| 2090 | hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); |
| 2091 | hcchar |= HCCHAR_CHENA; |
| 2092 | hcchar &= ~HCCHAR_CHDIS; |
| 2093 | writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); |
| 2094 | } |
| 2095 | |
| 2096 | /** |
| 2097 | * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for |
| 2098 | * the HFIR register according to PHY type and speed |
| 2099 | * |
| 2100 | * @hsotg: Programming view of DWC_otg controller |
| 2101 | * |
| 2102 | * NOTE: The caller can modify the value of the HFIR register only after the |
| 2103 | * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) |
| 2104 | * has been set |
| 2105 | */ |
| 2106 | u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) |
| 2107 | { |
| 2108 | u32 usbcfg; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2109 | u32 hprt0; |
| 2110 | int clock = 60; /* default value */ |
| 2111 | |
| 2112 | usbcfg = readl(hsotg->regs + GUSBCFG); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2113 | hprt0 = readl(hsotg->regs + HPRT0); |
| 2114 | |
| 2115 | if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && |
| 2116 | !(usbcfg & GUSBCFG_PHYIF16)) |
| 2117 | clock = 60; |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2118 | if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2119 | GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) |
| 2120 | clock = 48; |
| 2121 | if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && |
| 2122 | !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) |
| 2123 | clock = 30; |
| 2124 | if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && |
| 2125 | !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) |
| 2126 | clock = 60; |
| 2127 | if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && |
| 2128 | !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) |
| 2129 | clock = 48; |
| 2130 | if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2131 | hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2132 | clock = 48; |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 2133 | if ((usbcfg & GUSBCFG_PHYSEL) && |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2134 | hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2135 | clock = 48; |
| 2136 | |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 2137 | if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2138 | /* High speed case */ |
| 2139 | return 125 * clock; |
| 2140 | else |
| 2141 | /* FS/LS case */ |
| 2142 | return 1000 * clock; |
| 2143 | } |
| 2144 | |
| 2145 | /** |
| 2146 | * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination |
| 2147 | * buffer |
| 2148 | * |
| 2149 | * @core_if: Programming view of DWC_otg controller |
| 2150 | * @dest: Destination buffer for the packet |
| 2151 | * @bytes: Number of bytes to copy to the destination |
| 2152 | */ |
| 2153 | void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) |
| 2154 | { |
| 2155 | u32 __iomem *fifo = hsotg->regs + HCFIFO(0); |
| 2156 | u32 *data_buf = (u32 *)dest; |
| 2157 | int word_count = (bytes + 3) / 4; |
| 2158 | int i; |
| 2159 | |
| 2160 | /* |
| 2161 | * Todo: Account for the case where dest is not dword aligned. This |
| 2162 | * requires reading data from the FIFO into a u32 temp buffer, then |
| 2163 | * moving it into the data buffer. |
| 2164 | */ |
| 2165 | |
| 2166 | dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); |
| 2167 | |
| 2168 | for (i = 0; i < word_count; i++, data_buf++) |
| 2169 | *data_buf = readl(fifo); |
| 2170 | } |
| 2171 | |
| 2172 | /** |
| 2173 | * dwc2_dump_host_registers() - Prints the host registers |
| 2174 | * |
| 2175 | * @hsotg: Programming view of DWC_otg controller |
| 2176 | * |
| 2177 | * NOTE: This function will be removed once the peripheral controller code |
| 2178 | * is integrated and the driver is stable |
| 2179 | */ |
| 2180 | void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) |
| 2181 | { |
| 2182 | #ifdef DEBUG |
| 2183 | u32 __iomem *addr; |
| 2184 | int i; |
| 2185 | |
| 2186 | dev_dbg(hsotg->dev, "Host Global Registers\n"); |
| 2187 | addr = hsotg->regs + HCFG; |
| 2188 | dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", |
| 2189 | (unsigned long)addr, readl(addr)); |
| 2190 | addr = hsotg->regs + HFIR; |
| 2191 | dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", |
| 2192 | (unsigned long)addr, readl(addr)); |
| 2193 | addr = hsotg->regs + HFNUM; |
| 2194 | dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", |
| 2195 | (unsigned long)addr, readl(addr)); |
| 2196 | addr = hsotg->regs + HPTXSTS; |
| 2197 | dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", |
| 2198 | (unsigned long)addr, readl(addr)); |
| 2199 | addr = hsotg->regs + HAINT; |
| 2200 | dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", |
| 2201 | (unsigned long)addr, readl(addr)); |
| 2202 | addr = hsotg->regs + HAINTMSK; |
| 2203 | dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", |
| 2204 | (unsigned long)addr, readl(addr)); |
| 2205 | if (hsotg->core_params->dma_desc_enable > 0) { |
| 2206 | addr = hsotg->regs + HFLBADDR; |
| 2207 | dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", |
| 2208 | (unsigned long)addr, readl(addr)); |
| 2209 | } |
| 2210 | |
| 2211 | addr = hsotg->regs + HPRT0; |
| 2212 | dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", |
| 2213 | (unsigned long)addr, readl(addr)); |
| 2214 | |
| 2215 | for (i = 0; i < hsotg->core_params->host_channels; i++) { |
| 2216 | dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); |
| 2217 | addr = hsotg->regs + HCCHAR(i); |
| 2218 | dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", |
| 2219 | (unsigned long)addr, readl(addr)); |
| 2220 | addr = hsotg->regs + HCSPLT(i); |
| 2221 | dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", |
| 2222 | (unsigned long)addr, readl(addr)); |
| 2223 | addr = hsotg->regs + HCINT(i); |
| 2224 | dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", |
| 2225 | (unsigned long)addr, readl(addr)); |
| 2226 | addr = hsotg->regs + HCINTMSK(i); |
| 2227 | dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", |
| 2228 | (unsigned long)addr, readl(addr)); |
| 2229 | addr = hsotg->regs + HCTSIZ(i); |
| 2230 | dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", |
| 2231 | (unsigned long)addr, readl(addr)); |
| 2232 | addr = hsotg->regs + HCDMA(i); |
| 2233 | dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", |
| 2234 | (unsigned long)addr, readl(addr)); |
| 2235 | if (hsotg->core_params->dma_desc_enable > 0) { |
| 2236 | addr = hsotg->regs + HCDMAB(i); |
| 2237 | dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", |
| 2238 | (unsigned long)addr, readl(addr)); |
| 2239 | } |
| 2240 | } |
| 2241 | #endif |
| 2242 | } |
| 2243 | |
| 2244 | /** |
| 2245 | * dwc2_dump_global_registers() - Prints the core global registers |
| 2246 | * |
| 2247 | * @hsotg: Programming view of DWC_otg controller |
| 2248 | * |
| 2249 | * NOTE: This function will be removed once the peripheral controller code |
| 2250 | * is integrated and the driver is stable |
| 2251 | */ |
| 2252 | void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) |
| 2253 | { |
| 2254 | #ifdef DEBUG |
| 2255 | u32 __iomem *addr; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2256 | |
| 2257 | dev_dbg(hsotg->dev, "Core Global Registers\n"); |
| 2258 | addr = hsotg->regs + GOTGCTL; |
| 2259 | dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", |
| 2260 | (unsigned long)addr, readl(addr)); |
| 2261 | addr = hsotg->regs + GOTGINT; |
| 2262 | dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", |
| 2263 | (unsigned long)addr, readl(addr)); |
| 2264 | addr = hsotg->regs + GAHBCFG; |
| 2265 | dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", |
| 2266 | (unsigned long)addr, readl(addr)); |
| 2267 | addr = hsotg->regs + GUSBCFG; |
| 2268 | dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", |
| 2269 | (unsigned long)addr, readl(addr)); |
| 2270 | addr = hsotg->regs + GRSTCTL; |
| 2271 | dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", |
| 2272 | (unsigned long)addr, readl(addr)); |
| 2273 | addr = hsotg->regs + GINTSTS; |
| 2274 | dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", |
| 2275 | (unsigned long)addr, readl(addr)); |
| 2276 | addr = hsotg->regs + GINTMSK; |
| 2277 | dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", |
| 2278 | (unsigned long)addr, readl(addr)); |
| 2279 | addr = hsotg->regs + GRXSTSR; |
| 2280 | dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", |
| 2281 | (unsigned long)addr, readl(addr)); |
| 2282 | addr = hsotg->regs + GRXFSIZ; |
| 2283 | dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", |
| 2284 | (unsigned long)addr, readl(addr)); |
| 2285 | addr = hsotg->regs + GNPTXFSIZ; |
| 2286 | dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", |
| 2287 | (unsigned long)addr, readl(addr)); |
| 2288 | addr = hsotg->regs + GNPTXSTS; |
| 2289 | dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", |
| 2290 | (unsigned long)addr, readl(addr)); |
| 2291 | addr = hsotg->regs + GI2CCTL; |
| 2292 | dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", |
| 2293 | (unsigned long)addr, readl(addr)); |
| 2294 | addr = hsotg->regs + GPVNDCTL; |
| 2295 | dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", |
| 2296 | (unsigned long)addr, readl(addr)); |
| 2297 | addr = hsotg->regs + GGPIO; |
| 2298 | dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", |
| 2299 | (unsigned long)addr, readl(addr)); |
| 2300 | addr = hsotg->regs + GUID; |
| 2301 | dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", |
| 2302 | (unsigned long)addr, readl(addr)); |
| 2303 | addr = hsotg->regs + GSNPSID; |
| 2304 | dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", |
| 2305 | (unsigned long)addr, readl(addr)); |
| 2306 | addr = hsotg->regs + GHWCFG1; |
| 2307 | dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", |
| 2308 | (unsigned long)addr, readl(addr)); |
| 2309 | addr = hsotg->regs + GHWCFG2; |
| 2310 | dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", |
| 2311 | (unsigned long)addr, readl(addr)); |
| 2312 | addr = hsotg->regs + GHWCFG3; |
| 2313 | dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", |
| 2314 | (unsigned long)addr, readl(addr)); |
| 2315 | addr = hsotg->regs + GHWCFG4; |
| 2316 | dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", |
| 2317 | (unsigned long)addr, readl(addr)); |
| 2318 | addr = hsotg->regs + GLPMCFG; |
| 2319 | dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", |
| 2320 | (unsigned long)addr, readl(addr)); |
| 2321 | addr = hsotg->regs + GPWRDN; |
| 2322 | dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", |
| 2323 | (unsigned long)addr, readl(addr)); |
| 2324 | addr = hsotg->regs + GDFIFOCFG; |
| 2325 | dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", |
| 2326 | (unsigned long)addr, readl(addr)); |
| 2327 | addr = hsotg->regs + HPTXFSIZ; |
| 2328 | dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", |
| 2329 | (unsigned long)addr, readl(addr)); |
| 2330 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2331 | addr = hsotg->regs + PCGCTL; |
| 2332 | dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", |
| 2333 | (unsigned long)addr, readl(addr)); |
| 2334 | #endif |
| 2335 | } |
| 2336 | |
| 2337 | /** |
| 2338 | * dwc2_flush_tx_fifo() - Flushes a Tx FIFO |
| 2339 | * |
| 2340 | * @hsotg: Programming view of DWC_otg controller |
| 2341 | * @num: Tx FIFO to flush |
| 2342 | */ |
| 2343 | void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) |
| 2344 | { |
| 2345 | u32 greset; |
| 2346 | int count = 0; |
| 2347 | |
| 2348 | dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); |
| 2349 | |
| 2350 | greset = GRSTCTL_TXFFLSH; |
| 2351 | greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; |
| 2352 | writel(greset, hsotg->regs + GRSTCTL); |
| 2353 | |
| 2354 | do { |
| 2355 | greset = readl(hsotg->regs + GRSTCTL); |
| 2356 | if (++count > 10000) { |
| 2357 | dev_warn(hsotg->dev, |
| 2358 | "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", |
| 2359 | __func__, greset, |
| 2360 | readl(hsotg->regs + GNPTXSTS)); |
| 2361 | break; |
| 2362 | } |
| 2363 | udelay(1); |
| 2364 | } while (greset & GRSTCTL_TXFFLSH); |
| 2365 | |
| 2366 | /* Wait for at least 3 PHY Clocks */ |
| 2367 | udelay(1); |
| 2368 | } |
| 2369 | |
| 2370 | /** |
| 2371 | * dwc2_flush_rx_fifo() - Flushes the Rx FIFO |
| 2372 | * |
| 2373 | * @hsotg: Programming view of DWC_otg controller |
| 2374 | */ |
| 2375 | void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) |
| 2376 | { |
| 2377 | u32 greset; |
| 2378 | int count = 0; |
| 2379 | |
| 2380 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
| 2381 | |
| 2382 | greset = GRSTCTL_RXFFLSH; |
| 2383 | writel(greset, hsotg->regs + GRSTCTL); |
| 2384 | |
| 2385 | do { |
| 2386 | greset = readl(hsotg->regs + GRSTCTL); |
| 2387 | if (++count > 10000) { |
| 2388 | dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", |
| 2389 | __func__, greset); |
| 2390 | break; |
| 2391 | } |
| 2392 | udelay(1); |
| 2393 | } while (greset & GRSTCTL_RXFFLSH); |
| 2394 | |
| 2395 | /* Wait for at least 3 PHY Clocks */ |
| 2396 | udelay(1); |
| 2397 | } |
| 2398 | |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2399 | #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c)) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2400 | |
| 2401 | /* Parameter access functions */ |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2402 | void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2403 | { |
| 2404 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2405 | |
| 2406 | switch (val) { |
| 2407 | case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2408 | if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2409 | valid = 0; |
| 2410 | break; |
| 2411 | case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2412 | switch (hsotg->hw_params.op_mode) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2413 | case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: |
| 2414 | case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: |
| 2415 | case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: |
| 2416 | case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: |
| 2417 | break; |
| 2418 | default: |
| 2419 | valid = 0; |
| 2420 | break; |
| 2421 | } |
| 2422 | break; |
| 2423 | case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: |
| 2424 | /* always valid */ |
| 2425 | break; |
| 2426 | default: |
| 2427 | valid = 0; |
| 2428 | break; |
| 2429 | } |
| 2430 | |
| 2431 | if (!valid) { |
| 2432 | if (val >= 0) |
| 2433 | dev_err(hsotg->dev, |
| 2434 | "%d invalid for otg_cap parameter. Check HW configuration.\n", |
| 2435 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2436 | switch (hsotg->hw_params.op_mode) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2437 | case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: |
| 2438 | val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; |
| 2439 | break; |
| 2440 | case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: |
| 2441 | case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: |
| 2442 | case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: |
| 2443 | val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; |
| 2444 | break; |
| 2445 | default: |
| 2446 | val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; |
| 2447 | break; |
| 2448 | } |
| 2449 | dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2450 | } |
| 2451 | |
| 2452 | hsotg->core_params->otg_cap = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2453 | } |
| 2454 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2455 | void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2456 | { |
| 2457 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2458 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2459 | if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2460 | valid = 0; |
| 2461 | if (val < 0) |
| 2462 | valid = 0; |
| 2463 | |
| 2464 | if (!valid) { |
| 2465 | if (val >= 0) |
| 2466 | dev_err(hsotg->dev, |
| 2467 | "%d invalid for dma_enable parameter. Check HW configuration.\n", |
| 2468 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2469 | val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2470 | dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2471 | } |
| 2472 | |
| 2473 | hsotg->core_params->dma_enable = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2474 | } |
| 2475 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2476 | void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2477 | { |
| 2478 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2479 | |
| 2480 | if (val > 0 && (hsotg->core_params->dma_enable <= 0 || |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2481 | !hsotg->hw_params.dma_desc_enable)) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2482 | valid = 0; |
| 2483 | if (val < 0) |
| 2484 | valid = 0; |
| 2485 | |
| 2486 | if (!valid) { |
| 2487 | if (val >= 0) |
| 2488 | dev_err(hsotg->dev, |
| 2489 | "%d invalid for dma_desc_enable parameter. Check HW configuration.\n", |
| 2490 | val); |
| 2491 | val = (hsotg->core_params->dma_enable > 0 && |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2492 | hsotg->hw_params.dma_desc_enable); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2493 | dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2494 | } |
| 2495 | |
| 2496 | hsotg->core_params->dma_desc_enable = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2497 | } |
| 2498 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2499 | void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, |
| 2500 | int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2501 | { |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2502 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2503 | if (val >= 0) { |
| 2504 | dev_err(hsotg->dev, |
| 2505 | "Wrong value for host_support_fs_low_power\n"); |
| 2506 | dev_err(hsotg->dev, |
| 2507 | "host_support_fs_low_power must be 0 or 1\n"); |
| 2508 | } |
| 2509 | val = 0; |
| 2510 | dev_dbg(hsotg->dev, |
| 2511 | "Setting host_support_fs_low_power to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2512 | } |
| 2513 | |
| 2514 | hsotg->core_params->host_support_fs_ls_low_power = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2515 | } |
| 2516 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2517 | void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2518 | { |
| 2519 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2520 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2521 | if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2522 | valid = 0; |
| 2523 | if (val < 0) |
| 2524 | valid = 0; |
| 2525 | |
| 2526 | if (!valid) { |
| 2527 | if (val >= 0) |
| 2528 | dev_err(hsotg->dev, |
| 2529 | "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n", |
| 2530 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2531 | val = hsotg->hw_params.enable_dynamic_fifo; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2532 | dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2533 | } |
| 2534 | |
| 2535 | hsotg->core_params->enable_dynamic_fifo = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2536 | } |
| 2537 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2538 | void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2539 | { |
| 2540 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2541 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2542 | if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2543 | valid = 0; |
| 2544 | |
| 2545 | if (!valid) { |
| 2546 | if (val >= 0) |
| 2547 | dev_err(hsotg->dev, |
| 2548 | "%d invalid for host_rx_fifo_size. Check HW configuration.\n", |
| 2549 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2550 | val = hsotg->hw_params.host_rx_fifo_size; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2551 | dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2552 | } |
| 2553 | |
| 2554 | hsotg->core_params->host_rx_fifo_size = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2555 | } |
| 2556 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2557 | void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2558 | { |
| 2559 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2560 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2561 | if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2562 | valid = 0; |
| 2563 | |
| 2564 | if (!valid) { |
| 2565 | if (val >= 0) |
| 2566 | dev_err(hsotg->dev, |
| 2567 | "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", |
| 2568 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2569 | val = hsotg->hw_params.host_nperio_tx_fifo_size; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2570 | dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", |
| 2571 | val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2572 | } |
| 2573 | |
| 2574 | hsotg->core_params->host_nperio_tx_fifo_size = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2575 | } |
| 2576 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2577 | void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2578 | { |
| 2579 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2580 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2581 | if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2582 | valid = 0; |
| 2583 | |
| 2584 | if (!valid) { |
| 2585 | if (val >= 0) |
| 2586 | dev_err(hsotg->dev, |
| 2587 | "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", |
| 2588 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2589 | val = hsotg->hw_params.host_perio_tx_fifo_size; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2590 | dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", |
| 2591 | val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2592 | } |
| 2593 | |
| 2594 | hsotg->core_params->host_perio_tx_fifo_size = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2595 | } |
| 2596 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2597 | void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2598 | { |
| 2599 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2600 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2601 | if (val < 2047 || val > hsotg->hw_params.max_transfer_size) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2602 | valid = 0; |
| 2603 | |
| 2604 | if (!valid) { |
| 2605 | if (val >= 0) |
| 2606 | dev_err(hsotg->dev, |
| 2607 | "%d invalid for max_transfer_size. Check HW configuration.\n", |
| 2608 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2609 | val = hsotg->hw_params.max_transfer_size; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2610 | dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2611 | } |
| 2612 | |
| 2613 | hsotg->core_params->max_transfer_size = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2614 | } |
| 2615 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2616 | void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2617 | { |
| 2618 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2619 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2620 | if (val < 15 || val > hsotg->hw_params.max_packet_count) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2621 | valid = 0; |
| 2622 | |
| 2623 | if (!valid) { |
| 2624 | if (val >= 0) |
| 2625 | dev_err(hsotg->dev, |
| 2626 | "%d invalid for max_packet_count. Check HW configuration.\n", |
| 2627 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2628 | val = hsotg->hw_params.max_packet_count; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2629 | dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2630 | } |
| 2631 | |
| 2632 | hsotg->core_params->max_packet_count = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2633 | } |
| 2634 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2635 | void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2636 | { |
| 2637 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2638 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2639 | if (val < 1 || val > hsotg->hw_params.host_channels) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2640 | valid = 0; |
| 2641 | |
| 2642 | if (!valid) { |
| 2643 | if (val >= 0) |
| 2644 | dev_err(hsotg->dev, |
| 2645 | "%d invalid for host_channels. Check HW configuration.\n", |
| 2646 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2647 | val = hsotg->hw_params.host_channels; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2648 | dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2649 | } |
| 2650 | |
| 2651 | hsotg->core_params->host_channels = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2652 | } |
| 2653 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2654 | void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2655 | { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2656 | int valid = 0; |
Luis Ortega Perez de Villar | 0464a3d | 2013-09-25 13:10:50 +0200 | [diff] [blame] | 2657 | u32 hs_phy_type, fs_phy_type; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2658 | |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2659 | if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS, |
| 2660 | DWC2_PHY_TYPE_PARAM_ULPI)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2661 | if (val >= 0) { |
| 2662 | dev_err(hsotg->dev, "Wrong value for phy_type\n"); |
| 2663 | dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); |
| 2664 | } |
| 2665 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2666 | valid = 0; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2667 | } |
| 2668 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2669 | hs_phy_type = hsotg->hw_params.hs_phy_type; |
| 2670 | fs_phy_type = hsotg->hw_params.fs_phy_type; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2671 | if (val == DWC2_PHY_TYPE_PARAM_UTMI && |
| 2672 | (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || |
| 2673 | hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) |
| 2674 | valid = 1; |
| 2675 | else if (val == DWC2_PHY_TYPE_PARAM_ULPI && |
| 2676 | (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI || |
| 2677 | hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) |
| 2678 | valid = 1; |
| 2679 | else if (val == DWC2_PHY_TYPE_PARAM_FS && |
| 2680 | fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) |
| 2681 | valid = 1; |
| 2682 | |
| 2683 | if (!valid) { |
| 2684 | if (val >= 0) |
| 2685 | dev_err(hsotg->dev, |
| 2686 | "%d invalid for phy_type. Check HW configuration.\n", |
| 2687 | val); |
Matthijs Kooijman | 929aea0 | 2013-04-29 19:36:48 +0000 | [diff] [blame] | 2688 | val = DWC2_PHY_TYPE_PARAM_FS; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2689 | if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { |
| 2690 | if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || |
| 2691 | hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) |
| 2692 | val = DWC2_PHY_TYPE_PARAM_UTMI; |
| 2693 | else |
| 2694 | val = DWC2_PHY_TYPE_PARAM_ULPI; |
| 2695 | } |
| 2696 | dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2697 | } |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2698 | |
| 2699 | hsotg->core_params->phy_type = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2700 | } |
| 2701 | |
| 2702 | static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) |
| 2703 | { |
| 2704 | return hsotg->core_params->phy_type; |
| 2705 | } |
| 2706 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2707 | void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2708 | { |
| 2709 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2710 | |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2711 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2712 | if (val >= 0) { |
| 2713 | dev_err(hsotg->dev, "Wrong value for speed parameter\n"); |
| 2714 | dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n"); |
| 2715 | } |
| 2716 | valid = 0; |
| 2717 | } |
| 2718 | |
Matthijs Kooijman | 929aea0 | 2013-04-29 19:36:48 +0000 | [diff] [blame] | 2719 | if (val == DWC2_SPEED_PARAM_HIGH && |
| 2720 | dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2721 | valid = 0; |
| 2722 | |
| 2723 | if (!valid) { |
| 2724 | if (val >= 0) |
| 2725 | dev_err(hsotg->dev, |
| 2726 | "%d invalid for speed parameter. Check HW configuration.\n", |
| 2727 | val); |
| 2728 | val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? |
Matthijs Kooijman | 929aea0 | 2013-04-29 19:36:48 +0000 | [diff] [blame] | 2729 | DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2730 | dev_dbg(hsotg->dev, "Setting speed to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2731 | } |
| 2732 | |
| 2733 | hsotg->core_params->speed = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2734 | } |
| 2735 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2736 | void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2737 | { |
| 2738 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2739 | |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2740 | if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, |
| 2741 | DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2742 | if (val >= 0) { |
| 2743 | dev_err(hsotg->dev, |
| 2744 | "Wrong value for host_ls_low_power_phy_clk parameter\n"); |
| 2745 | dev_err(hsotg->dev, |
| 2746 | "host_ls_low_power_phy_clk must be 0 or 1\n"); |
| 2747 | } |
| 2748 | valid = 0; |
| 2749 | } |
| 2750 | |
| 2751 | if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ && |
| 2752 | dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) |
| 2753 | valid = 0; |
| 2754 | |
| 2755 | if (!valid) { |
| 2756 | if (val >= 0) |
| 2757 | dev_err(hsotg->dev, |
| 2758 | "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", |
| 2759 | val); |
| 2760 | val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS |
| 2761 | ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ |
| 2762 | : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; |
| 2763 | dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", |
| 2764 | val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2765 | } |
| 2766 | |
| 2767 | hsotg->core_params->host_ls_low_power_phy_clk = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2768 | } |
| 2769 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2770 | void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2771 | { |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2772 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2773 | if (val >= 0) { |
| 2774 | dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); |
| 2775 | dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); |
| 2776 | } |
| 2777 | val = 0; |
| 2778 | dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2779 | } |
| 2780 | |
| 2781 | hsotg->core_params->phy_ulpi_ddr = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2782 | } |
| 2783 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2784 | void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2785 | { |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2786 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2787 | if (val >= 0) { |
| 2788 | dev_err(hsotg->dev, |
| 2789 | "Wrong value for phy_ulpi_ext_vbus\n"); |
| 2790 | dev_err(hsotg->dev, |
| 2791 | "phy_ulpi_ext_vbus must be 0 or 1\n"); |
| 2792 | } |
| 2793 | val = 0; |
| 2794 | dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2795 | } |
| 2796 | |
| 2797 | hsotg->core_params->phy_ulpi_ext_vbus = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2798 | } |
| 2799 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2800 | void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2801 | { |
Matthijs Kooijman | de4a193 | 2013-08-30 18:45:22 +0200 | [diff] [blame] | 2802 | int valid = 0; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2803 | |
Matthijs Kooijman | de4a193 | 2013-08-30 18:45:22 +0200 | [diff] [blame] | 2804 | switch (hsotg->hw_params.utmi_phy_data_width) { |
| 2805 | case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: |
| 2806 | valid = (val == 8); |
| 2807 | break; |
| 2808 | case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: |
| 2809 | valid = (val == 16); |
| 2810 | break; |
| 2811 | case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: |
| 2812 | valid = (val == 8 || val == 16); |
| 2813 | break; |
| 2814 | } |
| 2815 | |
| 2816 | if (!valid) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2817 | if (val >= 0) { |
Matthijs Kooijman | de4a193 | 2013-08-30 18:45:22 +0200 | [diff] [blame] | 2818 | dev_err(hsotg->dev, |
| 2819 | "%d invalid for phy_utmi_width. Check HW configuration.\n", |
| 2820 | val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2821 | } |
Matthijs Kooijman | de4a193 | 2013-08-30 18:45:22 +0200 | [diff] [blame] | 2822 | val = (hsotg->hw_params.utmi_phy_data_width == |
| 2823 | GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2824 | dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2825 | } |
| 2826 | |
| 2827 | hsotg->core_params->phy_utmi_width = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2828 | } |
| 2829 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2830 | void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2831 | { |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2832 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2833 | if (val >= 0) { |
| 2834 | dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); |
| 2835 | dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); |
| 2836 | } |
| 2837 | val = 0; |
| 2838 | dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2839 | } |
| 2840 | |
| 2841 | hsotg->core_params->ulpi_fs_ls = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2842 | } |
| 2843 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2844 | void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2845 | { |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2846 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2847 | if (val >= 0) { |
| 2848 | dev_err(hsotg->dev, "Wrong value for ts_dline\n"); |
| 2849 | dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); |
| 2850 | } |
| 2851 | val = 0; |
| 2852 | dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2853 | } |
| 2854 | |
| 2855 | hsotg->core_params->ts_dline = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2856 | } |
| 2857 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2858 | void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2859 | { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2860 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2861 | |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2862 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2863 | if (val >= 0) { |
| 2864 | dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); |
| 2865 | dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); |
| 2866 | } |
| 2867 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2868 | valid = 0; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2869 | } |
| 2870 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2871 | if (val == 1 && !(hsotg->hw_params.i2c_enable)) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2872 | valid = 0; |
| 2873 | |
| 2874 | if (!valid) { |
| 2875 | if (val >= 0) |
| 2876 | dev_err(hsotg->dev, |
| 2877 | "%d invalid for i2c_enable. Check HW configuration.\n", |
| 2878 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2879 | val = hsotg->hw_params.i2c_enable; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2880 | dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2881 | } |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2882 | |
| 2883 | hsotg->core_params->i2c_enable = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2884 | } |
| 2885 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2886 | void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2887 | { |
| 2888 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2889 | |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2890 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2891 | if (val >= 0) { |
| 2892 | dev_err(hsotg->dev, |
| 2893 | "Wrong value for en_multiple_tx_fifo,\n"); |
| 2894 | dev_err(hsotg->dev, |
| 2895 | "en_multiple_tx_fifo must be 0 or 1\n"); |
| 2896 | } |
| 2897 | valid = 0; |
| 2898 | } |
| 2899 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2900 | if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2901 | valid = 0; |
| 2902 | |
| 2903 | if (!valid) { |
| 2904 | if (val >= 0) |
| 2905 | dev_err(hsotg->dev, |
| 2906 | "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", |
| 2907 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2908 | val = hsotg->hw_params.en_multiple_tx_fifo; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2909 | dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2910 | } |
| 2911 | |
| 2912 | hsotg->core_params->en_multiple_tx_fifo = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2913 | } |
| 2914 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2915 | void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2916 | { |
| 2917 | int valid = 1; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2918 | |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2919 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2920 | if (val >= 0) { |
| 2921 | dev_err(hsotg->dev, |
| 2922 | "'%d' invalid for parameter reload_ctl\n", val); |
| 2923 | dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n"); |
| 2924 | } |
| 2925 | valid = 0; |
| 2926 | } |
| 2927 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2928 | if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2929 | valid = 0; |
| 2930 | |
| 2931 | if (!valid) { |
| 2932 | if (val >= 0) |
| 2933 | dev_err(hsotg->dev, |
| 2934 | "%d invalid for parameter reload_ctl. Check HW configuration.\n", |
| 2935 | val); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 2936 | val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2937 | dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2938 | } |
| 2939 | |
| 2940 | hsotg->core_params->reload_ctl = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2941 | } |
| 2942 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2943 | void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2944 | { |
Paul Zimmerman | 4d3190e | 2013-07-16 12:22:12 -0700 | [diff] [blame] | 2945 | if (val != -1) |
| 2946 | hsotg->core_params->ahbcfg = val; |
| 2947 | else |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 2948 | hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << |
Luis Ortega Perez de Villar | 0464a3d | 2013-09-25 13:10:50 +0200 | [diff] [blame] | 2949 | GAHBCFG_HBSTLEN_SHIFT; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2950 | } |
| 2951 | |
Paul Zimmerman | 7218dae | 2013-11-22 16:43:48 -0800 | [diff] [blame] | 2952 | void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2953 | { |
Paul Zimmerman | 498f066 | 2013-11-22 16:43:47 -0800 | [diff] [blame] | 2954 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2955 | if (val >= 0) { |
| 2956 | dev_err(hsotg->dev, |
| 2957 | "'%d' invalid for parameter otg_ver\n", val); |
| 2958 | dev_err(hsotg->dev, |
| 2959 | "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n"); |
| 2960 | } |
| 2961 | val = 0; |
| 2962 | dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2963 | } |
| 2964 | |
| 2965 | hsotg->core_params->otg_ver = val; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 2966 | } |
| 2967 | |
Wei Yongjun | 49cf10c | 2013-11-28 10:27:59 +0800 | [diff] [blame] | 2968 | static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) |
Paul Zimmerman | e8576e6 | 2013-11-25 13:42:47 -0800 | [diff] [blame] | 2969 | { |
| 2970 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
| 2971 | if (val >= 0) { |
| 2972 | dev_err(hsotg->dev, |
| 2973 | "'%d' invalid for parameter uframe_sched\n", |
| 2974 | val); |
| 2975 | dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); |
| 2976 | } |
| 2977 | val = 1; |
| 2978 | dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); |
| 2979 | } |
| 2980 | |
| 2981 | hsotg->core_params->uframe_sched = val; |
| 2982 | } |
| 2983 | |
Gregory Herrero | a6d249d | 2015-04-29 22:09:04 +0200 | [diff] [blame] | 2984 | static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg, |
| 2985 | int val) |
| 2986 | { |
| 2987 | if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { |
| 2988 | if (val >= 0) { |
| 2989 | dev_err(hsotg->dev, |
| 2990 | "'%d' invalid for parameter external_id_pin_ctl\n", |
| 2991 | val); |
| 2992 | dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n"); |
| 2993 | } |
| 2994 | val = 0; |
| 2995 | dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val); |
| 2996 | } |
| 2997 | |
| 2998 | hsotg->core_params->external_id_pin_ctl = val; |
| 2999 | } |
| 3000 | |
Paul Zimmerman | e8576e6 | 2013-11-25 13:42:47 -0800 | [diff] [blame] | 3001 | /* |
| 3002 | * This function is called during module intialization to pass module parameters |
| 3003 | * for the DWC_otg core. |
| 3004 | */ |
| 3005 | void dwc2_set_parameters(struct dwc2_hsotg *hsotg, |
| 3006 | const struct dwc2_core_params *params) |
| 3007 | { |
| 3008 | dev_dbg(hsotg->dev, "%s()\n", __func__); |
| 3009 | |
| 3010 | dwc2_set_param_otg_cap(hsotg, params->otg_cap); |
| 3011 | dwc2_set_param_dma_enable(hsotg, params->dma_enable); |
| 3012 | dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); |
| 3013 | dwc2_set_param_host_support_fs_ls_low_power(hsotg, |
| 3014 | params->host_support_fs_ls_low_power); |
| 3015 | dwc2_set_param_enable_dynamic_fifo(hsotg, |
| 3016 | params->enable_dynamic_fifo); |
| 3017 | dwc2_set_param_host_rx_fifo_size(hsotg, |
| 3018 | params->host_rx_fifo_size); |
| 3019 | dwc2_set_param_host_nperio_tx_fifo_size(hsotg, |
| 3020 | params->host_nperio_tx_fifo_size); |
| 3021 | dwc2_set_param_host_perio_tx_fifo_size(hsotg, |
| 3022 | params->host_perio_tx_fifo_size); |
| 3023 | dwc2_set_param_max_transfer_size(hsotg, |
| 3024 | params->max_transfer_size); |
| 3025 | dwc2_set_param_max_packet_count(hsotg, |
| 3026 | params->max_packet_count); |
| 3027 | dwc2_set_param_host_channels(hsotg, params->host_channels); |
| 3028 | dwc2_set_param_phy_type(hsotg, params->phy_type); |
| 3029 | dwc2_set_param_speed(hsotg, params->speed); |
| 3030 | dwc2_set_param_host_ls_low_power_phy_clk(hsotg, |
| 3031 | params->host_ls_low_power_phy_clk); |
| 3032 | dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); |
| 3033 | dwc2_set_param_phy_ulpi_ext_vbus(hsotg, |
| 3034 | params->phy_ulpi_ext_vbus); |
| 3035 | dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); |
| 3036 | dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); |
| 3037 | dwc2_set_param_ts_dline(hsotg, params->ts_dline); |
| 3038 | dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); |
| 3039 | dwc2_set_param_en_multiple_tx_fifo(hsotg, |
| 3040 | params->en_multiple_tx_fifo); |
| 3041 | dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); |
| 3042 | dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); |
| 3043 | dwc2_set_param_otg_ver(hsotg, params->otg_ver); |
| 3044 | dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); |
Gregory Herrero | a6d249d | 2015-04-29 22:09:04 +0200 | [diff] [blame] | 3045 | dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl); |
Paul Zimmerman | e8576e6 | 2013-11-25 13:42:47 -0800 | [diff] [blame] | 3046 | } |
| 3047 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 3048 | /** |
| 3049 | * During device initialization, read various hardware configuration |
| 3050 | * registers and interpret the contents. |
| 3051 | */ |
| 3052 | int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) |
| 3053 | { |
| 3054 | struct dwc2_hw_params *hw = &hsotg->hw_params; |
| 3055 | unsigned width; |
| 3056 | u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; |
| 3057 | u32 hptxfsiz, grxfsiz, gnptxfsiz; |
| 3058 | u32 gusbcfg; |
| 3059 | |
| 3060 | /* |
| 3061 | * Attempt to ensure this device is really a DWC_otg Controller. |
| 3062 | * Read and verify the GSNPSID register contents. The value should be |
| 3063 | * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", |
| 3064 | * as in "OTG version 2.xx" or "OTG version 3.xx". |
| 3065 | */ |
| 3066 | hw->snpsid = readl(hsotg->regs + GSNPSID); |
| 3067 | if ((hw->snpsid & 0xfffff000) != 0x4f542000 && |
| 3068 | (hw->snpsid & 0xfffff000) != 0x4f543000) { |
| 3069 | dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", |
| 3070 | hw->snpsid); |
| 3071 | return -ENODEV; |
| 3072 | } |
| 3073 | |
| 3074 | dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", |
| 3075 | hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, |
| 3076 | hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); |
| 3077 | |
| 3078 | hwcfg1 = readl(hsotg->regs + GHWCFG1); |
| 3079 | hwcfg2 = readl(hsotg->regs + GHWCFG2); |
| 3080 | hwcfg3 = readl(hsotg->regs + GHWCFG3); |
| 3081 | hwcfg4 = readl(hsotg->regs + GHWCFG4); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 3082 | grxfsiz = readl(hsotg->regs + GRXFSIZ); |
| 3083 | |
| 3084 | dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); |
| 3085 | dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); |
| 3086 | dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); |
| 3087 | dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 3088 | dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); |
| 3089 | |
Doug Anderson | 2867c05 | 2014-08-07 12:48:11 -0700 | [diff] [blame] | 3090 | /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */ |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 3091 | gusbcfg = readl(hsotg->regs + GUSBCFG); |
| 3092 | gusbcfg |= GUSBCFG_FORCEHOSTMODE; |
| 3093 | writel(gusbcfg, hsotg->regs + GUSBCFG); |
| 3094 | usleep_range(100000, 150000); |
| 3095 | |
Doug Anderson | 2867c05 | 2014-08-07 12:48:11 -0700 | [diff] [blame] | 3096 | gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 3097 | hptxfsiz = readl(hsotg->regs + HPTXFSIZ); |
Doug Anderson | 2867c05 | 2014-08-07 12:48:11 -0700 | [diff] [blame] | 3098 | dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 3099 | dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); |
| 3100 | gusbcfg = readl(hsotg->regs + GUSBCFG); |
| 3101 | gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; |
| 3102 | writel(gusbcfg, hsotg->regs + GUSBCFG); |
| 3103 | usleep_range(100000, 150000); |
| 3104 | |
| 3105 | /* hwcfg2 */ |
| 3106 | hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> |
| 3107 | GHWCFG2_OP_MODE_SHIFT; |
| 3108 | hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> |
| 3109 | GHWCFG2_ARCHITECTURE_SHIFT; |
| 3110 | hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); |
| 3111 | hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> |
| 3112 | GHWCFG2_NUM_HOST_CHAN_SHIFT); |
| 3113 | hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> |
| 3114 | GHWCFG2_HS_PHY_TYPE_SHIFT; |
| 3115 | hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> |
| 3116 | GHWCFG2_FS_PHY_TYPE_SHIFT; |
| 3117 | hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> |
| 3118 | GHWCFG2_NUM_DEV_EP_SHIFT; |
| 3119 | hw->nperio_tx_q_depth = |
| 3120 | (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> |
| 3121 | GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; |
| 3122 | hw->host_perio_tx_q_depth = |
| 3123 | (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> |
| 3124 | GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; |
| 3125 | hw->dev_token_q_depth = |
| 3126 | (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> |
| 3127 | GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; |
| 3128 | |
| 3129 | /* hwcfg3 */ |
| 3130 | width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> |
| 3131 | GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; |
| 3132 | hw->max_transfer_size = (1 << (width + 11)) - 1; |
Paul Zimmerman | e8f8c14 | 2014-09-16 13:47:26 -0700 | [diff] [blame] | 3133 | /* |
| 3134 | * Clip max_transfer_size to 65535. dwc2_hc_setup_align_buf() allocates |
| 3135 | * coherent buffers with this size, and if it's too large we can |
| 3136 | * exhaust the coherent DMA pool. |
| 3137 | */ |
| 3138 | if (hw->max_transfer_size > 65535) |
| 3139 | hw->max_transfer_size = 65535; |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 3140 | width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> |
| 3141 | GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; |
| 3142 | hw->max_packet_count = (1 << (width + 4)) - 1; |
| 3143 | hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); |
| 3144 | hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> |
| 3145 | GHWCFG3_DFIFO_DEPTH_SHIFT; |
| 3146 | |
| 3147 | /* hwcfg4 */ |
| 3148 | hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); |
| 3149 | hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> |
| 3150 | GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; |
| 3151 | hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); |
| 3152 | hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); |
Matthijs Kooijman | de4a193 | 2013-08-30 18:45:22 +0200 | [diff] [blame] | 3153 | hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> |
| 3154 | GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 3155 | |
| 3156 | /* fifo sizes */ |
| 3157 | hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> |
| 3158 | GRXFSIZ_DEPTH_SHIFT; |
| 3159 | hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> |
| 3160 | FIFOSIZE_DEPTH_SHIFT; |
| 3161 | hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> |
| 3162 | FIFOSIZE_DEPTH_SHIFT; |
| 3163 | |
| 3164 | dev_dbg(hsotg->dev, "Detected values from hardware:\n"); |
| 3165 | dev_dbg(hsotg->dev, " op_mode=%d\n", |
| 3166 | hw->op_mode); |
| 3167 | dev_dbg(hsotg->dev, " arch=%d\n", |
| 3168 | hw->arch); |
| 3169 | dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", |
| 3170 | hw->dma_desc_enable); |
| 3171 | dev_dbg(hsotg->dev, " power_optimized=%d\n", |
| 3172 | hw->power_optimized); |
| 3173 | dev_dbg(hsotg->dev, " i2c_enable=%d\n", |
| 3174 | hw->i2c_enable); |
| 3175 | dev_dbg(hsotg->dev, " hs_phy_type=%d\n", |
| 3176 | hw->hs_phy_type); |
| 3177 | dev_dbg(hsotg->dev, " fs_phy_type=%d\n", |
| 3178 | hw->fs_phy_type); |
Matthijs Kooijman | de4a193 | 2013-08-30 18:45:22 +0200 | [diff] [blame] | 3179 | dev_dbg(hsotg->dev, " utmi_phy_data_wdith=%d\n", |
| 3180 | hw->utmi_phy_data_width); |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 3181 | dev_dbg(hsotg->dev, " num_dev_ep=%d\n", |
| 3182 | hw->num_dev_ep); |
| 3183 | dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", |
| 3184 | hw->num_dev_perio_in_ep); |
| 3185 | dev_dbg(hsotg->dev, " host_channels=%d\n", |
| 3186 | hw->host_channels); |
| 3187 | dev_dbg(hsotg->dev, " max_transfer_size=%d\n", |
| 3188 | hw->max_transfer_size); |
| 3189 | dev_dbg(hsotg->dev, " max_packet_count=%d\n", |
| 3190 | hw->max_packet_count); |
| 3191 | dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", |
| 3192 | hw->nperio_tx_q_depth); |
| 3193 | dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", |
| 3194 | hw->host_perio_tx_q_depth); |
| 3195 | dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", |
| 3196 | hw->dev_token_q_depth); |
| 3197 | dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", |
| 3198 | hw->enable_dynamic_fifo); |
| 3199 | dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", |
| 3200 | hw->en_multiple_tx_fifo); |
| 3201 | dev_dbg(hsotg->dev, " total_fifo_size=%d\n", |
| 3202 | hw->total_fifo_size); |
| 3203 | dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n", |
| 3204 | hw->host_rx_fifo_size); |
| 3205 | dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", |
| 3206 | hw->host_nperio_tx_fifo_size); |
| 3207 | dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", |
| 3208 | hw->host_perio_tx_fifo_size); |
| 3209 | dev_dbg(hsotg->dev, "\n"); |
| 3210 | |
| 3211 | return 0; |
| 3212 | } |
Mian Yousaf Kaukab | ecb176c | 2015-04-29 22:09:05 +0200 | [diff] [blame] | 3213 | |
| 3214 | /* |
| 3215 | * Sets all parameters to the given value. |
| 3216 | * |
| 3217 | * Assumes that the dwc2_core_params struct contains only integers. |
| 3218 | */ |
| 3219 | void dwc2_set_all_params(struct dwc2_core_params *params, int value) |
| 3220 | { |
| 3221 | int *p = (int *)params; |
| 3222 | size_t size = sizeof(*params) / sizeof(*p); |
| 3223 | int i; |
| 3224 | |
| 3225 | for (i = 0; i < size; i++) |
| 3226 | p[i] = value; |
| 3227 | } |
Mian Yousaf Kaukab | ecb176c | 2015-04-29 22:09:05 +0200 | [diff] [blame] | 3228 | |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 3229 | |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 3230 | u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg) |
| 3231 | { |
Paul Zimmerman | b66a3f0 | 2013-11-22 16:43:50 -0800 | [diff] [blame] | 3232 | return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 3233 | } |
| 3234 | |
Paul Zimmerman | 057715f | 2013-11-22 16:43:51 -0800 | [diff] [blame] | 3235 | bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 3236 | { |
| 3237 | if (readl(hsotg->regs + GSNPSID) == 0xffffffff) |
Paul Zimmerman | 057715f | 2013-11-22 16:43:51 -0800 | [diff] [blame] | 3238 | return false; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 3239 | else |
Paul Zimmerman | 057715f | 2013-11-22 16:43:51 -0800 | [diff] [blame] | 3240 | return true; |
Paul Zimmerman | 56f5b1c | 2013-03-11 17:47:58 -0700 | [diff] [blame] | 3241 | } |
| 3242 | |
| 3243 | /** |
| 3244 | * dwc2_enable_global_interrupts() - Enables the controller's Global |
| 3245 | * Interrupt in the AHB Config register |
| 3246 | * |
| 3247 | * @hsotg: Programming view of DWC_otg controller |
| 3248 | */ |
| 3249 | void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) |
| 3250 | { |
| 3251 | u32 ahbcfg = readl(hsotg->regs + GAHBCFG); |
| 3252 | |
| 3253 | ahbcfg |= GAHBCFG_GLBL_INTR_EN; |
| 3254 | writel(ahbcfg, hsotg->regs + GAHBCFG); |
| 3255 | } |
| 3256 | |
| 3257 | /** |
| 3258 | * dwc2_disable_global_interrupts() - Disables the controller's Global |
| 3259 | * Interrupt in the AHB Config register |
| 3260 | * |
| 3261 | * @hsotg: Programming view of DWC_otg controller |
| 3262 | */ |
| 3263 | void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) |
| 3264 | { |
| 3265 | u32 ahbcfg = readl(hsotg->regs + GAHBCFG); |
| 3266 | |
| 3267 | ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; |
| 3268 | writel(ahbcfg, hsotg->regs + GAHBCFG); |
| 3269 | } |
| 3270 | |
| 3271 | MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); |
| 3272 | MODULE_AUTHOR("Synopsys, Inc."); |
| 3273 | MODULE_LICENSE("Dual BSD/GPL"); |