Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2002 ARM Ltd. |
| 3 | * Copyright (C) 2008 STMicroelctronics. |
| 4 | * Copyright (C) 2009 ST-Ericsson. |
| 5 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> |
| 6 | * |
| 7 | * This file is based on arm realview platform |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/errno.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/device.h> |
| 17 | #include <linux/smp.h> |
| 18 | #include <linux/io.h> |
| 19 | |
| 20 | #include <asm/cacheflush.h> |
Russell King | 0f7b332 | 2011-04-03 13:01:30 +0100 | [diff] [blame] | 21 | #include <asm/hardware/gic.h> |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 22 | #include <asm/smp_scu.h> |
| 23 | #include <mach/hardware.h> |
Rabin Vincent | 92389ca | 2010-12-08 11:07:57 +0530 | [diff] [blame] | 24 | #include <mach/setup.h> |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 25 | |
Linus Walleij | 4d5336d | 2011-05-06 12:56:27 +0100 | [diff] [blame] | 26 | /* This is called from headsmp.S to wakeup the secondary core */ |
| 27 | extern void u8500_secondary_startup(void); |
| 28 | |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 29 | /* |
| 30 | * control for which core is the next to come out of the secondary |
| 31 | * boot "holding pen" |
| 32 | */ |
Jonas Aaberg | 3c5728e | 2010-12-15 08:36:02 +0100 | [diff] [blame] | 33 | volatile int pen_release = -1; |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 34 | |
Russell King | 3705ff6 | 2010-12-18 10:53:12 +0000 | [diff] [blame] | 35 | /* |
| 36 | * Write pen_release in a way that is guaranteed to be visible to all |
| 37 | * observers, irrespective of whether they're taking part in coherency |
| 38 | * or not. This is necessary for the hotplug code to work reliably. |
| 39 | */ |
| 40 | static void write_pen_release(int val) |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 41 | { |
Russell King | 3705ff6 | 2010-12-18 10:53:12 +0000 | [diff] [blame] | 42 | pen_release = val; |
| 43 | smp_wmb(); |
| 44 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); |
| 45 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 46 | } |
| 47 | |
Rabin Vincent | 92389ca | 2010-12-08 11:07:57 +0530 | [diff] [blame] | 48 | static void __iomem *scu_base_addr(void) |
| 49 | { |
| 50 | if (cpu_is_u5500()) |
| 51 | return __io_address(U5500_SCU_BASE); |
| 52 | else if (cpu_is_u8500()) |
| 53 | return __io_address(U8500_SCU_BASE); |
| 54 | else |
| 55 | ux500_unknown_soc(); |
| 56 | |
| 57 | return NULL; |
| 58 | } |
| 59 | |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 60 | static DEFINE_SPINLOCK(boot_lock); |
| 61 | |
| 62 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 63 | { |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 64 | /* |
| 65 | * if any interrupts are already enabled for the primary |
| 66 | * core (e.g. timer irq), then they will not have been enabled |
| 67 | * for us: do so |
| 68 | */ |
Russell King | 3848953 | 2010-12-04 16:01:03 +0000 | [diff] [blame] | 69 | gic_secondary_init(0); |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 70 | |
| 71 | /* |
| 72 | * let the primary processor know we're out of the |
| 73 | * pen, then head off into the C entry point |
| 74 | */ |
Russell King | 3705ff6 | 2010-12-18 10:53:12 +0000 | [diff] [blame] | 75 | write_pen_release(-1); |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * Synchronise with the boot thread. |
| 79 | */ |
| 80 | spin_lock(&boot_lock); |
| 81 | spin_unlock(&boot_lock); |
| 82 | } |
| 83 | |
| 84 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 85 | { |
| 86 | unsigned long timeout; |
| 87 | |
| 88 | /* |
| 89 | * set synchronisation state between this boot processor |
| 90 | * and the secondary one |
| 91 | */ |
| 92 | spin_lock(&boot_lock); |
| 93 | |
| 94 | /* |
| 95 | * The secondary processor is waiting to be released from |
| 96 | * the holding pen - release it, then wait for it to flag |
| 97 | * that it has been released by resetting pen_release. |
| 98 | */ |
Will Deacon | 2876348 | 2011-08-09 12:21:36 +0100 | [diff] [blame^] | 99 | write_pen_release(cpu_logical_map(cpu)); |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 100 | |
Russell King | 0f7b332 | 2011-04-03 13:01:30 +0100 | [diff] [blame] | 101 | gic_raise_softirq(cpumask_of(cpu), 1); |
Sundar Iyer | 9d704c0 | 2010-09-15 10:45:51 +0100 | [diff] [blame] | 102 | |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 103 | timeout = jiffies + (1 * HZ); |
| 104 | while (time_before(jiffies, timeout)) { |
| 105 | if (pen_release == -1) |
| 106 | break; |
| 107 | } |
| 108 | |
| 109 | /* |
| 110 | * now the secondary core is starting up let it run its |
| 111 | * calibrations, then wait for it to finish |
| 112 | */ |
| 113 | spin_unlock(&boot_lock); |
| 114 | |
| 115 | return pen_release != -1 ? -ENOSYS : 0; |
| 116 | } |
| 117 | |
| 118 | static void __init wakeup_secondary(void) |
| 119 | { |
Rabin Vincent | 92389ca | 2010-12-08 11:07:57 +0530 | [diff] [blame] | 120 | void __iomem *backupram; |
| 121 | |
| 122 | if (cpu_is_u5500()) |
| 123 | backupram = __io_address(U5500_BACKUPRAM0_BASE); |
| 124 | else if (cpu_is_u8500()) |
| 125 | backupram = __io_address(U8500_BACKUPRAM0_BASE); |
| 126 | else |
| 127 | ux500_unknown_soc(); |
| 128 | |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 129 | /* |
| 130 | * write the address of secondary startup into the backup ram register |
| 131 | * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the |
| 132 | * backup ram register at offset 0x1FF0, which is what boot rom code |
| 133 | * is waiting for. This would wake up the secondary core from WFE |
| 134 | */ |
Rabin Vincent | 92389ca | 2010-12-08 11:07:57 +0530 | [diff] [blame] | 135 | #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 136 | __raw_writel(virt_to_phys(u8500_secondary_startup), |
Rabin Vincent | 92389ca | 2010-12-08 11:07:57 +0530 | [diff] [blame] | 137 | backupram + UX500_CPU1_JUMPADDR_OFFSET); |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 138 | |
Rabin Vincent | 92389ca | 2010-12-08 11:07:57 +0530 | [diff] [blame] | 139 | #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 140 | __raw_writel(0xA1FEED01, |
Rabin Vincent | 92389ca | 2010-12-08 11:07:57 +0530 | [diff] [blame] | 141 | backupram + UX500_CPU1_WAKEMAGIC_OFFSET); |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 142 | |
| 143 | /* make sure write buffer is drained */ |
| 144 | mb(); |
| 145 | } |
| 146 | |
| 147 | /* |
| 148 | * Initialise the CPU possible map early - this describes the CPUs |
| 149 | * which may be present or become present in the system. |
| 150 | */ |
| 151 | void __init smp_init_cpus(void) |
| 152 | { |
Rabin Vincent | 92389ca | 2010-12-08 11:07:57 +0530 | [diff] [blame] | 153 | void __iomem *scu_base = scu_base_addr(); |
Russell King | fd778f0 | 2010-12-02 18:09:37 +0000 | [diff] [blame] | 154 | unsigned int i, ncores; |
| 155 | |
Rabin Vincent | 92389ca | 2010-12-08 11:07:57 +0530 | [diff] [blame] | 156 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 157 | |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 158 | /* sanity check */ |
Russell King | bbc3d14e9 | 2010-12-03 10:42:58 +0000 | [diff] [blame] | 159 | if (ncores > NR_CPUS) { |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 160 | printk(KERN_WARNING |
| 161 | "U8500: no. of cores (%d) greater than configured " |
| 162 | "maximum of %d - clipping\n", |
Russell King | bbc3d14e9 | 2010-12-03 10:42:58 +0000 | [diff] [blame] | 163 | ncores, NR_CPUS); |
| 164 | ncores = NR_CPUS; |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 165 | } |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 166 | |
| 167 | for (i = 0; i < ncores; i++) |
| 168 | set_cpu_possible(i, true); |
Russell King | 0f7b332 | 2011-04-03 13:01:30 +0100 | [diff] [blame] | 169 | |
| 170 | set_smp_cross_call(gic_raise_softirq); |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 171 | } |
| 172 | |
Russell King | 05c74a6 | 2010-12-03 11:09:48 +0000 | [diff] [blame] | 173 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 174 | { |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 175 | |
Rabin Vincent | 92389ca | 2010-12-08 11:07:57 +0530 | [diff] [blame] | 176 | scu_enable(scu_base_addr()); |
Russell King | 05c74a6 | 2010-12-03 11:09:48 +0000 | [diff] [blame] | 177 | wakeup_secondary(); |
Srinidhi Kasagar | aa44ef4 | 2009-11-28 08:17:18 +0100 | [diff] [blame] | 178 | } |