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Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -07001/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
18 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
19 */
20
21#ifndef __DMAR_H__
22#define __DMAR_H__
23
24#include <linux/acpi.h>
25#include <linux/types.h>
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070026#include <linux/msi.h>
Suresh Siddha1531a6a2009-03-16 17:04:57 -070027#include <linux/irqreturn.h>
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070028
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -070029struct intel_iommu;
Suresh Siddha29b61be2009-03-16 17:05:02 -070030#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070031struct dmar_drhd_unit {
32 struct list_head list; /* list of drhd units */
Suresh Siddha1886e8a2008-07-10 11:16:37 -070033 struct acpi_dmar_header *hdr; /* ACPI header */
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -070034 u64 reg_base_addr; /* register base address*/
35 struct pci_dev **devices; /* target device array */
36 int devices_cnt; /* target device count */
37 u8 ignored:1; /* ignore drhd */
38 u8 include_all:1;
39 struct intel_iommu *iommu;
40};
41
Suresh Siddha2ae21012008-07-10 11:16:43 -070042extern struct list_head dmar_drhd_units;
43
44#define for_each_drhd_unit(drhd) \
45 list_for_each_entry(drhd, &dmar_drhd_units, list)
46
47extern int dmar_table_init(void);
Suresh Siddha2ae21012008-07-10 11:16:43 -070048extern int dmar_dev_scope_init(void);
49
50/* Intel IOMMU detection */
51extern void detect_intel_iommu(void);
Suresh Siddha9d783ba2009-03-16 17:04:55 -070052extern int enable_drhd_fault_handling(void);
Suresh Siddha2ae21012008-07-10 11:16:43 -070053
Suresh Siddha2ae21012008-07-10 11:16:43 -070054extern int parse_ioapics_under_ir(void);
55extern int alloc_iommu(struct dmar_drhd_unit *);
56#else
57static inline void detect_intel_iommu(void)
58{
59 return;
60}
61
62static inline int dmar_table_init(void)
63{
64 return -ENODEV;
65}
Suresh Siddha29b61be2009-03-16 17:05:02 -070066static inline int enable_drhd_fault_handling(void)
67{
68 return -1;
69}
Suresh Siddha2ae21012008-07-10 11:16:43 -070070#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
71
Suresh Siddha2ae21012008-07-10 11:16:43 -070072struct irte {
73 union {
74 struct {
75 __u64 present : 1,
76 fpd : 1,
77 dst_mode : 1,
78 redir_hint : 1,
79 trigger_mode : 1,
80 dlvry_mode : 3,
81 avail : 4,
82 __reserved_1 : 4,
83 vector : 8,
84 __reserved_2 : 8,
85 dest_id : 32;
86 };
87 __u64 low;
88 };
89
90 union {
91 struct {
92 __u64 sid : 16,
93 sq : 2,
94 svt : 2,
95 __reserved_3 : 44;
96 };
97 __u64 high;
98 };
99};
Suresh Siddha29b61be2009-03-16 17:05:02 -0700100#ifdef CONFIG_INTR_REMAP
101extern int intr_remapping_enabled;
102extern int enable_intr_remapping(int);
103
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700104extern int get_irte(int irq, struct irte *entry);
105extern int modify_irte(int irq, struct irte *irte_modified);
106extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
107extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
108 u16 sub_handle);
109extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
110extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index);
111extern int flush_irte(int irq);
112extern int free_irte(int irq);
113
114extern int irq_remapped(int irq);
Suresh Siddha75c46fa2008-07-10 11:16:57 -0700115extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
Suresh Siddha89027d32008-07-10 11:16:56 -0700116extern struct intel_iommu *map_ioapic_to_ir(int apic);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700117#else
Suresh Siddha29b61be2009-03-16 17:05:02 -0700118static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
119{
120 return -1;
121}
122static inline int modify_irte(int irq, struct irte *irte_modified)
123{
124 return -1;
125}
126static inline int free_irte(int irq)
127{
128 return -1;
129}
130static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
131{
132 return -1;
133}
134static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
135 u16 sub_handle)
136{
137 return -1;
138}
139static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
140{
141 return NULL;
142}
143static inline struct intel_iommu *map_ioapic_to_ir(int apic)
144{
145 return NULL;
146}
Suresh Siddhab6fcb332008-07-10 11:16:44 -0700147#define irq_remapped(irq) (0)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700148#define enable_intr_remapping(mode) (-1)
149#define intr_remapping_enabled (0)
150#endif
151
Suresh Siddha2ae21012008-07-10 11:16:43 -0700152/* Can't use the common MSI interrupt functions
153 * since DMAR is not a pci device
154 */
155extern void dmar_msi_unmask(unsigned int irq);
156extern void dmar_msi_mask(unsigned int irq);
157extern void dmar_msi_read(int irq, struct msi_msg *msg);
158extern void dmar_msi_write(int irq, struct msi_msg *msg);
159extern int dmar_set_interrupt(struct intel_iommu *iommu);
Suresh Siddha1531a6a2009-03-16 17:04:57 -0700160extern irqreturn_t dmar_fault(int irq, void *dev_id);
Suresh Siddha2ae21012008-07-10 11:16:43 -0700161extern int arch_setup_dmar_msi(unsigned int irq);
162
Suresh Siddha9d783ba2009-03-16 17:04:55 -0700163#ifdef CONFIG_DMAR
Suresh Siddha2ae21012008-07-10 11:16:43 -0700164extern int iommu_detected, no_iommu;
165extern struct list_head dmar_rmrr_units;
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700166struct dmar_rmrr_unit {
167 struct list_head list; /* list of rmrr units */
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700168 struct acpi_dmar_header *hdr; /* ACPI header */
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700169 u64 base_address; /* reserved base address*/
170 u64 end_address; /* reserved end address */
171 struct pci_dev **devices; /* target devices */
172 int devices_cnt; /* target device count */
173};
174
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700175#define for_each_rmrr_units(rmrr) \
176 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
Suresh Siddha2ae21012008-07-10 11:16:43 -0700177/* Intel DMAR initialization functions */
178extern int intel_iommu_init(void);
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700179#else
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700180static inline int intel_iommu_init(void)
181{
Suresh Siddha2ae21012008-07-10 11:16:43 -0700182#ifdef CONFIG_INTR_REMAP
183 return dmar_dev_scope_init();
184#else
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700185 return -ENODEV;
Suresh Siddha2ae21012008-07-10 11:16:43 -0700186#endif
Suresh Siddha1886e8a2008-07-10 11:16:37 -0700187}
Keshavamurthy, Anil Sba395922007-10-21 16:41:49 -0700188#endif /* !CONFIG_DMAR */
Keshavamurthy, Anil S10e52472007-10-21 16:41:41 -0700189#endif /* __DMAR_H__ */