blob: 9ec830c77af0be7afdba4c9b32f13f1b277bdbe8 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
Dave Airlieeb1f8e42010-05-07 06:42:51 +000029#include "drm_crtc_helper.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020030#include "radeon_drm.h"
31#include "radeon_reg.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020032#include "radeon.h"
33#include "atom.h"
34
Jerome Glisse771fe6b2009-06-05 14:42:42 +020035irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS)
36{
37 struct drm_device *dev = (struct drm_device *) arg;
38 struct radeon_device *rdev = dev->dev_private;
39
40 return radeon_irq_process(rdev);
41}
42
Alex Deucherd4877cf2009-12-04 16:56:37 -050043/*
44 * Handle hotplug events outside the interrupt handler proper.
45 */
46static void radeon_hotplug_work_func(struct work_struct *work)
47{
48 struct radeon_device *rdev = container_of(work, struct radeon_device,
49 hotplug_work);
50 struct drm_device *dev = rdev->ddev;
51 struct drm_mode_config *mode_config = &dev->mode_config;
52 struct drm_connector *connector;
53
54 if (mode_config->num_connector) {
55 list_for_each_entry(connector, &mode_config->connector_list, head)
56 radeon_connector_hotplug(connector);
57 }
58 /* Just fire off a uevent and let userspace tell us what to do */
Dave Airlieeb1f8e42010-05-07 06:42:51 +000059 drm_helper_hpd_irq_event(dev);
Alex Deucherd4877cf2009-12-04 16:56:37 -050060}
61
Jerome Glisse771fe6b2009-06-05 14:42:42 +020062void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
63{
64 struct radeon_device *rdev = dev->dev_private;
65 unsigned i;
66
67 /* Disable *all* interrupts */
68 rdev->irq.sw_int = false;
Alex Deucher2031f772010-04-22 12:52:11 -040069 rdev->irq.gui_idle = false;
Alex Deucher9e7b4142010-03-16 17:08:06 -040070 for (i = 0; i < rdev->num_crtc; i++)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020071 rdev->irq.crtc_vblank_int[i] = false;
Alex Deucher6f34be52010-11-21 10:59:01 -050072 for (i = 0; i < 6; i++) {
Alex Deucher9e7b4142010-03-16 17:08:06 -040073 rdev->irq.hpd[i] = false;
Alex Deucher6f34be52010-11-21 10:59:01 -050074 rdev->irq.pflip[i] = false;
75 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +020076 radeon_irq_set(rdev);
77 /* Clear bits */
78 radeon_irq_process(rdev);
79}
80
81int radeon_driver_irq_postinstall_kms(struct drm_device *dev)
82{
83 struct radeon_device *rdev = dev->dev_private;
84
85 dev->max_vblank_count = 0x001fffff;
86 rdev->irq.sw_int = true;
87 radeon_irq_set(rdev);
88 return 0;
89}
90
91void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
92{
93 struct radeon_device *rdev = dev->dev_private;
94 unsigned i;
95
96 if (rdev == NULL) {
97 return;
98 }
99 /* Disable *all* interrupts */
100 rdev->irq.sw_int = false;
Alex Deucher2031f772010-04-22 12:52:11 -0400101 rdev->irq.gui_idle = false;
Alex Deucher9e7b4142010-03-16 17:08:06 -0400102 for (i = 0; i < rdev->num_crtc; i++)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200103 rdev->irq.crtc_vblank_int[i] = false;
Alex Deucher6f34be52010-11-21 10:59:01 -0500104 for (i = 0; i < 6; i++) {
Jerome Glisse003e69f2010-01-07 15:39:14 +0100105 rdev->irq.hpd[i] = false;
Alex Deucher6f34be52010-11-21 10:59:01 -0500106 rdev->irq.pflip[i] = false;
107 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200108 radeon_irq_set(rdev);
109}
110
111int radeon_irq_kms_init(struct radeon_device *rdev)
112{
Michel Dänzer29d9ebc2011-01-11 10:44:54 +0100113 int i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200114 int r = 0;
115
Tejun Heo32c87fc2011-01-03 14:49:32 +0100116 INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);
117
Dave Airlie1614f8b2009-12-01 16:04:56 +1000118 spin_lock_init(&rdev->irq.sw_lock);
Michel Dänzer29d9ebc2011-01-11 10:44:54 +0100119 for (i = 0; i < rdev->num_crtc; i++)
120 spin_lock_init(&rdev->irq.pflip_lock[i]);
Alex Deucher9e7b4142010-03-16 17:08:06 -0400121 r = drm_vblank_init(rdev->ddev, rdev->num_crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200122 if (r) {
123 return r;
124 }
Alex Deucher3e5cb982009-10-16 12:21:24 -0400125 /* enable msi */
126 rdev->msi_enabled = 0;
Alex Deucherc414a112010-03-30 17:22:32 -0400127 /* MSIs don't seem to work reliably on all IGP
128 * chips. Disable MSI on them for now.
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500129 */
130 if ((rdev->family >= CHIP_RV380) &&
Alex Deucherbbbf9b72010-11-22 17:56:36 -0500131 ((!(rdev->flags & RADEON_IS_IGP)) || (rdev->family >= CHIP_PALM)) &&
Alex Deucherda7be682010-08-12 18:05:34 -0400132 (!(rdev->flags & RADEON_IS_AGP))) {
Alex Deucher3e5cb982009-10-16 12:21:24 -0400133 int ret = pci_enable_msi(rdev->pdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500134 if (!ret) {
Alex Deucher3e5cb982009-10-16 12:21:24 -0400135 rdev->msi_enabled = 1;
Alex Deucherda7be682010-08-12 18:05:34 -0400136 dev_info(rdev->dev, "radeon: using MSI.\n");
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500137 }
Alex Deucher3e5cb982009-10-16 12:21:24 -0400138 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200139 rdev->irq.installed = true;
Jerome Glisse003e69f2010-01-07 15:39:14 +0100140 r = drm_irq_install(rdev->ddev);
141 if (r) {
142 rdev->irq.installed = false;
143 return r;
144 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200145 DRM_INFO("radeon: irq initialized.\n");
146 return 0;
147}
148
149void radeon_irq_kms_fini(struct radeon_device *rdev)
150{
Jerome Glisse003e69f2010-01-07 15:39:14 +0100151 drm_vblank_cleanup(rdev->ddev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200152 if (rdev->irq.installed) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200153 drm_irq_uninstall(rdev->ddev);
Jerome Glisse003e69f2010-01-07 15:39:14 +0100154 rdev->irq.installed = false;
Alex Deucher3e5cb982009-10-16 12:21:24 -0400155 if (rdev->msi_enabled)
156 pci_disable_msi(rdev->pdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200157 }
Tejun Heo32c87fc2011-01-03 14:49:32 +0100158 flush_work_sync(&rdev->hotplug_work);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200159}
Dave Airlie1614f8b2009-12-01 16:04:56 +1000160
161void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev)
162{
163 unsigned long irqflags;
164
165 spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
166 if (rdev->ddev->irq_enabled && (++rdev->irq.sw_refcount == 1)) {
167 rdev->irq.sw_int = true;
168 radeon_irq_set(rdev);
169 }
170 spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
171}
172
173void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev)
174{
175 unsigned long irqflags;
176
177 spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
178 BUG_ON(rdev->ddev->irq_enabled && rdev->irq.sw_refcount <= 0);
179 if (rdev->ddev->irq_enabled && (--rdev->irq.sw_refcount == 0)) {
180 rdev->irq.sw_int = false;
181 radeon_irq_set(rdev);
182 }
183 spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
184}
185
Alex Deucher6f34be52010-11-21 10:59:01 -0500186void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)
187{
188 unsigned long irqflags;
189
190 if (crtc < 0 || crtc >= rdev->num_crtc)
191 return;
192
193 spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
194 if (rdev->ddev->irq_enabled && (++rdev->irq.pflip_refcount[crtc] == 1)) {
195 rdev->irq.pflip[crtc] = true;
196 radeon_irq_set(rdev);
197 }
198 spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
199}
200
201void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc)
202{
203 unsigned long irqflags;
204
205 if (crtc < 0 || crtc >= rdev->num_crtc)
206 return;
207
208 spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
209 BUG_ON(rdev->ddev->irq_enabled && rdev->irq.pflip_refcount[crtc] <= 0);
210 if (rdev->ddev->irq_enabled && (--rdev->irq.pflip_refcount[crtc] == 0)) {
211 rdev->irq.pflip[crtc] = false;
212 radeon_irq_set(rdev);
213 }
214 spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
215}
216