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gerrit-public.fairphone.software / kernel / msm-4.9 / 2aa9fd06e221da4e69693dc1b5c6c6bc84c76f32 / . / arch / mips / include / uapi / asm / inst.h
blob: 471533778a6938a29b3f673a2a0f5086a08575b2 [file] [log] [blame]
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]1/*
2 * Format of an instruction in memory.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame^]10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]11 */
12#ifndef _UAPI_ASM_INST_H
13#define _UAPI_ASM_INST_H
14
15/*
16 * Major opcodes; before MIPS IV cop1x was called cop3.
17 */
18enum major_op {
19 spec_op, bcond_op, j_op, jal_op,
20 beq_op, bne_op, blez_op, bgtz_op,
21 addi_op, addiu_op, slti_op, sltiu_op,
22 andi_op, ori_op, xori_op, lui_op,
23 cop0_op, cop1_op, cop2_op, cop1x_op,
24 beql_op, bnel_op, blezl_op, bgtzl_op,
25 daddi_op, daddiu_op, ldl_op, ldr_op,
26 spec2_op, jalx_op, mdmx_op, spec3_op,
27 lb_op, lh_op, lwl_op, lw_op,
28 lbu_op, lhu_op, lwr_op, lwu_op,
29 sb_op, sh_op, swl_op, sw_op,
30 sdl_op, sdr_op, swr_op, cache_op,
31 ll_op, lwc1_op, lwc2_op, pref_op,
32 lld_op, ldc1_op, ldc2_op, ld_op,
33 sc_op, swc1_op, swc2_op, major_3b_op,
34 scd_op, sdc1_op, sdc2_op, sd_op
35};
36
37/*
38 * func field of spec opcode.
39 */
40enum spec_op {
41 sll_op, movc_op, srl_op, sra_op,
42 sllv_op, pmon_op, srlv_op, srav_op,
43 jr_op, jalr_op, movz_op, movn_op,
44 syscall_op, break_op, spim_op, sync_op,
45 mfhi_op, mthi_op, mflo_op, mtlo_op,
46 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
47 mult_op, multu_op, div_op, divu_op,
48 dmult_op, dmultu_op, ddiv_op, ddivu_op,
49 add_op, addu_op, sub_op, subu_op,
50 and_op, or_op, xor_op, nor_op,
51 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
52 dadd_op, daddu_op, dsub_op, dsubu_op,
53 tge_op, tgeu_op, tlt_op, tltu_op,
54 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
55 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
56 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
57};
58
59/*
60 * func field of spec2 opcode.
61 */
62enum spec2_op {
63 madd_op, maddu_op, mul_op, spec2_3_unused_op,
64 msub_op, msubu_op, /* more unused ops */
65 clz_op = 0x20, clo_op,
66 dclz_op = 0x24, dclo_op,
67 sdbpp_op = 0x3f
68};
69
70/*
71 * func field of spec3 opcode.
72 */
73enum spec3_op {
74 ext_op, dextm_op, dextu_op, dext_op,
75 ins_op, dinsm_op, dinsu_op, dins_op,
76 lx_op = 0x0a,
77 bshfl_op = 0x20,
78 dbshfl_op = 0x24,
79 rdhwr_op = 0x3b
80};
81
82/*
83 * rt field of bcond opcodes.
84 */
85enum rt_op {
86 bltz_op, bgez_op, bltzl_op, bgezl_op,
87 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
88 tgei_op, tgeiu_op, tlti_op, tltiu_op,
89 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
90 bltzal_op, bgezal_op, bltzall_op, bgezall_op,
91 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
92 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
93 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
94};
95
96/*
97 * rs field of cop opcodes.
98 */
99enum cop_op {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]100 mfc_op = 0x00, dmfc_op = 0x01,
101 cfc_op = 0x02, mtc_op = 0x04,
102 dmtc_op = 0x05, ctc_op = 0x06,
103 bc_op = 0x08, cop_op = 0x10,
104 copm_op = 0x18
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]105};
106
107/*
108 * rt field of cop.bc_op opcodes
109 */
110enum bcop_op {
111 bcf_op, bct_op, bcfl_op, bctl_op
112};
113
114/*
115 * func field of cop0 coi opcodes.
116 */
117enum cop0_coi_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]118 tlbr_op = 0x01, tlbwi_op = 0x02,
119 tlbwr_op = 0x06, tlbp_op = 0x08,
120 rfe_op = 0x10, eret_op = 0x18
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]121};
122
123/*
124 * func field of cop0 com opcodes.
125 */
126enum cop0_com_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]127 tlbr1_op = 0x01, tlbw_op = 0x02,
128 tlbp1_op = 0x08, dctr_op = 0x09,
129 dctw_op = 0x0a
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]130};
131
132/*
133 * fmt field of cop1 opcodes.
134 */
135enum cop1_fmt {
136 s_fmt, d_fmt, e_fmt, q_fmt,
137 w_fmt, l_fmt
138};
139
140/*
141 * func field of cop1 instructions using d, s or w format.
142 */
143enum cop1_sdw_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]144 fadd_op = 0x00, fsub_op = 0x01,
145 fmul_op = 0x02, fdiv_op = 0x03,
146 fsqrt_op = 0x04, fabs_op = 0x05,
147 fmov_op = 0x06, fneg_op = 0x07,
148 froundl_op = 0x08, ftruncl_op = 0x09,
149 fceill_op = 0x0a, ffloorl_op = 0x0b,
150 fround_op = 0x0c, ftrunc_op = 0x0d,
151 fceil_op = 0x0e, ffloor_op = 0x0f,
152 fmovc_op = 0x11, fmovz_op = 0x12,
153 fmovn_op = 0x13, frecip_op = 0x15,
154 frsqrt_op = 0x16, fcvts_op = 0x20,
155 fcvtd_op = 0x21, fcvte_op = 0x22,
156 fcvtw_op = 0x24, fcvtl_op = 0x25,
157 fcmp_op = 0x30
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]158};
159
160/*
161 * func field of cop1x opcodes (MIPS IV).
162 */
163enum cop1x_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]164 lwxc1_op = 0x00, ldxc1_op = 0x01,
165 pfetch_op = 0x07, swxc1_op = 0x08,
166 sdxc1_op = 0x09, madd_s_op = 0x20,
167 madd_d_op = 0x21, madd_e_op = 0x22,
168 msub_s_op = 0x28, msub_d_op = 0x29,
169 msub_e_op = 0x2a, nmadd_s_op = 0x30,
170 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
171 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
172 nmsub_e_op = 0x3a
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]173};
174
175/*
176 * func field for mad opcodes (MIPS IV).
177 */
178enum mad_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]179 madd_fp_op = 0x08, msub_fp_op = 0x0a,
180 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]181};
182
183/*
184 * func field for special3 lx opcodes (Cavium Octeon).
185 */
186enum lx_func {
187 lwx_op = 0x00,
188 lhx_op = 0x04,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]189 lbux_op = 0x06,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]190 ldx_op = 0x08,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]191 lwux_op = 0x10,
192 lhux_op = 0x14,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]193 lbx_op = 0x16,
194};
195
196/*
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame^]197 * (microMIPS) Major opcodes.
198 */
199enum mm_major_op {
200 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
201 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
202 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
203 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
204 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
205 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
206 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
207 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
208 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
209 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
210 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
211 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
212 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
213 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
214 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
215 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
216};
217
218/*
219 * (microMIPS) POOL32I minor opcodes.
220 */
221enum mm_32i_minor_op {
222 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
223 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
224 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
225 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
226 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
227 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
228 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
229 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
230 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
231};
232
233/*
234 * (microMIPS) POOL32A minor opcodes.
235 */
236enum mm_32a_minor_op {
237 mm_sll32_op = 0x000,
238 mm_ins_op = 0x00c,
239 mm_ext_op = 0x02c,
240 mm_pool32axf_op = 0x03c,
241 mm_srl32_op = 0x040,
242 mm_sra_op = 0x080,
243 mm_rotr_op = 0x0c0,
244 mm_lwxs_op = 0x118,
245 mm_addu32_op = 0x150,
246 mm_subu32_op = 0x1d0,
247 mm_and_op = 0x250,
248 mm_or32_op = 0x290,
249 mm_xor32_op = 0x310,
250};
251
252/*
253 * (microMIPS) POOL32B functions.
254 */
255enum mm_32b_func {
256 mm_lwc2_func = 0x0,
257 mm_lwp_func = 0x1,
258 mm_ldc2_func = 0x2,
259 mm_ldp_func = 0x4,
260 mm_lwm32_func = 0x5,
261 mm_cache_func = 0x6,
262 mm_ldm_func = 0x7,
263 mm_swc2_func = 0x8,
264 mm_swp_func = 0x9,
265 mm_sdc2_func = 0xa,
266 mm_sdp_func = 0xc,
267 mm_swm32_func = 0xd,
268 mm_sdm_func = 0xf,
269};
270
271/*
272 * (microMIPS) POOL32C functions.
273 */
274enum mm_32c_func {
275 mm_pref_func = 0x2,
276 mm_ll_func = 0x3,
277 mm_swr_func = 0x9,
278 mm_sc_func = 0xb,
279 mm_lwu_func = 0xe,
280};
281
282/*
283 * (microMIPS) POOL32AXF minor opcodes.
284 */
285enum mm_32axf_minor_op {
286 mm_mfc0_op = 0x003,
287 mm_mtc0_op = 0x00b,
288 mm_tlbp_op = 0x00d,
289 mm_jalr_op = 0x03c,
290 mm_tlbr_op = 0x04d,
291 mm_jalrhb_op = 0x07c,
292 mm_tlbwi_op = 0x08d,
293 mm_tlbwr_op = 0x0cd,
294 mm_jalrs_op = 0x13c,
295 mm_jalrshb_op = 0x17c,
296 mm_syscall_op = 0x22d,
297 mm_eret_op = 0x3cd,
298};
299
300/*
301 * (microMIPS) POOL32F minor opcodes.
302 */
303enum mm_32f_minor_op {
304 mm_32f_00_op = 0x00,
305 mm_32f_01_op = 0x01,
306 mm_32f_02_op = 0x02,
307 mm_32f_10_op = 0x08,
308 mm_32f_11_op = 0x09,
309 mm_32f_12_op = 0x0a,
310 mm_32f_20_op = 0x10,
311 mm_32f_30_op = 0x18,
312 mm_32f_40_op = 0x20,
313 mm_32f_41_op = 0x21,
314 mm_32f_42_op = 0x22,
315 mm_32f_50_op = 0x28,
316 mm_32f_51_op = 0x29,
317 mm_32f_52_op = 0x2a,
318 mm_32f_60_op = 0x30,
319 mm_32f_70_op = 0x38,
320 mm_32f_73_op = 0x3b,
321 mm_32f_74_op = 0x3c,
322};
323
324/*
325 * (microMIPS) POOL32F secondary minor opcodes.
326 */
327enum mm_32f_10_minor_op {
328 mm_lwxc1_op = 0x1,
329 mm_swxc1_op,
330 mm_ldxc1_op,
331 mm_sdxc1_op,
332 mm_luxc1_op,
333 mm_suxc1_op,
334};
335
336enum mm_32f_func {
337 mm_lwxc1_func = 0x048,
338 mm_swxc1_func = 0x088,
339 mm_ldxc1_func = 0x0c8,
340 mm_sdxc1_func = 0x108,
341};
342
343/*
344 * (microMIPS) POOL32F secondary minor opcodes.
345 */
346enum mm_32f_40_minor_op {
347 mm_fmovf_op,
348 mm_fmovt_op,
349};
350
351/*
352 * (microMIPS) POOL32F secondary minor opcodes.
353 */
354enum mm_32f_60_minor_op {
355 mm_fadd_op,
356 mm_fsub_op,
357 mm_fmul_op,
358 mm_fdiv_op,
359};
360
361/*
362 * (microMIPS) POOL32F secondary minor opcodes.
363 */
364enum mm_32f_70_minor_op {
365 mm_fmovn_op,
366 mm_fmovz_op,
367};
368
369/*
370 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
371 */
372enum mm_32f_73_minor_op {
373 mm_fmov0_op = 0x01,
374 mm_fcvtl_op = 0x04,
375 mm_movf0_op = 0x05,
376 mm_frsqrt_op = 0x08,
377 mm_ffloorl_op = 0x0c,
378 mm_fabs0_op = 0x0d,
379 mm_fcvtw_op = 0x24,
380 mm_movt0_op = 0x25,
381 mm_fsqrt_op = 0x28,
382 mm_ffloorw_op = 0x2c,
383 mm_fneg0_op = 0x2d,
384 mm_cfc1_op = 0x40,
385 mm_frecip_op = 0x48,
386 mm_fceill_op = 0x4c,
387 mm_fcvtd0_op = 0x4d,
388 mm_ctc1_op = 0x60,
389 mm_fceilw_op = 0x6c,
390 mm_fcvts0_op = 0x6d,
391 mm_mfc1_op = 0x80,
392 mm_fmov1_op = 0x81,
393 mm_movf1_op = 0x85,
394 mm_ftruncl_op = 0x8c,
395 mm_fabs1_op = 0x8d,
396 mm_mtc1_op = 0xa0,
397 mm_movt1_op = 0xa5,
398 mm_ftruncw_op = 0xac,
399 mm_fneg1_op = 0xad,
400 mm_froundl_op = 0xcc,
401 mm_fcvtd1_op = 0xcd,
402 mm_froundw_op = 0xec,
403 mm_fcvts1_op = 0xed,
404};
405
406/*
407 * (microMIPS) POOL16C minor opcodes.
408 */
409enum mm_16c_minor_op {
410 mm_lwm16_op = 0x04,
411 mm_swm16_op = 0x05,
412 mm_jr16_op = 0x18,
413 mm_jrc_op = 0x1a,
414 mm_jalr16_op = 0x1c,
415 mm_jalrs16_op = 0x1e,
416};
417
418/*
419 * (microMIPS) POOL16D minor opcodes.
420 */
421enum mm_16d_minor_op {
422 mm_addius5_func,
423 mm_addiusp_func,
424};
425
426/*
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]427 * Damn ... bitfields depend from byteorder :-(
428 */
429#ifdef __MIPSEB__
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]430#define BITFIELD_FIELD(field, more) \
431 field; \
432 more
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]433
434#elif defined(__MIPSEL__)
435
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]436#define BITFIELD_FIELD(field, more) \
437 more \
438 field;
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]439
440#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
441#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
442#endif
443
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]444struct j_format {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]445 BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]446 BITFIELD_FIELD(unsigned int target : 26,
447 ;))
448};
449
450struct i_format { /* signed immediate format */
451 BITFIELD_FIELD(unsigned int opcode : 6,
452 BITFIELD_FIELD(unsigned int rs : 5,
453 BITFIELD_FIELD(unsigned int rt : 5,
454 BITFIELD_FIELD(signed int simmediate : 16,
455 ;))))
456};
457
458struct u_format { /* unsigned immediate format */
459 BITFIELD_FIELD(unsigned int opcode : 6,
460 BITFIELD_FIELD(unsigned int rs : 5,
461 BITFIELD_FIELD(unsigned int rt : 5,
462 BITFIELD_FIELD(unsigned int uimmediate : 16,
463 ;))))
464};
465
466struct c_format { /* Cache (>= R6000) format */
467 BITFIELD_FIELD(unsigned int opcode : 6,
468 BITFIELD_FIELD(unsigned int rs : 5,
469 BITFIELD_FIELD(unsigned int c_op : 3,
470 BITFIELD_FIELD(unsigned int cache : 2,
471 BITFIELD_FIELD(unsigned int simmediate : 16,
472 ;)))))
473};
474
475struct r_format { /* Register format */
476 BITFIELD_FIELD(unsigned int opcode : 6,
477 BITFIELD_FIELD(unsigned int rs : 5,
478 BITFIELD_FIELD(unsigned int rt : 5,
479 BITFIELD_FIELD(unsigned int rd : 5,
480 BITFIELD_FIELD(unsigned int re : 5,
481 BITFIELD_FIELD(unsigned int func : 6,
482 ;))))))
483};
484
485struct p_format { /* Performance counter format (R10000) */
486 BITFIELD_FIELD(unsigned int opcode : 6,
487 BITFIELD_FIELD(unsigned int rs : 5,
488 BITFIELD_FIELD(unsigned int rt : 5,
489 BITFIELD_FIELD(unsigned int rd : 5,
490 BITFIELD_FIELD(unsigned int re : 5,
491 BITFIELD_FIELD(unsigned int func : 6,
492 ;))))))
493};
494
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]495struct f_format { /* FPU register format */
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]496 BITFIELD_FIELD(unsigned int opcode : 6,
497 BITFIELD_FIELD(unsigned int : 1,
498 BITFIELD_FIELD(unsigned int fmt : 4,
499 BITFIELD_FIELD(unsigned int rt : 5,
500 BITFIELD_FIELD(unsigned int rd : 5,
501 BITFIELD_FIELD(unsigned int re : 5,
502 BITFIELD_FIELD(unsigned int func : 6,
503 ;)))))))
504};
505
506struct ma_format { /* FPU multiply and add format (MIPS IV) */
507 BITFIELD_FIELD(unsigned int opcode : 6,
508 BITFIELD_FIELD(unsigned int fr : 5,
509 BITFIELD_FIELD(unsigned int ft : 5,
510 BITFIELD_FIELD(unsigned int fs : 5,
511 BITFIELD_FIELD(unsigned int fd : 5,
512 BITFIELD_FIELD(unsigned int func : 4,
513 BITFIELD_FIELD(unsigned int fmt : 2,
514 ;)))))))
515};
516
517struct b_format { /* BREAK and SYSCALL */
518 BITFIELD_FIELD(unsigned int opcode : 6,
519 BITFIELD_FIELD(unsigned int code : 20,
520 BITFIELD_FIELD(unsigned int func : 6,
521 ;)))
522};
523
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]524struct ps_format { /* MIPS-3D / paired single format */
525 BITFIELD_FIELD(unsigned int opcode : 6,
526 BITFIELD_FIELD(unsigned int rs : 5,
527 BITFIELD_FIELD(unsigned int ft : 5,
528 BITFIELD_FIELD(unsigned int fs : 5,
529 BITFIELD_FIELD(unsigned int fd : 5,
530 BITFIELD_FIELD(unsigned int func : 6,
531 ;))))))
532};
533
534struct v_format { /* MDMX vector format */
535 BITFIELD_FIELD(unsigned int opcode : 6,
536 BITFIELD_FIELD(unsigned int sel : 4,
537 BITFIELD_FIELD(unsigned int fmt : 1,
538 BITFIELD_FIELD(unsigned int vt : 5,
539 BITFIELD_FIELD(unsigned int vs : 5,
540 BITFIELD_FIELD(unsigned int vd : 5,
541 BITFIELD_FIELD(unsigned int func : 6,
542 ;)))))))
543};
544
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame^]545/*
546 * microMIPS instruction formats (32-bit length)
547 *
548 * NOTE:
549 * Parenthesis denote whether the format is a microMIPS instruction or
550 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
551 */
552struct fb_format { /* FPU branch format (MIPS32) */
553 BITFIELD_FIELD(unsigned int opcode : 6,
554 BITFIELD_FIELD(unsigned int bc : 5,
555 BITFIELD_FIELD(unsigned int cc : 3,
556 BITFIELD_FIELD(unsigned int flag : 2,
557 BITFIELD_FIELD(signed int simmediate : 16,
558 ;)))))
559};
560
561struct fp0_format { /* FPU multiply and add format (MIPS32) */
562 BITFIELD_FIELD(unsigned int opcode : 6,
563 BITFIELD_FIELD(unsigned int fmt : 5,
564 BITFIELD_FIELD(unsigned int ft : 5,
565 BITFIELD_FIELD(unsigned int fs : 5,
566 BITFIELD_FIELD(unsigned int fd : 5,
567 BITFIELD_FIELD(unsigned int func : 6,
568 ;))))))
569};
570
571struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */
572 BITFIELD_FIELD(unsigned int opcode : 6,
573 BITFIELD_FIELD(unsigned int ft : 5,
574 BITFIELD_FIELD(unsigned int fs : 5,
575 BITFIELD_FIELD(unsigned int fd : 5,
576 BITFIELD_FIELD(unsigned int fmt : 3,
577 BITFIELD_FIELD(unsigned int op : 2,
578 BITFIELD_FIELD(unsigned int func : 6,
579 ;)))))))
580};
581
582struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
583 BITFIELD_FIELD(unsigned int opcode : 6,
584 BITFIELD_FIELD(unsigned int op : 5,
585 BITFIELD_FIELD(unsigned int rt : 5,
586 BITFIELD_FIELD(unsigned int fs : 5,
587 BITFIELD_FIELD(unsigned int fd : 5,
588 BITFIELD_FIELD(unsigned int func : 6,
589 ;))))))
590};
591
592struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
593 BITFIELD_FIELD(unsigned int opcode : 6,
594 BITFIELD_FIELD(unsigned int rt : 5,
595 BITFIELD_FIELD(unsigned int fs : 5,
596 BITFIELD_FIELD(unsigned int fmt : 2,
597 BITFIELD_FIELD(unsigned int op : 8,
598 BITFIELD_FIELD(unsigned int func : 6,
599 ;))))))
600};
601
602struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
603 BITFIELD_FIELD(unsigned int opcode : 6,
604 BITFIELD_FIELD(unsigned int fd : 5,
605 BITFIELD_FIELD(unsigned int fs : 5,
606 BITFIELD_FIELD(unsigned int cc : 3,
607 BITFIELD_FIELD(unsigned int zero : 2,
608 BITFIELD_FIELD(unsigned int fmt : 2,
609 BITFIELD_FIELD(unsigned int op : 3,
610 BITFIELD_FIELD(unsigned int func : 6,
611 ;))))))))
612};
613
614struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
615 BITFIELD_FIELD(unsigned int opcode : 6,
616 BITFIELD_FIELD(unsigned int rt : 5,
617 BITFIELD_FIELD(unsigned int fs : 5,
618 BITFIELD_FIELD(unsigned int fmt : 3,
619 BITFIELD_FIELD(unsigned int op : 7,
620 BITFIELD_FIELD(unsigned int func : 6,
621 ;))))))
622};
623
624struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
625 BITFIELD_FIELD(unsigned int opcode : 6,
626 BITFIELD_FIELD(unsigned int rt : 5,
627 BITFIELD_FIELD(unsigned int fs : 5,
628 BITFIELD_FIELD(unsigned int cc : 3,
629 BITFIELD_FIELD(unsigned int fmt : 3,
630 BITFIELD_FIELD(unsigned int cond : 4,
631 BITFIELD_FIELD(unsigned int func : 6,
632 ;)))))))
633};
634
635struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
636 BITFIELD_FIELD(unsigned int opcode : 6,
637 BITFIELD_FIELD(unsigned int index : 5,
638 BITFIELD_FIELD(unsigned int base : 5,
639 BITFIELD_FIELD(unsigned int fd : 5,
640 BITFIELD_FIELD(unsigned int op : 5,
641 BITFIELD_FIELD(unsigned int func : 6,
642 ;))))))
643};
644
645struct fp6_format { /* FPU madd and msub format (MIPS IV) */
646 BITFIELD_FIELD(unsigned int opcode : 6,
647 BITFIELD_FIELD(unsigned int fr : 5,
648 BITFIELD_FIELD(unsigned int ft : 5,
649 BITFIELD_FIELD(unsigned int fs : 5,
650 BITFIELD_FIELD(unsigned int fd : 5,
651 BITFIELD_FIELD(unsigned int func : 6,
652 ;))))))
653};
654
655struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
656 BITFIELD_FIELD(unsigned int opcode : 6,
657 BITFIELD_FIELD(unsigned int ft : 5,
658 BITFIELD_FIELD(unsigned int fs : 5,
659 BITFIELD_FIELD(unsigned int fd : 5,
660 BITFIELD_FIELD(unsigned int fr : 5,
661 BITFIELD_FIELD(unsigned int func : 6,
662 ;))))))
663};
664
665struct mm_i_format { /* Immediate format (microMIPS) */
666 BITFIELD_FIELD(unsigned int opcode : 6,
667 BITFIELD_FIELD(unsigned int rt : 5,
668 BITFIELD_FIELD(unsigned int rs : 5,
669 BITFIELD_FIELD(signed int simmediate : 16,
670 ;))))
671};
672
673struct mm_m_format { /* Multi-word load/store format (microMIPS) */
674 BITFIELD_FIELD(unsigned int opcode : 6,
675 BITFIELD_FIELD(unsigned int rd : 5,
676 BITFIELD_FIELD(unsigned int base : 5,
677 BITFIELD_FIELD(unsigned int func : 4,
678 BITFIELD_FIELD(signed int simmediate : 12,
679 ;)))))
680};
681
682struct mm_x_format { /* Scaled indexed load format (microMIPS) */
683 BITFIELD_FIELD(unsigned int opcode : 6,
684 BITFIELD_FIELD(unsigned int index : 5,
685 BITFIELD_FIELD(unsigned int base : 5,
686 BITFIELD_FIELD(unsigned int rd : 5,
687 BITFIELD_FIELD(unsigned int func : 11,
688 ;)))))
689};
690
691/*
692 * microMIPS instruction formats (16-bit length)
693 */
694struct mm_b0_format { /* Unconditional branch format (microMIPS) */
695 BITFIELD_FIELD(unsigned int opcode : 6,
696 BITFIELD_FIELD(signed int simmediate : 10,
697 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
698 ;)))
699};
700
701struct mm_b1_format { /* Conditional branch format (microMIPS) */
702 BITFIELD_FIELD(unsigned int opcode : 6,
703 BITFIELD_FIELD(unsigned int rs : 3,
704 BITFIELD_FIELD(signed int simmediate : 7,
705 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
706 ;))))
707};
708
709struct mm16_m_format { /* Multi-word load/store format */
710 BITFIELD_FIELD(unsigned int opcode : 6,
711 BITFIELD_FIELD(unsigned int func : 4,
712 BITFIELD_FIELD(unsigned int rlist : 2,
713 BITFIELD_FIELD(unsigned int imm : 4,
714 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
715 ;)))))
716};
717
718struct mm16_rb_format { /* Signed immediate format */
719 BITFIELD_FIELD(unsigned int opcode : 6,
720 BITFIELD_FIELD(unsigned int rt : 3,
721 BITFIELD_FIELD(unsigned int base : 3,
722 BITFIELD_FIELD(signed int simmediate : 4,
723 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
724 ;)))))
725};
726
727struct mm16_r3_format { /* Load from global pointer format */
728 BITFIELD_FIELD(unsigned int opcode : 6,
729 BITFIELD_FIELD(unsigned int rt : 3,
730 BITFIELD_FIELD(signed int simmediate : 7,
731 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
732 ;))))
733};
734
735struct mm16_r5_format { /* Load/store from stack pointer format */
736 BITFIELD_FIELD(unsigned int opcode : 6,
737 BITFIELD_FIELD(unsigned int rt : 5,
738 BITFIELD_FIELD(signed int simmediate : 5,
739 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
740 ;))))
741};
742
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]743union mips_instruction {
744 unsigned int word;
745 unsigned short halfword[2];
746 unsigned char byte[4];
747 struct j_format j_format;
748 struct i_format i_format;
749 struct u_format u_format;
750 struct c_format c_format;
751 struct r_format r_format;
752 struct p_format p_format;
753 struct f_format f_format;
754 struct ma_format ma_format;
755 struct b_format b_format;
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]756 struct ps_format ps_format;
757 struct v_format v_format;
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame^]758 struct fb_format fb_format;
759 struct fp0_format fp0_format;
760 struct mm_fp0_format mm_fp0_format;
761 struct fp1_format fp1_format;
762 struct mm_fp1_format mm_fp1_format;
763 struct mm_fp2_format mm_fp2_format;
764 struct mm_fp3_format mm_fp3_format;
765 struct mm_fp4_format mm_fp4_format;
766 struct mm_fp5_format mm_fp5_format;
767 struct fp6_format fp6_format;
768 struct mm_fp6_format mm_fp6_format;
769 struct mm_i_format mm_i_format;
770 struct mm_m_format mm_m_format;
771 struct mm_x_format mm_x_format;
772 struct mm_b0_format mm_b0_format;
773 struct mm_b1_format mm_b1_format;
774 struct mm16_m_format mm16_m_format ;
775 struct mm16_rb_format mm16_rb_format;
776 struct mm16_r3_format mm16_r3_format;
777 struct mm16_r5_format mm16_r5_format;
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]778};
779
780#endif /* _UAPI_ASM_INST_H */