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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-sa1100/cpu-sa1110.c
3 *
4 * Copyright (C) 2001 Russell King
5 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Note: there are two erratas that apply to the SA1110 here:
11 * 7 - SDRAM auto-power-up failure (rev A0)
12 * 13 - Corruption of internal register reads/writes following
13 * SDRAM reads (rev A0, B0, B1)
14 *
15 * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
Russell Kingba532012006-06-29 20:56:47 +010016 *
17 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
Linus Torvalds1da177e2005-04-16 15:20:36 -070018 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/cpufreq.h>
20#include <linux/delay.h>
21#include <linux/init.h>
Russell King31696632012-06-06 11:42:36 +010022#include <linux/io.h>
Marcelo Roberto Jimenez9f15d2c2010-12-16 20:51:30 +010023#include <linux/kernel.h>
24#include <linux/moduleparam.h>
25#include <linux/types.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Russell King0ba8b9b2008-08-10 18:08:10 +010027#include <asm/cputype.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <asm/mach-types.h>
Marcelo Roberto Jimenez9f15d2c2010-12-16 20:51:30 +010029
30#include <mach/hardware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
32#include "generic.h"
33
34#undef DEBUG
35
Linus Torvalds1da177e2005-04-16 15:20:36 -070036struct sdram_params {
Marcelo Roberto Jimenez9f15d2c2010-12-16 20:51:30 +010037 const char name[20];
Linus Torvalds1da177e2005-04-16 15:20:36 -070038 u_char rows; /* bits */
39 u_char cas_latency; /* cycles */
40 u_char tck; /* clock cycle time (ns) */
41 u_char trcd; /* activate to r/w (ns) */
42 u_char trp; /* precharge to activate (ns) */
43 u_char twr; /* write recovery time (ns) */
44 u_short refresh; /* refresh time for array (us) */
45};
46
47struct sdram_info {
48 u_int mdcnfg;
49 u_int mdrefr;
50 u_int mdcas[3];
51};
52
Russell Kingba532012006-06-29 20:56:47 +010053static struct sdram_params sdram_tbl[] __initdata = {
54 { /* Toshiba TC59SM716 CL2 */
55 .name = "TC59SM716-CL2",
56 .rows = 12,
57 .tck = 10,
58 .trcd = 20,
59 .trp = 20,
60 .twr = 10,
61 .refresh = 64000,
62 .cas_latency = 2,
63 }, { /* Toshiba TC59SM716 CL3 */
64 .name = "TC59SM716-CL3",
65 .rows = 12,
66 .tck = 8,
67 .trcd = 20,
68 .trp = 20,
69 .twr = 8,
70 .refresh = 64000,
71 .cas_latency = 3,
72 }, { /* Samsung K4S641632D TC75 */
73 .name = "K4S641632D",
74 .rows = 14,
75 .tck = 9,
76 .trcd = 27,
77 .trp = 20,
78 .twr = 9,
79 .refresh = 64000,
80 .cas_latency = 3,
Kristoffer Ericson93982532008-11-26 20:58:43 +010081 }, { /* Samsung K4S281632B-1H */
82 .name = "K4S281632B-1H",
83 .rows = 12,
84 .tck = 10,
85 .trp = 20,
86 .twr = 10,
87 .refresh = 64000,
88 .cas_latency = 3,
Russell Kingba532012006-06-29 20:56:47 +010089 }, { /* Samsung KM416S4030CT */
90 .name = "KM416S4030CT",
91 .rows = 13,
92 .tck = 8,
93 .trcd = 24, /* 3 CLKs */
94 .trp = 24, /* 3 CLKs */
95 .twr = 16, /* Trdl: 2 CLKs */
96 .refresh = 64000,
97 .cas_latency = 3,
98 }, { /* Winbond W982516AH75L CL3 */
99 .name = "W982516AH75L",
100 .rows = 16,
101 .tck = 8,
102 .trcd = 20,
103 .trp = 20,
104 .twr = 8,
105 .refresh = 64000,
106 .cas_latency = 3,
Marcelo Roberto Jimenez9f15d2c2010-12-16 20:51:30 +0100107 }, { /* Micron MT48LC8M16A2TG-75 */
108 .name = "MT48LC8M16A2TG-75",
109 .rows = 12,
110 .tck = 8,
111 .trcd = 20,
112 .trp = 20,
113 .twr = 8,
114 .refresh = 64000,
115 .cas_latency = 3,
Russell Kingba532012006-06-29 20:56:47 +0100116 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117};
118
119static struct sdram_params sdram_params;
120
121/*
122 * Given a period in ns and frequency in khz, calculate the number of
123 * cycles of frequency in period. Note that we round up to the next
124 * cycle, even if we are only slightly over.
125 */
126static inline u_int ns_to_cycles(u_int ns, u_int khz)
127{
128 return (ns * khz + 999999) / 1000000;
129}
130
131/*
132 * Create the MDCAS register bit pattern.
133 */
134static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
135{
136 u_int shift;
137
138 rcd = 2 * rcd - 1;
139 shift = delayed + 1 + rcd;
140
141 mdcas[0] = (1 << rcd) - 1;
142 mdcas[0] |= 0x55555555 << shift;
143 mdcas[1] = mdcas[2] = 0x55555555 << (shift & 1);
144}
145
146static void
147sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
148 struct sdram_params *sdram)
149{
150 u_int mem_khz, sd_khz, trp, twr;
151
152 mem_khz = cpu_khz / 2;
153 sd_khz = mem_khz;
154
155 /*
156 * If SDCLK would invalidate the SDRAM timings,
157 * run SDCLK at half speed.
158 *
159 * CPU steppings prior to B2 must either run the memory at
160 * half speed or use delayed read latching (errata 13).
161 */
162 if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
163 (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
164 sd_khz /= 2;
165
166 sd->mdcnfg = MDCNFG & 0x007f007f;
167
168 twr = ns_to_cycles(sdram->twr, mem_khz);
169
170 /* trp should always be >1 */
171 trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
172 if (trp < 1)
173 trp = 1;
174
175 sd->mdcnfg |= trp << 8;
176 sd->mdcnfg |= trp << 24;
177 sd->mdcnfg |= sdram->cas_latency << 12;
178 sd->mdcnfg |= sdram->cas_latency << 28;
179 sd->mdcnfg |= twr << 14;
180 sd->mdcnfg |= twr << 30;
181
182 sd->mdrefr = MDREFR & 0xffbffff0;
183 sd->mdrefr |= 7;
184
185 if (sd_khz != mem_khz)
186 sd->mdrefr |= MDREFR_K1DB2;
187
188 /* initial number of '1's in MDCAS + 1 */
Marcelo Roberto Jimenez47bb3b32010-10-18 22:32:48 +0100189 set_mdcas(sd->mdcas, sd_khz >= 62000,
190 ns_to_cycles(sdram->trcd, mem_khz));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
192#ifdef DEBUG
Marcelo Roberto Jimenez47bb3b32010-10-18 22:32:48 +0100193 printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
194 sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
195 sd->mdcas[2]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196#endif
197}
198
199/*
200 * Set the SDRAM refresh rate.
201 */
202static inline void sdram_set_refresh(u_int dri)
203{
204 MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
205 (void) MDREFR;
206}
207
208/*
209 * Update the refresh period. We do this such that we always refresh
210 * the SDRAMs within their permissible period. The refresh period is
211 * always a multiple of the memory clock (fixed at cpu_clock / 2).
212 *
213 * FIXME: we don't currently take account of burst accesses here,
214 * but neither do Intels DM nor Angel.
215 */
216static void
217sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
218{
219 u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
220 u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
221
222#ifdef DEBUG
223 mdelay(250);
Marcelo Roberto Jimenez47bb3b32010-10-18 22:32:48 +0100224 printk(KERN_DEBUG "new dri value = %d\n", dri);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225#endif
226
227 sdram_set_refresh(dri);
228}
229
230/*
Kristoffer Ericson93982532008-11-26 20:58:43 +0100231 * Ok, set the CPU frequency.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 */
233static int sa1110_target(struct cpufreq_policy *policy,
234 unsigned int target_freq,
235 unsigned int relation)
236{
237 struct sdram_params *sdram = &sdram_params;
238 struct cpufreq_freqs freqs;
239 struct sdram_info sd;
240 unsigned long flags;
241 unsigned int ppcr, unused;
242
Marcelo Roberto Jimenez47bb3b32010-10-18 22:32:48 +0100243 switch (relation) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244 case CPUFREQ_RELATION_L:
245 ppcr = sa11x0_freq_to_ppcr(target_freq);
246 if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
247 ppcr--;
248 break;
249 case CPUFREQ_RELATION_H:
250 ppcr = sa11x0_freq_to_ppcr(target_freq);
251 if (ppcr && (sa11x0_ppcr_to_freq(ppcr) > target_freq) &&
252 (sa11x0_ppcr_to_freq(ppcr-1) >= policy->min))
253 ppcr--;
254 break;
255 default:
256 return -EINVAL;
257 }
258
259 freqs.old = sa11x0_getspeed(0);
260 freqs.new = sa11x0_ppcr_to_freq(ppcr);
261 freqs.cpu = 0;
262
263 sdram_calculate_timing(&sd, freqs.new, sdram);
264
265#if 0
266 /*
267 * These values are wrong according to the SA1110 documentation
268 * and errata, but they seem to work. Need to get a storage
269 * scope on to the SDRAM signals to work out why.
270 */
271 if (policy->max < 147500) {
272 sd.mdrefr |= MDREFR_K1DB2;
273 sd.mdcas[0] = 0xaaaaaa7f;
274 } else {
275 sd.mdrefr &= ~MDREFR_K1DB2;
276 sd.mdcas[0] = 0xaaaaaa9f;
277 }
278 sd.mdcas[1] = 0xaaaaaaaa;
279 sd.mdcas[2] = 0xaaaaaaaa;
280#endif
281
282 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
283
284 /*
285 * The clock could be going away for some time. Set the SDRAMs
286 * to refresh rapidly (every 64 memory clock cycles). To get
287 * through the whole array, we need to wait 262144 mclk cycles.
288 * We wait 20ms to be safe.
289 */
290 sdram_set_refresh(2);
Marcelo Roberto Jimenez47bb3b32010-10-18 22:32:48 +0100291 if (!irqs_disabled())
Nishanth Aravamudandb579552005-07-01 12:11:51 +0100292 msleep(20);
Marcelo Roberto Jimenez47bb3b32010-10-18 22:32:48 +0100293 else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 mdelay(20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295
296 /*
297 * Reprogram the DRAM timings with interrupts disabled, and
298 * ensure that we are doing this within a complete cache line.
299 * This means that we won't access SDRAM for the duration of
300 * the programming.
301 */
302 local_irq_save(flags);
303 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
304 udelay(10);
Marcelo Roberto Jimenez47bb3b32010-10-18 22:32:48 +0100305 __asm__ __volatile__("\n\
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 b 2f \n\
307 .align 5 \n\
3081: str %3, [%1, #0] @ MDCNFG \n\
309 str %4, [%1, #28] @ MDREFR \n\
310 str %5, [%1, #4] @ MDCAS0 \n\
311 str %6, [%1, #8] @ MDCAS1 \n\
312 str %7, [%1, #12] @ MDCAS2 \n\
313 str %8, [%2, #0] @ PPCR \n\
314 ldr %0, [%1, #0] \n\
315 b 3f \n\
3162: b 1b \n\
3173: nop \n\
318 nop"
319 : "=&r" (unused)
320 : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
321 "r" (sd.mdrefr), "r" (sd.mdcas[0]),
322 "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
323 local_irq_restore(flags);
324
325 /*
326 * Now, return the SDRAM refresh back to normal.
327 */
328 sdram_update_refresh(freqs.new, sdram);
329
330 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
331
332 return 0;
333}
334
335static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
336{
337 if (policy->cpu != 0)
338 return -EINVAL;
339 policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 policy->cpuinfo.min_freq = 59000;
341 policy->cpuinfo.max_freq = 287000;
342 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
343 return 0;
344}
345
Marcelo Roberto Jimenez9f15d2c2010-12-16 20:51:30 +0100346/* sa1110_driver needs __refdata because it must remain after init registers
347 * it with cpufreq_register_driver() */
348static struct cpufreq_driver sa1110_driver __refdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349 .flags = CPUFREQ_STICKY,
350 .verify = sa11x0_verify_speed,
351 .target = sa1110_target,
352 .get = sa11x0_getspeed,
353 .init = sa1110_cpu_init,
354 .name = "sa1110",
355};
356
Russell Kingba532012006-06-29 20:56:47 +0100357static struct sdram_params *sa1110_find_sdram(const char *name)
358{
359 struct sdram_params *sdram;
360
Marcelo Roberto Jimenez47bb3b32010-10-18 22:32:48 +0100361 for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
362 sdram++)
Russell Kingba532012006-06-29 20:56:47 +0100363 if (strcmp(name, sdram->name) == 0)
364 return sdram;
365
366 return NULL;
367}
368
369static char sdram_name[16];
370
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371static int __init sa1110_clk_init(void)
372{
Russell Kingba532012006-06-29 20:56:47 +0100373 struct sdram_params *sdram;
374 const char *name = sdram_name;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375
Dmitry Artamonowe5992c02010-04-30 21:31:36 +0100376 if (!cpu_is_sa1110())
377 return -ENODEV;
378
Russell Kingba532012006-06-29 20:56:47 +0100379 if (!name[0]) {
380 if (machine_is_assabet())
381 name = "TC59SM716-CL3";
Russell Kingba532012006-06-29 20:56:47 +0100382 if (machine_is_pt_system3())
383 name = "K4S641632D";
Russell Kingba532012006-06-29 20:56:47 +0100384 if (machine_is_h3100())
385 name = "KM416S4030CT";
Kristoffer Ericson48e3bec2006-10-08 19:52:30 +0100386 if (machine_is_jornada720())
Marcelo Roberto Jimenez47bb3b32010-10-18 22:32:48 +0100387 name = "K4S281632B-1H";
Marcelo Roberto Jimenez9f15d2c2010-12-16 20:51:30 +0100388 if (machine_is_nanoengine())
389 name = "MT48LC8M16A2TG-75";
Russell Kingba532012006-06-29 20:56:47 +0100390 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391
Russell Kingba532012006-06-29 20:56:47 +0100392 sdram = sa1110_find_sdram(name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393 if (sdram) {
394 printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
395 " twr: %d refresh: %d cas_latency: %d\n",
396 sdram->tck, sdram->trcd, sdram->trp,
397 sdram->twr, sdram->refresh, sdram->cas_latency);
398
399 memcpy(&sdram_params, sdram, sizeof(sdram_params));
400
401 return cpufreq_register_driver(&sa1110_driver);
402 }
403
404 return 0;
405}
406
Russell Kingba532012006-06-29 20:56:47 +0100407module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408arch_initcall(sa1110_clk_init);