Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems) |
| 3 | * |
| 4 | * Copyright (C) 2014 Atmel Corporation |
| 5 | * |
| 6 | * Author: Ludovic Desroches <ludovic.desroches@atmel.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License version 2 as published by |
| 10 | * the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include <asm/barrier.h> |
| 22 | #include <dt-bindings/dma/at91.h> |
| 23 | #include <linux/clk.h> |
| 24 | #include <linux/dmaengine.h> |
| 25 | #include <linux/dmapool.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/irq.h> |
Ludovic Desroches | 6d3a7d9 | 2015-01-27 16:30:32 +0100 | [diff] [blame] | 28 | #include <linux/kernel.h> |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 29 | #include <linux/list.h> |
| 30 | #include <linux/module.h> |
| 31 | #include <linux/of_dma.h> |
| 32 | #include <linux/of_platform.h> |
| 33 | #include <linux/platform_device.h> |
| 34 | #include <linux/pm.h> |
| 35 | |
| 36 | #include "dmaengine.h" |
| 37 | |
| 38 | /* Global registers */ |
| 39 | #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */ |
| 40 | #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */ |
| 41 | #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */ |
| 42 | #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */ |
| 43 | #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */ |
| 44 | #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */ |
| 45 | #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */ |
| 46 | #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */ |
| 47 | #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */ |
| 48 | #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */ |
| 49 | #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */ |
| 50 | #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */ |
| 51 | #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */ |
| 52 | #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */ |
| 53 | #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */ |
| 54 | #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */ |
| 55 | #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */ |
| 56 | #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */ |
| 57 | #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */ |
| 58 | #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */ |
| 59 | #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */ |
| 60 | |
| 61 | /* Channel relative registers offsets */ |
| 62 | #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */ |
| 63 | #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */ |
| 64 | #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */ |
| 65 | #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */ |
| 66 | #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */ |
| 67 | #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */ |
| 68 | #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */ |
| 69 | #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */ |
| 70 | #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */ |
| 71 | #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */ |
| 72 | #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */ |
| 73 | #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */ |
| 74 | #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */ |
| 75 | #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */ |
| 76 | #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */ |
| 77 | #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */ |
| 78 | #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */ |
| 79 | #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */ |
| 80 | #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */ |
| 81 | #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */ |
| 82 | #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */ |
| 83 | #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */ |
| 84 | #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */ |
| 85 | #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */ |
| 86 | #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */ |
| 87 | #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */ |
| 88 | #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */ |
| 89 | #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */ |
| 90 | #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */ |
| 91 | #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */ |
| 92 | #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */ |
| 93 | #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */ |
| 94 | #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */ |
| 95 | #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */ |
| 96 | #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */ |
| 97 | #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */ |
| 98 | #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */ |
| 99 | #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */ |
| 100 | #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */ |
| 101 | #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */ |
| 102 | #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */ |
| 103 | #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */ |
| 104 | #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */ |
| 105 | #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */ |
| 106 | #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */ |
| 107 | #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */ |
| 108 | #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */ |
| 109 | #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */ |
| 110 | #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */ |
| 111 | #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */ |
| 112 | #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */ |
| 113 | #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1) |
| 114 | #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1) |
| 115 | #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1) |
| 116 | #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1) |
| 117 | #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1) |
| 118 | #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */ |
| 119 | #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4) |
| 120 | #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4) |
| 121 | #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */ |
| 122 | #define AT_XDMAC_CC_PROT_SEC (0x0 << 5) |
| 123 | #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5) |
| 124 | #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */ |
| 125 | #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6) |
| 126 | #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6) |
| 127 | #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */ |
| 128 | #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7) |
| 129 | #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7) |
| 130 | #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */ |
| 131 | #define AT_XDMAC_CC_DWIDTH_OFFSET 11 |
| 132 | #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET) |
| 133 | #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */ |
| 134 | #define AT_XDMAC_CC_DWIDTH_BYTE 0x0 |
| 135 | #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1 |
| 136 | #define AT_XDMAC_CC_DWIDTH_WORD 0x2 |
| 137 | #define AT_XDMAC_CC_DWIDTH_DWORD 0x3 |
| 138 | #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */ |
| 139 | #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */ |
| 140 | #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */ |
| 141 | #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16) |
| 142 | #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16) |
| 143 | #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16) |
| 144 | #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16) |
| 145 | #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */ |
| 146 | #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18) |
| 147 | #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18) |
| 148 | #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18) |
| 149 | #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18) |
| 150 | #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */ |
| 151 | #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21) |
| 152 | #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21) |
| 153 | #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */ |
| 154 | #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22) |
| 155 | #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22) |
| 156 | #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */ |
| 157 | #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23) |
| 158 | #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23) |
| 159 | #define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */ |
| 160 | #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */ |
| 161 | #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */ |
| 162 | #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */ |
| 163 | |
| 164 | #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */ |
| 165 | |
| 166 | /* Microblock control members */ |
| 167 | #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */ |
| 168 | #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */ |
| 169 | #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */ |
| 170 | #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */ |
| 171 | #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */ |
| 172 | #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */ |
| 173 | #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */ |
| 174 | #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */ |
| 175 | |
| 176 | #define AT_XDMAC_MAX_CHAN 0x20 |
| 177 | |
Ludovic Desroches | 8ac82f8 | 2014-11-17 14:42:44 +0100 | [diff] [blame] | 178 | #define AT_XDMAC_DMA_BUSWIDTHS\ |
| 179 | (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\ |
| 180 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\ |
| 181 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\ |
| 182 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\ |
| 183 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) |
| 184 | |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 185 | enum atc_status { |
| 186 | AT_XDMAC_CHAN_IS_CYCLIC = 0, |
| 187 | AT_XDMAC_CHAN_IS_PAUSED, |
| 188 | }; |
| 189 | |
| 190 | /* ----- Channels ----- */ |
| 191 | struct at_xdmac_chan { |
| 192 | struct dma_chan chan; |
| 193 | void __iomem *ch_regs; |
| 194 | u32 mask; /* Channel Mask */ |
Ludovic Desroches | be83507 | 2015-01-27 16:30:31 +0100 | [diff] [blame] | 195 | u32 cfg[2]; /* Channel Configuration Register */ |
| 196 | #define AT_XDMAC_DEV_TO_MEM_CFG 0 /* Predifined dev to mem channel conf */ |
| 197 | #define AT_XDMAC_MEM_TO_DEV_CFG 1 /* Predifined mem to dev channel conf */ |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 198 | u8 perid; /* Peripheral ID */ |
| 199 | u8 perif; /* Peripheral Interface */ |
| 200 | u8 memif; /* Memory Interface */ |
| 201 | u32 per_src_addr; |
| 202 | u32 per_dst_addr; |
Ludovic Desroches | 734bb9a | 2015-01-27 16:30:30 +0100 | [diff] [blame] | 203 | u32 save_cc; |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 204 | u32 save_cim; |
| 205 | u32 save_cnda; |
| 206 | u32 save_cndc; |
| 207 | unsigned long status; |
| 208 | struct tasklet_struct tasklet; |
| 209 | |
| 210 | spinlock_t lock; |
| 211 | |
| 212 | struct list_head xfers_list; |
| 213 | struct list_head free_descs_list; |
| 214 | }; |
| 215 | |
| 216 | |
| 217 | /* ----- Controller ----- */ |
| 218 | struct at_xdmac { |
| 219 | struct dma_device dma; |
| 220 | void __iomem *regs; |
| 221 | int irq; |
| 222 | struct clk *clk; |
| 223 | u32 save_gim; |
| 224 | u32 save_gs; |
| 225 | struct dma_pool *at_xdmac_desc_pool; |
| 226 | struct at_xdmac_chan chan[0]; |
| 227 | }; |
| 228 | |
| 229 | |
| 230 | /* ----- Descriptors ----- */ |
| 231 | |
| 232 | /* Linked List Descriptor */ |
| 233 | struct at_xdmac_lld { |
| 234 | dma_addr_t mbr_nda; /* Next Descriptor Member */ |
| 235 | u32 mbr_ubc; /* Microblock Control Member */ |
| 236 | dma_addr_t mbr_sa; /* Source Address Member */ |
| 237 | dma_addr_t mbr_da; /* Destination Address Member */ |
| 238 | u32 mbr_cfg; /* Configuration Register */ |
| 239 | }; |
| 240 | |
| 241 | |
| 242 | struct at_xdmac_desc { |
| 243 | struct at_xdmac_lld lld; |
| 244 | enum dma_transfer_direction direction; |
| 245 | struct dma_async_tx_descriptor tx_dma_desc; |
| 246 | struct list_head desc_node; |
| 247 | /* Following members are only used by the first descriptor */ |
| 248 | bool active_xfer; |
| 249 | unsigned int xfer_size; |
| 250 | struct list_head descs_list; |
| 251 | struct list_head xfer_node; |
| 252 | }; |
| 253 | |
| 254 | static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) |
| 255 | { |
| 256 | return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40); |
| 257 | } |
| 258 | |
Ludovic Desroches | 6e5ae29 | 2014-11-13 11:52:39 +0100 | [diff] [blame] | 259 | #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg)) |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 260 | #define at_xdmac_write(atxdmac, reg, value) \ |
Ludovic Desroches | 6e5ae29 | 2014-11-13 11:52:39 +0100 | [diff] [blame] | 261 | writel_relaxed((value), (atxdmac)->regs + (reg)) |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 262 | |
Ludovic Desroches | 6e5ae29 | 2014-11-13 11:52:39 +0100 | [diff] [blame] | 263 | #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg)) |
| 264 | #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg)) |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 265 | |
| 266 | static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan) |
| 267 | { |
| 268 | return container_of(dchan, struct at_xdmac_chan, chan); |
| 269 | } |
| 270 | |
| 271 | static struct device *chan2dev(struct dma_chan *chan) |
| 272 | { |
| 273 | return &chan->dev->device; |
| 274 | } |
| 275 | |
| 276 | static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev) |
| 277 | { |
| 278 | return container_of(ddev, struct at_xdmac, dma); |
| 279 | } |
| 280 | |
| 281 | static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd) |
| 282 | { |
| 283 | return container_of(txd, struct at_xdmac_desc, tx_dma_desc); |
| 284 | } |
| 285 | |
| 286 | static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan) |
| 287 | { |
| 288 | return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status); |
| 289 | } |
| 290 | |
| 291 | static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan) |
| 292 | { |
| 293 | return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); |
| 294 | } |
| 295 | |
| 296 | static inline int at_xdmac_csize(u32 maxburst) |
| 297 | { |
| 298 | int csize; |
| 299 | |
| 300 | csize = ffs(maxburst) - 1; |
| 301 | if (csize > 4) |
| 302 | csize = -EINVAL; |
| 303 | |
| 304 | return csize; |
| 305 | }; |
| 306 | |
| 307 | static inline u8 at_xdmac_get_dwidth(u32 cfg) |
| 308 | { |
| 309 | return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET; |
| 310 | }; |
| 311 | |
| 312 | static unsigned int init_nr_desc_per_channel = 64; |
| 313 | module_param(init_nr_desc_per_channel, uint, 0644); |
| 314 | MODULE_PARM_DESC(init_nr_desc_per_channel, |
| 315 | "initial descriptors per channel (default: 64)"); |
| 316 | |
| 317 | |
| 318 | static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan) |
| 319 | { |
| 320 | return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask; |
| 321 | } |
| 322 | |
| 323 | static void at_xdmac_off(struct at_xdmac *atxdmac) |
| 324 | { |
| 325 | at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L); |
| 326 | |
| 327 | /* Wait that all chans are disabled. */ |
| 328 | while (at_xdmac_read(atxdmac, AT_XDMAC_GS)) |
| 329 | cpu_relax(); |
| 330 | |
| 331 | at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L); |
| 332 | } |
| 333 | |
| 334 | /* Call with lock hold. */ |
| 335 | static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, |
| 336 | struct at_xdmac_desc *first) |
| 337 | { |
| 338 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); |
| 339 | u32 reg; |
| 340 | |
| 341 | dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first); |
| 342 | |
| 343 | if (at_xdmac_chan_is_enabled(atchan)) |
| 344 | return; |
| 345 | |
| 346 | /* Set transfer as active to not try to start it again. */ |
| 347 | first->active_xfer = true; |
| 348 | |
| 349 | /* Tell xdmac where to get the first descriptor. */ |
| 350 | reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys) |
| 351 | | AT_XDMAC_CNDA_NDAIF(atchan->memif); |
| 352 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg); |
| 353 | |
| 354 | /* |
Ludovic Desroches | 6d3a7d9 | 2015-01-27 16:30:32 +0100 | [diff] [blame] | 355 | * When doing non cyclic transfer we need to use the next |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 356 | * descriptor view 2 since some fields of the configuration register |
| 357 | * depend on transfer size and src/dest addresses. |
| 358 | */ |
Ludovic Desroches | 6d3a7d9 | 2015-01-27 16:30:32 +0100 | [diff] [blame] | 359 | if (at_xdmac_chan_is_cyclic(atchan)) { |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 360 | reg = AT_XDMAC_CNDC_NDVIEW_NDV1; |
Ludovic Desroches | be83507 | 2015-01-27 16:30:31 +0100 | [diff] [blame] | 361 | at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 362 | } else { |
| 363 | /* |
| 364 | * No need to write AT_XDMAC_CC reg, it will be done when the |
| 365 | * descriptor is fecthed. |
| 366 | */ |
| 367 | reg = AT_XDMAC_CNDC_NDVIEW_NDV2; |
| 368 | } |
| 369 | |
| 370 | reg |= AT_XDMAC_CNDC_NDDUP |
| 371 | | AT_XDMAC_CNDC_NDSUP |
| 372 | | AT_XDMAC_CNDC_NDE; |
| 373 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg); |
| 374 | |
| 375 | dev_vdbg(chan2dev(&atchan->chan), |
| 376 | "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", |
| 377 | __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), |
| 378 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), |
| 379 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), |
| 380 | at_xdmac_chan_read(atchan, AT_XDMAC_CSA), |
| 381 | at_xdmac_chan_read(atchan, AT_XDMAC_CDA), |
| 382 | at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); |
| 383 | |
| 384 | at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff); |
| 385 | reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE; |
| 386 | /* |
| 387 | * There is no end of list when doing cyclic dma, we need to get |
| 388 | * an interrupt after each periods. |
| 389 | */ |
| 390 | if (at_xdmac_chan_is_cyclic(atchan)) |
| 391 | at_xdmac_chan_write(atchan, AT_XDMAC_CIE, |
| 392 | reg | AT_XDMAC_CIE_BIE); |
| 393 | else |
| 394 | at_xdmac_chan_write(atchan, AT_XDMAC_CIE, |
| 395 | reg | AT_XDMAC_CIE_LIE); |
| 396 | at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask); |
| 397 | dev_vdbg(chan2dev(&atchan->chan), |
| 398 | "%s: enable channel (0x%08x)\n", __func__, atchan->mask); |
| 399 | wmb(); |
| 400 | at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); |
| 401 | |
| 402 | dev_vdbg(chan2dev(&atchan->chan), |
| 403 | "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", |
| 404 | __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), |
| 405 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), |
| 406 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), |
| 407 | at_xdmac_chan_read(atchan, AT_XDMAC_CSA), |
| 408 | at_xdmac_chan_read(atchan, AT_XDMAC_CDA), |
| 409 | at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); |
| 410 | |
| 411 | } |
| 412 | |
| 413 | static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx) |
| 414 | { |
| 415 | struct at_xdmac_desc *desc = txd_to_at_desc(tx); |
| 416 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan); |
| 417 | dma_cookie_t cookie; |
| 418 | |
| 419 | spin_lock_bh(&atchan->lock); |
| 420 | cookie = dma_cookie_assign(tx); |
| 421 | |
| 422 | dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", |
| 423 | __func__, atchan, desc); |
| 424 | list_add_tail(&desc->xfer_node, &atchan->xfers_list); |
| 425 | if (list_is_singular(&atchan->xfers_list)) |
| 426 | at_xdmac_start_xfer(atchan, desc); |
| 427 | |
| 428 | spin_unlock_bh(&atchan->lock); |
| 429 | return cookie; |
| 430 | } |
| 431 | |
| 432 | static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan, |
| 433 | gfp_t gfp_flags) |
| 434 | { |
| 435 | struct at_xdmac_desc *desc; |
| 436 | struct at_xdmac *atxdmac = to_at_xdmac(chan->device); |
| 437 | dma_addr_t phys; |
| 438 | |
| 439 | desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys); |
| 440 | if (desc) { |
| 441 | memset(desc, 0, sizeof(*desc)); |
| 442 | INIT_LIST_HEAD(&desc->descs_list); |
| 443 | dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan); |
| 444 | desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit; |
| 445 | desc->tx_dma_desc.phys = phys; |
| 446 | } |
| 447 | |
| 448 | return desc; |
| 449 | } |
| 450 | |
| 451 | /* Call must be protected by lock. */ |
| 452 | static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan) |
| 453 | { |
| 454 | struct at_xdmac_desc *desc; |
| 455 | |
| 456 | if (list_empty(&atchan->free_descs_list)) { |
| 457 | desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT); |
| 458 | } else { |
| 459 | desc = list_first_entry(&atchan->free_descs_list, |
| 460 | struct at_xdmac_desc, desc_node); |
| 461 | list_del(&desc->desc_node); |
| 462 | desc->active_xfer = false; |
| 463 | } |
| 464 | |
| 465 | return desc; |
| 466 | } |
| 467 | |
| 468 | static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec, |
| 469 | struct of_dma *of_dma) |
| 470 | { |
| 471 | struct at_xdmac *atxdmac = of_dma->of_dma_data; |
| 472 | struct at_xdmac_chan *atchan; |
| 473 | struct dma_chan *chan; |
| 474 | struct device *dev = atxdmac->dma.dev; |
| 475 | |
| 476 | if (dma_spec->args_count != 1) { |
| 477 | dev_err(dev, "dma phandler args: bad number of args\n"); |
| 478 | return NULL; |
| 479 | } |
| 480 | |
| 481 | chan = dma_get_any_slave_channel(&atxdmac->dma); |
| 482 | if (!chan) { |
| 483 | dev_err(dev, "can't get a dma channel\n"); |
| 484 | return NULL; |
| 485 | } |
| 486 | |
| 487 | atchan = to_at_xdmac_chan(chan); |
| 488 | atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]); |
| 489 | atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]); |
| 490 | atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]); |
| 491 | dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n", |
| 492 | atchan->memif, atchan->perif, atchan->perid); |
| 493 | |
| 494 | return chan; |
| 495 | } |
| 496 | |
| 497 | static int at_xdmac_set_slave_config(struct dma_chan *chan, |
| 498 | struct dma_slave_config *sconfig) |
| 499 | { |
| 500 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 501 | u8 dwidth; |
| 502 | int csize; |
| 503 | |
| 504 | atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] = |
| 505 | AT91_XDMAC_DT_PERID(atchan->perid) |
| 506 | | AT_XDMAC_CC_DAM_INCREMENTED_AM |
| 507 | | AT_XDMAC_CC_SAM_FIXED_AM |
| 508 | | AT_XDMAC_CC_DIF(atchan->memif) |
| 509 | | AT_XDMAC_CC_SIF(atchan->perif) |
| 510 | | AT_XDMAC_CC_SWREQ_HWR_CONNECTED |
| 511 | | AT_XDMAC_CC_DSYNC_PER2MEM |
| 512 | | AT_XDMAC_CC_MBSIZE_SIXTEEN |
| 513 | | AT_XDMAC_CC_TYPE_PER_TRAN; |
| 514 | csize = at_xdmac_csize(sconfig->src_maxburst); |
| 515 | if (csize < 0) { |
| 516 | dev_err(chan2dev(chan), "invalid src maxburst value\n"); |
| 517 | return -EINVAL; |
| 518 | } |
| 519 | atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] |= AT_XDMAC_CC_CSIZE(csize); |
| 520 | dwidth = ffs(sconfig->src_addr_width) - 1; |
| 521 | atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG] |= AT_XDMAC_CC_DWIDTH(dwidth); |
| 522 | |
| 523 | |
| 524 | atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] = |
| 525 | AT91_XDMAC_DT_PERID(atchan->perid) |
| 526 | | AT_XDMAC_CC_DAM_FIXED_AM |
| 527 | | AT_XDMAC_CC_SAM_INCREMENTED_AM |
| 528 | | AT_XDMAC_CC_DIF(atchan->perif) |
| 529 | | AT_XDMAC_CC_SIF(atchan->memif) |
| 530 | | AT_XDMAC_CC_SWREQ_HWR_CONNECTED |
| 531 | | AT_XDMAC_CC_DSYNC_MEM2PER |
| 532 | | AT_XDMAC_CC_MBSIZE_SIXTEEN |
| 533 | | AT_XDMAC_CC_TYPE_PER_TRAN; |
| 534 | csize = at_xdmac_csize(sconfig->dst_maxburst); |
| 535 | if (csize < 0) { |
| 536 | dev_err(chan2dev(chan), "invalid src maxburst value\n"); |
| 537 | return -EINVAL; |
| 538 | } |
| 539 | atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] |= AT_XDMAC_CC_CSIZE(csize); |
| 540 | dwidth = ffs(sconfig->dst_addr_width) - 1; |
| 541 | atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG] |= AT_XDMAC_CC_DWIDTH(dwidth); |
| 542 | |
| 543 | /* Src and dst addr are needed to configure the link list descriptor. */ |
| 544 | atchan->per_src_addr = sconfig->src_addr; |
| 545 | atchan->per_dst_addr = sconfig->dst_addr; |
| 546 | |
| 547 | dev_dbg(chan2dev(chan), |
| 548 | "%s: cfg[dev2mem]=0x%08x, cfg[mem2dev]=0x%08x, per_src_addr=0x%08x, per_dst_addr=0x%08x\n", |
| 549 | __func__, atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG], |
| 550 | atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG], |
| 551 | atchan->per_src_addr, atchan->per_dst_addr); |
| 552 | |
| 553 | return 0; |
| 554 | } |
| 555 | |
| 556 | static struct dma_async_tx_descriptor * |
| 557 | at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, |
| 558 | unsigned int sg_len, enum dma_transfer_direction direction, |
| 559 | unsigned long flags, void *context) |
| 560 | { |
| 561 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 562 | struct at_xdmac_desc *first = NULL, *prev = NULL; |
| 563 | struct scatterlist *sg; |
| 564 | int i; |
Cyrille Pitchen | 5781927 | 2014-11-13 11:52:42 +0100 | [diff] [blame] | 565 | unsigned int xfer_size = 0; |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 566 | |
| 567 | if (!sgl) |
| 568 | return NULL; |
| 569 | |
| 570 | if (!is_slave_direction(direction)) { |
| 571 | dev_err(chan2dev(chan), "invalid DMA direction\n"); |
| 572 | return NULL; |
| 573 | } |
| 574 | |
| 575 | dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n", |
| 576 | __func__, sg_len, |
| 577 | direction == DMA_MEM_TO_DEV ? "to device" : "from device", |
| 578 | flags); |
| 579 | |
| 580 | /* Protect dma_sconfig field that can be modified by set_slave_conf. */ |
| 581 | spin_lock_bh(&atchan->lock); |
| 582 | |
| 583 | /* Prepare descriptors. */ |
| 584 | for_each_sg(sgl, sg, sg_len, i) { |
| 585 | struct at_xdmac_desc *desc = NULL; |
Ludovic Desroches | 6d3a7d9 | 2015-01-27 16:30:32 +0100 | [diff] [blame] | 586 | u32 len, mem, dwidth, fixed_dwidth; |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 587 | |
| 588 | len = sg_dma_len(sg); |
| 589 | mem = sg_dma_address(sg); |
| 590 | if (unlikely(!len)) { |
| 591 | dev_err(chan2dev(chan), "sg data length is zero\n"); |
| 592 | spin_unlock_bh(&atchan->lock); |
| 593 | return NULL; |
| 594 | } |
| 595 | dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n", |
| 596 | __func__, i, len, mem); |
| 597 | |
| 598 | desc = at_xdmac_get_desc(atchan); |
| 599 | if (!desc) { |
| 600 | dev_err(chan2dev(chan), "can't get descriptor\n"); |
| 601 | if (first) |
| 602 | list_splice_init(&first->descs_list, &atchan->free_descs_list); |
| 603 | spin_unlock_bh(&atchan->lock); |
| 604 | return NULL; |
| 605 | } |
| 606 | |
| 607 | /* Linked list descriptor setup. */ |
| 608 | if (direction == DMA_DEV_TO_MEM) { |
| 609 | desc->lld.mbr_sa = atchan->per_src_addr; |
| 610 | desc->lld.mbr_da = mem; |
Ludovic Desroches | be83507 | 2015-01-27 16:30:31 +0100 | [diff] [blame] | 611 | desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG]; |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 612 | } else { |
| 613 | desc->lld.mbr_sa = mem; |
| 614 | desc->lld.mbr_da = atchan->per_dst_addr; |
Ludovic Desroches | be83507 | 2015-01-27 16:30:31 +0100 | [diff] [blame] | 615 | desc->lld.mbr_cfg = atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG]; |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 616 | } |
Ludovic Desroches | 6d3a7d9 | 2015-01-27 16:30:32 +0100 | [diff] [blame] | 617 | dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg); |
| 618 | fixed_dwidth = IS_ALIGNED(len, 1 << dwidth) |
| 619 | ? at_xdmac_get_dwidth(desc->lld.mbr_cfg) |
| 620 | : AT_XDMAC_CC_DWIDTH_BYTE; |
| 621 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */ |
Ludovic Desroches | be83507 | 2015-01-27 16:30:31 +0100 | [diff] [blame] | 622 | | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */ |
| 623 | | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */ |
| 624 | | (i == sg_len - 1 ? 0 : AT_XDMAC_MBR_UBC_NDE) /* descriptor fetch */ |
Ludovic Desroches | 6d3a7d9 | 2015-01-27 16:30:32 +0100 | [diff] [blame] | 625 | | (len >> fixed_dwidth); /* microblock length */ |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 626 | dev_dbg(chan2dev(chan), |
Vinod Koul | 82e2424 | 2014-11-06 18:02:52 +0530 | [diff] [blame] | 627 | "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", |
| 628 | __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 629 | |
| 630 | /* Chain lld. */ |
| 631 | if (prev) { |
| 632 | prev->lld.mbr_nda = desc->tx_dma_desc.phys; |
| 633 | dev_dbg(chan2dev(chan), |
Vinod Koul | 82e2424 | 2014-11-06 18:02:52 +0530 | [diff] [blame] | 634 | "%s: chain lld: prev=0x%p, mbr_nda=%pad\n", |
| 635 | __func__, prev, &prev->lld.mbr_nda); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 636 | } |
| 637 | |
| 638 | prev = desc; |
| 639 | if (!first) |
| 640 | first = desc; |
| 641 | |
| 642 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", |
| 643 | __func__, desc, first); |
| 644 | list_add_tail(&desc->desc_node, &first->descs_list); |
Cyrille Pitchen | 5781927 | 2014-11-13 11:52:42 +0100 | [diff] [blame] | 645 | xfer_size += len; |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 646 | } |
| 647 | |
| 648 | spin_unlock_bh(&atchan->lock); |
| 649 | |
| 650 | first->tx_dma_desc.flags = flags; |
Cyrille Pitchen | 5781927 | 2014-11-13 11:52:42 +0100 | [diff] [blame] | 651 | first->xfer_size = xfer_size; |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 652 | first->direction = direction; |
| 653 | |
| 654 | return &first->tx_dma_desc; |
| 655 | } |
| 656 | |
| 657 | static struct dma_async_tx_descriptor * |
| 658 | at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, |
| 659 | size_t buf_len, size_t period_len, |
| 660 | enum dma_transfer_direction direction, |
| 661 | unsigned long flags) |
| 662 | { |
| 663 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 664 | struct at_xdmac_desc *first = NULL, *prev = NULL; |
| 665 | unsigned int periods = buf_len / period_len; |
| 666 | int i; |
| 667 | u32 cfg; |
| 668 | |
Vinod Koul | 82e2424 | 2014-11-06 18:02:52 +0530 | [diff] [blame] | 669 | dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n", |
| 670 | __func__, &buf_addr, buf_len, period_len, |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 671 | direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags); |
| 672 | |
| 673 | if (!is_slave_direction(direction)) { |
| 674 | dev_err(chan2dev(chan), "invalid DMA direction\n"); |
| 675 | return NULL; |
| 676 | } |
| 677 | |
| 678 | if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) { |
| 679 | dev_err(chan2dev(chan), "channel currently used\n"); |
| 680 | return NULL; |
| 681 | } |
| 682 | |
| 683 | for (i = 0; i < periods; i++) { |
| 684 | struct at_xdmac_desc *desc = NULL; |
| 685 | |
| 686 | spin_lock_bh(&atchan->lock); |
| 687 | desc = at_xdmac_get_desc(atchan); |
| 688 | if (!desc) { |
| 689 | dev_err(chan2dev(chan), "can't get descriptor\n"); |
| 690 | if (first) |
| 691 | list_splice_init(&first->descs_list, &atchan->free_descs_list); |
| 692 | spin_unlock_bh(&atchan->lock); |
| 693 | return NULL; |
| 694 | } |
| 695 | spin_unlock_bh(&atchan->lock); |
| 696 | dev_dbg(chan2dev(chan), |
Vinod Koul | 82e2424 | 2014-11-06 18:02:52 +0530 | [diff] [blame] | 697 | "%s: desc=0x%p, tx_dma_desc.phys=%pad\n", |
| 698 | __func__, desc, &desc->tx_dma_desc.phys); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 699 | |
| 700 | if (direction == DMA_DEV_TO_MEM) { |
| 701 | desc->lld.mbr_sa = atchan->per_src_addr; |
| 702 | desc->lld.mbr_da = buf_addr + i * period_len; |
| 703 | cfg = atchan->cfg[AT_XDMAC_DEV_TO_MEM_CFG]; |
| 704 | } else { |
| 705 | desc->lld.mbr_sa = buf_addr + i * period_len; |
| 706 | desc->lld.mbr_da = atchan->per_dst_addr; |
| 707 | cfg = atchan->cfg[AT_XDMAC_MEM_TO_DEV_CFG]; |
kbuild test robot | 5ac7d58 | 2014-11-06 17:28:08 +0800 | [diff] [blame] | 708 | } |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 709 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1 |
| 710 | | AT_XDMAC_MBR_UBC_NDEN |
| 711 | | AT_XDMAC_MBR_UBC_NSEN |
| 712 | | AT_XDMAC_MBR_UBC_NDE |
| 713 | | period_len >> at_xdmac_get_dwidth(cfg); |
| 714 | |
| 715 | dev_dbg(chan2dev(chan), |
Vinod Koul | 82e2424 | 2014-11-06 18:02:52 +0530 | [diff] [blame] | 716 | "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", |
| 717 | __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 718 | |
| 719 | /* Chain lld. */ |
| 720 | if (prev) { |
| 721 | prev->lld.mbr_nda = desc->tx_dma_desc.phys; |
| 722 | dev_dbg(chan2dev(chan), |
Vinod Koul | 82e2424 | 2014-11-06 18:02:52 +0530 | [diff] [blame] | 723 | "%s: chain lld: prev=0x%p, mbr_nda=%pad\n", |
| 724 | __func__, prev, &prev->lld.mbr_nda); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 725 | } |
| 726 | |
| 727 | prev = desc; |
| 728 | if (!first) |
| 729 | first = desc; |
| 730 | |
| 731 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", |
| 732 | __func__, desc, first); |
| 733 | list_add_tail(&desc->desc_node, &first->descs_list); |
| 734 | } |
| 735 | |
| 736 | prev->lld.mbr_nda = first->tx_dma_desc.phys; |
| 737 | dev_dbg(chan2dev(chan), |
Vinod Koul | 82e2424 | 2014-11-06 18:02:52 +0530 | [diff] [blame] | 738 | "%s: chain lld: prev=0x%p, mbr_nda=%pad\n", |
| 739 | __func__, prev, &prev->lld.mbr_nda); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 740 | first->tx_dma_desc.flags = flags; |
| 741 | first->xfer_size = buf_len; |
| 742 | first->direction = direction; |
| 743 | |
| 744 | return &first->tx_dma_desc; |
| 745 | } |
| 746 | |
| 747 | static struct dma_async_tx_descriptor * |
| 748 | at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 749 | size_t len, unsigned long flags) |
| 750 | { |
| 751 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 752 | struct at_xdmac_desc *first = NULL, *prev = NULL; |
| 753 | size_t remaining_size = len, xfer_size = 0, ublen; |
| 754 | dma_addr_t src_addr = src, dst_addr = dest; |
| 755 | u32 dwidth; |
| 756 | /* |
| 757 | * WARNING: We don't know the direction, it involves we can't |
| 758 | * dynamically set the source and dest interface so we have to use the |
| 759 | * same one. Only interface 0 allows EBI access. Hopefully we can |
| 760 | * access DDR through both ports (at least on SAMA5D4x), so we can use |
| 761 | * the same interface for source and dest, that solves the fact we |
| 762 | * don't know the direction. |
| 763 | */ |
| 764 | u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM |
| 765 | | AT_XDMAC_CC_SAM_INCREMENTED_AM |
| 766 | | AT_XDMAC_CC_DIF(0) |
| 767 | | AT_XDMAC_CC_SIF(0) |
| 768 | | AT_XDMAC_CC_MBSIZE_SIXTEEN |
| 769 | | AT_XDMAC_CC_TYPE_MEM_TRAN; |
| 770 | |
Vinod Koul | 82e2424 | 2014-11-06 18:02:52 +0530 | [diff] [blame] | 771 | dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n", |
| 772 | __func__, &src, &dest, len, flags); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 773 | |
| 774 | if (unlikely(!len)) |
| 775 | return NULL; |
| 776 | |
| 777 | /* |
| 778 | * Check address alignment to select the greater data width we can use. |
| 779 | * Some XDMAC implementations don't provide dword transfer, in this |
| 780 | * case selecting dword has the same behavior as selecting word transfers. |
| 781 | */ |
| 782 | if (!((src_addr | dst_addr) & 7)) { |
| 783 | dwidth = AT_XDMAC_CC_DWIDTH_DWORD; |
| 784 | dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__); |
| 785 | } else if (!((src_addr | dst_addr) & 3)) { |
| 786 | dwidth = AT_XDMAC_CC_DWIDTH_WORD; |
| 787 | dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__); |
| 788 | } else if (!((src_addr | dst_addr) & 1)) { |
| 789 | dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD; |
| 790 | dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__); |
| 791 | } else { |
| 792 | dwidth = AT_XDMAC_CC_DWIDTH_BYTE; |
| 793 | dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__); |
| 794 | } |
| 795 | |
| 796 | /* Prepare descriptors. */ |
| 797 | while (remaining_size) { |
| 798 | struct at_xdmac_desc *desc = NULL; |
| 799 | |
Vinod Koul | c66ec04 | 2014-11-06 17:37:48 +0530 | [diff] [blame] | 800 | dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 801 | |
| 802 | spin_lock_bh(&atchan->lock); |
| 803 | desc = at_xdmac_get_desc(atchan); |
| 804 | spin_unlock_bh(&atchan->lock); |
| 805 | if (!desc) { |
| 806 | dev_err(chan2dev(chan), "can't get descriptor\n"); |
| 807 | if (first) |
| 808 | list_splice_init(&first->descs_list, &atchan->free_descs_list); |
| 809 | return NULL; |
| 810 | } |
| 811 | |
| 812 | /* Update src and dest addresses. */ |
| 813 | src_addr += xfer_size; |
| 814 | dst_addr += xfer_size; |
| 815 | |
| 816 | if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth) |
| 817 | xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth; |
| 818 | else |
| 819 | xfer_size = remaining_size; |
| 820 | |
Vinod Koul | c66ec04 | 2014-11-06 17:37:48 +0530 | [diff] [blame] | 821 | dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 822 | |
| 823 | /* Check remaining length and change data width if needed. */ |
| 824 | if (!((src_addr | dst_addr | xfer_size) & 7)) { |
| 825 | dwidth = AT_XDMAC_CC_DWIDTH_DWORD; |
| 826 | dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__); |
| 827 | } else if (!((src_addr | dst_addr | xfer_size) & 3)) { |
| 828 | dwidth = AT_XDMAC_CC_DWIDTH_WORD; |
| 829 | dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__); |
| 830 | } else if (!((src_addr | dst_addr | xfer_size) & 1)) { |
| 831 | dwidth = AT_XDMAC_CC_DWIDTH_HALFWORD; |
| 832 | dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__); |
| 833 | } else if ((src_addr | dst_addr | xfer_size) & 1) { |
| 834 | dwidth = AT_XDMAC_CC_DWIDTH_BYTE; |
| 835 | dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__); |
| 836 | } |
| 837 | chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth); |
| 838 | |
| 839 | ublen = xfer_size >> dwidth; |
| 840 | remaining_size -= xfer_size; |
| 841 | |
| 842 | desc->lld.mbr_sa = src_addr; |
| 843 | desc->lld.mbr_da = dst_addr; |
| 844 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 |
| 845 | | AT_XDMAC_MBR_UBC_NDEN |
| 846 | | AT_XDMAC_MBR_UBC_NSEN |
| 847 | | (remaining_size ? AT_XDMAC_MBR_UBC_NDE : 0) |
| 848 | | ublen; |
| 849 | desc->lld.mbr_cfg = chan_cc; |
| 850 | |
| 851 | dev_dbg(chan2dev(chan), |
Vinod Koul | 82e2424 | 2014-11-06 18:02:52 +0530 | [diff] [blame] | 852 | "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", |
| 853 | __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 854 | |
| 855 | /* Chain lld. */ |
| 856 | if (prev) { |
| 857 | prev->lld.mbr_nda = desc->tx_dma_desc.phys; |
| 858 | dev_dbg(chan2dev(chan), |
| 859 | "%s: chain lld: prev=0x%p, mbr_nda=0x%08x\n", |
| 860 | __func__, prev, prev->lld.mbr_nda); |
| 861 | } |
| 862 | |
| 863 | prev = desc; |
| 864 | if (!first) |
| 865 | first = desc; |
| 866 | |
| 867 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", |
| 868 | __func__, desc, first); |
| 869 | list_add_tail(&desc->desc_node, &first->descs_list); |
| 870 | } |
| 871 | |
| 872 | first->tx_dma_desc.flags = flags; |
| 873 | first->xfer_size = len; |
| 874 | |
| 875 | return &first->tx_dma_desc; |
| 876 | } |
| 877 | |
| 878 | static enum dma_status |
| 879 | at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie, |
| 880 | struct dma_tx_state *txstate) |
| 881 | { |
| 882 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 883 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); |
| 884 | struct at_xdmac_desc *desc, *_desc; |
| 885 | struct list_head *descs_list; |
| 886 | enum dma_status ret; |
| 887 | int residue; |
Cyrille Pitchen | 4e09782 | 2014-11-13 11:52:41 +0100 | [diff] [blame] | 888 | u32 cur_nda, mask, value; |
Ludovic Desroches | be83507 | 2015-01-27 16:30:31 +0100 | [diff] [blame] | 889 | u8 dwidth = 0; |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 890 | |
| 891 | ret = dma_cookie_status(chan, cookie, txstate); |
| 892 | if (ret == DMA_COMPLETE) |
| 893 | return ret; |
| 894 | |
| 895 | if (!txstate) |
| 896 | return ret; |
| 897 | |
| 898 | spin_lock_bh(&atchan->lock); |
| 899 | |
| 900 | desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); |
| 901 | |
| 902 | /* |
| 903 | * If the transfer has not been started yet, don't need to compute the |
| 904 | * residue, it's the transfer length. |
| 905 | */ |
| 906 | if (!desc->active_xfer) { |
| 907 | dma_set_residue(txstate, desc->xfer_size); |
Ludovic Desroches | 8780983 | 2014-11-13 11:52:43 +0100 | [diff] [blame] | 908 | spin_unlock_bh(&atchan->lock); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 909 | return ret; |
| 910 | } |
| 911 | |
| 912 | residue = desc->xfer_size; |
Cyrille Pitchen | 4e09782 | 2014-11-13 11:52:41 +0100 | [diff] [blame] | 913 | /* |
| 914 | * Flush FIFO: only relevant when the transfer is source peripheral |
| 915 | * synchronized. |
| 916 | */ |
| 917 | mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC; |
| 918 | value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM; |
Ludovic Desroches | be83507 | 2015-01-27 16:30:31 +0100 | [diff] [blame] | 919 | if ((desc->lld.mbr_cfg & mask) == value) { |
Cyrille Pitchen | 4e09782 | 2014-11-13 11:52:41 +0100 | [diff] [blame] | 920 | at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); |
| 921 | while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) |
| 922 | cpu_relax(); |
| 923 | } |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 924 | |
| 925 | cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc; |
| 926 | /* |
| 927 | * Remove size of all microblocks already transferred and the current |
| 928 | * one. Then add the remaining size to transfer of the current |
| 929 | * microblock. |
| 930 | */ |
| 931 | descs_list = &desc->descs_list; |
| 932 | list_for_each_entry_safe(desc, _desc, descs_list, desc_node) { |
Ludovic Desroches | be83507 | 2015-01-27 16:30:31 +0100 | [diff] [blame] | 933 | dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 934 | residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth; |
| 935 | if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda) |
| 936 | break; |
| 937 | } |
| 938 | residue += at_xdmac_chan_read(atchan, AT_XDMAC_CUBC) << dwidth; |
| 939 | |
| 940 | spin_unlock_bh(&atchan->lock); |
| 941 | |
| 942 | dma_set_residue(txstate, residue); |
| 943 | |
| 944 | dev_dbg(chan2dev(chan), |
Vinod Koul | 82e2424 | 2014-11-06 18:02:52 +0530 | [diff] [blame] | 945 | "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n", |
| 946 | __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 947 | |
| 948 | return ret; |
| 949 | } |
| 950 | |
| 951 | /* Call must be protected by lock. */ |
| 952 | static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan, |
| 953 | struct at_xdmac_desc *desc) |
| 954 | { |
| 955 | dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); |
| 956 | |
| 957 | /* |
| 958 | * Remove the transfer from the transfer list then move the transfer |
| 959 | * descriptors into the free descriptors list. |
| 960 | */ |
| 961 | list_del(&desc->xfer_node); |
| 962 | list_splice_init(&desc->descs_list, &atchan->free_descs_list); |
| 963 | } |
| 964 | |
| 965 | static void at_xdmac_advance_work(struct at_xdmac_chan *atchan) |
| 966 | { |
| 967 | struct at_xdmac_desc *desc; |
| 968 | |
| 969 | spin_lock_bh(&atchan->lock); |
| 970 | |
| 971 | /* |
| 972 | * If channel is enabled, do nothing, advance_work will be triggered |
| 973 | * after the interruption. |
| 974 | */ |
| 975 | if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) { |
| 976 | desc = list_first_entry(&atchan->xfers_list, |
| 977 | struct at_xdmac_desc, |
| 978 | xfer_node); |
| 979 | dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); |
| 980 | if (!desc->active_xfer) |
| 981 | at_xdmac_start_xfer(atchan, desc); |
| 982 | } |
| 983 | |
| 984 | spin_unlock_bh(&atchan->lock); |
| 985 | } |
| 986 | |
| 987 | static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan) |
| 988 | { |
| 989 | struct at_xdmac_desc *desc; |
| 990 | struct dma_async_tx_descriptor *txd; |
| 991 | |
| 992 | desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); |
| 993 | txd = &desc->tx_dma_desc; |
| 994 | |
| 995 | if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT)) |
| 996 | txd->callback(txd->callback_param); |
| 997 | } |
| 998 | |
| 999 | static void at_xdmac_tasklet(unsigned long data) |
| 1000 | { |
| 1001 | struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data; |
| 1002 | struct at_xdmac_desc *desc; |
| 1003 | u32 error_mask; |
| 1004 | |
| 1005 | dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n", |
| 1006 | __func__, atchan->status); |
| 1007 | |
| 1008 | error_mask = AT_XDMAC_CIS_RBEIS |
| 1009 | | AT_XDMAC_CIS_WBEIS |
| 1010 | | AT_XDMAC_CIS_ROIS; |
| 1011 | |
| 1012 | if (at_xdmac_chan_is_cyclic(atchan)) { |
| 1013 | at_xdmac_handle_cyclic(atchan); |
| 1014 | } else if ((atchan->status & AT_XDMAC_CIS_LIS) |
| 1015 | || (atchan->status & error_mask)) { |
| 1016 | struct dma_async_tx_descriptor *txd; |
| 1017 | |
| 1018 | if (atchan->status & AT_XDMAC_CIS_RBEIS) |
| 1019 | dev_err(chan2dev(&atchan->chan), "read bus error!!!"); |
| 1020 | if (atchan->status & AT_XDMAC_CIS_WBEIS) |
| 1021 | dev_err(chan2dev(&atchan->chan), "write bus error!!!"); |
| 1022 | if (atchan->status & AT_XDMAC_CIS_ROIS) |
| 1023 | dev_err(chan2dev(&atchan->chan), "request overflow error!!!"); |
| 1024 | |
| 1025 | spin_lock_bh(&atchan->lock); |
| 1026 | desc = list_first_entry(&atchan->xfers_list, |
| 1027 | struct at_xdmac_desc, |
| 1028 | xfer_node); |
| 1029 | dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); |
| 1030 | BUG_ON(!desc->active_xfer); |
| 1031 | |
| 1032 | txd = &desc->tx_dma_desc; |
| 1033 | |
| 1034 | at_xdmac_remove_xfer(atchan, desc); |
| 1035 | spin_unlock_bh(&atchan->lock); |
| 1036 | |
| 1037 | if (!at_xdmac_chan_is_cyclic(atchan)) { |
| 1038 | dma_cookie_complete(txd); |
| 1039 | if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT)) |
| 1040 | txd->callback(txd->callback_param); |
| 1041 | } |
| 1042 | |
| 1043 | dma_run_dependencies(txd); |
| 1044 | |
| 1045 | at_xdmac_advance_work(atchan); |
| 1046 | } |
| 1047 | } |
| 1048 | |
| 1049 | static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id) |
| 1050 | { |
| 1051 | struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id; |
| 1052 | struct at_xdmac_chan *atchan; |
| 1053 | u32 imr, status, pending; |
| 1054 | u32 chan_imr, chan_status; |
| 1055 | int i, ret = IRQ_NONE; |
| 1056 | |
| 1057 | do { |
| 1058 | imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM); |
| 1059 | status = at_xdmac_read(atxdmac, AT_XDMAC_GIS); |
| 1060 | pending = status & imr; |
| 1061 | |
| 1062 | dev_vdbg(atxdmac->dma.dev, |
| 1063 | "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n", |
| 1064 | __func__, status, imr, pending); |
| 1065 | |
| 1066 | if (!pending) |
| 1067 | break; |
| 1068 | |
| 1069 | /* We have to find which channel has generated the interrupt. */ |
| 1070 | for (i = 0; i < atxdmac->dma.chancnt; i++) { |
| 1071 | if (!((1 << i) & pending)) |
| 1072 | continue; |
| 1073 | |
| 1074 | atchan = &atxdmac->chan[i]; |
| 1075 | chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM); |
| 1076 | chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS); |
| 1077 | atchan->status = chan_status & chan_imr; |
| 1078 | dev_vdbg(atxdmac->dma.dev, |
| 1079 | "%s: chan%d: imr=0x%x, status=0x%x\n", |
| 1080 | __func__, i, chan_imr, chan_status); |
| 1081 | dev_vdbg(chan2dev(&atchan->chan), |
| 1082 | "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", |
| 1083 | __func__, |
| 1084 | at_xdmac_chan_read(atchan, AT_XDMAC_CC), |
| 1085 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), |
| 1086 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), |
| 1087 | at_xdmac_chan_read(atchan, AT_XDMAC_CSA), |
| 1088 | at_xdmac_chan_read(atchan, AT_XDMAC_CDA), |
| 1089 | at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); |
| 1090 | |
| 1091 | if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS)) |
| 1092 | at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); |
| 1093 | |
| 1094 | tasklet_schedule(&atchan->tasklet); |
| 1095 | ret = IRQ_HANDLED; |
| 1096 | } |
| 1097 | |
| 1098 | } while (pending); |
| 1099 | |
| 1100 | return ret; |
| 1101 | } |
| 1102 | |
| 1103 | static void at_xdmac_issue_pending(struct dma_chan *chan) |
| 1104 | { |
| 1105 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 1106 | |
| 1107 | dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__); |
| 1108 | |
| 1109 | if (!at_xdmac_chan_is_cyclic(atchan)) |
| 1110 | at_xdmac_advance_work(atchan); |
| 1111 | |
| 1112 | return; |
| 1113 | } |
| 1114 | |
Ludovic Desroches | 3d13887 | 2014-11-17 14:42:07 +0100 | [diff] [blame] | 1115 | static int at_xdmac_device_config(struct dma_chan *chan, |
| 1116 | struct dma_slave_config *config) |
| 1117 | { |
| 1118 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 1119 | int ret; |
| 1120 | |
| 1121 | dev_dbg(chan2dev(chan), "%s\n", __func__); |
| 1122 | |
| 1123 | spin_lock_bh(&atchan->lock); |
| 1124 | ret = at_xdmac_set_slave_config(chan, config); |
| 1125 | spin_unlock_bh(&atchan->lock); |
| 1126 | |
| 1127 | return ret; |
| 1128 | } |
| 1129 | |
| 1130 | static int at_xdmac_device_pause(struct dma_chan *chan) |
| 1131 | { |
| 1132 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 1133 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); |
| 1134 | |
| 1135 | dev_dbg(chan2dev(chan), "%s\n", __func__); |
| 1136 | |
Cyrille Pitchen | cbb85e6 | 2015-01-27 16:30:29 +0100 | [diff] [blame] | 1137 | if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status)) |
| 1138 | return 0; |
| 1139 | |
Ludovic Desroches | 3d13887 | 2014-11-17 14:42:07 +0100 | [diff] [blame] | 1140 | spin_lock_bh(&atchan->lock); |
| 1141 | at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask); |
Cyrille Pitchen | cbb85e6 | 2015-01-27 16:30:29 +0100 | [diff] [blame] | 1142 | while (at_xdmac_chan_read(atchan, AT_XDMAC_CC) |
| 1143 | & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP)) |
| 1144 | cpu_relax(); |
Ludovic Desroches | 3d13887 | 2014-11-17 14:42:07 +0100 | [diff] [blame] | 1145 | spin_unlock_bh(&atchan->lock); |
| 1146 | |
| 1147 | return 0; |
| 1148 | } |
| 1149 | |
| 1150 | static int at_xdmac_device_resume(struct dma_chan *chan) |
| 1151 | { |
| 1152 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 1153 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); |
| 1154 | |
| 1155 | dev_dbg(chan2dev(chan), "%s\n", __func__); |
| 1156 | |
| 1157 | spin_lock_bh(&atchan->lock); |
| 1158 | if (!at_xdmac_chan_is_paused(atchan)) |
| 1159 | return 0; |
| 1160 | |
| 1161 | at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask); |
| 1162 | clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); |
| 1163 | spin_unlock_bh(&atchan->lock); |
| 1164 | |
| 1165 | return 0; |
| 1166 | } |
| 1167 | |
| 1168 | static int at_xdmac_device_terminate_all(struct dma_chan *chan) |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1169 | { |
| 1170 | struct at_xdmac_desc *desc, *_desc; |
| 1171 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 1172 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1173 | |
Ludovic Desroches | 3d13887 | 2014-11-17 14:42:07 +0100 | [diff] [blame] | 1174 | dev_dbg(chan2dev(chan), "%s\n", __func__); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1175 | |
| 1176 | spin_lock_bh(&atchan->lock); |
Ludovic Desroches | 3d13887 | 2014-11-17 14:42:07 +0100 | [diff] [blame] | 1177 | at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); |
| 1178 | while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask) |
| 1179 | cpu_relax(); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1180 | |
Ludovic Desroches | 3d13887 | 2014-11-17 14:42:07 +0100 | [diff] [blame] | 1181 | /* Cancel all pending transfers. */ |
| 1182 | list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node) |
| 1183 | at_xdmac_remove_xfer(atchan, desc); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1184 | |
Ludovic Desroches | 3d13887 | 2014-11-17 14:42:07 +0100 | [diff] [blame] | 1185 | clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1186 | spin_unlock_bh(&atchan->lock); |
| 1187 | |
Ludovic Desroches | 3d13887 | 2014-11-17 14:42:07 +0100 | [diff] [blame] | 1188 | return 0; |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1189 | } |
| 1190 | |
| 1191 | static int at_xdmac_alloc_chan_resources(struct dma_chan *chan) |
| 1192 | { |
| 1193 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 1194 | struct at_xdmac_desc *desc; |
| 1195 | int i; |
| 1196 | |
| 1197 | spin_lock_bh(&atchan->lock); |
| 1198 | |
| 1199 | if (at_xdmac_chan_is_enabled(atchan)) { |
| 1200 | dev_err(chan2dev(chan), |
| 1201 | "can't allocate channel resources (channel enabled)\n"); |
| 1202 | i = -EIO; |
| 1203 | goto spin_unlock; |
| 1204 | } |
| 1205 | |
| 1206 | if (!list_empty(&atchan->free_descs_list)) { |
| 1207 | dev_err(chan2dev(chan), |
| 1208 | "can't allocate channel resources (channel not free from a previous use)\n"); |
| 1209 | i = -EIO; |
| 1210 | goto spin_unlock; |
| 1211 | } |
| 1212 | |
| 1213 | for (i = 0; i < init_nr_desc_per_channel; i++) { |
| 1214 | desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC); |
| 1215 | if (!desc) { |
| 1216 | dev_warn(chan2dev(chan), |
| 1217 | "only %d descriptors have been allocated\n", i); |
| 1218 | break; |
| 1219 | } |
| 1220 | list_add_tail(&desc->desc_node, &atchan->free_descs_list); |
| 1221 | } |
| 1222 | |
| 1223 | dma_cookie_init(chan); |
| 1224 | |
| 1225 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); |
| 1226 | |
| 1227 | spin_unlock: |
| 1228 | spin_unlock_bh(&atchan->lock); |
| 1229 | return i; |
| 1230 | } |
| 1231 | |
| 1232 | static void at_xdmac_free_chan_resources(struct dma_chan *chan) |
| 1233 | { |
| 1234 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 1235 | struct at_xdmac *atxdmac = to_at_xdmac(chan->device); |
| 1236 | struct at_xdmac_desc *desc, *_desc; |
| 1237 | |
| 1238 | list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) { |
| 1239 | dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc); |
| 1240 | list_del(&desc->desc_node); |
| 1241 | dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys); |
| 1242 | } |
| 1243 | |
| 1244 | return; |
| 1245 | } |
| 1246 | |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1247 | #ifdef CONFIG_PM |
| 1248 | static int atmel_xdmac_prepare(struct device *dev) |
| 1249 | { |
| 1250 | struct platform_device *pdev = to_platform_device(dev); |
| 1251 | struct at_xdmac *atxdmac = platform_get_drvdata(pdev); |
| 1252 | struct dma_chan *chan, *_chan; |
| 1253 | |
| 1254 | list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { |
| 1255 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 1256 | |
| 1257 | /* Wait for transfer completion, except in cyclic case. */ |
| 1258 | if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan)) |
| 1259 | return -EAGAIN; |
| 1260 | } |
| 1261 | return 0; |
| 1262 | } |
| 1263 | #else |
| 1264 | # define atmel_xdmac_prepare NULL |
| 1265 | #endif |
| 1266 | |
| 1267 | #ifdef CONFIG_PM_SLEEP |
| 1268 | static int atmel_xdmac_suspend(struct device *dev) |
| 1269 | { |
| 1270 | struct platform_device *pdev = to_platform_device(dev); |
| 1271 | struct at_xdmac *atxdmac = platform_get_drvdata(pdev); |
| 1272 | struct dma_chan *chan, *_chan; |
| 1273 | |
| 1274 | list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { |
| 1275 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
| 1276 | |
Ludovic Desroches | 734bb9a | 2015-01-27 16:30:30 +0100 | [diff] [blame] | 1277 | atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1278 | if (at_xdmac_chan_is_cyclic(atchan)) { |
| 1279 | if (!at_xdmac_chan_is_paused(atchan)) |
Ludovic Desroches | 3d13887 | 2014-11-17 14:42:07 +0100 | [diff] [blame] | 1280 | at_xdmac_device_pause(chan); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1281 | atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM); |
| 1282 | atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA); |
| 1283 | atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC); |
| 1284 | } |
| 1285 | } |
| 1286 | atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM); |
| 1287 | |
| 1288 | at_xdmac_off(atxdmac); |
| 1289 | clk_disable_unprepare(atxdmac->clk); |
| 1290 | return 0; |
| 1291 | } |
| 1292 | |
| 1293 | static int atmel_xdmac_resume(struct device *dev) |
| 1294 | { |
| 1295 | struct platform_device *pdev = to_platform_device(dev); |
| 1296 | struct at_xdmac *atxdmac = platform_get_drvdata(pdev); |
| 1297 | struct at_xdmac_chan *atchan; |
| 1298 | struct dma_chan *chan, *_chan; |
| 1299 | int i; |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1300 | |
| 1301 | clk_prepare_enable(atxdmac->clk); |
| 1302 | |
| 1303 | /* Clear pending interrupts. */ |
| 1304 | for (i = 0; i < atxdmac->dma.chancnt; i++) { |
| 1305 | atchan = &atxdmac->chan[i]; |
| 1306 | while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS)) |
| 1307 | cpu_relax(); |
| 1308 | } |
| 1309 | |
| 1310 | at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim); |
| 1311 | at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs); |
| 1312 | list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { |
| 1313 | atchan = to_at_xdmac_chan(chan); |
Ludovic Desroches | 734bb9a | 2015-01-27 16:30:30 +0100 | [diff] [blame] | 1314 | at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1315 | if (at_xdmac_chan_is_cyclic(atchan)) { |
| 1316 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda); |
| 1317 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc); |
| 1318 | at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim); |
| 1319 | wmb(); |
| 1320 | at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); |
| 1321 | } |
| 1322 | } |
| 1323 | return 0; |
| 1324 | } |
| 1325 | #endif /* CONFIG_PM_SLEEP */ |
| 1326 | |
| 1327 | static int at_xdmac_probe(struct platform_device *pdev) |
| 1328 | { |
| 1329 | struct resource *res; |
| 1330 | struct at_xdmac *atxdmac; |
| 1331 | int irq, size, nr_channels, i, ret; |
| 1332 | void __iomem *base; |
| 1333 | u32 reg; |
| 1334 | |
| 1335 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1336 | if (!res) |
| 1337 | return -EINVAL; |
| 1338 | |
| 1339 | irq = platform_get_irq(pdev, 0); |
| 1340 | if (irq < 0) |
| 1341 | return irq; |
| 1342 | |
| 1343 | base = devm_ioremap_resource(&pdev->dev, res); |
| 1344 | if (IS_ERR(base)) |
| 1345 | return PTR_ERR(base); |
| 1346 | |
| 1347 | /* |
| 1348 | * Read number of xdmac channels, read helper function can't be used |
| 1349 | * since atxdmac is not yet allocated and we need to know the number |
| 1350 | * of channels to do the allocation. |
| 1351 | */ |
| 1352 | reg = readl_relaxed(base + AT_XDMAC_GTYPE); |
| 1353 | nr_channels = AT_XDMAC_NB_CH(reg); |
| 1354 | if (nr_channels > AT_XDMAC_MAX_CHAN) { |
| 1355 | dev_err(&pdev->dev, "invalid number of channels (%u)\n", |
| 1356 | nr_channels); |
| 1357 | return -EINVAL; |
| 1358 | } |
| 1359 | |
| 1360 | size = sizeof(*atxdmac); |
| 1361 | size += nr_channels * sizeof(struct at_xdmac_chan); |
| 1362 | atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
| 1363 | if (!atxdmac) { |
| 1364 | dev_err(&pdev->dev, "can't allocate at_xdmac structure\n"); |
| 1365 | return -ENOMEM; |
| 1366 | } |
| 1367 | |
| 1368 | atxdmac->regs = base; |
| 1369 | atxdmac->irq = irq; |
| 1370 | |
| 1371 | atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk"); |
| 1372 | if (IS_ERR(atxdmac->clk)) { |
| 1373 | dev_err(&pdev->dev, "can't get dma_clk\n"); |
| 1374 | return PTR_ERR(atxdmac->clk); |
| 1375 | } |
| 1376 | |
| 1377 | /* Do not use dev res to prevent races with tasklet */ |
| 1378 | ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac); |
| 1379 | if (ret) { |
| 1380 | dev_err(&pdev->dev, "can't request irq\n"); |
| 1381 | return ret; |
| 1382 | } |
| 1383 | |
| 1384 | ret = clk_prepare_enable(atxdmac->clk); |
| 1385 | if (ret) { |
| 1386 | dev_err(&pdev->dev, "can't prepare or enable clock\n"); |
| 1387 | goto err_free_irq; |
| 1388 | } |
| 1389 | |
| 1390 | atxdmac->at_xdmac_desc_pool = |
| 1391 | dmam_pool_create(dev_name(&pdev->dev), &pdev->dev, |
| 1392 | sizeof(struct at_xdmac_desc), 4, 0); |
| 1393 | if (!atxdmac->at_xdmac_desc_pool) { |
| 1394 | dev_err(&pdev->dev, "no memory for descriptors dma pool\n"); |
| 1395 | ret = -ENOMEM; |
| 1396 | goto err_clk_disable; |
| 1397 | } |
| 1398 | |
| 1399 | dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask); |
| 1400 | dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask); |
| 1401 | dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask); |
Ludovic Desroches | fef4cbf | 2014-11-13 11:52:45 +0100 | [diff] [blame] | 1402 | /* |
| 1403 | * Without DMA_PRIVATE the driver is not able to allocate more than |
| 1404 | * one channel, second allocation fails in private_candidate. |
| 1405 | */ |
| 1406 | dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask); |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1407 | atxdmac->dma.dev = &pdev->dev; |
| 1408 | atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources; |
| 1409 | atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources; |
| 1410 | atxdmac->dma.device_tx_status = at_xdmac_tx_status; |
| 1411 | atxdmac->dma.device_issue_pending = at_xdmac_issue_pending; |
| 1412 | atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic; |
| 1413 | atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy; |
| 1414 | atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg; |
Ludovic Desroches | 3d13887 | 2014-11-17 14:42:07 +0100 | [diff] [blame] | 1415 | atxdmac->dma.device_config = at_xdmac_device_config; |
| 1416 | atxdmac->dma.device_pause = at_xdmac_device_pause; |
| 1417 | atxdmac->dma.device_resume = at_xdmac_device_resume; |
| 1418 | atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all; |
Ludovic Desroches | 8ac82f8 | 2014-11-17 14:42:44 +0100 | [diff] [blame] | 1419 | atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS; |
| 1420 | atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS; |
| 1421 | atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); |
| 1422 | atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1423 | |
| 1424 | /* Disable all chans and interrupts. */ |
| 1425 | at_xdmac_off(atxdmac); |
| 1426 | |
| 1427 | /* Init channels. */ |
| 1428 | INIT_LIST_HEAD(&atxdmac->dma.channels); |
| 1429 | for (i = 0; i < nr_channels; i++) { |
| 1430 | struct at_xdmac_chan *atchan = &atxdmac->chan[i]; |
| 1431 | |
| 1432 | atchan->chan.device = &atxdmac->dma; |
| 1433 | list_add_tail(&atchan->chan.device_node, |
| 1434 | &atxdmac->dma.channels); |
| 1435 | |
| 1436 | atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i); |
| 1437 | atchan->mask = 1 << i; |
| 1438 | |
| 1439 | spin_lock_init(&atchan->lock); |
| 1440 | INIT_LIST_HEAD(&atchan->xfers_list); |
| 1441 | INIT_LIST_HEAD(&atchan->free_descs_list); |
| 1442 | tasklet_init(&atchan->tasklet, at_xdmac_tasklet, |
| 1443 | (unsigned long)atchan); |
| 1444 | |
| 1445 | /* Clear pending interrupts. */ |
| 1446 | while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS)) |
| 1447 | cpu_relax(); |
| 1448 | } |
| 1449 | platform_set_drvdata(pdev, atxdmac); |
| 1450 | |
| 1451 | ret = dma_async_device_register(&atxdmac->dma); |
| 1452 | if (ret) { |
| 1453 | dev_err(&pdev->dev, "fail to register DMA engine device\n"); |
| 1454 | goto err_clk_disable; |
| 1455 | } |
| 1456 | |
| 1457 | ret = of_dma_controller_register(pdev->dev.of_node, |
| 1458 | at_xdmac_xlate, atxdmac); |
| 1459 | if (ret) { |
| 1460 | dev_err(&pdev->dev, "could not register of dma controller\n"); |
| 1461 | goto err_dma_unregister; |
| 1462 | } |
| 1463 | |
| 1464 | dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n", |
| 1465 | nr_channels, atxdmac->regs); |
| 1466 | |
| 1467 | return 0; |
| 1468 | |
| 1469 | err_dma_unregister: |
| 1470 | dma_async_device_unregister(&atxdmac->dma); |
| 1471 | err_clk_disable: |
| 1472 | clk_disable_unprepare(atxdmac->clk); |
| 1473 | err_free_irq: |
| 1474 | free_irq(atxdmac->irq, atxdmac->dma.dev); |
| 1475 | return ret; |
| 1476 | } |
| 1477 | |
| 1478 | static int at_xdmac_remove(struct platform_device *pdev) |
| 1479 | { |
| 1480 | struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev); |
| 1481 | int i; |
| 1482 | |
| 1483 | at_xdmac_off(atxdmac); |
| 1484 | of_dma_controller_free(pdev->dev.of_node); |
| 1485 | dma_async_device_unregister(&atxdmac->dma); |
| 1486 | clk_disable_unprepare(atxdmac->clk); |
| 1487 | |
| 1488 | synchronize_irq(atxdmac->irq); |
| 1489 | |
| 1490 | free_irq(atxdmac->irq, atxdmac->dma.dev); |
| 1491 | |
| 1492 | for (i = 0; i < atxdmac->dma.chancnt; i++) { |
| 1493 | struct at_xdmac_chan *atchan = &atxdmac->chan[i]; |
| 1494 | |
| 1495 | tasklet_kill(&atchan->tasklet); |
| 1496 | at_xdmac_free_chan_resources(&atchan->chan); |
| 1497 | } |
| 1498 | |
| 1499 | return 0; |
| 1500 | } |
| 1501 | |
| 1502 | static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = { |
| 1503 | .prepare = atmel_xdmac_prepare, |
| 1504 | SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume) |
| 1505 | }; |
| 1506 | |
| 1507 | static const struct of_device_id atmel_xdmac_dt_ids[] = { |
| 1508 | { |
| 1509 | .compatible = "atmel,sama5d4-dma", |
| 1510 | }, { |
| 1511 | /* sentinel */ |
| 1512 | } |
| 1513 | }; |
| 1514 | MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids); |
| 1515 | |
| 1516 | static struct platform_driver at_xdmac_driver = { |
| 1517 | .probe = at_xdmac_probe, |
| 1518 | .remove = at_xdmac_remove, |
| 1519 | .driver = { |
| 1520 | .name = "at_xdmac", |
Ludovic Desroches | e1f7c9e | 2014-10-22 17:22:18 +0200 | [diff] [blame] | 1521 | .of_match_table = of_match_ptr(atmel_xdmac_dt_ids), |
| 1522 | .pm = &atmel_xdmac_dev_pm_ops, |
| 1523 | } |
| 1524 | }; |
| 1525 | |
| 1526 | static int __init at_xdmac_init(void) |
| 1527 | { |
| 1528 | return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe); |
| 1529 | } |
| 1530 | subsys_initcall(at_xdmac_init); |
| 1531 | |
| 1532 | MODULE_DESCRIPTION("Atmel Extended DMA Controller driver"); |
| 1533 | MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); |
| 1534 | MODULE_LICENSE("GPL"); |