Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Marvell International Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 8 | |
Thierry Reding | 7331205 | 2013-01-21 11:09:00 +0100 | [diff] [blame] | 9 | #include <linux/err.h> |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 10 | #include <linux/module.h> |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/types.h> |
| 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/dma-mapping.h> |
| 15 | #include <linux/slab.h> |
| 16 | #include <linux/dmaengine.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/device.h> |
| 19 | #include <linux/platform_data/mmp_dma.h> |
| 20 | #include <linux/dmapool.h> |
| 21 | #include <linux/of_device.h> |
Daniel Mack | a9a7cf0 | 2013-08-10 18:52:19 +0200 | [diff] [blame] | 22 | #include <linux/of_dma.h> |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 23 | #include <linux/of.h> |
Daniel Mack | 13b3006 | 2013-08-10 18:52:18 +0200 | [diff] [blame] | 24 | #include <linux/dma/mmp-pdma.h> |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 25 | |
| 26 | #include "dmaengine.h" |
| 27 | |
| 28 | #define DCSR 0x0000 |
| 29 | #define DALGN 0x00a0 |
| 30 | #define DINT 0x00f0 |
| 31 | #define DDADR 0x0200 |
Daniel Mack | 1b38da2 | 2014-02-17 12:29:06 +0100 | [diff] [blame] | 32 | #define DSADR(n) (0x0204 + ((n) << 4)) |
| 33 | #define DTADR(n) (0x0208 + ((n) << 4)) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 34 | #define DCMD 0x020c |
| 35 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 36 | #define DCSR_RUN BIT(31) /* Run Bit (read / write) */ |
| 37 | #define DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */ |
| 38 | #define DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (read / write) */ |
| 39 | #define DCSR_REQPEND BIT(8) /* Request Pending (read-only) */ |
| 40 | #define DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */ |
| 41 | #define DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */ |
| 42 | #define DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */ |
| 43 | #define DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */ |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 44 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 45 | #define DCSR_EORIRQEN BIT(28) /* End of Receive Interrupt Enable (R/W) */ |
| 46 | #define DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */ |
| 47 | #define DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */ |
| 48 | #define DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */ |
| 49 | #define DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */ |
| 50 | #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ |
| 51 | #define DCSR_EORINTR BIT(9) /* The end of Receive */ |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 52 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 53 | #define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + (((n) & 0x3f) << 2)) |
| 54 | #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ |
| 55 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 56 | |
| 57 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 58 | #define DDADR_STOP BIT(0) /* Stop (read / write) */ |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 59 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 60 | #define DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */ |
| 61 | #define DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */ |
| 62 | #define DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */ |
| 63 | #define DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */ |
| 64 | #define DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */ |
| 65 | #define DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */ |
| 66 | #define DCMD_ENDIAN BIT(18) /* Device Endian-ness. */ |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 67 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ |
| 68 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ |
| 69 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ |
| 70 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ |
| 71 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ |
| 72 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ |
| 73 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ |
| 74 | |
| 75 | #define PDMA_ALIGNMENT 3 |
Daniel Mack | 1ac0e84 | 2013-08-10 18:52:17 +0200 | [diff] [blame] | 76 | #define PDMA_MAX_DESC_BYTES DCMD_LENGTH |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 77 | |
| 78 | struct mmp_pdma_desc_hw { |
| 79 | u32 ddadr; /* Points to the next descriptor + flags */ |
| 80 | u32 dsadr; /* DSADR value for the current transfer */ |
| 81 | u32 dtadr; /* DTADR value for the current transfer */ |
| 82 | u32 dcmd; /* DCMD value for the current transfer */ |
| 83 | } __aligned(32); |
| 84 | |
| 85 | struct mmp_pdma_desc_sw { |
| 86 | struct mmp_pdma_desc_hw desc; |
| 87 | struct list_head node; |
| 88 | struct list_head tx_list; |
| 89 | struct dma_async_tx_descriptor async_tx; |
| 90 | }; |
| 91 | |
| 92 | struct mmp_pdma_phy; |
| 93 | |
| 94 | struct mmp_pdma_chan { |
| 95 | struct device *dev; |
| 96 | struct dma_chan chan; |
| 97 | struct dma_async_tx_descriptor desc; |
| 98 | struct mmp_pdma_phy *phy; |
| 99 | enum dma_transfer_direction dir; |
| 100 | |
Daniel Mack | 50440d7 | 2013-08-21 14:08:56 +0200 | [diff] [blame] | 101 | struct mmp_pdma_desc_sw *cyclic_first; /* first desc_sw if channel |
| 102 | * is in cyclic mode */ |
| 103 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 104 | /* channel's basic info */ |
| 105 | struct tasklet_struct tasklet; |
| 106 | u32 dcmd; |
| 107 | u32 drcmr; |
| 108 | u32 dev_addr; |
| 109 | |
| 110 | /* list for desc */ |
| 111 | spinlock_t desc_lock; /* Descriptor list lock */ |
| 112 | struct list_head chain_pending; /* Link descriptors queue for pending */ |
| 113 | struct list_head chain_running; /* Link descriptors queue for running */ |
| 114 | bool idle; /* channel statue machine */ |
Daniel Mack | 6fc4573 | 2013-08-10 18:52:22 +0200 | [diff] [blame] | 115 | bool byte_align; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 116 | |
| 117 | struct dma_pool *desc_pool; /* Descriptors pool */ |
| 118 | }; |
| 119 | |
| 120 | struct mmp_pdma_phy { |
| 121 | int idx; |
| 122 | void __iomem *base; |
| 123 | struct mmp_pdma_chan *vchan; |
| 124 | }; |
| 125 | |
| 126 | struct mmp_pdma_device { |
| 127 | int dma_channels; |
| 128 | void __iomem *base; |
| 129 | struct device *dev; |
| 130 | struct dma_device device; |
| 131 | struct mmp_pdma_phy *phy; |
Xiang Wang | 027f28b | 2013-06-18 14:55:58 +0800 | [diff] [blame] | 132 | spinlock_t phy_lock; /* protect alloc/free phy channels */ |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 133 | }; |
| 134 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 135 | #define tx_to_mmp_pdma_desc(tx) \ |
| 136 | container_of(tx, struct mmp_pdma_desc_sw, async_tx) |
| 137 | #define to_mmp_pdma_desc(lh) \ |
| 138 | container_of(lh, struct mmp_pdma_desc_sw, node) |
| 139 | #define to_mmp_pdma_chan(dchan) \ |
| 140 | container_of(dchan, struct mmp_pdma_chan, chan) |
| 141 | #define to_mmp_pdma_dev(dmadev) \ |
| 142 | container_of(dmadev, struct mmp_pdma_device, device) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 143 | |
| 144 | static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr) |
| 145 | { |
| 146 | u32 reg = (phy->idx << 4) + DDADR; |
| 147 | |
| 148 | writel(addr, phy->base + reg); |
| 149 | } |
| 150 | |
| 151 | static void enable_chan(struct mmp_pdma_phy *phy) |
| 152 | { |
Daniel Mack | 6fc4573 | 2013-08-10 18:52:22 +0200 | [diff] [blame] | 153 | u32 reg, dalgn; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 154 | |
| 155 | if (!phy->vchan) |
| 156 | return; |
| 157 | |
Daniel Mack | 8b298de | 2013-08-10 18:52:15 +0200 | [diff] [blame] | 158 | reg = DRCMR(phy->vchan->drcmr); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 159 | writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); |
| 160 | |
Daniel Mack | 6fc4573 | 2013-08-10 18:52:22 +0200 | [diff] [blame] | 161 | dalgn = readl(phy->base + DALGN); |
| 162 | if (phy->vchan->byte_align) |
| 163 | dalgn |= 1 << phy->idx; |
| 164 | else |
| 165 | dalgn &= ~(1 << phy->idx); |
| 166 | writel(dalgn, phy->base + DALGN); |
| 167 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 168 | reg = (phy->idx << 2) + DCSR; |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 169 | writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | static void disable_chan(struct mmp_pdma_phy *phy) |
| 173 | { |
| 174 | u32 reg; |
| 175 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 176 | if (!phy) |
| 177 | return; |
| 178 | |
| 179 | reg = (phy->idx << 2) + DCSR; |
| 180 | writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | static int clear_chan_irq(struct mmp_pdma_phy *phy) |
| 184 | { |
| 185 | u32 dcsr; |
| 186 | u32 dint = readl(phy->base + DINT); |
| 187 | u32 reg = (phy->idx << 2) + DCSR; |
| 188 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 189 | if (!(dint & BIT(phy->idx))) |
| 190 | return -EAGAIN; |
| 191 | |
| 192 | /* clear irq */ |
| 193 | dcsr = readl(phy->base + reg); |
| 194 | writel(dcsr, phy->base + reg); |
| 195 | if ((dcsr & DCSR_BUSERR) && (phy->vchan)) |
| 196 | dev_warn(phy->vchan->dev, "DCSR_BUSERR\n"); |
| 197 | |
| 198 | return 0; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | static irqreturn_t mmp_pdma_chan_handler(int irq, void *dev_id) |
| 202 | { |
| 203 | struct mmp_pdma_phy *phy = dev_id; |
| 204 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 205 | if (clear_chan_irq(phy) != 0) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 206 | return IRQ_NONE; |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 207 | |
| 208 | tasklet_schedule(&phy->vchan->tasklet); |
| 209 | return IRQ_HANDLED; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | static irqreturn_t mmp_pdma_int_handler(int irq, void *dev_id) |
| 213 | { |
| 214 | struct mmp_pdma_device *pdev = dev_id; |
| 215 | struct mmp_pdma_phy *phy; |
| 216 | u32 dint = readl(pdev->base + DINT); |
| 217 | int i, ret; |
| 218 | int irq_num = 0; |
| 219 | |
| 220 | while (dint) { |
| 221 | i = __ffs(dint); |
| 222 | dint &= (dint - 1); |
| 223 | phy = &pdev->phy[i]; |
| 224 | ret = mmp_pdma_chan_handler(irq, phy); |
| 225 | if (ret == IRQ_HANDLED) |
| 226 | irq_num++; |
| 227 | } |
| 228 | |
| 229 | if (irq_num) |
| 230 | return IRQ_HANDLED; |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 231 | |
| 232 | return IRQ_NONE; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 233 | } |
| 234 | |
| 235 | /* lookup free phy channel as descending priority */ |
| 236 | static struct mmp_pdma_phy *lookup_phy(struct mmp_pdma_chan *pchan) |
| 237 | { |
| 238 | int prio, i; |
| 239 | struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device); |
Daniel Mack | 638a542 | 2013-08-10 18:52:16 +0200 | [diff] [blame] | 240 | struct mmp_pdma_phy *phy, *found = NULL; |
Xiang Wang | 027f28b | 2013-06-18 14:55:58 +0800 | [diff] [blame] | 241 | unsigned long flags; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 242 | |
| 243 | /* |
| 244 | * dma channel priorities |
| 245 | * ch 0 - 3, 16 - 19 <--> (0) |
| 246 | * ch 4 - 7, 20 - 23 <--> (1) |
| 247 | * ch 8 - 11, 24 - 27 <--> (2) |
| 248 | * ch 12 - 15, 28 - 31 <--> (3) |
| 249 | */ |
Xiang Wang | 027f28b | 2013-06-18 14:55:58 +0800 | [diff] [blame] | 250 | |
| 251 | spin_lock_irqsave(&pdev->phy_lock, flags); |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 252 | for (prio = 0; prio <= ((pdev->dma_channels - 1) & 0xf) >> 2; prio++) { |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 253 | for (i = 0; i < pdev->dma_channels; i++) { |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 254 | if (prio != (i & 0xf) >> 2) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 255 | continue; |
| 256 | phy = &pdev->phy[i]; |
| 257 | if (!phy->vchan) { |
| 258 | phy->vchan = pchan; |
Daniel Mack | 638a542 | 2013-08-10 18:52:16 +0200 | [diff] [blame] | 259 | found = phy; |
| 260 | goto out_unlock; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 261 | } |
| 262 | } |
| 263 | } |
| 264 | |
Daniel Mack | 638a542 | 2013-08-10 18:52:16 +0200 | [diff] [blame] | 265 | out_unlock: |
Xiang Wang | 027f28b | 2013-06-18 14:55:58 +0800 | [diff] [blame] | 266 | spin_unlock_irqrestore(&pdev->phy_lock, flags); |
Daniel Mack | 638a542 | 2013-08-10 18:52:16 +0200 | [diff] [blame] | 267 | return found; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 268 | } |
| 269 | |
Xiang Wang | 027f28b | 2013-06-18 14:55:58 +0800 | [diff] [blame] | 270 | static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan) |
| 271 | { |
| 272 | struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device); |
| 273 | unsigned long flags; |
Xiang Wang | 26a2dfd | 2013-06-18 14:55:59 +0800 | [diff] [blame] | 274 | u32 reg; |
Xiang Wang | 027f28b | 2013-06-18 14:55:58 +0800 | [diff] [blame] | 275 | |
| 276 | if (!pchan->phy) |
| 277 | return; |
| 278 | |
Xiang Wang | 26a2dfd | 2013-06-18 14:55:59 +0800 | [diff] [blame] | 279 | /* clear the channel mapping in DRCMR */ |
Laurent Pinchart | a2a7c17 | 2014-04-15 17:13:34 +0200 | [diff] [blame] | 280 | reg = DRCMR(pchan->drcmr); |
Xiang Wang | 26a2dfd | 2013-06-18 14:55:59 +0800 | [diff] [blame] | 281 | writel(0, pchan->phy->base + reg); |
| 282 | |
Xiang Wang | 027f28b | 2013-06-18 14:55:58 +0800 | [diff] [blame] | 283 | spin_lock_irqsave(&pdev->phy_lock, flags); |
| 284 | pchan->phy->vchan = NULL; |
| 285 | pchan->phy = NULL; |
| 286 | spin_unlock_irqrestore(&pdev->phy_lock, flags); |
| 287 | } |
| 288 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 289 | /** |
| 290 | * start_pending_queue - transfer any pending transactions |
| 291 | * pending list ==> running list |
| 292 | */ |
| 293 | static void start_pending_queue(struct mmp_pdma_chan *chan) |
| 294 | { |
| 295 | struct mmp_pdma_desc_sw *desc; |
| 296 | |
| 297 | /* still in running, irq will start the pending list */ |
| 298 | if (!chan->idle) { |
| 299 | dev_dbg(chan->dev, "DMA controller still busy\n"); |
| 300 | return; |
| 301 | } |
| 302 | |
| 303 | if (list_empty(&chan->chain_pending)) { |
| 304 | /* chance to re-fetch phy channel with higher prio */ |
Xiang Wang | 027f28b | 2013-06-18 14:55:58 +0800 | [diff] [blame] | 305 | mmp_pdma_free_phy(chan); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 306 | dev_dbg(chan->dev, "no pending list\n"); |
| 307 | return; |
| 308 | } |
| 309 | |
| 310 | if (!chan->phy) { |
| 311 | chan->phy = lookup_phy(chan); |
| 312 | if (!chan->phy) { |
| 313 | dev_dbg(chan->dev, "no free dma channel\n"); |
| 314 | return; |
| 315 | } |
| 316 | } |
| 317 | |
| 318 | /* |
| 319 | * pending -> running |
| 320 | * reintilize pending list |
| 321 | */ |
| 322 | desc = list_first_entry(&chan->chain_pending, |
| 323 | struct mmp_pdma_desc_sw, node); |
| 324 | list_splice_tail_init(&chan->chain_pending, &chan->chain_running); |
| 325 | |
| 326 | /* |
| 327 | * Program the descriptor's address into the DMA controller, |
| 328 | * then start the DMA transaction |
| 329 | */ |
| 330 | set_desc(chan->phy, desc->async_tx.phys); |
| 331 | enable_chan(chan->phy); |
| 332 | chan->idle = false; |
| 333 | } |
| 334 | |
| 335 | |
| 336 | /* desc->tx_list ==> pending list */ |
| 337 | static dma_cookie_t mmp_pdma_tx_submit(struct dma_async_tx_descriptor *tx) |
| 338 | { |
| 339 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(tx->chan); |
| 340 | struct mmp_pdma_desc_sw *desc = tx_to_mmp_pdma_desc(tx); |
| 341 | struct mmp_pdma_desc_sw *child; |
| 342 | unsigned long flags; |
| 343 | dma_cookie_t cookie = -EBUSY; |
| 344 | |
| 345 | spin_lock_irqsave(&chan->desc_lock, flags); |
| 346 | |
| 347 | list_for_each_entry(child, &desc->tx_list, node) { |
| 348 | cookie = dma_cookie_assign(&child->async_tx); |
| 349 | } |
| 350 | |
Daniel Mack | 0cd6156 | 2013-08-21 14:08:55 +0200 | [diff] [blame] | 351 | /* softly link to pending list - desc->tx_list ==> pending list */ |
| 352 | list_splice_tail_init(&desc->tx_list, &chan->chain_pending); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 353 | |
| 354 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
| 355 | |
| 356 | return cookie; |
| 357 | } |
| 358 | |
Jingoo Han | 69c9f0a | 2013-08-06 19:35:13 +0900 | [diff] [blame] | 359 | static struct mmp_pdma_desc_sw * |
| 360 | mmp_pdma_alloc_descriptor(struct mmp_pdma_chan *chan) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 361 | { |
| 362 | struct mmp_pdma_desc_sw *desc; |
| 363 | dma_addr_t pdesc; |
| 364 | |
| 365 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); |
| 366 | if (!desc) { |
| 367 | dev_err(chan->dev, "out of memory for link descriptor\n"); |
| 368 | return NULL; |
| 369 | } |
| 370 | |
| 371 | memset(desc, 0, sizeof(*desc)); |
| 372 | INIT_LIST_HEAD(&desc->tx_list); |
| 373 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan); |
| 374 | /* each desc has submit */ |
| 375 | desc->async_tx.tx_submit = mmp_pdma_tx_submit; |
| 376 | desc->async_tx.phys = pdesc; |
| 377 | |
| 378 | return desc; |
| 379 | } |
| 380 | |
| 381 | /** |
| 382 | * mmp_pdma_alloc_chan_resources - Allocate resources for DMA channel. |
| 383 | * |
| 384 | * This function will create a dma pool for descriptor allocation. |
| 385 | * Request irq only when channel is requested |
| 386 | * Return - The number of allocated descriptors. |
| 387 | */ |
| 388 | |
| 389 | static int mmp_pdma_alloc_chan_resources(struct dma_chan *dchan) |
| 390 | { |
| 391 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); |
| 392 | |
| 393 | if (chan->desc_pool) |
| 394 | return 1; |
| 395 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 396 | chan->desc_pool = dma_pool_create(dev_name(&dchan->dev->device), |
| 397 | chan->dev, |
| 398 | sizeof(struct mmp_pdma_desc_sw), |
| 399 | __alignof__(struct mmp_pdma_desc_sw), |
| 400 | 0); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 401 | if (!chan->desc_pool) { |
| 402 | dev_err(chan->dev, "unable to allocate descriptor pool\n"); |
| 403 | return -ENOMEM; |
| 404 | } |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 405 | |
Xiang Wang | 027f28b | 2013-06-18 14:55:58 +0800 | [diff] [blame] | 406 | mmp_pdma_free_phy(chan); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 407 | chan->idle = true; |
| 408 | chan->dev_addr = 0; |
| 409 | return 1; |
| 410 | } |
| 411 | |
| 412 | static void mmp_pdma_free_desc_list(struct mmp_pdma_chan *chan, |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 413 | struct list_head *list) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 414 | { |
| 415 | struct mmp_pdma_desc_sw *desc, *_desc; |
| 416 | |
| 417 | list_for_each_entry_safe(desc, _desc, list, node) { |
| 418 | list_del(&desc->node); |
| 419 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); |
| 420 | } |
| 421 | } |
| 422 | |
| 423 | static void mmp_pdma_free_chan_resources(struct dma_chan *dchan) |
| 424 | { |
| 425 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); |
| 426 | unsigned long flags; |
| 427 | |
| 428 | spin_lock_irqsave(&chan->desc_lock, flags); |
| 429 | mmp_pdma_free_desc_list(chan, &chan->chain_pending); |
| 430 | mmp_pdma_free_desc_list(chan, &chan->chain_running); |
| 431 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
| 432 | |
| 433 | dma_pool_destroy(chan->desc_pool); |
| 434 | chan->desc_pool = NULL; |
| 435 | chan->idle = true; |
| 436 | chan->dev_addr = 0; |
Xiang Wang | 027f28b | 2013-06-18 14:55:58 +0800 | [diff] [blame] | 437 | mmp_pdma_free_phy(chan); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 438 | return; |
| 439 | } |
| 440 | |
| 441 | static struct dma_async_tx_descriptor * |
| 442 | mmp_pdma_prep_memcpy(struct dma_chan *dchan, |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 443 | dma_addr_t dma_dst, dma_addr_t dma_src, |
| 444 | size_t len, unsigned long flags) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 445 | { |
| 446 | struct mmp_pdma_chan *chan; |
| 447 | struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new; |
| 448 | size_t copy = 0; |
| 449 | |
| 450 | if (!dchan) |
| 451 | return NULL; |
| 452 | |
| 453 | if (!len) |
| 454 | return NULL; |
| 455 | |
| 456 | chan = to_mmp_pdma_chan(dchan); |
Daniel Mack | 6fc4573 | 2013-08-10 18:52:22 +0200 | [diff] [blame] | 457 | chan->byte_align = false; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 458 | |
| 459 | if (!chan->dir) { |
| 460 | chan->dir = DMA_MEM_TO_MEM; |
| 461 | chan->dcmd = DCMD_INCTRGADDR | DCMD_INCSRCADDR; |
| 462 | chan->dcmd |= DCMD_BURST32; |
| 463 | } |
| 464 | |
| 465 | do { |
| 466 | /* Allocate the link descriptor from DMA pool */ |
| 467 | new = mmp_pdma_alloc_descriptor(chan); |
| 468 | if (!new) { |
| 469 | dev_err(chan->dev, "no memory for desc\n"); |
| 470 | goto fail; |
| 471 | } |
| 472 | |
| 473 | copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES); |
Daniel Mack | 6fc4573 | 2013-08-10 18:52:22 +0200 | [diff] [blame] | 474 | if (dma_src & 0x7 || dma_dst & 0x7) |
| 475 | chan->byte_align = true; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 476 | |
| 477 | new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & copy); |
| 478 | new->desc.dsadr = dma_src; |
| 479 | new->desc.dtadr = dma_dst; |
| 480 | |
| 481 | if (!first) |
| 482 | first = new; |
| 483 | else |
| 484 | prev->desc.ddadr = new->async_tx.phys; |
| 485 | |
| 486 | new->async_tx.cookie = 0; |
| 487 | async_tx_ack(&new->async_tx); |
| 488 | |
| 489 | prev = new; |
| 490 | len -= copy; |
| 491 | |
| 492 | if (chan->dir == DMA_MEM_TO_DEV) { |
| 493 | dma_src += copy; |
| 494 | } else if (chan->dir == DMA_DEV_TO_MEM) { |
| 495 | dma_dst += copy; |
| 496 | } else if (chan->dir == DMA_MEM_TO_MEM) { |
| 497 | dma_src += copy; |
| 498 | dma_dst += copy; |
| 499 | } |
| 500 | |
| 501 | /* Insert the link descriptor to the LD ring */ |
| 502 | list_add_tail(&new->node, &first->tx_list); |
| 503 | } while (len); |
| 504 | |
| 505 | first->async_tx.flags = flags; /* client is in control of this ack */ |
| 506 | first->async_tx.cookie = -EBUSY; |
| 507 | |
| 508 | /* last desc and fire IRQ */ |
| 509 | new->desc.ddadr = DDADR_STOP; |
| 510 | new->desc.dcmd |= DCMD_ENDIRQEN; |
| 511 | |
Daniel Mack | 50440d7 | 2013-08-21 14:08:56 +0200 | [diff] [blame] | 512 | chan->cyclic_first = NULL; |
| 513 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 514 | return &first->async_tx; |
| 515 | |
| 516 | fail: |
| 517 | if (first) |
| 518 | mmp_pdma_free_desc_list(chan, &first->tx_list); |
| 519 | return NULL; |
| 520 | } |
| 521 | |
| 522 | static struct dma_async_tx_descriptor * |
| 523 | mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 524 | unsigned int sg_len, enum dma_transfer_direction dir, |
| 525 | unsigned long flags, void *context) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 526 | { |
| 527 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); |
| 528 | struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new = NULL; |
| 529 | size_t len, avail; |
| 530 | struct scatterlist *sg; |
| 531 | dma_addr_t addr; |
| 532 | int i; |
| 533 | |
| 534 | if ((sgl == NULL) || (sg_len == 0)) |
| 535 | return NULL; |
| 536 | |
Daniel Mack | 6fc4573 | 2013-08-10 18:52:22 +0200 | [diff] [blame] | 537 | chan->byte_align = false; |
| 538 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 539 | for_each_sg(sgl, sg, sg_len, i) { |
| 540 | addr = sg_dma_address(sg); |
| 541 | avail = sg_dma_len(sgl); |
| 542 | |
| 543 | do { |
| 544 | len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES); |
Daniel Mack | 6fc4573 | 2013-08-10 18:52:22 +0200 | [diff] [blame] | 545 | if (addr & 0x7) |
| 546 | chan->byte_align = true; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 547 | |
| 548 | /* allocate and populate the descriptor */ |
| 549 | new = mmp_pdma_alloc_descriptor(chan); |
| 550 | if (!new) { |
| 551 | dev_err(chan->dev, "no memory for desc\n"); |
| 552 | goto fail; |
| 553 | } |
| 554 | |
| 555 | new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & len); |
| 556 | if (dir == DMA_MEM_TO_DEV) { |
| 557 | new->desc.dsadr = addr; |
| 558 | new->desc.dtadr = chan->dev_addr; |
| 559 | } else { |
| 560 | new->desc.dsadr = chan->dev_addr; |
| 561 | new->desc.dtadr = addr; |
| 562 | } |
| 563 | |
| 564 | if (!first) |
| 565 | first = new; |
| 566 | else |
| 567 | prev->desc.ddadr = new->async_tx.phys; |
| 568 | |
| 569 | new->async_tx.cookie = 0; |
| 570 | async_tx_ack(&new->async_tx); |
| 571 | prev = new; |
| 572 | |
| 573 | /* Insert the link descriptor to the LD ring */ |
| 574 | list_add_tail(&new->node, &first->tx_list); |
| 575 | |
| 576 | /* update metadata */ |
| 577 | addr += len; |
| 578 | avail -= len; |
| 579 | } while (avail); |
| 580 | } |
| 581 | |
| 582 | first->async_tx.cookie = -EBUSY; |
| 583 | first->async_tx.flags = flags; |
| 584 | |
| 585 | /* last desc and fire IRQ */ |
| 586 | new->desc.ddadr = DDADR_STOP; |
| 587 | new->desc.dcmd |= DCMD_ENDIRQEN; |
| 588 | |
Daniel Mack | 50440d7 | 2013-08-21 14:08:56 +0200 | [diff] [blame] | 589 | chan->dir = dir; |
| 590 | chan->cyclic_first = NULL; |
| 591 | |
| 592 | return &first->async_tx; |
| 593 | |
| 594 | fail: |
| 595 | if (first) |
| 596 | mmp_pdma_free_desc_list(chan, &first->tx_list); |
| 597 | return NULL; |
| 598 | } |
| 599 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 600 | static struct dma_async_tx_descriptor * |
| 601 | mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan, |
| 602 | dma_addr_t buf_addr, size_t len, size_t period_len, |
| 603 | enum dma_transfer_direction direction, |
Laurent Pinchart | 31c1e5a | 2014-08-01 12:20:10 +0200 | [diff] [blame] | 604 | unsigned long flags) |
Daniel Mack | 50440d7 | 2013-08-21 14:08:56 +0200 | [diff] [blame] | 605 | { |
| 606 | struct mmp_pdma_chan *chan; |
| 607 | struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new; |
| 608 | dma_addr_t dma_src, dma_dst; |
| 609 | |
| 610 | if (!dchan || !len || !period_len) |
| 611 | return NULL; |
| 612 | |
| 613 | /* the buffer length must be a multiple of period_len */ |
| 614 | if (len % period_len != 0) |
| 615 | return NULL; |
| 616 | |
| 617 | if (period_len > PDMA_MAX_DESC_BYTES) |
| 618 | return NULL; |
| 619 | |
| 620 | chan = to_mmp_pdma_chan(dchan); |
| 621 | |
| 622 | switch (direction) { |
| 623 | case DMA_MEM_TO_DEV: |
| 624 | dma_src = buf_addr; |
| 625 | dma_dst = chan->dev_addr; |
| 626 | break; |
| 627 | case DMA_DEV_TO_MEM: |
| 628 | dma_dst = buf_addr; |
| 629 | dma_src = chan->dev_addr; |
| 630 | break; |
| 631 | default: |
| 632 | dev_err(chan->dev, "Unsupported direction for cyclic DMA\n"); |
| 633 | return NULL; |
| 634 | } |
| 635 | |
| 636 | chan->dir = direction; |
| 637 | |
| 638 | do { |
| 639 | /* Allocate the link descriptor from DMA pool */ |
| 640 | new = mmp_pdma_alloc_descriptor(chan); |
| 641 | if (!new) { |
| 642 | dev_err(chan->dev, "no memory for desc\n"); |
| 643 | goto fail; |
| 644 | } |
| 645 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 646 | new->desc.dcmd = (chan->dcmd | DCMD_ENDIRQEN | |
| 647 | (DCMD_LENGTH & period_len)); |
Daniel Mack | 50440d7 | 2013-08-21 14:08:56 +0200 | [diff] [blame] | 648 | new->desc.dsadr = dma_src; |
| 649 | new->desc.dtadr = dma_dst; |
| 650 | |
| 651 | if (!first) |
| 652 | first = new; |
| 653 | else |
| 654 | prev->desc.ddadr = new->async_tx.phys; |
| 655 | |
| 656 | new->async_tx.cookie = 0; |
| 657 | async_tx_ack(&new->async_tx); |
| 658 | |
| 659 | prev = new; |
| 660 | len -= period_len; |
| 661 | |
| 662 | if (chan->dir == DMA_MEM_TO_DEV) |
| 663 | dma_src += period_len; |
| 664 | else |
| 665 | dma_dst += period_len; |
| 666 | |
| 667 | /* Insert the link descriptor to the LD ring */ |
| 668 | list_add_tail(&new->node, &first->tx_list); |
| 669 | } while (len); |
| 670 | |
| 671 | first->async_tx.flags = flags; /* client is in control of this ack */ |
| 672 | first->async_tx.cookie = -EBUSY; |
| 673 | |
| 674 | /* make the cyclic link */ |
| 675 | new->desc.ddadr = first->async_tx.phys; |
| 676 | chan->cyclic_first = first; |
| 677 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 678 | return &first->async_tx; |
| 679 | |
| 680 | fail: |
| 681 | if (first) |
| 682 | mmp_pdma_free_desc_list(chan, &first->tx_list); |
| 683 | return NULL; |
| 684 | } |
| 685 | |
Maxime Ripard | a0abd67 | 2014-11-17 14:42:21 +0100 | [diff] [blame] | 686 | static int mmp_pdma_config(struct dma_chan *dchan, |
| 687 | struct dma_slave_config *cfg) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 688 | { |
| 689 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 690 | u32 maxburst = 0, addr = 0; |
| 691 | enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
| 692 | |
| 693 | if (!dchan) |
| 694 | return -EINVAL; |
| 695 | |
Maxime Ripard | a0abd67 | 2014-11-17 14:42:21 +0100 | [diff] [blame] | 696 | if (cfg->direction == DMA_DEV_TO_MEM) { |
| 697 | chan->dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC; |
| 698 | maxburst = cfg->src_maxburst; |
| 699 | width = cfg->src_addr_width; |
| 700 | addr = cfg->src_addr; |
| 701 | } else if (cfg->direction == DMA_MEM_TO_DEV) { |
| 702 | chan->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG; |
| 703 | maxburst = cfg->dst_maxburst; |
| 704 | width = cfg->dst_addr_width; |
| 705 | addr = cfg->dst_addr; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 706 | } |
| 707 | |
Maxime Ripard | a0abd67 | 2014-11-17 14:42:21 +0100 | [diff] [blame] | 708 | if (width == DMA_SLAVE_BUSWIDTH_1_BYTE) |
| 709 | chan->dcmd |= DCMD_WIDTH1; |
| 710 | else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES) |
| 711 | chan->dcmd |= DCMD_WIDTH2; |
| 712 | else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES) |
| 713 | chan->dcmd |= DCMD_WIDTH4; |
| 714 | |
| 715 | if (maxburst == 8) |
| 716 | chan->dcmd |= DCMD_BURST8; |
| 717 | else if (maxburst == 16) |
| 718 | chan->dcmd |= DCMD_BURST16; |
| 719 | else if (maxburst == 32) |
| 720 | chan->dcmd |= DCMD_BURST32; |
| 721 | |
| 722 | chan->dir = cfg->direction; |
| 723 | chan->dev_addr = addr; |
| 724 | /* FIXME: drivers should be ported over to use the filter |
| 725 | * function. Once that's done, the following two lines can |
| 726 | * be removed. |
| 727 | */ |
| 728 | if (cfg->slave_id) |
| 729 | chan->drcmr = cfg->slave_id; |
| 730 | |
| 731 | return 0; |
| 732 | } |
| 733 | |
| 734 | static int mmp_pdma_terminate_all(struct dma_chan *dchan) |
| 735 | { |
| 736 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); |
| 737 | unsigned long flags; |
| 738 | |
| 739 | if (!dchan) |
| 740 | return -EINVAL; |
| 741 | |
| 742 | disable_chan(chan->phy); |
| 743 | mmp_pdma_free_phy(chan); |
| 744 | spin_lock_irqsave(&chan->desc_lock, flags); |
| 745 | mmp_pdma_free_desc_list(chan, &chan->chain_pending); |
| 746 | mmp_pdma_free_desc_list(chan, &chan->chain_running); |
| 747 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
| 748 | chan->idle = true; |
| 749 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 750 | return 0; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 751 | } |
| 752 | |
Daniel Mack | 1b38da2 | 2014-02-17 12:29:06 +0100 | [diff] [blame] | 753 | static unsigned int mmp_pdma_residue(struct mmp_pdma_chan *chan, |
| 754 | dma_cookie_t cookie) |
| 755 | { |
| 756 | struct mmp_pdma_desc_sw *sw; |
| 757 | u32 curr, residue = 0; |
| 758 | bool passed = false; |
| 759 | bool cyclic = chan->cyclic_first != NULL; |
| 760 | |
| 761 | /* |
| 762 | * If the channel does not have a phy pointer anymore, it has already |
| 763 | * been completed. Therefore, its residue is 0. |
| 764 | */ |
| 765 | if (!chan->phy) |
| 766 | return 0; |
| 767 | |
| 768 | if (chan->dir == DMA_DEV_TO_MEM) |
| 769 | curr = readl(chan->phy->base + DTADR(chan->phy->idx)); |
| 770 | else |
| 771 | curr = readl(chan->phy->base + DSADR(chan->phy->idx)); |
| 772 | |
| 773 | list_for_each_entry(sw, &chan->chain_running, node) { |
| 774 | u32 start, end, len; |
| 775 | |
| 776 | if (chan->dir == DMA_DEV_TO_MEM) |
| 777 | start = sw->desc.dtadr; |
| 778 | else |
| 779 | start = sw->desc.dsadr; |
| 780 | |
| 781 | len = sw->desc.dcmd & DCMD_LENGTH; |
| 782 | end = start + len; |
| 783 | |
| 784 | /* |
| 785 | * 'passed' will be latched once we found the descriptor which |
| 786 | * lies inside the boundaries of the curr pointer. All |
| 787 | * descriptors that occur in the list _after_ we found that |
| 788 | * partially handled descriptor are still to be processed and |
| 789 | * are hence added to the residual bytes counter. |
| 790 | */ |
| 791 | |
| 792 | if (passed) { |
| 793 | residue += len; |
| 794 | } else if (curr >= start && curr <= end) { |
| 795 | residue += end - curr; |
| 796 | passed = true; |
| 797 | } |
| 798 | |
| 799 | /* |
| 800 | * Descriptors that have the ENDIRQEN bit set mark the end of a |
| 801 | * transaction chain, and the cookie assigned with it has been |
| 802 | * returned previously from mmp_pdma_tx_submit(). |
| 803 | * |
| 804 | * In case we have multiple transactions in the running chain, |
| 805 | * and the cookie does not match the one the user asked us |
| 806 | * about, reset the state variables and start over. |
| 807 | * |
| 808 | * This logic does not apply to cyclic transactions, where all |
| 809 | * descriptors have the ENDIRQEN bit set, and for which we |
| 810 | * can't have multiple transactions on one channel anyway. |
| 811 | */ |
| 812 | if (cyclic || !(sw->desc.dcmd & DCMD_ENDIRQEN)) |
| 813 | continue; |
| 814 | |
| 815 | if (sw->async_tx.cookie == cookie) { |
| 816 | return residue; |
| 817 | } else { |
| 818 | residue = 0; |
| 819 | passed = false; |
| 820 | } |
| 821 | } |
| 822 | |
| 823 | /* We should only get here in case of cyclic transactions */ |
| 824 | return residue; |
| 825 | } |
| 826 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 827 | static enum dma_status mmp_pdma_tx_status(struct dma_chan *dchan, |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 828 | dma_cookie_t cookie, |
| 829 | struct dma_tx_state *txstate) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 830 | { |
Daniel Mack | 1b38da2 | 2014-02-17 12:29:06 +0100 | [diff] [blame] | 831 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); |
| 832 | enum dma_status ret; |
| 833 | |
| 834 | ret = dma_cookie_status(dchan, cookie, txstate); |
| 835 | if (likely(ret != DMA_ERROR)) |
| 836 | dma_set_residue(txstate, mmp_pdma_residue(chan, cookie)); |
| 837 | |
| 838 | return ret; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 839 | } |
| 840 | |
| 841 | /** |
| 842 | * mmp_pdma_issue_pending - Issue the DMA start command |
| 843 | * pending list ==> running list |
| 844 | */ |
| 845 | static void mmp_pdma_issue_pending(struct dma_chan *dchan) |
| 846 | { |
| 847 | struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan); |
| 848 | unsigned long flags; |
| 849 | |
| 850 | spin_lock_irqsave(&chan->desc_lock, flags); |
| 851 | start_pending_queue(chan); |
| 852 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
| 853 | } |
| 854 | |
| 855 | /* |
| 856 | * dma_do_tasklet |
| 857 | * Do call back |
| 858 | * Start pending list |
| 859 | */ |
| 860 | static void dma_do_tasklet(unsigned long data) |
| 861 | { |
| 862 | struct mmp_pdma_chan *chan = (struct mmp_pdma_chan *)data; |
| 863 | struct mmp_pdma_desc_sw *desc, *_desc; |
| 864 | LIST_HEAD(chain_cleanup); |
| 865 | unsigned long flags; |
| 866 | |
Daniel Mack | 50440d7 | 2013-08-21 14:08:56 +0200 | [diff] [blame] | 867 | if (chan->cyclic_first) { |
| 868 | dma_async_tx_callback cb = NULL; |
| 869 | void *cb_data = NULL; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 870 | |
Daniel Mack | 50440d7 | 2013-08-21 14:08:56 +0200 | [diff] [blame] | 871 | spin_lock_irqsave(&chan->desc_lock, flags); |
| 872 | desc = chan->cyclic_first; |
| 873 | cb = desc->async_tx.callback; |
| 874 | cb_data = desc->async_tx.callback_param; |
| 875 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
| 876 | |
| 877 | if (cb) |
| 878 | cb(cb_data); |
| 879 | |
| 880 | return; |
| 881 | } |
| 882 | |
| 883 | /* submit pending list; callback for each desc; free desc */ |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 884 | spin_lock_irqsave(&chan->desc_lock, flags); |
| 885 | |
Daniel Mack | b721f9e | 2013-08-21 14:08:54 +0200 | [diff] [blame] | 886 | list_for_each_entry_safe(desc, _desc, &chan->chain_running, node) { |
| 887 | /* |
| 888 | * move the descriptors to a temporary list so we can drop |
| 889 | * the lock during the entire cleanup operation |
| 890 | */ |
Wei Yongjun | f358c28 | 2013-09-23 14:07:20 +0800 | [diff] [blame] | 891 | list_move(&desc->node, &chain_cleanup); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 892 | |
Daniel Mack | b721f9e | 2013-08-21 14:08:54 +0200 | [diff] [blame] | 893 | /* |
| 894 | * Look for the first list entry which has the ENDIRQEN flag |
| 895 | * set. That is the descriptor we got an interrupt for, so |
| 896 | * complete that transaction and its cookie. |
| 897 | */ |
| 898 | if (desc->desc.dcmd & DCMD_ENDIRQEN) { |
| 899 | dma_cookie_t cookie = desc->async_tx.cookie; |
| 900 | dma_cookie_complete(&desc->async_tx); |
| 901 | dev_dbg(chan->dev, "completed_cookie=%d\n", cookie); |
| 902 | break; |
| 903 | } |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 904 | } |
| 905 | |
| 906 | /* |
Daniel Mack | b721f9e | 2013-08-21 14:08:54 +0200 | [diff] [blame] | 907 | * The hardware is idle and ready for more when the |
| 908 | * chain_running list is empty. |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 909 | */ |
Daniel Mack | b721f9e | 2013-08-21 14:08:54 +0200 | [diff] [blame] | 910 | chan->idle = list_empty(&chan->chain_running); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 911 | |
| 912 | /* Start any pending transactions automatically */ |
| 913 | start_pending_queue(chan); |
| 914 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
| 915 | |
| 916 | /* Run the callback for each descriptor, in order */ |
| 917 | list_for_each_entry_safe(desc, _desc, &chain_cleanup, node) { |
| 918 | struct dma_async_tx_descriptor *txd = &desc->async_tx; |
| 919 | |
| 920 | /* Remove from the list of transactions */ |
| 921 | list_del(&desc->node); |
| 922 | /* Run the link descriptor callback function */ |
| 923 | if (txd->callback) |
| 924 | txd->callback(txd->callback_param); |
| 925 | |
| 926 | dma_pool_free(chan->desc_pool, desc, txd->phys); |
| 927 | } |
| 928 | } |
| 929 | |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 930 | static int mmp_pdma_remove(struct platform_device *op) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 931 | { |
| 932 | struct mmp_pdma_device *pdev = platform_get_drvdata(op); |
| 933 | |
| 934 | dma_async_device_unregister(&pdev->device); |
| 935 | return 0; |
| 936 | } |
| 937 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 938 | static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev, int idx, int irq) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 939 | { |
| 940 | struct mmp_pdma_phy *phy = &pdev->phy[idx]; |
| 941 | struct mmp_pdma_chan *chan; |
| 942 | int ret; |
| 943 | |
Laurent Pinchart | 593d9c2 | 2014-04-15 17:13:35 +0200 | [diff] [blame] | 944 | chan = devm_kzalloc(pdev->dev, sizeof(*chan), GFP_KERNEL); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 945 | if (chan == NULL) |
| 946 | return -ENOMEM; |
| 947 | |
| 948 | phy->idx = idx; |
| 949 | phy->base = pdev->base; |
| 950 | |
| 951 | if (irq) { |
Chao Xie | f0b5077 | 2014-01-27 09:44:07 +0800 | [diff] [blame] | 952 | ret = devm_request_irq(pdev->dev, irq, mmp_pdma_chan_handler, |
| 953 | IRQF_SHARED, "pdma", phy); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 954 | if (ret) { |
| 955 | dev_err(pdev->dev, "channel request irq fail!\n"); |
| 956 | return ret; |
| 957 | } |
| 958 | } |
| 959 | |
| 960 | spin_lock_init(&chan->desc_lock); |
| 961 | chan->dev = pdev->dev; |
| 962 | chan->chan.device = &pdev->device; |
| 963 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); |
| 964 | INIT_LIST_HEAD(&chan->chain_pending); |
| 965 | INIT_LIST_HEAD(&chan->chain_running); |
| 966 | |
| 967 | /* register virt channel to dma engine */ |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 968 | list_add_tail(&chan->chan.device_node, &pdev->device.channels); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 969 | |
| 970 | return 0; |
| 971 | } |
| 972 | |
| 973 | static struct of_device_id mmp_pdma_dt_ids[] = { |
| 974 | { .compatible = "marvell,pdma-1.0", }, |
| 975 | {} |
| 976 | }; |
| 977 | MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids); |
| 978 | |
Daniel Mack | a9a7cf0 | 2013-08-10 18:52:19 +0200 | [diff] [blame] | 979 | static struct dma_chan *mmp_pdma_dma_xlate(struct of_phandle_args *dma_spec, |
| 980 | struct of_dma *ofdma) |
| 981 | { |
| 982 | struct mmp_pdma_device *d = ofdma->of_dma_data; |
Stephen Warren | 8010dad | 2013-11-26 12:40:51 -0700 | [diff] [blame] | 983 | struct dma_chan *chan; |
Daniel Mack | a9a7cf0 | 2013-08-10 18:52:19 +0200 | [diff] [blame] | 984 | |
Stephen Warren | 8010dad | 2013-11-26 12:40:51 -0700 | [diff] [blame] | 985 | chan = dma_get_any_slave_channel(&d->device); |
| 986 | if (!chan) |
Daniel Mack | a9a7cf0 | 2013-08-10 18:52:19 +0200 | [diff] [blame] | 987 | return NULL; |
| 988 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 989 | to_mmp_pdma_chan(chan)->drcmr = dma_spec->args[0]; |
| 990 | |
| 991 | return chan; |
Daniel Mack | a9a7cf0 | 2013-08-10 18:52:19 +0200 | [diff] [blame] | 992 | } |
| 993 | |
Bill Pemberton | 463a1f8 | 2012-11-19 13:22:55 -0500 | [diff] [blame] | 994 | static int mmp_pdma_probe(struct platform_device *op) |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 995 | { |
| 996 | struct mmp_pdma_device *pdev; |
| 997 | const struct of_device_id *of_id; |
| 998 | struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev); |
| 999 | struct resource *iores; |
| 1000 | int i, ret, irq = 0; |
| 1001 | int dma_channels = 0, irq_num = 0; |
| 1002 | |
| 1003 | pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL); |
| 1004 | if (!pdev) |
| 1005 | return -ENOMEM; |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 1006 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1007 | pdev->dev = &op->dev; |
| 1008 | |
Xiang Wang | 027f28b | 2013-06-18 14:55:58 +0800 | [diff] [blame] | 1009 | spin_lock_init(&pdev->phy_lock); |
| 1010 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1011 | iores = platform_get_resource(op, IORESOURCE_MEM, 0); |
Thierry Reding | 7331205 | 2013-01-21 11:09:00 +0100 | [diff] [blame] | 1012 | pdev->base = devm_ioremap_resource(pdev->dev, iores); |
| 1013 | if (IS_ERR(pdev->base)) |
| 1014 | return PTR_ERR(pdev->base); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1015 | |
| 1016 | of_id = of_match_device(mmp_pdma_dt_ids, pdev->dev); |
| 1017 | if (of_id) |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 1018 | of_property_read_u32(pdev->dev->of_node, "#dma-channels", |
| 1019 | &dma_channels); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1020 | else if (pdata && pdata->dma_channels) |
| 1021 | dma_channels = pdata->dma_channels; |
| 1022 | else |
| 1023 | dma_channels = 32; /* default 32 channel */ |
| 1024 | pdev->dma_channels = dma_channels; |
| 1025 | |
| 1026 | for (i = 0; i < dma_channels; i++) { |
| 1027 | if (platform_get_irq(op, i) > 0) |
| 1028 | irq_num++; |
| 1029 | } |
| 1030 | |
Laurent Pinchart | 593d9c2 | 2014-04-15 17:13:35 +0200 | [diff] [blame] | 1031 | pdev->phy = devm_kcalloc(pdev->dev, dma_channels, sizeof(*pdev->phy), |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 1032 | GFP_KERNEL); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1033 | if (pdev->phy == NULL) |
| 1034 | return -ENOMEM; |
| 1035 | |
| 1036 | INIT_LIST_HEAD(&pdev->device.channels); |
| 1037 | |
| 1038 | if (irq_num != dma_channels) { |
| 1039 | /* all chan share one irq, demux inside */ |
| 1040 | irq = platform_get_irq(op, 0); |
Chao Xie | f0b5077 | 2014-01-27 09:44:07 +0800 | [diff] [blame] | 1041 | ret = devm_request_irq(pdev->dev, irq, mmp_pdma_int_handler, |
| 1042 | IRQF_SHARED, "pdma", pdev); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1043 | if (ret) |
| 1044 | return ret; |
| 1045 | } |
| 1046 | |
| 1047 | for (i = 0; i < dma_channels; i++) { |
| 1048 | irq = (irq_num != dma_channels) ? 0 : platform_get_irq(op, i); |
| 1049 | ret = mmp_pdma_chan_init(pdev, i, irq); |
| 1050 | if (ret) |
| 1051 | return ret; |
| 1052 | } |
| 1053 | |
| 1054 | dma_cap_set(DMA_SLAVE, pdev->device.cap_mask); |
| 1055 | dma_cap_set(DMA_MEMCPY, pdev->device.cap_mask); |
Daniel Mack | 50440d7 | 2013-08-21 14:08:56 +0200 | [diff] [blame] | 1056 | dma_cap_set(DMA_CYCLIC, pdev->device.cap_mask); |
Daniel Mack | 023bf55 | 2013-08-21 14:08:58 +0200 | [diff] [blame] | 1057 | dma_cap_set(DMA_PRIVATE, pdev->device.cap_mask); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1058 | pdev->device.dev = &op->dev; |
| 1059 | pdev->device.device_alloc_chan_resources = mmp_pdma_alloc_chan_resources; |
| 1060 | pdev->device.device_free_chan_resources = mmp_pdma_free_chan_resources; |
| 1061 | pdev->device.device_tx_status = mmp_pdma_tx_status; |
| 1062 | pdev->device.device_prep_dma_memcpy = mmp_pdma_prep_memcpy; |
| 1063 | pdev->device.device_prep_slave_sg = mmp_pdma_prep_slave_sg; |
Daniel Mack | 50440d7 | 2013-08-21 14:08:56 +0200 | [diff] [blame] | 1064 | pdev->device.device_prep_dma_cyclic = mmp_pdma_prep_dma_cyclic; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1065 | pdev->device.device_issue_pending = mmp_pdma_issue_pending; |
Maxime Ripard | a0abd67 | 2014-11-17 14:42:21 +0100 | [diff] [blame] | 1066 | pdev->device.device_config = mmp_pdma_config; |
| 1067 | pdev->device.device_terminate_all = mmp_pdma_terminate_all; |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1068 | pdev->device.copy_align = PDMA_ALIGNMENT; |
| 1069 | |
| 1070 | if (pdev->dev->coherent_dma_mask) |
| 1071 | dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask); |
| 1072 | else |
| 1073 | dma_set_mask(pdev->dev, DMA_BIT_MASK(64)); |
| 1074 | |
| 1075 | ret = dma_async_device_register(&pdev->device); |
| 1076 | if (ret) { |
| 1077 | dev_err(pdev->device.dev, "unable to register\n"); |
| 1078 | return ret; |
| 1079 | } |
| 1080 | |
Daniel Mack | a9a7cf0 | 2013-08-10 18:52:19 +0200 | [diff] [blame] | 1081 | if (op->dev.of_node) { |
| 1082 | /* Device-tree DMA controller registration */ |
| 1083 | ret = of_dma_controller_register(op->dev.of_node, |
| 1084 | mmp_pdma_dma_xlate, pdev); |
| 1085 | if (ret < 0) { |
| 1086 | dev_err(&op->dev, "of_dma_controller_register failed\n"); |
| 1087 | return ret; |
| 1088 | } |
| 1089 | } |
| 1090 | |
Wei Yongjun | 086b0af | 2013-11-25 15:15:14 +0800 | [diff] [blame] | 1091 | platform_set_drvdata(op, pdev); |
Daniel Mack | 419d1f1 | 2013-08-10 18:52:20 +0200 | [diff] [blame] | 1092 | dev_info(pdev->device.dev, "initialized %d channels\n", dma_channels); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1093 | return 0; |
| 1094 | } |
| 1095 | |
| 1096 | static const struct platform_device_id mmp_pdma_id_table[] = { |
| 1097 | { "mmp-pdma", }, |
| 1098 | { }, |
| 1099 | }; |
| 1100 | |
| 1101 | static struct platform_driver mmp_pdma_driver = { |
| 1102 | .driver = { |
| 1103 | .name = "mmp-pdma", |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1104 | .of_match_table = mmp_pdma_dt_ids, |
| 1105 | }, |
| 1106 | .id_table = mmp_pdma_id_table, |
| 1107 | .probe = mmp_pdma_probe, |
Bill Pemberton | a7d6e3e | 2012-11-19 13:20:04 -0500 | [diff] [blame] | 1108 | .remove = mmp_pdma_remove, |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1109 | }; |
| 1110 | |
Daniel Mack | 13b3006 | 2013-08-10 18:52:18 +0200 | [diff] [blame] | 1111 | bool mmp_pdma_filter_fn(struct dma_chan *chan, void *param) |
| 1112 | { |
| 1113 | struct mmp_pdma_chan *c = to_mmp_pdma_chan(chan); |
| 1114 | |
| 1115 | if (chan->device->dev->driver != &mmp_pdma_driver.driver) |
| 1116 | return false; |
| 1117 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 1118 | c->drcmr = *(unsigned int *)param; |
Daniel Mack | 13b3006 | 2013-08-10 18:52:18 +0200 | [diff] [blame] | 1119 | |
| 1120 | return true; |
| 1121 | } |
| 1122 | EXPORT_SYMBOL_GPL(mmp_pdma_filter_fn); |
| 1123 | |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1124 | module_platform_driver(mmp_pdma_driver); |
| 1125 | |
Joe Perches | 2b7f65b | 2013-11-17 12:12:56 -0800 | [diff] [blame] | 1126 | MODULE_DESCRIPTION("MARVELL MMP Peripheral DMA Driver"); |
Zhangfei Gao | c8acd6a | 2012-09-03 11:03:45 +0800 | [diff] [blame] | 1127 | MODULE_AUTHOR("Marvell International Ltd."); |
| 1128 | MODULE_LICENSE("GPL v2"); |