blob: 5064f3ea20f1b6f362928bd7a5b3cce39894b259 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Tejun Heo8c3d3d42013-05-14 11:09:50 -07004 * Maintained by: Tejun Heo <tj@kernel.org>
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04005 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090045#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050047#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048#include <linux/libata.h>
Anton Vorontsov365cfa12010-03-28 00:22:14 -040049#include "ahci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090052#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
Linus Torvalds1da177e2005-04-16 15:20:36 -070054enum {
Alessandro Rubini318893e2012-01-06 13:33:39 +010055 AHCI_PCI_BAR_STA2X11 = 0,
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -080056 AHCI_PCI_BAR_ENMOTUS = 2,
Alessandro Rubini318893e2012-01-06 13:33:39 +010057 AHCI_PCI_BAR_STANDARD = 5,
Tejun Heo441577e2010-03-29 10:32:39 +090058};
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Tejun Heo441577e2010-03-29 10:32:39 +090060enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nosntf,
Tejun Heo5f173102010-07-24 16:53:48 +020065 board_ahci_yes_fbs,
Tejun Heo441577e2010-03-29 10:32:39 +090066
67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090069 board_ahci_mcp77,
70 board_ahci_mcp89,
Tejun Heo441577e2010-03-29 10:32:39 +090071 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090080 board_ahci_mcp79 = board_ahci_mcp77,
Linus Torvalds1da177e2005-04-16 15:20:36 -070081};
82
Jeff Garzik2dcb4072007-10-19 06:42:56 -040083static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heoa1efdab2008-03-25 12:22:50 +090084static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
Tejun Heo438ac6d2007-03-02 17:31:26 +090088#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +090089static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +090091#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070092
Tejun Heofad16e72010-09-21 09:25:48 +020093static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95};
96
Tejun Heo029cfd62008-03-25 12:22:49 +090097static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +090099 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +0900100};
101
Tejun Heo029cfd62008-03-25 12:22:49 +0900102static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900104 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900105};
106
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100107static const struct ata_port_info ahci_port_info[] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900108 /* by features */
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530109 [board_ahci] = {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900110 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100111 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400112 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113 .port_ops = &ahci_ops,
114 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530115 [board_ahci_ign_iferr] = {
Tejun Heo417a1a62007-09-23 13:19:55 +0900116 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
117 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100118 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400119 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900120 .port_ops = &ahci_ops,
121 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530122 [board_ahci_nosntf] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900123 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
124 .flags = AHCI_FLAG_COMMON,
125 .pio_mask = ATA_PIO4,
126 .udma_mask = ATA_UDMA6,
127 .port_ops = &ahci_ops,
128 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530129 [board_ahci_yes_fbs] = {
Tejun Heo5f173102010-07-24 16:53:48 +0200130 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
135 },
Tejun Heo441577e2010-03-29 10:32:39 +0900136 /* by chipsets */
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530137 [board_ahci_mcp65] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900138 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
139 AHCI_HFLAG_YES_NCQ),
Tejun Heoae01b242011-03-16 11:14:55 +0100140 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
Tejun Heo83f2b962010-03-30 10:28:32 +0900141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530145 [board_ahci_mcp77] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530152 [board_ahci_mcp89] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
Tejun Heo441577e2010-03-29 10:32:39 +0900154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
158 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530159 [board_ahci_mv] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
161 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300162 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
Tejun Heo441577e2010-03-29 10:32:39 +0900163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530167 [board_ahci_sb600] = {
Tejun Heo417a1a62007-09-23 13:19:55 +0900168 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900169 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
170 AHCI_HFLAG_32BIT_ONLY),
Tejun Heo417a1a62007-09-23 13:19:55 +0900171 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100172 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400173 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800174 .port_ops = &ahci_pmp_retry_srst_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800175 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530176 [board_ahci_sb700] = { /* for SB700 and SB800 */
Shane Huangbd172432008-06-10 15:52:04 +0800177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800178 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100179 .pio_mask = ATA_PIO4,
Shane Huange39fc8c2008-02-22 05:00:31 -0800180 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800181 .port_ops = &ahci_pmp_retry_srst_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800182 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530183 [board_ahci_vt8251] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900184 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heoe297d992008-06-10 00:13:04 +0900185 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100186 .pio_mask = ATA_PIO4,
Tejun Heoe297d992008-06-10 00:13:04 +0900187 .udma_mask = ATA_UDMA6,
Tejun Heo441577e2010-03-29 10:32:39 +0900188 .port_ops = &ahci_vt8251_ops,
Shaohua Li1b677af2009-11-16 09:56:05 +0800189 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190};
191
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500192static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400193 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400194 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
195 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
196 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
197 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
198 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900199 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400200 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900204 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
Shaohua Li1b677af2009-11-16 09:56:05 +0800205 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
Tejun Heo7a234af2007-09-03 12:44:57 +0900206 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
207 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
209 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400221 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
222 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800223 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
Mark Goodwinb2dde6a2009-06-26 10:44:11 -0500224 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800225 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
David Milburnc1f57d92009-07-22 15:15:56 -0500226 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700228 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700229 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500230 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700231 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700232 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500233 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
Seth Heasley5623cab2010-01-12 17:00:18 -0800234 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
Seth Heasley992b3fb2010-09-09 09:44:56 -0700240 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
241 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
242 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
Seth Heasley64a39032011-03-11 11:57:42 -0800243 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
Seth Heasleya4a461a2011-01-10 12:57:17 -0800244 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
Seth Heasley181e3ce2011-04-20 08:45:20 -0700245 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
Seth Heasley2cab7a42011-07-14 16:50:49 -0700251 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
Seth Heasleyea4ace62012-01-23 16:27:30 -0800252 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
James Ralston77b12bc92012-08-09 09:02:31 -0700260 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
262 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
Seth Heasley29e674d2013-01-25 12:01:05 -0800268 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
269 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
270 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
271 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
272 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
James Ralstonefda3322013-02-21 11:08:51 -0800284 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
285 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
James Ralston151743f2013-02-08 17:34:47 -0800286 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
287 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
288 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
289 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
290 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
291 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
292 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
Seth Heasley1cfc7df2013-06-19 16:36:45 -0700294 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400295
Tejun Heoe34bb372007-02-26 20:24:03 +0900296 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
297 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
298 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Ben Hutchings1fefb8f2012-09-10 01:09:04 +0100299 /* JMicron 362B and 362C have an AHCI function with IDE class code */
300 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
301 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400302
303 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800304 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800305 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
306 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
307 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
308 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
309 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
310 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400311
Shane Huange2dd90b2009-07-29 11:34:49 +0800312 /* AMD */
Shane Huang5deab532009-10-13 11:14:00 +0800313 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
Shane Huangfafe5c3d82013-06-03 18:24:10 +0800314 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
Shane Huange2dd90b2009-07-29 11:34:49 +0800315 /* AMD is using RAID class only for ahci controllers */
316 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
317 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
318
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400319 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400320 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900321 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400322
323 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900324 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
325 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
326 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
327 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
328 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
329 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
330 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
331 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Tejun Heo441577e2010-03-29 10:32:39 +0900332 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
333 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
334 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
335 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
336 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
337 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
338 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
343 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
344 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
345 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
346 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
347 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
348 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
349 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
350 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
351 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
361 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
362 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
363 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
364 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
365 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
366 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
367 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
371 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
372 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
373 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
374 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
375 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
376 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
377 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
378 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
379 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
383 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
384 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
385 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
386 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
387 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
388 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
389 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
390 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
391 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
395 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
396 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
397 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
398 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
399 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
400 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
401 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
402 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
403 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
404 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
406 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
407 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400408
Jeff Garzik95916ed2006-07-29 04:10:14 -0400409 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900410 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
411 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
412 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400413
Alessandro Rubini318893e2012-01-06 13:33:39 +0100414 /* ST Microelectronics */
415 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
416
Jeff Garzikcd70c262007-07-08 02:29:42 -0400417 /* Marvell */
418 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100419 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600420 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
Anssi Hannula10aca062011-01-18 20:03:26 -0500421 .class = PCI_CLASS_STORAGE_SATA_AHCI,
422 .class_mask = 0xffffff,
Tejun Heo5f173102010-07-24 16:53:48 +0200423 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600424 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
Per Jessen467b41c2011-02-08 13:54:32 +0100425 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600426 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
Matt Johnson642d8922012-04-27 01:42:30 -0500427 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
George Spelvinfcce9a32013-05-29 10:20:35 +0900428 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
429 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600430 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
Alan Cox17c60c62012-09-04 16:07:18 +0100431 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
Myron Stowe69fd3152013-04-08 11:32:49 -0600432 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
Tejun Heo50be5e32010-11-29 15:57:14 +0100433 .driver_data = board_ahci_yes_fbs },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400434
Mark Nelsonc77a0362008-10-23 14:08:16 +1100435 /* Promise */
436 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
437
Keng-Yu Linc9703762011-11-09 01:47:36 -0500438 /* Asmedia */
Alan Cox7b4f6ec2012-09-04 16:25:25 +0100439 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
440 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
441 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
442 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
Keng-Yu Linc9703762011-11-09 01:47:36 -0500443
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -0800444 /* Enmotus */
445 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
446
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500447 /* Generic, PCI class code for AHCI */
448 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500449 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500450
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451 { } /* terminate list */
452};
453
454
455static struct pci_driver ahci_pci_driver = {
456 .name = DRV_NAME,
457 .id_table = ahci_pci_tbl,
458 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900459 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900460#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900461 .suspend = ahci_pci_device_suspend,
462 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900463#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464};
465
Alan Cox5b66c822008-09-03 14:48:34 +0100466#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
467static int marvell_enable;
468#else
469static int marvell_enable = 1;
470#endif
471module_param(marvell_enable, int, 0644);
472MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
473
474
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300475static void ahci_pci_save_initial_config(struct pci_dev *pdev,
476 struct ahci_host_priv *hpriv)
477{
478 unsigned int force_port_map = 0;
479 unsigned int mask_port_map = 0;
480
481 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
482 dev_info(&pdev->dev, "JMB361 has only one port\n");
483 force_port_map = 1;
484 }
485
486 /*
487 * Temporary Marvell 6145 hack: PATA port presence
488 * is asserted through the standard AHCI port
489 * presence register, as bit 4 (counting from 0)
490 */
491 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
492 if (pdev->device == 0x6121)
493 mask_port_map = 0x3;
494 else
495 mask_port_map = 0xf;
496 dev_info(&pdev->dev,
497 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
498 }
499
Anton Vorontsov1d513352010-03-03 20:17:37 +0300500 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
501 mask_port_map);
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300502}
503
Anton Vorontsov33030402010-03-03 20:17:39 +0300504static int ahci_pci_reset_controller(struct ata_host *host)
505{
506 struct pci_dev *pdev = to_pci_dev(host->dev);
507
508 ahci_reset_controller(host);
509
Tejun Heod91542c2006-07-26 15:59:26 +0900510 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300511 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heod91542c2006-07-26 15:59:26 +0900512 u16 tmp16;
513
514 /* configure PCS */
515 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +0900516 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
517 tmp16 |= hpriv->port_map;
518 pci_write_config_word(pdev, 0x92, tmp16);
519 }
Tejun Heod91542c2006-07-26 15:59:26 +0900520 }
521
522 return 0;
523}
524
Anton Vorontsov781d6552010-03-03 20:17:42 +0300525static void ahci_pci_init_controller(struct ata_host *host)
526{
527 struct ahci_host_priv *hpriv = host->private_data;
528 struct pci_dev *pdev = to_pci_dev(host->dev);
529 void __iomem *port_mmio;
530 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100531 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +0900532
Tejun Heo417a1a62007-09-23 13:19:55 +0900533 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100534 if (pdev->device == 0x6121)
535 mv = 2;
536 else
537 mv = 4;
538 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -0400539
540 writel(0, port_mmio + PORT_IRQ_MASK);
541
542 /* clear port IRQ */
543 tmp = readl(port_mmio + PORT_IRQ_STAT);
544 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
545 if (tmp)
546 writel(tmp, port_mmio + PORT_IRQ_STAT);
547 }
548
Anton Vorontsov781d6552010-03-03 20:17:42 +0300549 ahci_init_controller(host);
Tejun Heod91542c2006-07-26 15:59:26 +0900550}
551
Tejun Heocc0680a2007-08-06 18:36:23 +0900552static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +0900553 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +0900554{
Tejun Heocc0680a2007-08-06 18:36:23 +0900555 struct ata_port *ap = link->ap;
Tejun Heo9dadd452008-04-07 22:47:19 +0900556 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +0900557 int rc;
558
559 DPRINTK("ENTER\n");
560
Tejun Heo4447d352007-04-17 23:44:08 +0900561 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900562
Tejun Heocc0680a2007-08-06 18:36:23 +0900563 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900564 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +0900565
Tejun Heo4447d352007-04-17 23:44:08 +0900566 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900567
568 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
569
570 /* vt8251 doesn't clear BSY on signature FIS reception,
571 * request follow-up softreset.
572 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900573 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +0900574}
575
Tejun Heoedc93052007-10-25 14:59:16 +0900576static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
577 unsigned long deadline)
578{
579 struct ata_port *ap = link->ap;
580 struct ahci_port_priv *pp = ap->private_data;
581 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
582 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +0900583 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +0900584 int rc;
585
586 ahci_stop_engine(ap);
587
588 /* clear D2H reception area to properly wait for D2H FIS */
589 ata_tf_init(link->device, &tf);
Sergei Shtylyov9bbb1b02013-06-23 01:39:39 +0400590 tf.command = ATA_BUSY;
Tejun Heoedc93052007-10-25 14:59:16 +0900591 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
592
593 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900594 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +0900595
596 ahci_start_engine(ap);
597
Tejun Heoedc93052007-10-25 14:59:16 +0900598 /* The pseudo configuration device on SIMG4726 attached to
599 * ASUS P5W-DH Deluxe doesn't send signature FIS after
600 * hardreset if no device is attached to the first downstream
601 * port && the pseudo device locks up on SRST w/ PMP==0. To
602 * work around this, wait for !BSY only briefly. If BSY isn't
603 * cleared, perform CLO and proceed to IDENTIFY (achieved by
604 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
605 *
606 * Wait for two seconds. Devices attached to downstream port
607 * which can't process the following IDENTIFY after this will
608 * have to be reset again. For most cases, this should
609 * suffice while making probing snappish enough.
610 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900611 if (online) {
612 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
613 ahci_check_ready);
614 if (rc)
Shane Huang78d5ae32009-08-07 15:05:52 +0800615 ahci_kick_engine(ap);
Tejun Heo9dadd452008-04-07 22:47:19 +0900616 }
Tejun Heo9dadd452008-04-07 22:47:19 +0900617 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +0900618}
619
Tejun Heo438ac6d2007-03-02 17:31:26 +0900620#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900621static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
622{
Jingoo Han0a86e1c2013-06-03 14:05:36 +0900623 struct ata_host *host = pci_get_drvdata(pdev);
Tejun Heo9b10ae82009-05-30 20:50:12 +0900624 struct ahci_host_priv *hpriv = host->private_data;
Anton Vorontsovd8993342010-03-03 20:17:34 +0300625 void __iomem *mmio = hpriv->mmio;
Tejun Heoc1332872006-07-26 15:59:26 +0900626 u32 ctl;
627
Tejun Heo9b10ae82009-05-30 20:50:12 +0900628 if (mesg.event & PM_EVENT_SUSPEND &&
629 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700630 dev_err(&pdev->dev,
631 "BIOS update required for suspend/resume\n");
Tejun Heo9b10ae82009-05-30 20:50:12 +0900632 return -EIO;
633 }
634
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100635 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +0900636 /* AHCI spec rev1.1 section 8.3.3:
637 * Software must disable interrupts prior to requesting a
638 * transition of the HBA to D3 state.
639 */
640 ctl = readl(mmio + HOST_CTL);
641 ctl &= ~HOST_IRQ_EN;
642 writel(ctl, mmio + HOST_CTL);
643 readl(mmio + HOST_CTL); /* flush */
644 }
645
646 return ata_pci_device_suspend(pdev, mesg);
647}
648
649static int ahci_pci_device_resume(struct pci_dev *pdev)
650{
Jingoo Han0a86e1c2013-06-03 14:05:36 +0900651 struct ata_host *host = pci_get_drvdata(pdev);
Tejun Heoc1332872006-07-26 15:59:26 +0900652 int rc;
653
Tejun Heo553c4aa2006-12-26 19:39:50 +0900654 rc = ata_pci_device_do_resume(pdev);
655 if (rc)
656 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +0900657
658 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300659 rc = ahci_pci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900660 if (rc)
661 return rc;
662
Anton Vorontsov781d6552010-03-03 20:17:42 +0300663 ahci_pci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900664 }
665
Jeff Garzikcca39742006-08-24 03:19:22 -0400666 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900667
668 return 0;
669}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900670#endif
Tejun Heoc1332872006-07-26 15:59:26 +0900671
Tejun Heo4447d352007-04-17 23:44:08 +0900672static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675
Alessandro Rubini318893e2012-01-06 13:33:39 +0100676 /*
677 * If the device fixup already set the dma_mask to some non-standard
678 * value, don't extend it here. This happens on STA2X11, for example.
679 */
680 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
681 return 0;
682
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 if (using_dac &&
Yang Hongyang6a355282009-04-06 19:01:13 -0700684 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
685 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -0700687 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700689 dev_err(&pdev->dev,
690 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691 return rc;
692 }
693 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -0700695 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700697 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698 return rc;
699 }
Yang Hongyang284901a2009-04-06 19:01:15 -0700700 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700702 dev_err(&pdev->dev,
703 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704 return rc;
705 }
706 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707 return 0;
708}
709
Anton Vorontsov439fcae2010-03-03 20:17:43 +0300710static void ahci_pci_print_info(struct ata_host *host)
711{
712 struct pci_dev *pdev = to_pci_dev(host->dev);
713 u16 cc;
714 const char *scc_s;
715
716 pci_read_config_word(pdev, 0x0a, &cc);
717 if (cc == PCI_CLASS_STORAGE_IDE)
718 scc_s = "IDE";
719 else if (cc == PCI_CLASS_STORAGE_SATA)
720 scc_s = "SATA";
721 else if (cc == PCI_CLASS_STORAGE_RAID)
722 scc_s = "RAID";
723 else
724 scc_s = "unknown";
725
726 ahci_print_info(host, scc_s);
727}
728
Tejun Heoedc93052007-10-25 14:59:16 +0900729/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
730 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
731 * support PMP and the 4726 either directly exports the device
732 * attached to the first downstream port or acts as a hardware storage
733 * controller and emulate a single ATA device (can be RAID 0/1 or some
734 * other configuration).
735 *
736 * When there's no device attached to the first downstream port of the
737 * 4726, "Config Disk" appears, which is a pseudo ATA device to
738 * configure the 4726. However, ATA emulation of the device is very
739 * lame. It doesn't send signature D2H Reg FIS after the initial
740 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
741 *
742 * The following function works around the problem by always using
743 * hardreset on the port and not depending on receiving signature FIS
744 * afterward. If signature FIS isn't received soon, ATA class is
745 * assumed without follow-up softreset.
746 */
747static void ahci_p5wdh_workaround(struct ata_host *host)
748{
749 static struct dmi_system_id sysids[] = {
750 {
751 .ident = "P5W DH Deluxe",
752 .matches = {
753 DMI_MATCH(DMI_SYS_VENDOR,
754 "ASUSTEK COMPUTER INC"),
755 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
756 },
757 },
758 { }
759 };
760 struct pci_dev *pdev = to_pci_dev(host->dev);
761
762 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
763 dmi_check_system(sysids)) {
764 struct ata_port *ap = host->ports[1];
765
Joe Perchesa44fec12011-04-15 15:51:58 -0700766 dev_info(&pdev->dev,
767 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
Tejun Heoedc93052007-10-25 14:59:16 +0900768
769 ap->ops = &ahci_p5wdh_ops;
770 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
771 }
772}
773
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900774/* only some SB600 ahci controllers can do 64bit DMA */
775static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
Shane Huang58a09b32009-05-27 15:04:43 +0800776{
777 static const struct dmi_system_id sysids[] = {
Tejun Heo03d783b2009-08-16 21:04:02 +0900778 /*
779 * The oldest version known to be broken is 0901 and
780 * working is 1501 which was released on 2007-10-26.
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900781 * Enable 64bit DMA on 1501 and anything newer.
782 *
Tejun Heo03d783b2009-08-16 21:04:02 +0900783 * Please read bko#9412 for more info.
784 */
Shane Huang58a09b32009-05-27 15:04:43 +0800785 {
786 .ident = "ASUS M2A-VM",
787 .matches = {
788 DMI_MATCH(DMI_BOARD_VENDOR,
789 "ASUSTeK Computer INC."),
790 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
791 },
Tejun Heo03d783b2009-08-16 21:04:02 +0900792 .driver_data = "20071026", /* yyyymmdd */
Shane Huang58a09b32009-05-27 15:04:43 +0800793 },
Mark Nelsone65cc192009-11-03 20:06:48 +1100794 /*
795 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
796 * support 64bit DMA.
797 *
798 * BIOS versions earlier than 1.5 had the Manufacturer DMI
799 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
800 * This spelling mistake was fixed in BIOS version 1.5, so
801 * 1.5 and later have the Manufacturer as
802 * "MICRO-STAR INTERNATIONAL CO.,LTD".
803 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
804 *
805 * BIOS versions earlier than 1.9 had a Board Product Name
806 * DMI field of "MS-7376". This was changed to be
807 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
808 * match on DMI_BOARD_NAME of "MS-7376".
809 */
810 {
811 .ident = "MSI K9A2 Platinum",
812 .matches = {
813 DMI_MATCH(DMI_BOARD_VENDOR,
814 "MICRO-STAR INTER"),
815 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
816 },
817 },
Mark Nelson3c4aa912011-06-27 16:33:44 +1000818 /*
Mark Nelsonff0173c2012-06-28 12:32:14 +1000819 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
820 * 64bit DMA.
821 *
822 * This board also had the typo mentioned above in the
823 * Manufacturer DMI field (fixed in BIOS version 1.5), so
824 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
825 */
826 {
827 .ident = "MSI K9AGM2",
828 .matches = {
829 DMI_MATCH(DMI_BOARD_VENDOR,
830 "MICRO-STAR INTER"),
831 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
832 },
833 },
834 /*
Mark Nelson3c4aa912011-06-27 16:33:44 +1000835 * All BIOS versions for the Asus M3A support 64bit DMA.
836 * (all release versions from 0301 to 1206 were tested)
837 */
838 {
839 .ident = "ASUS M3A",
840 .matches = {
841 DMI_MATCH(DMI_BOARD_VENDOR,
842 "ASUSTeK Computer INC."),
843 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
844 },
845 },
Shane Huang58a09b32009-05-27 15:04:43 +0800846 { }
847 };
Tejun Heo03d783b2009-08-16 21:04:02 +0900848 const struct dmi_system_id *match;
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900849 int year, month, date;
850 char buf[9];
Shane Huang58a09b32009-05-27 15:04:43 +0800851
Tejun Heo03d783b2009-08-16 21:04:02 +0900852 match = dmi_first_match(sysids);
Shane Huang58a09b32009-05-27 15:04:43 +0800853 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
Tejun Heo03d783b2009-08-16 21:04:02 +0900854 !match)
Shane Huang58a09b32009-05-27 15:04:43 +0800855 return false;
856
Mark Nelsone65cc192009-11-03 20:06:48 +1100857 if (!match->driver_data)
858 goto enable_64bit;
859
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900860 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
861 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Shane Huang58a09b32009-05-27 15:04:43 +0800862
Mark Nelsone65cc192009-11-03 20:06:48 +1100863 if (strcmp(buf, match->driver_data) >= 0)
864 goto enable_64bit;
865 else {
Joe Perchesa44fec12011-04-15 15:51:58 -0700866 dev_warn(&pdev->dev,
867 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
868 match->ident);
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900869 return false;
870 }
Mark Nelsone65cc192009-11-03 20:06:48 +1100871
872enable_64bit:
Joe Perchesa44fec12011-04-15 15:51:58 -0700873 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
Mark Nelsone65cc192009-11-03 20:06:48 +1100874 return true;
Shane Huang58a09b32009-05-27 15:04:43 +0800875}
876
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100877static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
878{
879 static const struct dmi_system_id broken_systems[] = {
880 {
881 .ident = "HP Compaq nx6310",
882 .matches = {
883 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
884 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
885 },
886 /* PCI slot number of the controller */
887 .driver_data = (void *)0x1FUL,
888 },
Maciej Ruteckid2f9c062009-03-20 00:06:46 +0100889 {
890 .ident = "HP Compaq 6720s",
891 .matches = {
892 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
893 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
894 },
895 /* PCI slot number of the controller */
896 .driver_data = (void *)0x1FUL,
897 },
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100898
899 { } /* terminate list */
900 };
901 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
902
903 if (dmi) {
904 unsigned long slot = (unsigned long)dmi->driver_data;
905 /* apply the quirk only to on-board controllers */
906 return slot == PCI_SLOT(pdev->devfn);
907 }
908
909 return false;
910}
911
Tejun Heo9b10ae82009-05-30 20:50:12 +0900912static bool ahci_broken_suspend(struct pci_dev *pdev)
913{
914 static const struct dmi_system_id sysids[] = {
915 /*
916 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
917 * to the harddisk doesn't become online after
918 * resuming from STR. Warn and fail suspend.
Tejun Heo9deb3432010-03-16 09:50:26 +0900919 *
920 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
921 *
922 * Use dates instead of versions to match as HP is
923 * apparently recycling both product and version
924 * strings.
925 *
926 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
Tejun Heo9b10ae82009-05-30 20:50:12 +0900927 */
928 {
929 .ident = "dv4",
930 .matches = {
931 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
932 DMI_MATCH(DMI_PRODUCT_NAME,
933 "HP Pavilion dv4 Notebook PC"),
934 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900935 .driver_data = "20090105", /* F.30 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900936 },
937 {
938 .ident = "dv5",
939 .matches = {
940 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
941 DMI_MATCH(DMI_PRODUCT_NAME,
942 "HP Pavilion dv5 Notebook PC"),
943 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900944 .driver_data = "20090506", /* F.16 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900945 },
946 {
947 .ident = "dv6",
948 .matches = {
949 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
950 DMI_MATCH(DMI_PRODUCT_NAME,
951 "HP Pavilion dv6 Notebook PC"),
952 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900953 .driver_data = "20090423", /* F.21 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900954 },
955 {
956 .ident = "HDX18",
957 .matches = {
958 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
959 DMI_MATCH(DMI_PRODUCT_NAME,
960 "HP HDX18 Notebook PC"),
961 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900962 .driver_data = "20090430", /* F.23 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900963 },
Tejun Heocedc9bf2010-01-28 16:04:15 +0900964 /*
965 * Acer eMachines G725 has the same problem. BIOS
966 * V1.03 is known to be broken. V3.04 is known to
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300967 * work. Between, there are V1.06, V2.06 and V3.03
Tejun Heocedc9bf2010-01-28 16:04:15 +0900968 * that we don't have much idea about. For now,
969 * blacklist anything older than V3.04.
Tejun Heo9deb3432010-03-16 09:50:26 +0900970 *
971 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
Tejun Heocedc9bf2010-01-28 16:04:15 +0900972 */
973 {
974 .ident = "G725",
975 .matches = {
976 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
977 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
978 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900979 .driver_data = "20091216", /* V3.04 */
Tejun Heocedc9bf2010-01-28 16:04:15 +0900980 },
Tejun Heo9b10ae82009-05-30 20:50:12 +0900981 { } /* terminate list */
982 };
983 const struct dmi_system_id *dmi = dmi_first_match(sysids);
Tejun Heo9deb3432010-03-16 09:50:26 +0900984 int year, month, date;
985 char buf[9];
Tejun Heo9b10ae82009-05-30 20:50:12 +0900986
987 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
988 return false;
989
Tejun Heo9deb3432010-03-16 09:50:26 +0900990 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
991 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Tejun Heo9b10ae82009-05-30 20:50:12 +0900992
Tejun Heo9deb3432010-03-16 09:50:26 +0900993 return strcmp(buf, dmi->driver_data) < 0;
Tejun Heo9b10ae82009-05-30 20:50:12 +0900994}
995
Tejun Heo55946392009-08-04 14:30:08 +0900996static bool ahci_broken_online(struct pci_dev *pdev)
997{
998#define ENCODE_BUSDEVFN(bus, slot, func) \
999 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1000 static const struct dmi_system_id sysids[] = {
1001 /*
1002 * There are several gigabyte boards which use
1003 * SIMG5723s configured as hardware RAID. Certain
1004 * 5723 firmware revisions shipped there keep the link
1005 * online but fail to answer properly to SRST or
1006 * IDENTIFY when no device is attached downstream
1007 * causing libata to retry quite a few times leading
1008 * to excessive detection delay.
1009 *
1010 * As these firmwares respond to the second reset try
1011 * with invalid device signature, considering unknown
1012 * sig as offline works around the problem acceptably.
1013 */
1014 {
1015 .ident = "EP45-DQ6",
1016 .matches = {
1017 DMI_MATCH(DMI_BOARD_VENDOR,
1018 "Gigabyte Technology Co., Ltd."),
1019 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1020 },
1021 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1022 },
1023 {
1024 .ident = "EP45-DS5",
1025 .matches = {
1026 DMI_MATCH(DMI_BOARD_VENDOR,
1027 "Gigabyte Technology Co., Ltd."),
1028 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1029 },
1030 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1031 },
1032 { } /* terminate list */
1033 };
1034#undef ENCODE_BUSDEVFN
1035 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1036 unsigned int val;
1037
1038 if (!dmi)
1039 return false;
1040
1041 val = (unsigned long)dmi->driver_data;
1042
1043 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1044}
1045
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001046#ifdef CONFIG_ATA_ACPI
Tejun Heof80ae7e2009-09-16 04:18:03 +09001047static void ahci_gtf_filter_workaround(struct ata_host *host)
1048{
1049 static const struct dmi_system_id sysids[] = {
1050 /*
1051 * Aspire 3810T issues a bunch of SATA enable commands
1052 * via _GTF including an invalid one and one which is
1053 * rejected by the device. Among the successful ones
1054 * is FPDMA non-zero offset enable which when enabled
1055 * only on the drive side leads to NCQ command
1056 * failures. Filter it out.
1057 */
1058 {
1059 .ident = "Aspire 3810T",
1060 .matches = {
1061 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1062 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1063 },
1064 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1065 },
1066 { }
1067 };
1068 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1069 unsigned int filter;
1070 int i;
1071
1072 if (!dmi)
1073 return;
1074
1075 filter = (unsigned long)dmi->driver_data;
Joe Perchesa44fec12011-04-15 15:51:58 -07001076 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1077 filter, dmi->ident);
Tejun Heof80ae7e2009-09-16 04:18:03 +09001078
1079 for (i = 0; i < host->n_ports; i++) {
1080 struct ata_port *ap = host->ports[i];
1081 struct ata_link *link;
1082 struct ata_device *dev;
1083
1084 ata_for_each_link(link, ap, EDGE)
1085 ata_for_each_dev(dev, link, ALL)
1086 dev->gtf_filter |= filter;
1087 }
1088}
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001089#else
1090static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1091{}
1092#endif
Tejun Heof80ae7e2009-09-16 04:18:03 +09001093
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001094int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1095{
1096 int rc;
1097 unsigned int maxvec;
1098
1099 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1100 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1101 if (rc > 0) {
1102 if ((rc == maxvec) || (rc == 1))
1103 return rc;
1104 /*
1105 * Assume that advantage of multipe MSIs is negated,
1106 * so fallback to single MSI mode to save resources
1107 */
1108 pci_disable_msi(pdev);
1109 if (!pci_enable_msi(pdev))
1110 return 1;
1111 }
1112 }
1113
1114 pci_intx(pdev, 1);
1115 return 0;
1116}
1117
1118/**
1119 * ahci_host_activate - start AHCI host, request IRQs and register it
1120 * @host: target ATA host
1121 * @irq: base IRQ number to request
1122 * @n_msis: number of MSIs allocated for this host
1123 * @irq_handler: irq_handler used when requesting IRQs
1124 * @irq_flags: irq_flags used when requesting IRQs
1125 *
1126 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1127 * when multiple MSIs were allocated. That is one MSI per port, starting
1128 * from @irq.
1129 *
1130 * LOCKING:
1131 * Inherited from calling layer (may sleep).
1132 *
1133 * RETURNS:
1134 * 0 on success, -errno otherwise.
1135 */
1136int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1137{
1138 int i, rc;
1139
1140 /* Sharing Last Message among several ports is not supported */
1141 if (n_msis < host->n_ports)
1142 return -EINVAL;
1143
1144 rc = ata_host_start(host);
1145 if (rc)
1146 return rc;
1147
1148 for (i = 0; i < host->n_ports; i++) {
Alexander Gordeevb29900e2013-05-22 08:53:48 +09001149 struct ahci_port_priv *pp = host->ports[i]->private_data;
1150
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001151 rc = devm_request_threaded_irq(host->dev,
1152 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
Alexander Gordeevb29900e2013-05-22 08:53:48 +09001153 pp->irq_desc, host->ports[i]);
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001154 if (rc)
1155 goto out_free_irqs;
1156 }
1157
1158 for (i = 0; i < host->n_ports; i++)
1159 ata_port_desc(host->ports[i], "irq %d", irq + i);
1160
1161 rc = ata_host_register(host, &ahci_sht);
1162 if (rc)
1163 goto out_free_all_irqs;
1164
1165 return 0;
1166
1167out_free_all_irqs:
1168 i = host->n_ports;
1169out_free_irqs:
1170 for (i--; i >= 0; i--)
1171 devm_free_irq(host->dev, irq + i, host->ports[i]);
1172
1173 return rc;
1174}
1175
Tejun Heo24dc5f32007-01-20 16:00:28 +09001176static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001177{
Tejun Heoe297d992008-06-10 00:13:04 +09001178 unsigned int board_id = ent->driver_data;
1179 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09001180 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09001181 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001182 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09001183 struct ata_host *host;
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001184 int n_ports, n_msis, i, rc;
Alessandro Rubini318893e2012-01-06 13:33:39 +01001185 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001186
1187 VPRINTK("ENTER\n");
1188
Justin P. Mattockb429dd52010-07-03 07:29:25 -07001189 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001190
Joe Perches06296a12011-04-15 15:52:00 -07001191 ata_print_version_once(&pdev->dev, DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001192
Alan Cox5b66c822008-09-03 14:48:34 +01001193 /* The AHCI driver can only drive the SATA ports, the PATA driver
1194 can drive them all so if both drivers are selected make sure
1195 AHCI stays out of the way */
1196 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1197 return -ENODEV;
1198
Tejun Heoc6353b42010-06-17 11:42:22 +02001199 /*
1200 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1201 * ahci, use ata_generic instead.
1202 */
1203 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1204 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1205 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1206 pdev->subsystem_device == 0xcb89)
1207 return -ENODEV;
1208
Mark Nelson7a022672009-11-22 12:07:41 +11001209 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1210 * At the moment, we can only use the AHCI mode. Let the users know
1211 * that for SAS drives they're out of luck.
1212 */
1213 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
Joe Perchesa44fec12011-04-15 15:51:58 -07001214 dev_info(&pdev->dev,
1215 "PDC42819 can only drive SATA devices with this driver\n");
Mark Nelson7a022672009-11-22 12:07:41 +11001216
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -08001217 /* Both Connext and Enmotus devices use non-standard BARs */
Alessandro Rubini318893e2012-01-06 13:33:39 +01001218 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1219 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -08001220 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1221 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
Alessandro Rubini318893e2012-01-06 13:33:39 +01001222
Tejun Heo4447d352007-04-17 23:44:08 +09001223 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001224 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225 if (rc)
1226 return rc;
1227
Tejun Heodea55132008-03-11 19:52:31 +09001228 /* AHCI controllers often implement SFF compatible interface.
1229 * Grab all PCI BARs just in case.
1230 */
Alessandro Rubini318893e2012-01-06 13:33:39 +01001231 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001232 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001233 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001234 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001235 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001236
Tejun Heoc4f77922007-12-06 15:09:43 +09001237 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1238 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1239 u8 map;
1240
1241 /* ICH6s share the same PCI ID for both piix and ahci
1242 * modes. Enabling ahci mode while MAP indicates
1243 * combined mode is a bad idea. Yield to ata_piix.
1244 */
1245 pci_read_config_byte(pdev, ICH_MAP, &map);
1246 if (map & 0x3) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001247 dev_info(&pdev->dev,
1248 "controller is in combined mode, can't enable AHCI mode\n");
Tejun Heoc4f77922007-12-06 15:09:43 +09001249 return -ENODEV;
1250 }
1251 }
1252
Tejun Heo24dc5f32007-01-20 16:00:28 +09001253 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1254 if (!hpriv)
1255 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09001256 hpriv->flags |= (unsigned long)pi.private_data;
1257
Tejun Heoe297d992008-06-10 00:13:04 +09001258 /* MCP65 revision A1 and A2 can't do MSI */
1259 if (board_id == board_ahci_mcp65 &&
1260 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1261 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1262
Shane Huange427fe02008-12-30 10:53:41 +08001263 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1264 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1265 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1266
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001267 /* only some SB600s can do 64bit DMA */
1268 if (ahci_sb600_enable_64bit(pdev))
1269 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
Shane Huang58a09b32009-05-27 15:04:43 +08001270
Alessandro Rubini318893e2012-01-06 13:33:39 +01001271 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
Anton Vorontsovd8993342010-03-03 20:17:34 +03001272
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001273 n_msis = ahci_init_interrupts(pdev, hpriv);
1274 if (n_msis > 1)
1275 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1276
Tejun Heo4447d352007-04-17 23:44:08 +09001277 /* save initial config */
Anton Vorontsov394d6e52010-03-03 20:17:36 +03001278 ahci_pci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001279
Tejun Heo4447d352007-04-17 23:44:08 +09001280 /* prepare host */
Robert Hancock453d3132010-01-26 22:33:23 -06001281 if (hpriv->cap & HOST_CAP_NCQ) {
1282 pi.flags |= ATA_FLAG_NCQ;
Tejun Heo83f2b962010-03-30 10:28:32 +09001283 /*
1284 * Auto-activate optimization is supposed to be
1285 * supported on all AHCI controllers indicating NCQ
1286 * capability, but it seems to be broken on some
1287 * chipsets including NVIDIAs.
1288 */
1289 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
Robert Hancock453d3132010-01-26 22:33:23 -06001290 pi.flags |= ATA_FLAG_FPDMA_AA;
1291 }
Tejun Heo4447d352007-04-17 23:44:08 +09001292
Tejun Heo7d50b602007-09-23 13:19:54 +09001293 if (hpriv->cap & HOST_CAP_PMP)
1294 pi.flags |= ATA_FLAG_PMP;
1295
Anton Vorontsov0cbb0e72010-03-03 20:17:45 +03001296 ahci_set_em_messages(hpriv, &pi);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001297
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01001298 if (ahci_broken_system_poweroff(pdev)) {
1299 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1300 dev_info(&pdev->dev,
1301 "quirky BIOS, skipping spindown on poweroff\n");
1302 }
1303
Tejun Heo9b10ae82009-05-30 20:50:12 +09001304 if (ahci_broken_suspend(pdev)) {
1305 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
Joe Perchesa44fec12011-04-15 15:51:58 -07001306 dev_warn(&pdev->dev,
1307 "BIOS update required for suspend/resume\n");
Tejun Heo9b10ae82009-05-30 20:50:12 +09001308 }
1309
Tejun Heo55946392009-08-04 14:30:08 +09001310 if (ahci_broken_online(pdev)) {
1311 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1312 dev_info(&pdev->dev,
1313 "online status unreliable, applying workaround\n");
1314 }
1315
Tejun Heo837f5f82008-02-06 15:13:51 +09001316 /* CAP.NP sometimes indicate the index of the last enabled
1317 * port, at other times, that of the last possible port, so
1318 * determining the maximum port number requires looking at
1319 * both CAP.NP and port_map.
1320 */
1321 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1322
1323 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09001324 if (!host)
1325 return -ENOMEM;
Tejun Heo4447d352007-04-17 23:44:08 +09001326 host->private_data = hpriv;
1327
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001328 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
Arjan van de Ven886ad092009-01-09 15:54:07 -08001329 host->flags |= ATA_HOST_PARALLEL_SCAN;
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001330 else
1331 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
Arjan van de Ven886ad092009-01-09 15:54:07 -08001332
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001333 if (pi.flags & ATA_FLAG_EM)
1334 ahci_reset_em(host);
1335
Tejun Heo4447d352007-04-17 23:44:08 +09001336 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04001337 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09001338
Alessandro Rubini318893e2012-01-06 13:33:39 +01001339 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1340 ata_port_pbar_desc(ap, ahci_pci_bar,
Tejun Heocbcdd872007-08-18 13:14:55 +09001341 0x100 + ap->port_no * 0x80, "port");
1342
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001343 /* set enclosure management message type */
1344 if (ap->flags & ATA_FLAG_EM)
Harry Zhang008dbd62010-04-23 17:27:19 +08001345 ap->em_message_type = hpriv->em_msg_type;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001346
1347
Jeff Garzikdab632e2007-05-28 08:33:01 -04001348 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09001349 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04001350 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09001351 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352
Tejun Heoedc93052007-10-25 14:59:16 +09001353 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1354 ahci_p5wdh_workaround(host);
1355
Tejun Heof80ae7e2009-09-16 04:18:03 +09001356 /* apply gtf filter quirk */
1357 ahci_gtf_filter_workaround(host);
1358
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09001360 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001362 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363
Anton Vorontsov33030402010-03-03 20:17:39 +03001364 rc = ahci_pci_reset_controller(host);
Tejun Heo4447d352007-04-17 23:44:08 +09001365 if (rc)
1366 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001367
Anton Vorontsov781d6552010-03-03 20:17:42 +03001368 ahci_pci_init_controller(host);
Anton Vorontsov439fcae2010-03-03 20:17:43 +03001369 ahci_pci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370
Tejun Heo4447d352007-04-17 23:44:08 +09001371 pci_set_master(pdev);
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001372
1373 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1374 return ahci_host_activate(host, pdev->irq, n_msis);
1375
Tejun Heo4447d352007-04-17 23:44:08 +09001376 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1377 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04001378}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001379
Axel Lin2fc75da2012-04-19 13:43:05 +08001380module_pci_driver(ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001381
1382MODULE_AUTHOR("Jeff Garzik");
1383MODULE_DESCRIPTION("AHCI SATA low-level driver");
1384MODULE_LICENSE("GPL");
1385MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001386MODULE_VERSION(DRV_VERSION);