Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 1 | /* |
| 2 | * pxa168 clock framework source file |
| 3 | * |
| 4 | * Copyright (C) 2012 Marvell |
| 5 | * Chao Xie <xiechao.mail@gmail.com> |
| 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public |
| 8 | * License version 2. This program is licensed "as is" without any |
| 9 | * warranty of any kind, whether express or implied. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/spinlock.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/err.h> |
| 18 | |
| 19 | #include <mach/addr-map.h> |
| 20 | |
| 21 | #include "clk.h" |
| 22 | |
| 23 | #define APBC_RTC 0x28 |
| 24 | #define APBC_TWSI0 0x2c |
| 25 | #define APBC_KPC 0x30 |
| 26 | #define APBC_UART0 0x0 |
| 27 | #define APBC_UART1 0x4 |
| 28 | #define APBC_GPIO 0x8 |
| 29 | #define APBC_PWM0 0xc |
| 30 | #define APBC_PWM1 0x10 |
| 31 | #define APBC_PWM2 0x14 |
| 32 | #define APBC_PWM3 0x18 |
| 33 | #define APBC_SSP0 0x81c |
| 34 | #define APBC_SSP1 0x820 |
| 35 | #define APBC_SSP2 0x84c |
| 36 | #define APBC_SSP3 0x858 |
| 37 | #define APBC_SSP4 0x85c |
| 38 | #define APBC_TWSI1 0x6c |
| 39 | #define APBC_UART2 0x70 |
| 40 | #define APMU_SDH0 0x54 |
| 41 | #define APMU_SDH1 0x58 |
| 42 | #define APMU_USB 0x5c |
| 43 | #define APMU_DISP0 0x4c |
| 44 | #define APMU_CCIC0 0x50 |
| 45 | #define APMU_DFC 0x60 |
| 46 | #define MPMU_UART_PLL 0x14 |
| 47 | |
| 48 | static DEFINE_SPINLOCK(clk_lock); |
| 49 | |
| 50 | static struct clk_factor_masks uart_factor_masks = { |
| 51 | .factor = 2, |
| 52 | .num_mask = 0x1fff, |
| 53 | .den_mask = 0x1fff, |
| 54 | .num_shift = 16, |
| 55 | .den_shift = 0, |
| 56 | }; |
| 57 | |
| 58 | static struct clk_factor_tbl uart_factor_tbl[] = { |
| 59 | {.num = 8125, .den = 1536}, /*14.745MHZ */ |
| 60 | }; |
| 61 | |
| 62 | static const char *uart_parent[] = {"pll1_3_16", "uart_pll"}; |
| 63 | static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; |
| 64 | static const char *sdh_parent[] = {"pll1_12", "pll1_13"}; |
| 65 | static const char *disp_parent[] = {"pll1_2", "pll1_12"}; |
| 66 | static const char *ccic_parent[] = {"pll1_2", "pll1_12"}; |
| 67 | static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; |
| 68 | |
| 69 | void __init pxa168_clk_init(void) |
| 70 | { |
| 71 | struct clk *clk; |
| 72 | struct clk *uart_pll; |
| 73 | void __iomem *mpmu_base; |
| 74 | void __iomem *apmu_base; |
| 75 | void __iomem *apbc_base; |
| 76 | |
| 77 | mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K); |
| 78 | if (mpmu_base == NULL) { |
| 79 | pr_err("error to ioremap MPMU base\n"); |
| 80 | return; |
| 81 | } |
| 82 | |
| 83 | apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K); |
| 84 | if (apmu_base == NULL) { |
| 85 | pr_err("error to ioremap APMU base\n"); |
| 86 | return; |
| 87 | } |
| 88 | |
| 89 | apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K); |
| 90 | if (apbc_base == NULL) { |
| 91 | pr_err("error to ioremap APBC base\n"); |
| 92 | return; |
| 93 | } |
| 94 | |
| 95 | clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); |
| 96 | clk_register_clkdev(clk, "clk32", NULL); |
| 97 | |
| 98 | clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, |
| 99 | 26000000); |
| 100 | clk_register_clkdev(clk, "vctcxo", NULL); |
| 101 | |
| 102 | clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, |
| 103 | 624000000); |
| 104 | clk_register_clkdev(clk, "pll1", NULL); |
| 105 | |
| 106 | clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", |
| 107 | CLK_SET_RATE_PARENT, 1, 2); |
| 108 | clk_register_clkdev(clk, "pll1_2", NULL); |
| 109 | |
| 110 | clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", |
| 111 | CLK_SET_RATE_PARENT, 1, 2); |
| 112 | clk_register_clkdev(clk, "pll1_4", NULL); |
| 113 | |
| 114 | clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", |
| 115 | CLK_SET_RATE_PARENT, 1, 2); |
| 116 | clk_register_clkdev(clk, "pll1_8", NULL); |
| 117 | |
| 118 | clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", |
| 119 | CLK_SET_RATE_PARENT, 1, 2); |
| 120 | clk_register_clkdev(clk, "pll1_16", NULL); |
| 121 | |
| 122 | clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", |
| 123 | CLK_SET_RATE_PARENT, 1, 3); |
| 124 | clk_register_clkdev(clk, "pll1_6", NULL); |
| 125 | |
| 126 | clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", |
| 127 | CLK_SET_RATE_PARENT, 1, 2); |
| 128 | clk_register_clkdev(clk, "pll1_12", NULL); |
| 129 | |
| 130 | clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", |
| 131 | CLK_SET_RATE_PARENT, 1, 2); |
| 132 | clk_register_clkdev(clk, "pll1_24", NULL); |
| 133 | |
| 134 | clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", |
| 135 | CLK_SET_RATE_PARENT, 1, 2); |
| 136 | clk_register_clkdev(clk, "pll1_48", NULL); |
| 137 | |
| 138 | clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", |
| 139 | CLK_SET_RATE_PARENT, 1, 2); |
| 140 | clk_register_clkdev(clk, "pll1_96", NULL); |
| 141 | |
| 142 | clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", |
| 143 | CLK_SET_RATE_PARENT, 1, 13); |
| 144 | clk_register_clkdev(clk, "pll1_13", NULL); |
| 145 | |
| 146 | clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", |
| 147 | CLK_SET_RATE_PARENT, 2, 3); |
| 148 | clk_register_clkdev(clk, "pll1_13_1_5", NULL); |
| 149 | |
| 150 | clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", |
| 151 | CLK_SET_RATE_PARENT, 2, 3); |
| 152 | clk_register_clkdev(clk, "pll1_2_1_5", NULL); |
| 153 | |
| 154 | clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", |
| 155 | CLK_SET_RATE_PARENT, 3, 16); |
| 156 | clk_register_clkdev(clk, "pll1_3_16", NULL); |
| 157 | |
| 158 | uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0, |
| 159 | mpmu_base + MPMU_UART_PLL, |
| 160 | &uart_factor_masks, uart_factor_tbl, |
| 161 | ARRAY_SIZE(uart_factor_tbl)); |
| 162 | clk_set_rate(uart_pll, 14745600); |
| 163 | clk_register_clkdev(uart_pll, "uart_pll", NULL); |
| 164 | |
| 165 | clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", |
| 166 | apbc_base + APBC_TWSI0, 10, 0, &clk_lock); |
| 167 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); |
| 168 | |
| 169 | clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", |
| 170 | apbc_base + APBC_TWSI1, 10, 0, &clk_lock); |
| 171 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); |
| 172 | |
| 173 | clk = mmp_clk_register_apbc("gpio", "vctcxo", |
| 174 | apbc_base + APBC_GPIO, 10, 0, &clk_lock); |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 175 | clk_register_clkdev(clk, NULL, "mmp-gpio"); |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 176 | |
| 177 | clk = mmp_clk_register_apbc("kpc", "clk32", |
| 178 | apbc_base + APBC_KPC, 10, 0, &clk_lock); |
| 179 | clk_register_clkdev(clk, NULL, "pxa27x-keypad"); |
| 180 | |
| 181 | clk = mmp_clk_register_apbc("rtc", "clk32", |
| 182 | apbc_base + APBC_RTC, 10, 0, &clk_lock); |
| 183 | clk_register_clkdev(clk, NULL, "sa1100-rtc"); |
| 184 | |
| 185 | clk = mmp_clk_register_apbc("pwm0", "pll1_48", |
| 186 | apbc_base + APBC_PWM0, 10, 0, &clk_lock); |
| 187 | clk_register_clkdev(clk, NULL, "pxa168-pwm.0"); |
| 188 | |
| 189 | clk = mmp_clk_register_apbc("pwm1", "pll1_48", |
| 190 | apbc_base + APBC_PWM1, 10, 0, &clk_lock); |
| 191 | clk_register_clkdev(clk, NULL, "pxa168-pwm.1"); |
| 192 | |
| 193 | clk = mmp_clk_register_apbc("pwm2", "pll1_48", |
| 194 | apbc_base + APBC_PWM2, 10, 0, &clk_lock); |
| 195 | clk_register_clkdev(clk, NULL, "pxa168-pwm.2"); |
| 196 | |
| 197 | clk = mmp_clk_register_apbc("pwm3", "pll1_48", |
| 198 | apbc_base + APBC_PWM3, 10, 0, &clk_lock); |
| 199 | clk_register_clkdev(clk, NULL, "pxa168-pwm.3"); |
| 200 | |
| 201 | clk = clk_register_mux(NULL, "uart0_mux", uart_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 202 | ARRAY_SIZE(uart_parent), |
| 203 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 204 | apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); |
| 205 | clk_set_parent(clk, uart_pll); |
| 206 | clk_register_clkdev(clk, "uart_mux.0", NULL); |
| 207 | |
| 208 | clk = mmp_clk_register_apbc("uart0", "uart0_mux", |
| 209 | apbc_base + APBC_UART0, 10, 0, &clk_lock); |
| 210 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); |
| 211 | |
| 212 | clk = clk_register_mux(NULL, "uart1_mux", uart_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 213 | ARRAY_SIZE(uart_parent), |
| 214 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 215 | apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); |
| 216 | clk_set_parent(clk, uart_pll); |
| 217 | clk_register_clkdev(clk, "uart_mux.1", NULL); |
| 218 | |
| 219 | clk = mmp_clk_register_apbc("uart1", "uart1_mux", |
| 220 | apbc_base + APBC_UART1, 10, 0, &clk_lock); |
| 221 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); |
| 222 | |
| 223 | clk = clk_register_mux(NULL, "uart2_mux", uart_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 224 | ARRAY_SIZE(uart_parent), |
| 225 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 226 | apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); |
| 227 | clk_set_parent(clk, uart_pll); |
| 228 | clk_register_clkdev(clk, "uart_mux.2", NULL); |
| 229 | |
| 230 | clk = mmp_clk_register_apbc("uart2", "uart2_mux", |
| 231 | apbc_base + APBC_UART2, 10, 0, &clk_lock); |
| 232 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); |
| 233 | |
| 234 | clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 235 | ARRAY_SIZE(ssp_parent), |
| 236 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 237 | apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); |
| 238 | clk_register_clkdev(clk, "uart_mux.0", NULL); |
| 239 | |
| 240 | clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, |
| 241 | 10, 0, &clk_lock); |
| 242 | clk_register_clkdev(clk, NULL, "mmp-ssp.0"); |
| 243 | |
| 244 | clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 245 | ARRAY_SIZE(ssp_parent), |
| 246 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 247 | apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); |
| 248 | clk_register_clkdev(clk, "ssp_mux.1", NULL); |
| 249 | |
| 250 | clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, |
| 251 | 10, 0, &clk_lock); |
| 252 | clk_register_clkdev(clk, NULL, "mmp-ssp.1"); |
| 253 | |
| 254 | clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 255 | ARRAY_SIZE(ssp_parent), |
| 256 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 257 | apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); |
| 258 | clk_register_clkdev(clk, "ssp_mux.2", NULL); |
| 259 | |
| 260 | clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, |
| 261 | 10, 0, &clk_lock); |
| 262 | clk_register_clkdev(clk, NULL, "mmp-ssp.2"); |
| 263 | |
| 264 | clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 265 | ARRAY_SIZE(ssp_parent), |
| 266 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 267 | apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); |
| 268 | clk_register_clkdev(clk, "ssp_mux.3", NULL); |
| 269 | |
| 270 | clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3, |
| 271 | 10, 0, &clk_lock); |
| 272 | clk_register_clkdev(clk, NULL, "mmp-ssp.3"); |
| 273 | |
| 274 | clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 275 | ARRAY_SIZE(ssp_parent), |
| 276 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 277 | apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); |
| 278 | clk_register_clkdev(clk, "ssp_mux.4", NULL); |
| 279 | |
| 280 | clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4, |
| 281 | 10, 0, &clk_lock); |
| 282 | clk_register_clkdev(clk, NULL, "mmp-ssp.4"); |
| 283 | |
| 284 | clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, |
| 285 | 0x19b, &clk_lock); |
| 286 | clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); |
| 287 | |
| 288 | clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 289 | ARRAY_SIZE(sdh_parent), |
| 290 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 291 | apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); |
| 292 | clk_register_clkdev(clk, "sdh0_mux", NULL); |
| 293 | |
| 294 | clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0, |
| 295 | 0x1b, &clk_lock); |
| 296 | clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); |
| 297 | |
| 298 | clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 299 | ARRAY_SIZE(sdh_parent), |
| 300 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 301 | apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); |
| 302 | clk_register_clkdev(clk, "sdh1_mux", NULL); |
| 303 | |
| 304 | clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1, |
| 305 | 0x1b, &clk_lock); |
| 306 | clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); |
| 307 | |
| 308 | clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, |
| 309 | 0x9, &clk_lock); |
| 310 | clk_register_clkdev(clk, "usb_clk", NULL); |
| 311 | |
| 312 | clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, |
| 313 | 0x12, &clk_lock); |
| 314 | clk_register_clkdev(clk, "sph_clk", NULL); |
| 315 | |
| 316 | clk = clk_register_mux(NULL, "disp0_mux", disp_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 317 | ARRAY_SIZE(disp_parent), |
| 318 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 319 | apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); |
| 320 | clk_register_clkdev(clk, "disp_mux.0", NULL); |
| 321 | |
| 322 | clk = mmp_clk_register_apmu("disp0", "disp0_mux", |
| 323 | apmu_base + APMU_DISP0, 0x1b, &clk_lock); |
| 324 | clk_register_clkdev(clk, "fnclk", "mmp-disp.0"); |
| 325 | |
| 326 | clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux", |
| 327 | apmu_base + APMU_DISP0, 0x24, &clk_lock); |
| 328 | clk_register_clkdev(clk, "hclk", "mmp-disp.0"); |
| 329 | |
| 330 | clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 331 | ARRAY_SIZE(ccic_parent), |
| 332 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 333 | apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); |
| 334 | clk_register_clkdev(clk, "ccic_mux.0", NULL); |
| 335 | |
| 336 | clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", |
| 337 | apmu_base + APMU_CCIC0, 0x1b, &clk_lock); |
| 338 | clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); |
| 339 | |
| 340 | clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, |
| 341 | ARRAY_SIZE(ccic_phy_parent), |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 342 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
| 343 | apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); |
Chao Xie | e1b53b3 | 2012-08-20 02:55:12 +0000 | [diff] [blame] | 344 | clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); |
| 345 | |
| 346 | clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", |
| 347 | apmu_base + APMU_CCIC0, 0x24, &clk_lock); |
| 348 | clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); |
| 349 | |
| 350 | clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", |
| 351 | CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, |
| 352 | 10, 5, 0, &clk_lock); |
| 353 | clk_register_clkdev(clk, "sphyclk_div", NULL); |
| 354 | |
| 355 | clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", |
| 356 | apmu_base + APMU_CCIC0, 0x300, &clk_lock); |
| 357 | clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); |
| 358 | } |