Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Keith Packard <keithp@keithp.com> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include <linux/seq_file.h> |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 30 | #include <linux/circ_buf.h> |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 31 | #include <linux/ctype.h> |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 32 | #include <linux/debugfs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 33 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 34 | #include <linux/export.h> |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 35 | #include <linux/list_sort.h> |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 36 | #include <asm/msr-index.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/drmP.h> |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 38 | #include "intel_drv.h" |
Chris Wilson | e5c6526 | 2010-11-01 11:35:28 +0000 | [diff] [blame] | 39 | #include "intel_ringbuffer.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 40 | #include <drm/i915_drm.h> |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 41 | #include "i915_drv.h" |
| 42 | |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 43 | enum { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 44 | ACTIVE_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 45 | INACTIVE_LIST, |
Chris Wilson | d21d597 | 2010-09-26 11:19:33 +0100 | [diff] [blame] | 46 | PINNED_LIST, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 47 | }; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 48 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 49 | static const char *yesno(int v) |
| 50 | { |
| 51 | return v ? "yes" : "no"; |
| 52 | } |
| 53 | |
Damien Lespiau | 497666d | 2013-10-15 18:55:39 +0100 | [diff] [blame] | 54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
| 55 | * allocated we need to hook into the minor for release. */ |
| 56 | static int |
| 57 | drm_add_fake_info_node(struct drm_minor *minor, |
| 58 | struct dentry *ent, |
| 59 | const void *key) |
| 60 | { |
| 61 | struct drm_info_node *node; |
| 62 | |
| 63 | node = kmalloc(sizeof(*node), GFP_KERNEL); |
| 64 | if (node == NULL) { |
| 65 | debugfs_remove(ent); |
| 66 | return -ENOMEM; |
| 67 | } |
| 68 | |
| 69 | node->minor = minor; |
| 70 | node->dent = ent; |
| 71 | node->info_ent = (void *) key; |
| 72 | |
| 73 | mutex_lock(&minor->debugfs_lock); |
| 74 | list_add(&node->list, &minor->debugfs_list); |
| 75 | mutex_unlock(&minor->debugfs_lock); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 80 | static int i915_capabilities(struct seq_file *m, void *data) |
| 81 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 82 | struct drm_info_node *node = m->private; |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 83 | struct drm_device *dev = node->minor->dev; |
| 84 | const struct intel_device_info *info = INTEL_INFO(dev); |
| 85 | |
| 86 | seq_printf(m, "gen: %d\n", info->gen); |
Paulo Zanoni | 03d00ac | 2011-10-14 18:17:41 -0300 | [diff] [blame] | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
| 89 | #define SEP_SEMICOLON ; |
| 90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); |
| 91 | #undef PRINT_FLAG |
| 92 | #undef SEP_SEMICOLON |
Chris Wilson | 70d39fe | 2010-08-25 16:03:34 +0100 | [diff] [blame] | 93 | |
| 94 | return 0; |
| 95 | } |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 96 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 98 | { |
Daniel Vetter | 4feb765 | 2014-11-24 11:21:52 +0100 | [diff] [blame] | 99 | if (i915_gem_obj_is_pinned(obj)) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 100 | return "p"; |
| 101 | else |
| 102 | return " "; |
| 103 | } |
| 104 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 105 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 106 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 107 | switch (obj->tiling_mode) { |
| 108 | default: |
| 109 | case I915_TILING_NONE: return " "; |
| 110 | case I915_TILING_X: return "X"; |
| 111 | case I915_TILING_Y: return "Y"; |
| 112 | } |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 113 | } |
| 114 | |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 115 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
| 116 | { |
Tvrtko Ursulin | aff4376 | 2014-10-24 12:42:33 +0100 | [diff] [blame] | 117 | return i915_gem_obj_to_ggtt(obj) ? "g" : " "; |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 118 | } |
| 119 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 120 | static void |
| 121 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) |
| 122 | { |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 123 | struct i915_vma *vma; |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 124 | int pin_count = 0; |
| 125 | |
Ville Syrjälä | fb1ae91 | 2013-08-22 19:21:30 +0300 | [diff] [blame] | 126 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 127 | &obj->base, |
| 128 | get_pin_flag(obj), |
| 129 | get_tiling_flag(obj), |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 130 | get_global_flag(obj), |
Eric Anholt | a05a586 | 2011-12-20 08:54:15 -0800 | [diff] [blame] | 131 | obj->base.size / 1024, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 132 | obj->base.read_domains, |
| 133 | obj->base.write_domain, |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 134 | i915_gem_request_get_seqno(obj->last_read_req), |
| 135 | i915_gem_request_get_seqno(obj->last_write_req), |
| 136 | i915_gem_request_get_seqno(obj->last_fenced_req), |
Chris Wilson | 0a4cd7c | 2014-08-22 14:41:39 +0100 | [diff] [blame] | 137 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 138 | obj->dirty ? " dirty" : "", |
| 139 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); |
| 140 | if (obj->base.name) |
| 141 | seq_printf(m, " (name: %d)", obj->base.name); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 142 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 143 | if (vma->pin_count > 0) |
| 144 | pin_count++; |
| 145 | seq_printf(m, " (pinned x %d)", pin_count); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 146 | if (obj->pin_display) |
| 147 | seq_printf(m, " (display)"); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 148 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
| 149 | seq_printf(m, " (fence: %d)", obj->fence_reg); |
Ben Widawsky | 1d693bc | 2013-07-31 17:00:00 -0700 | [diff] [blame] | 150 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 151 | if (!i915_is_ggtt(vma->vm)) |
| 152 | seq_puts(m, " (pp"); |
| 153 | else |
| 154 | seq_puts(m, " (g"); |
| 155 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", |
| 156 | vma->node.start, vma->node.size); |
| 157 | } |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 158 | if (obj->stolen) |
| 159 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 160 | if (obj->pin_mappable || obj->fault_mappable) { |
| 161 | char s[3], *t = s; |
| 162 | if (obj->pin_mappable) |
| 163 | *t++ = 'p'; |
| 164 | if (obj->fault_mappable) |
| 165 | *t++ = 'f'; |
| 166 | *t = '\0'; |
| 167 | seq_printf(m, " (%s mappable)", s); |
| 168 | } |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 169 | if (obj->last_read_req != NULL) |
| 170 | seq_printf(m, " (%s)", |
| 171 | i915_gem_request_get_ring(obj->last_read_req)->name); |
Daniel Vetter | d5a81ef | 2014-06-18 14:46:49 +0200 | [diff] [blame] | 172 | if (obj->frontbuffer_bits) |
| 173 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 174 | } |
| 175 | |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 176 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 177 | { |
Oscar Mateo | ea0c76f | 2014-07-03 16:27:59 +0100 | [diff] [blame] | 178 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 179 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
| 180 | seq_putc(m, ' '); |
| 181 | } |
| 182 | |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 183 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 184 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 185 | struct drm_info_node *node = m->private; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 186 | uintptr_t list = (uintptr_t) node->info_ent->data; |
| 187 | struct list_head *head; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 188 | struct drm_device *dev = node->minor->dev; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 189 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 190 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 191 | struct i915_vma *vma; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 192 | size_t total_obj_size, total_gtt_size; |
| 193 | int count, ret; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 194 | |
| 195 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 196 | if (ret) |
| 197 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 198 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 199 | /* FIXME: the user of this interface might want more than just GGTT */ |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 200 | switch (list) { |
| 201 | case ACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 202 | seq_puts(m, "Active:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 203 | head = &vm->active_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 204 | break; |
| 205 | case INACTIVE_LIST: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 206 | seq_puts(m, "Inactive:\n"); |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 207 | head = &vm->inactive_list; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 208 | break; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 209 | default: |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 210 | mutex_unlock(&dev->struct_mutex); |
| 211 | return -EINVAL; |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 212 | } |
| 213 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 214 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 215 | list_for_each_entry(vma, head, mm_list) { |
| 216 | seq_printf(m, " "); |
| 217 | describe_obj(m, vma->obj); |
| 218 | seq_printf(m, "\n"); |
| 219 | total_obj_size += vma->obj->base.size; |
| 220 | total_gtt_size += vma->node.size; |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 221 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 222 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 223 | mutex_unlock(&dev->struct_mutex); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 224 | |
Chris Wilson | 8f2480f | 2010-09-26 11:44:19 +0100 | [diff] [blame] | 225 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 226 | count, total_obj_size, total_gtt_size); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 227 | return 0; |
| 228 | } |
| 229 | |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 230 | static int obj_rank_by_stolen(void *priv, |
| 231 | struct list_head *A, struct list_head *B) |
| 232 | { |
| 233 | struct drm_i915_gem_object *a = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 234 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 235 | struct drm_i915_gem_object *b = |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 236 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 237 | |
| 238 | return a->stolen->start - b->stolen->start; |
| 239 | } |
| 240 | |
| 241 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) |
| 242 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 243 | struct drm_info_node *node = m->private; |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 244 | struct drm_device *dev = node->minor->dev; |
| 245 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 246 | struct drm_i915_gem_object *obj; |
| 247 | size_t total_obj_size, total_gtt_size; |
| 248 | LIST_HEAD(stolen); |
| 249 | int count, ret; |
| 250 | |
| 251 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 252 | if (ret) |
| 253 | return ret; |
| 254 | |
| 255 | total_obj_size = total_gtt_size = count = 0; |
| 256 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 257 | if (obj->stolen == NULL) |
| 258 | continue; |
| 259 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 260 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 261 | |
| 262 | total_obj_size += obj->base.size; |
| 263 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
| 264 | count++; |
| 265 | } |
| 266 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
| 267 | if (obj->stolen == NULL) |
| 268 | continue; |
| 269 | |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 270 | list_add(&obj->obj_exec_link, &stolen); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 271 | |
| 272 | total_obj_size += obj->base.size; |
| 273 | count++; |
| 274 | } |
| 275 | list_sort(NULL, &stolen, obj_rank_by_stolen); |
| 276 | seq_puts(m, "Stolen:\n"); |
| 277 | while (!list_empty(&stolen)) { |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 278 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 279 | seq_puts(m, " "); |
| 280 | describe_obj(m, obj); |
| 281 | seq_putc(m, '\n'); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 282 | list_del_init(&obj->obj_exec_link); |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 283 | } |
| 284 | mutex_unlock(&dev->struct_mutex); |
| 285 | |
| 286 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 287 | count, total_obj_size, total_gtt_size); |
| 288 | return 0; |
| 289 | } |
| 290 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 291 | #define count_objects(list, member) do { \ |
| 292 | list_for_each_entry(obj, list, member) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 293 | size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 294 | ++count; \ |
| 295 | if (obj->map_and_fenceable) { \ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 296 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 297 | ++mappable_count; \ |
| 298 | } \ |
| 299 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 300 | } while (0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 301 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 302 | struct file_stats { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 303 | struct drm_i915_file_private *file_priv; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 304 | int count; |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 305 | size_t total, unbound; |
| 306 | size_t global, shared; |
| 307 | size_t active, inactive; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 308 | }; |
| 309 | |
| 310 | static int per_file_stats(int id, void *ptr, void *data) |
| 311 | { |
| 312 | struct drm_i915_gem_object *obj = ptr; |
| 313 | struct file_stats *stats = data; |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 314 | struct i915_vma *vma; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 315 | |
| 316 | stats->count++; |
| 317 | stats->total += obj->base.size; |
| 318 | |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 319 | if (obj->base.name || obj->base.dma_buf) |
| 320 | stats->shared += obj->base.size; |
| 321 | |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 322 | if (USES_FULL_PPGTT(obj->base.dev)) { |
| 323 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 324 | struct i915_hw_ppgtt *ppgtt; |
| 325 | |
| 326 | if (!drm_mm_node_allocated(&vma->node)) |
| 327 | continue; |
| 328 | |
| 329 | if (i915_is_ggtt(vma->vm)) { |
| 330 | stats->global += obj->base.size; |
| 331 | continue; |
| 332 | } |
| 333 | |
| 334 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); |
Daniel Vetter | 4d88470 | 2014-08-06 15:04:47 +0200 | [diff] [blame] | 335 | if (ppgtt->file_priv != stats->file_priv) |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 336 | continue; |
| 337 | |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 338 | if (obj->active) /* XXX per-vma statistic */ |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 339 | stats->active += obj->base.size; |
| 340 | else |
| 341 | stats->inactive += obj->base.size; |
| 342 | |
| 343 | return 0; |
| 344 | } |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 345 | } else { |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 346 | if (i915_gem_obj_ggtt_bound(obj)) { |
| 347 | stats->global += obj->base.size; |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 348 | if (obj->active) |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 349 | stats->active += obj->base.size; |
| 350 | else |
| 351 | stats->inactive += obj->base.size; |
| 352 | return 0; |
| 353 | } |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 354 | } |
| 355 | |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 356 | if (!list_empty(&obj->global_list)) |
| 357 | stats->unbound += obj->base.size; |
| 358 | |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 359 | return 0; |
| 360 | } |
| 361 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 362 | #define count_vmas(list, member) do { \ |
| 363 | list_for_each_entry(vma, list, member) { \ |
| 364 | size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 365 | ++count; \ |
| 366 | if (vma->obj->map_and_fenceable) { \ |
| 367 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ |
| 368 | ++mappable_count; \ |
| 369 | } \ |
| 370 | } \ |
| 371 | } while (0) |
| 372 | |
| 373 | static int i915_gem_object_info(struct seq_file *m, void* data) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 374 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 375 | struct drm_info_node *node = m->private; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 376 | struct drm_device *dev = node->minor->dev; |
| 377 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 378 | u32 count, mappable_count, purgeable_count; |
| 379 | size_t size, mappable_size, purgeable_size; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 380 | struct drm_i915_gem_object *obj; |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 381 | struct i915_address_space *vm = &dev_priv->gtt.base; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 382 | struct drm_file *file; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 383 | struct i915_vma *vma; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 384 | int ret; |
| 385 | |
| 386 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 387 | if (ret) |
| 388 | return ret; |
| 389 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 390 | seq_printf(m, "%u objects, %zu bytes\n", |
| 391 | dev_priv->mm.object_count, |
| 392 | dev_priv->mm.object_memory); |
| 393 | |
| 394 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 395 | count_objects(&dev_priv->mm.bound_list, global_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 396 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
| 397 | count, mappable_count, size, mappable_size); |
| 398 | |
| 399 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 400 | count_vmas(&vm->active_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 401 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
| 402 | count, mappable_count, size, mappable_size); |
| 403 | |
| 404 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 405 | count_vmas(&vm->inactive_list, mm_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 406 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
| 407 | count, mappable_count, size, mappable_size); |
| 408 | |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 409 | size = count = purgeable_size = purgeable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 410 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 411 | size += obj->base.size, ++count; |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 412 | if (obj->madv == I915_MADV_DONTNEED) |
| 413 | purgeable_size += obj->base.size, ++purgeable_count; |
| 414 | } |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 415 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
| 416 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 417 | size = count = mappable_size = mappable_count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 418 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 419 | if (obj->fault_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 420 | size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 421 | ++count; |
| 422 | } |
| 423 | if (obj->pin_mappable) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 424 | mappable_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 425 | ++mappable_count; |
| 426 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 427 | if (obj->madv == I915_MADV_DONTNEED) { |
| 428 | purgeable_size += obj->base.size; |
| 429 | ++purgeable_count; |
| 430 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 431 | } |
Chris Wilson | b7abb71 | 2012-08-20 11:33:30 +0200 | [diff] [blame] | 432 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
| 433 | purgeable_count, purgeable_size); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 434 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
| 435 | mappable_count, mappable_size); |
| 436 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", |
| 437 | count, size); |
| 438 | |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 439 | seq_printf(m, "%zu [%lu] gtt total\n", |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 440 | dev_priv->gtt.base.total, |
| 441 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 442 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 443 | seq_putc(m, '\n'); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 444 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 445 | struct file_stats stats; |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 446 | struct task_struct *task; |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 447 | |
| 448 | memset(&stats, 0, sizeof(stats)); |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 449 | stats.file_priv = file->driver_priv; |
Chris Wilson | 5b5ffff | 2014-06-17 09:56:24 +0100 | [diff] [blame] | 450 | spin_lock(&file->table_lock); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 451 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
Chris Wilson | 5b5ffff | 2014-06-17 09:56:24 +0100 | [diff] [blame] | 452 | spin_unlock(&file->table_lock); |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 453 | /* |
| 454 | * Although we have a valid reference on file->pid, that does |
| 455 | * not guarantee that the task_struct who called get_pid() is |
| 456 | * still alive (e.g. get_pid(current) => fork() => exit()). |
| 457 | * Therefore, we need to protect this ->comm access using RCU. |
| 458 | */ |
| 459 | rcu_read_lock(); |
| 460 | task = pid_task(file->pid, PIDTYPE_PID); |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 461 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 462 | task ? task->comm : "<unknown>", |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 463 | stats.count, |
| 464 | stats.total, |
| 465 | stats.active, |
| 466 | stats.inactive, |
Chris Wilson | 6313c20 | 2014-03-19 13:45:45 +0000 | [diff] [blame] | 467 | stats.global, |
Chris Wilson | c67a17e | 2014-03-19 13:45:46 +0000 | [diff] [blame] | 468 | stats.shared, |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 469 | stats.unbound); |
Tetsuo Handa | 3ec2f42 | 2014-01-03 20:42:18 +0900 | [diff] [blame] | 470 | rcu_read_unlock(); |
Chris Wilson | 2db8e9d | 2013-06-04 23:49:08 +0100 | [diff] [blame] | 471 | } |
| 472 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 473 | mutex_unlock(&dev->struct_mutex); |
| 474 | |
| 475 | return 0; |
| 476 | } |
| 477 | |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 478 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 479 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 480 | struct drm_info_node *node = m->private; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 481 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 482 | uintptr_t list = (uintptr_t) node->info_ent->data; |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 483 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 484 | struct drm_i915_gem_object *obj; |
| 485 | size_t total_obj_size, total_gtt_size; |
| 486 | int count, ret; |
| 487 | |
| 488 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 489 | if (ret) |
| 490 | return ret; |
| 491 | |
| 492 | total_obj_size = total_gtt_size = count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 493 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 494 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 495 | continue; |
| 496 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 497 | seq_puts(m, " "); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 498 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 499 | seq_putc(m, '\n'); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 500 | total_obj_size += obj->base.size; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 501 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 502 | count++; |
| 503 | } |
| 504 | |
| 505 | mutex_unlock(&dev->struct_mutex); |
| 506 | |
| 507 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
| 508 | count, total_obj_size, total_gtt_size); |
| 509 | |
| 510 | return 0; |
| 511 | } |
| 512 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 513 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
| 514 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 515 | struct drm_info_node *node = m->private; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 516 | struct drm_device *dev = node->minor->dev; |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 517 | struct drm_i915_private *dev_priv = dev->dev_private; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 518 | struct intel_crtc *crtc; |
Daniel Vetter | 8a270eb | 2014-06-17 22:34:37 +0200 | [diff] [blame] | 519 | int ret; |
| 520 | |
| 521 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 522 | if (ret) |
| 523 | return ret; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 524 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 525 | for_each_intel_crtc(dev, crtc) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 526 | const char pipe = pipe_name(crtc->pipe); |
| 527 | const char plane = plane_name(crtc->plane); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 528 | struct intel_unpin_work *work; |
| 529 | |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 530 | spin_lock_irq(&dev->event_lock); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 531 | work = crtc->unpin_work; |
| 532 | if (work == NULL) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 533 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 534 | pipe, plane); |
| 535 | } else { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 536 | u32 addr; |
| 537 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 538 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 539 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 540 | pipe, plane); |
| 541 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 542 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 543 | pipe, plane); |
| 544 | } |
Daniel Vetter | 3a8a946 | 2014-11-26 14:39:48 +0100 | [diff] [blame] | 545 | if (work->flip_queued_req) { |
| 546 | struct intel_engine_cs *ring = |
| 547 | i915_gem_request_get_ring(work->flip_queued_req); |
| 548 | |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 549 | seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n", |
Daniel Vetter | 3a8a946 | 2014-11-26 14:39:48 +0100 | [diff] [blame] | 550 | ring->name, |
John Harrison | f06cc1b | 2014-11-24 18:49:37 +0000 | [diff] [blame] | 551 | i915_gem_request_get_seqno(work->flip_queued_req), |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 552 | dev_priv->next_seqno, |
Daniel Vetter | 3a8a946 | 2014-11-26 14:39:48 +0100 | [diff] [blame] | 553 | ring->get_seqno(ring, true), |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 554 | i915_gem_request_completed(work->flip_queued_req, true)); |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 555 | } else |
| 556 | seq_printf(m, "Flip not associated with any ring\n"); |
| 557 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", |
| 558 | work->flip_queued_vblank, |
| 559 | work->flip_ready_vblank, |
| 560 | drm_vblank_count(dev, crtc->pipe)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 561 | if (work->enable_stall_check) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 562 | seq_puts(m, "Stall check enabled, "); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 563 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 564 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 565 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 566 | |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 567 | if (INTEL_INFO(dev)->gen >= 4) |
| 568 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); |
| 569 | else |
| 570 | addr = I915_READ(DSPADDR(crtc->plane)); |
| 571 | seq_printf(m, "Current scanout address 0x%08x\n", addr); |
| 572 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 573 | if (work->pending_flip_obj) { |
Chris Wilson | d6bbafa | 2014-09-05 07:13:24 +0100 | [diff] [blame] | 574 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); |
| 575 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 576 | } |
| 577 | } |
Daniel Vetter | 5e2d7af | 2014-09-15 14:55:22 +0200 | [diff] [blame] | 578 | spin_unlock_irq(&dev->event_lock); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 579 | } |
| 580 | |
Daniel Vetter | 8a270eb | 2014-06-17 22:34:37 +0200 | [diff] [blame] | 581 | mutex_unlock(&dev->struct_mutex); |
| 582 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 583 | return 0; |
| 584 | } |
| 585 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 586 | static int i915_gem_request_info(struct seq_file *m, void *data) |
| 587 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 588 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 589 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 590 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 591 | struct intel_engine_cs *ring; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 592 | struct drm_i915_gem_request *gem_request; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 593 | int ret, count, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 594 | |
| 595 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 596 | if (ret) |
| 597 | return ret; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 598 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 599 | count = 0; |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 600 | for_each_ring(ring, dev_priv, i) { |
| 601 | if (list_empty(&ring->request_list)) |
| 602 | continue; |
| 603 | |
| 604 | seq_printf(m, "%s requests:\n", ring->name); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 605 | list_for_each_entry(gem_request, |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 606 | &ring->request_list, |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 607 | list) { |
| 608 | seq_printf(m, " %d @ %d\n", |
| 609 | gem_request->seqno, |
| 610 | (int) (jiffies - gem_request->emitted_jiffies)); |
| 611 | } |
| 612 | count++; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 613 | } |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 614 | mutex_unlock(&dev->struct_mutex); |
| 615 | |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 616 | if (count == 0) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 617 | seq_puts(m, "No requests\n"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 618 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 619 | return 0; |
| 620 | } |
| 621 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 622 | static void i915_ring_seqno_info(struct seq_file *m, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 623 | struct intel_engine_cs *ring) |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 624 | { |
| 625 | if (ring->get_seqno) { |
Mika Kuoppala | 43a7b92 | 2012-12-04 15:12:01 +0200 | [diff] [blame] | 626 | seq_printf(m, "Current sequence (%s): %u\n", |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 627 | ring->name, ring->get_seqno(ring, false)); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 628 | } |
| 629 | } |
| 630 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 631 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
| 632 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 633 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 634 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 635 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 636 | struct intel_engine_cs *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 637 | int ret, i; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 638 | |
| 639 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 640 | if (ret) |
| 641 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 642 | intel_runtime_pm_get(dev_priv); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 643 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 644 | for_each_ring(ring, dev_priv, i) |
| 645 | i915_ring_seqno_info(m, ring); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 646 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 647 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 648 | mutex_unlock(&dev->struct_mutex); |
| 649 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 650 | return 0; |
| 651 | } |
| 652 | |
| 653 | |
| 654 | static int i915_interrupt_info(struct seq_file *m, void *data) |
| 655 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 656 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 657 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 658 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 659 | struct intel_engine_cs *ring; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 660 | int ret, i, pipe; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 661 | |
| 662 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 663 | if (ret) |
| 664 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 665 | intel_runtime_pm_get(dev_priv); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 666 | |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 667 | if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 668 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
| 669 | I915_READ(GEN8_MASTER_IRQ)); |
| 670 | |
| 671 | seq_printf(m, "Display IER:\t%08x\n", |
| 672 | I915_READ(VLV_IER)); |
| 673 | seq_printf(m, "Display IIR:\t%08x\n", |
| 674 | I915_READ(VLV_IIR)); |
| 675 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 676 | I915_READ(VLV_IIR_RW)); |
| 677 | seq_printf(m, "Display IMR:\t%08x\n", |
| 678 | I915_READ(VLV_IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 679 | for_each_pipe(dev_priv, pipe) |
Ville Syrjälä | 74e1ca8 | 2014-04-09 13:28:09 +0300 | [diff] [blame] | 680 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 681 | pipe_name(pipe), |
| 682 | I915_READ(PIPESTAT(pipe))); |
| 683 | |
| 684 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 685 | I915_READ(PORT_HOTPLUG_EN)); |
| 686 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 687 | I915_READ(VLV_DPFLIPSTAT)); |
| 688 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 689 | I915_READ(DPINVGTT)); |
| 690 | |
| 691 | for (i = 0; i < 4; i++) { |
| 692 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", |
| 693 | i, I915_READ(GEN8_GT_IMR(i))); |
| 694 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", |
| 695 | i, I915_READ(GEN8_GT_IIR(i))); |
| 696 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", |
| 697 | i, I915_READ(GEN8_GT_IER(i))); |
| 698 | } |
| 699 | |
| 700 | seq_printf(m, "PCU interrupt mask:\t%08x\n", |
| 701 | I915_READ(GEN8_PCU_IMR)); |
| 702 | seq_printf(m, "PCU interrupt identity:\t%08x\n", |
| 703 | I915_READ(GEN8_PCU_IIR)); |
| 704 | seq_printf(m, "PCU interrupt enable:\t%08x\n", |
| 705 | I915_READ(GEN8_PCU_IER)); |
| 706 | } else if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 707 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
| 708 | I915_READ(GEN8_MASTER_IRQ)); |
| 709 | |
| 710 | for (i = 0; i < 4; i++) { |
| 711 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", |
| 712 | i, I915_READ(GEN8_GT_IMR(i))); |
| 713 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", |
| 714 | i, I915_READ(GEN8_GT_IIR(i))); |
| 715 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", |
| 716 | i, I915_READ(GEN8_GT_IER(i))); |
| 717 | } |
| 718 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 719 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 720 | if (!intel_display_power_is_enabled(dev_priv, |
Paulo Zanoni | 22c5996 | 2014-08-08 17:45:32 -0300 | [diff] [blame] | 721 | POWER_DOMAIN_PIPE(pipe))) { |
| 722 | seq_printf(m, "Pipe %c power disabled\n", |
| 723 | pipe_name(pipe)); |
| 724 | continue; |
| 725 | } |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 726 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 727 | pipe_name(pipe), |
| 728 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 729 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 730 | pipe_name(pipe), |
| 731 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 732 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 733 | pipe_name(pipe), |
| 734 | I915_READ(GEN8_DE_PIPE_IER(pipe))); |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 735 | } |
| 736 | |
| 737 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", |
| 738 | I915_READ(GEN8_DE_PORT_IMR)); |
| 739 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", |
| 740 | I915_READ(GEN8_DE_PORT_IIR)); |
| 741 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", |
| 742 | I915_READ(GEN8_DE_PORT_IER)); |
| 743 | |
| 744 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", |
| 745 | I915_READ(GEN8_DE_MISC_IMR)); |
| 746 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", |
| 747 | I915_READ(GEN8_DE_MISC_IIR)); |
| 748 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", |
| 749 | I915_READ(GEN8_DE_MISC_IER)); |
| 750 | |
| 751 | seq_printf(m, "PCU interrupt mask:\t%08x\n", |
| 752 | I915_READ(GEN8_PCU_IMR)); |
| 753 | seq_printf(m, "PCU interrupt identity:\t%08x\n", |
| 754 | I915_READ(GEN8_PCU_IIR)); |
| 755 | seq_printf(m, "PCU interrupt enable:\t%08x\n", |
| 756 | I915_READ(GEN8_PCU_IER)); |
| 757 | } else if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 758 | seq_printf(m, "Display IER:\t%08x\n", |
| 759 | I915_READ(VLV_IER)); |
| 760 | seq_printf(m, "Display IIR:\t%08x\n", |
| 761 | I915_READ(VLV_IIR)); |
| 762 | seq_printf(m, "Display IIR_RW:\t%08x\n", |
| 763 | I915_READ(VLV_IIR_RW)); |
| 764 | seq_printf(m, "Display IMR:\t%08x\n", |
| 765 | I915_READ(VLV_IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 766 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 767 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
| 768 | pipe_name(pipe), |
| 769 | I915_READ(PIPESTAT(pipe))); |
| 770 | |
| 771 | seq_printf(m, "Master IER:\t%08x\n", |
| 772 | I915_READ(VLV_MASTER_IER)); |
| 773 | |
| 774 | seq_printf(m, "Render IER:\t%08x\n", |
| 775 | I915_READ(GTIER)); |
| 776 | seq_printf(m, "Render IIR:\t%08x\n", |
| 777 | I915_READ(GTIIR)); |
| 778 | seq_printf(m, "Render IMR:\t%08x\n", |
| 779 | I915_READ(GTIMR)); |
| 780 | |
| 781 | seq_printf(m, "PM IER:\t\t%08x\n", |
| 782 | I915_READ(GEN6_PMIER)); |
| 783 | seq_printf(m, "PM IIR:\t\t%08x\n", |
| 784 | I915_READ(GEN6_PMIIR)); |
| 785 | seq_printf(m, "PM IMR:\t\t%08x\n", |
| 786 | I915_READ(GEN6_PMIMR)); |
| 787 | |
| 788 | seq_printf(m, "Port hotplug:\t%08x\n", |
| 789 | I915_READ(PORT_HOTPLUG_EN)); |
| 790 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", |
| 791 | I915_READ(VLV_DPFLIPSTAT)); |
| 792 | seq_printf(m, "DPINVGTT:\t%08x\n", |
| 793 | I915_READ(DPINVGTT)); |
| 794 | |
| 795 | } else if (!HAS_PCH_SPLIT(dev)) { |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 796 | seq_printf(m, "Interrupt enable: %08x\n", |
| 797 | I915_READ(IER)); |
| 798 | seq_printf(m, "Interrupt identity: %08x\n", |
| 799 | I915_READ(IIR)); |
| 800 | seq_printf(m, "Interrupt mask: %08x\n", |
| 801 | I915_READ(IMR)); |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 802 | for_each_pipe(dev_priv, pipe) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 803 | seq_printf(m, "Pipe %c stat: %08x\n", |
| 804 | pipe_name(pipe), |
| 805 | I915_READ(PIPESTAT(pipe))); |
Zhenyu Wang | 5f6a169 | 2009-08-10 21:37:24 +0800 | [diff] [blame] | 806 | } else { |
| 807 | seq_printf(m, "North Display Interrupt enable: %08x\n", |
| 808 | I915_READ(DEIER)); |
| 809 | seq_printf(m, "North Display Interrupt identity: %08x\n", |
| 810 | I915_READ(DEIIR)); |
| 811 | seq_printf(m, "North Display Interrupt mask: %08x\n", |
| 812 | I915_READ(DEIMR)); |
| 813 | seq_printf(m, "South Display Interrupt enable: %08x\n", |
| 814 | I915_READ(SDEIER)); |
| 815 | seq_printf(m, "South Display Interrupt identity: %08x\n", |
| 816 | I915_READ(SDEIIR)); |
| 817 | seq_printf(m, "South Display Interrupt mask: %08x\n", |
| 818 | I915_READ(SDEIMR)); |
| 819 | seq_printf(m, "Graphics Interrupt enable: %08x\n", |
| 820 | I915_READ(GTIER)); |
| 821 | seq_printf(m, "Graphics Interrupt identity: %08x\n", |
| 822 | I915_READ(GTIIR)); |
| 823 | seq_printf(m, "Graphics Interrupt mask: %08x\n", |
| 824 | I915_READ(GTIMR)); |
| 825 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 826 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | a123f15 | 2013-11-02 21:07:10 -0700 | [diff] [blame] | 827 | if (INTEL_INFO(dev)->gen >= 6) { |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 828 | seq_printf(m, |
| 829 | "Graphics Interrupt mask (%s): %08x\n", |
| 830 | ring->name, I915_READ_IMR(ring)); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 831 | } |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 832 | i915_ring_seqno_info(m, ring); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 833 | } |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 834 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 835 | mutex_unlock(&dev->struct_mutex); |
| 836 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 837 | return 0; |
| 838 | } |
| 839 | |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 840 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
| 841 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 842 | struct drm_info_node *node = m->private; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 843 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 844 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 845 | int i, ret; |
| 846 | |
| 847 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 848 | if (ret) |
| 849 | return ret; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 850 | |
| 851 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); |
| 852 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
| 853 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 854 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 855 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 856 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
| 857 | i, dev_priv->fence_regs[i].pin_count); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 858 | if (obj == NULL) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 859 | seq_puts(m, "unused"); |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 860 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 861 | describe_obj(m, obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 862 | seq_putc(m, '\n'); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 863 | } |
| 864 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 865 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 866 | return 0; |
| 867 | } |
| 868 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 869 | static int i915_hws_info(struct seq_file *m, void *data) |
| 870 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 871 | struct drm_info_node *node = m->private; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 872 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 873 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 874 | struct intel_engine_cs *ring; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 875 | const u32 *hws; |
Chris Wilson | 4066c0a | 2010-10-29 21:00:54 +0100 | [diff] [blame] | 876 | int i; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 877 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 878 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 879 | hws = ring->status_page.page_addr; |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 880 | if (hws == NULL) |
| 881 | return 0; |
| 882 | |
| 883 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { |
| 884 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 885 | i * 4, |
| 886 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); |
| 887 | } |
| 888 | return 0; |
| 889 | } |
| 890 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 891 | static ssize_t |
| 892 | i915_error_state_write(struct file *filp, |
| 893 | const char __user *ubuf, |
| 894 | size_t cnt, |
| 895 | loff_t *ppos) |
| 896 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 897 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 898 | struct drm_device *dev = error_priv->dev; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 899 | int ret; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 900 | |
| 901 | DRM_DEBUG_DRIVER("Resetting error state\n"); |
| 902 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 903 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 904 | if (ret) |
| 905 | return ret; |
| 906 | |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 907 | i915_destroy_error_state(dev); |
| 908 | mutex_unlock(&dev->struct_mutex); |
| 909 | |
| 910 | return cnt; |
| 911 | } |
| 912 | |
| 913 | static int i915_error_state_open(struct inode *inode, struct file *file) |
| 914 | { |
| 915 | struct drm_device *dev = inode->i_private; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 916 | struct i915_error_state_file_priv *error_priv; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 917 | |
| 918 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); |
| 919 | if (!error_priv) |
| 920 | return -ENOMEM; |
| 921 | |
| 922 | error_priv->dev = dev; |
| 923 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 924 | i915_error_state_get(dev, error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 925 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 926 | file->private_data = error_priv; |
| 927 | |
| 928 | return 0; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 929 | } |
| 930 | |
| 931 | static int i915_error_state_release(struct inode *inode, struct file *file) |
| 932 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 933 | struct i915_error_state_file_priv *error_priv = file->private_data; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 934 | |
Mika Kuoppala | 95d5bfb | 2013-06-06 15:18:40 +0300 | [diff] [blame] | 935 | i915_error_state_put(error_priv); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 936 | kfree(error_priv); |
| 937 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 938 | return 0; |
| 939 | } |
| 940 | |
| 941 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
| 942 | size_t count, loff_t *pos) |
| 943 | { |
| 944 | struct i915_error_state_file_priv *error_priv = file->private_data; |
| 945 | struct drm_i915_error_state_buf error_str; |
| 946 | loff_t tmp_pos = 0; |
| 947 | ssize_t ret_count = 0; |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 948 | int ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 949 | |
Chris Wilson | 0a4cd7c | 2014-08-22 14:41:39 +0100 | [diff] [blame] | 950 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 951 | if (ret) |
| 952 | return ret; |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 953 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 954 | ret = i915_error_state_to_str(&error_str, error_priv); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 955 | if (ret) |
| 956 | goto out; |
| 957 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 958 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
| 959 | error_str.buf, |
| 960 | error_str.bytes); |
| 961 | |
| 962 | if (ret_count < 0) |
| 963 | ret = ret_count; |
| 964 | else |
| 965 | *pos = error_str.start + ret_count; |
| 966 | out: |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 967 | i915_error_state_buf_release(&error_str); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 968 | return ret ?: ret_count; |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 969 | } |
| 970 | |
| 971 | static const struct file_operations i915_error_state_fops = { |
| 972 | .owner = THIS_MODULE, |
| 973 | .open = i915_error_state_open, |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 974 | .read = i915_error_state_read, |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 975 | .write = i915_error_state_write, |
| 976 | .llseek = default_llseek, |
| 977 | .release = i915_error_state_release, |
| 978 | }; |
| 979 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 980 | static int |
| 981 | i915_next_seqno_get(void *data, u64 *val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 982 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 983 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 984 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 985 | int ret; |
| 986 | |
| 987 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 988 | if (ret) |
| 989 | return ret; |
| 990 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 991 | *val = dev_priv->next_seqno; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 992 | mutex_unlock(&dev->struct_mutex); |
| 993 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 994 | return 0; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 995 | } |
| 996 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 997 | static int |
| 998 | i915_next_seqno_set(void *data, u64 val) |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 999 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1000 | struct drm_device *dev = data; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1001 | int ret; |
| 1002 | |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1003 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1004 | if (ret) |
| 1005 | return ret; |
| 1006 | |
Mika Kuoppala | e94fbaa | 2012-12-19 11:13:09 +0200 | [diff] [blame] | 1007 | ret = i915_gem_set_seqno(dev, val); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1008 | mutex_unlock(&dev->struct_mutex); |
| 1009 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1010 | return ret; |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1011 | } |
| 1012 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 1013 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
| 1014 | i915_next_seqno_get, i915_next_seqno_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 1015 | "0x%llx\n"); |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 1016 | |
Deepak S | adb4bd1 | 2014-03-31 11:30:02 +0530 | [diff] [blame] | 1017 | static int i915_frequency_info(struct seq_file *m, void *unused) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1018 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1019 | struct drm_info_node *node = m->private; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1020 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1021 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1022 | int ret = 0; |
| 1023 | |
| 1024 | intel_runtime_pm_get(dev_priv); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1025 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 1026 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 1027 | |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1028 | if (IS_GEN5(dev)) { |
| 1029 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
| 1030 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); |
| 1031 | |
| 1032 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); |
| 1033 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); |
| 1034 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> |
| 1035 | MEMSTAT_VID_SHIFT); |
| 1036 | seq_printf(m, "Current P-state: %d\n", |
| 1037 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1038 | } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) || |
| 1039 | IS_BROADWELL(dev)) { |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1040 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 1041 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
| 1042 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1043 | u32 rpmodectl, rpinclimit, rpdeclimit; |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1044 | u32 rpstat, cagf, reqf; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1045 | u32 rpupei, rpcurup, rpprevup; |
| 1046 | u32 rpdownei, rpcurdown, rpprevdown; |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1047 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1048 | int max_freq; |
| 1049 | |
| 1050 | /* RPSTAT1 is in the GT power well */ |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1051 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1052 | if (ret) |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1053 | goto out; |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1054 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 1055 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1056 | |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1057 | reqf = I915_READ(GEN6_RPNSWREQ); |
| 1058 | reqf &= ~GEN6_TURBO_DISABLE; |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1059 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1060 | reqf >>= 24; |
| 1061 | else |
| 1062 | reqf >>= 25; |
| 1063 | reqf *= GT_FREQUENCY_MULTIPLIER; |
| 1064 | |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1065 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
| 1066 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); |
| 1067 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); |
| 1068 | |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1069 | rpstat = I915_READ(GEN6_RPSTAT1); |
| 1070 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); |
| 1071 | rpcurup = I915_READ(GEN6_RP_CUR_UP); |
| 1072 | rpprevup = I915_READ(GEN6_RP_PREV_UP); |
| 1073 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); |
| 1074 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); |
| 1075 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 1076 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1077 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
| 1078 | else |
| 1079 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; |
| 1080 | cagf *= GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1081 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 1082 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 1083 | mutex_unlock(&dev->struct_mutex); |
| 1084 | |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1085 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1086 | pm_ier = I915_READ(GEN6_PMIER); |
| 1087 | pm_imr = I915_READ(GEN6_PMIMR); |
| 1088 | pm_isr = I915_READ(GEN6_PMISR); |
| 1089 | pm_iir = I915_READ(GEN6_PMIIR); |
| 1090 | pm_mask = I915_READ(GEN6_PMINTRMSK); |
| 1091 | } else { |
| 1092 | pm_ier = I915_READ(GEN8_GT_IER(2)); |
| 1093 | pm_imr = I915_READ(GEN8_GT_IMR(2)); |
| 1094 | pm_isr = I915_READ(GEN8_GT_ISR(2)); |
| 1095 | pm_iir = I915_READ(GEN8_GT_IIR(2)); |
| 1096 | pm_mask = I915_READ(GEN6_PMINTRMSK); |
| 1097 | } |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1098 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
Paulo Zanoni | 9dd3c60 | 2014-08-01 18:14:48 -0300 | [diff] [blame] | 1099 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1100 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1101 | seq_printf(m, "Render p-state ratio: %d\n", |
| 1102 | (gt_perf_status & 0xff00) >> 8); |
| 1103 | seq_printf(m, "Render p-state VID: %d\n", |
| 1104 | gt_perf_status & 0xff); |
| 1105 | seq_printf(m, "Render p-state limit: %d\n", |
| 1106 | rp_state_limits & 0xff); |
Chris Wilson | 0d8f949 | 2014-03-27 09:06:14 +0000 | [diff] [blame] | 1107 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
| 1108 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); |
| 1109 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); |
| 1110 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); |
Chris Wilson | 8e8c06c | 2013-08-26 19:51:01 -0300 | [diff] [blame] | 1111 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
Ben Widawsky | f82855d | 2013-01-29 12:00:15 -0800 | [diff] [blame] | 1112 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
Jesse Barnes | ccab5c8 | 2011-01-18 15:49:25 -0800 | [diff] [blame] | 1113 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
| 1114 | GEN6_CURICONT_MASK); |
| 1115 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & |
| 1116 | GEN6_CURBSYTAVG_MASK); |
| 1117 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & |
| 1118 | GEN6_CURBSYTAVG_MASK); |
| 1119 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & |
| 1120 | GEN6_CURIAVG_MASK); |
| 1121 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & |
| 1122 | GEN6_CURBSYTAVG_MASK); |
| 1123 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & |
| 1124 | GEN6_CURBSYTAVG_MASK); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1125 | |
| 1126 | max_freq = (rp_state_cap & 0xff0000) >> 16; |
| 1127 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1128 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1129 | |
| 1130 | max_freq = (rp_state_cap & 0xff00) >> 8; |
| 1131 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1132 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1133 | |
| 1134 | max_freq = rp_state_cap & 0xff; |
| 1135 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1136 | max_freq * GT_FREQUENCY_MULTIPLIER); |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 1137 | |
| 1138 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1139 | dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1140 | } else if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 1141 | u32 freq_sts; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1142 | |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1143 | mutex_lock(&dev_priv->rps.hw_lock); |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 1144 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1145 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
| 1146 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); |
| 1147 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1148 | seq_printf(m, "max GPU freq: %d MHz\n", |
Deepak S | b2435c9 | 2014-07-17 14:21:14 +0530 | [diff] [blame] | 1149 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1150 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1151 | seq_printf(m, "min GPU freq: %d MHz\n", |
Deepak S | b2435c9 | 2014-07-17 14:21:14 +0530 | [diff] [blame] | 1152 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq)); |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 1153 | |
| 1154 | seq_printf(m, "efficient (RPe) frequency: %d MHz\n", |
Deepak S | b2435c9 | 2014-07-17 14:21:14 +0530 | [diff] [blame] | 1155 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 1156 | |
| 1157 | seq_printf(m, "current GPU freq: %d MHz\n", |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 1158 | vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
Jesse Barnes | 259bd5d | 2013-04-22 15:59:30 -0700 | [diff] [blame] | 1159 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1160 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1161 | seq_puts(m, "no P-state info available\n"); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1162 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1163 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1164 | out: |
| 1165 | intel_runtime_pm_put(dev_priv); |
| 1166 | return ret; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1167 | } |
| 1168 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1169 | static int ironlake_drpc_info(struct seq_file *m) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1170 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1171 | struct drm_info_node *node = m->private; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1172 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1173 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1174 | u32 rgvmodectl, rstdbyctl; |
| 1175 | u16 crstandvid; |
| 1176 | int ret; |
| 1177 | |
| 1178 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1179 | if (ret) |
| 1180 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1181 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1182 | |
| 1183 | rgvmodectl = I915_READ(MEMMODECTL); |
| 1184 | rstdbyctl = I915_READ(RSTDBYCTL); |
| 1185 | crstandvid = I915_READ16(CRSTANDVID); |
| 1186 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1187 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | 616fdb5 | 2011-10-05 11:44:54 -0700 | [diff] [blame] | 1188 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1189 | |
| 1190 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? |
| 1191 | "yes" : "no"); |
| 1192 | seq_printf(m, "Boost freq: %d\n", |
| 1193 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> |
| 1194 | MEMMODE_BOOST_FREQ_SHIFT); |
| 1195 | seq_printf(m, "HW control enabled: %s\n", |
| 1196 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); |
| 1197 | seq_printf(m, "SW control enabled: %s\n", |
| 1198 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); |
| 1199 | seq_printf(m, "Gated voltage change: %s\n", |
| 1200 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); |
| 1201 | seq_printf(m, "Starting frequency: P%d\n", |
| 1202 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1203 | seq_printf(m, "Max P-state: P%d\n", |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1204 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1205 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
| 1206 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); |
| 1207 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); |
| 1208 | seq_printf(m, "Render standby enabled: %s\n", |
| 1209 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1210 | seq_puts(m, "Current RS state: "); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1211 | switch (rstdbyctl & RSX_STATUS_MASK) { |
| 1212 | case RSX_STATUS_ON: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1213 | seq_puts(m, "on\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1214 | break; |
| 1215 | case RSX_STATUS_RC1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1216 | seq_puts(m, "RC1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1217 | break; |
| 1218 | case RSX_STATUS_RC1E: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1219 | seq_puts(m, "RC1E\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1220 | break; |
| 1221 | case RSX_STATUS_RS1: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1222 | seq_puts(m, "RS1\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1223 | break; |
| 1224 | case RSX_STATUS_RS2: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1225 | seq_puts(m, "RS2 (RC6)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1226 | break; |
| 1227 | case RSX_STATUS_RS3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1228 | seq_puts(m, "RC3 (RC6+)\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1229 | break; |
| 1230 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1231 | seq_puts(m, "unknown\n"); |
Jesse Barnes | 88271da | 2011-01-05 12:01:24 -0800 | [diff] [blame] | 1232 | break; |
| 1233 | } |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1234 | |
| 1235 | return 0; |
| 1236 | } |
| 1237 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1238 | static int vlv_drpc_info(struct seq_file *m) |
| 1239 | { |
| 1240 | |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1241 | struct drm_info_node *node = m->private; |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1242 | struct drm_device *dev = node->minor->dev; |
| 1243 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1244 | u32 rpmodectl1, rcctl1, pw_status; |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1245 | unsigned fw_rendercount = 0, fw_mediacount = 0; |
| 1246 | |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 1247 | intel_runtime_pm_get(dev_priv); |
| 1248 | |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1249 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1250 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1251 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1252 | |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 1253 | intel_runtime_pm_put(dev_priv); |
| 1254 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1255 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1256 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1257 | seq_printf(m, "Turbo enabled: %s\n", |
| 1258 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1259 | seq_printf(m, "HW control enabled: %s\n", |
| 1260 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1261 | seq_printf(m, "SW control enabled: %s\n", |
| 1262 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1263 | GEN6_RP_MEDIA_SW_MODE)); |
| 1264 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1265 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | |
| 1266 | GEN6_RC_CTL_EI_MODE(1)))); |
| 1267 | seq_printf(m, "Render Power Well: %s\n", |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1268 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1269 | seq_printf(m, "Media Power Well: %s\n", |
Ville Syrjälä | 6b312cd | 2014-11-19 20:07:42 +0200 | [diff] [blame] | 1270 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1271 | |
Imre Deak | 9cc19be | 2014-04-14 20:24:24 +0300 | [diff] [blame] | 1272 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
| 1273 | I915_READ(VLV_GT_RENDER_RC6)); |
| 1274 | seq_printf(m, "Media RC6 residency since boot: %u\n", |
| 1275 | I915_READ(VLV_GT_MEDIA_RC6)); |
| 1276 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1277 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1278 | fw_rendercount = dev_priv->uncore.fw_rendercount; |
| 1279 | fw_mediacount = dev_priv->uncore.fw_mediacount; |
| 1280 | spin_unlock_irq(&dev_priv->uncore.lock); |
| 1281 | |
| 1282 | seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount); |
| 1283 | seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount); |
| 1284 | |
| 1285 | |
| 1286 | return 0; |
| 1287 | } |
| 1288 | |
| 1289 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1290 | static int gen6_drpc_info(struct seq_file *m) |
| 1291 | { |
| 1292 | |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1293 | struct drm_info_node *node = m->private; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1294 | struct drm_device *dev = node->minor->dev; |
| 1295 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1296 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1297 | unsigned forcewake_count; |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1298 | int count = 0, ret; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1299 | |
| 1300 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1301 | if (ret) |
| 1302 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1303 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1304 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1305 | spin_lock_irq(&dev_priv->uncore.lock); |
| 1306 | forcewake_count = dev_priv->uncore.forcewake_count; |
| 1307 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 93b525d | 2012-01-25 13:52:43 +0100 | [diff] [blame] | 1308 | |
| 1309 | if (forcewake_count) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1310 | seq_puts(m, "RC information inaccurate because somebody " |
| 1311 | "holds a forcewake reference \n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1312 | } else { |
| 1313 | /* NB: we cannot use forcewake, else we read the wrong values */ |
| 1314 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) |
| 1315 | udelay(10); |
| 1316 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); |
| 1317 | } |
| 1318 | |
| 1319 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); |
Chris Wilson | ed71f1b | 2013-07-19 20:36:56 +0100 | [diff] [blame] | 1320 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1321 | |
| 1322 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
| 1323 | rcctl1 = I915_READ(GEN6_RC_CONTROL); |
| 1324 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 44cbd33 | 2012-11-06 14:36:36 +0000 | [diff] [blame] | 1325 | mutex_lock(&dev_priv->rps.hw_lock); |
| 1326 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 1327 | mutex_unlock(&dev_priv->rps.hw_lock); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1328 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1329 | intel_runtime_pm_put(dev_priv); |
| 1330 | |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1331 | seq_printf(m, "Video Turbo Mode: %s\n", |
| 1332 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); |
| 1333 | seq_printf(m, "HW control enabled: %s\n", |
| 1334 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); |
| 1335 | seq_printf(m, "SW control enabled: %s\n", |
| 1336 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == |
| 1337 | GEN6_RP_MEDIA_SW_MODE)); |
Eric Anholt | fff24e2 | 2012-01-23 16:14:05 -0800 | [diff] [blame] | 1338 | seq_printf(m, "RC1e Enabled: %s\n", |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1339 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
| 1340 | seq_printf(m, "RC6 Enabled: %s\n", |
| 1341 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); |
| 1342 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
| 1343 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); |
| 1344 | seq_printf(m, "Deepest RC6 Enabled: %s\n", |
| 1345 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1346 | seq_puts(m, "Current RC state: "); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1347 | switch (gt_core_status & GEN6_RCn_MASK) { |
| 1348 | case GEN6_RC0: |
| 1349 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1350 | seq_puts(m, "Core Power Down\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1351 | else |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1352 | seq_puts(m, "on\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1353 | break; |
| 1354 | case GEN6_RC3: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1355 | seq_puts(m, "RC3\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1356 | break; |
| 1357 | case GEN6_RC6: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1358 | seq_puts(m, "RC6\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1359 | break; |
| 1360 | case GEN6_RC7: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1361 | seq_puts(m, "RC7\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1362 | break; |
| 1363 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1364 | seq_puts(m, "Unknown\n"); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1365 | break; |
| 1366 | } |
| 1367 | |
| 1368 | seq_printf(m, "Core Power Down: %s\n", |
| 1369 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); |
Ben Widawsky | cce66a2 | 2012-03-27 18:59:38 -0700 | [diff] [blame] | 1370 | |
| 1371 | /* Not exactly sure what this is */ |
| 1372 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", |
| 1373 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); |
| 1374 | seq_printf(m, "RC6 residency since boot: %u\n", |
| 1375 | I915_READ(GEN6_GT_GFX_RC6)); |
| 1376 | seq_printf(m, "RC6+ residency since boot: %u\n", |
| 1377 | I915_READ(GEN6_GT_GFX_RC6p)); |
| 1378 | seq_printf(m, "RC6++ residency since boot: %u\n", |
| 1379 | I915_READ(GEN6_GT_GFX_RC6pp)); |
| 1380 | |
Ben Widawsky | ecd8fae | 2012-09-26 10:34:02 -0700 | [diff] [blame] | 1381 | seq_printf(m, "RC6 voltage: %dmV\n", |
| 1382 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); |
| 1383 | seq_printf(m, "RC6+ voltage: %dmV\n", |
| 1384 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); |
| 1385 | seq_printf(m, "RC6++ voltage: %dmV\n", |
| 1386 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1387 | return 0; |
| 1388 | } |
| 1389 | |
| 1390 | static int i915_drpc_info(struct seq_file *m, void *unused) |
| 1391 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1392 | struct drm_info_node *node = m->private; |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1393 | struct drm_device *dev = node->minor->dev; |
| 1394 | |
Deepak S | 669ab5a | 2014-01-10 15:18:26 +0530 | [diff] [blame] | 1395 | if (IS_VALLEYVIEW(dev)) |
| 1396 | return vlv_drpc_info(m); |
Vedang Patel | ac66cf4 | 2014-08-26 10:42:51 -0700 | [diff] [blame] | 1397 | else if (INTEL_INFO(dev)->gen >= 6) |
Ben Widawsky | 4d85529 | 2011-12-12 19:34:16 -0800 | [diff] [blame] | 1398 | return gen6_drpc_info(m); |
| 1399 | else |
| 1400 | return ironlake_drpc_info(m); |
| 1401 | } |
| 1402 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1403 | static int i915_fbc_status(struct seq_file *m, void *unused) |
| 1404 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1405 | struct drm_info_node *node = m->private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1406 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1407 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1408 | |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 1409 | if (!HAS_FBC(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1410 | seq_puts(m, "FBC unsupported on this chipset\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1411 | return 0; |
| 1412 | } |
| 1413 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1414 | intel_runtime_pm_get(dev_priv); |
| 1415 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1416 | if (intel_fbc_enabled(dev)) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1417 | seq_puts(m, "FBC enabled\n"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1418 | } else { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1419 | seq_puts(m, "FBC disabled: "); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 1420 | switch (dev_priv->fbc.no_fbc_reason) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 1421 | case FBC_OK: |
| 1422 | seq_puts(m, "FBC actived, but currently disabled in hardware"); |
| 1423 | break; |
| 1424 | case FBC_UNSUPPORTED: |
| 1425 | seq_puts(m, "unsupported by this chipset"); |
| 1426 | break; |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1427 | case FBC_NO_OUTPUT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1428 | seq_puts(m, "no outputs"); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 1429 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1430 | case FBC_STOLEN_TOO_SMALL: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1431 | seq_puts(m, "not enough stolen memory"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1432 | break; |
| 1433 | case FBC_UNSUPPORTED_MODE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1434 | seq_puts(m, "mode not supported"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1435 | break; |
| 1436 | case FBC_MODE_TOO_LARGE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1437 | seq_puts(m, "mode too large"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1438 | break; |
| 1439 | case FBC_BAD_PLANE: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1440 | seq_puts(m, "FBC unsupported on plane"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1441 | break; |
| 1442 | case FBC_NOT_TILED: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1443 | seq_puts(m, "scanout buffer not tiled"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1444 | break; |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1445 | case FBC_MULTIPLE_PIPES: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1446 | seq_puts(m, "multiple pipes are enabled"); |
Jesse Barnes | 9c928d1 | 2010-07-23 15:20:00 -0700 | [diff] [blame] | 1447 | break; |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1448 | case FBC_MODULE_PARAM: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1449 | seq_puts(m, "disabled per module param (default off)"); |
Jesse Barnes | c1a9f04 | 2011-05-05 15:24:21 -0700 | [diff] [blame] | 1450 | break; |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1451 | case FBC_CHIP_DEFAULT: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1452 | seq_puts(m, "disabled per chip default"); |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 1453 | break; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1454 | default: |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1455 | seq_puts(m, "unknown reason"); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1456 | } |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1457 | seq_putc(m, '\n'); |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1458 | } |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1459 | |
| 1460 | intel_runtime_pm_put(dev_priv); |
| 1461 | |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1462 | return 0; |
| 1463 | } |
| 1464 | |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 1465 | static int i915_fbc_fc_get(void *data, u64 *val) |
| 1466 | { |
| 1467 | struct drm_device *dev = data; |
| 1468 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1469 | |
| 1470 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) |
| 1471 | return -ENODEV; |
| 1472 | |
| 1473 | drm_modeset_lock_all(dev); |
| 1474 | *val = dev_priv->fbc.false_color; |
| 1475 | drm_modeset_unlock_all(dev); |
| 1476 | |
| 1477 | return 0; |
| 1478 | } |
| 1479 | |
| 1480 | static int i915_fbc_fc_set(void *data, u64 val) |
| 1481 | { |
| 1482 | struct drm_device *dev = data; |
| 1483 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1484 | u32 reg; |
| 1485 | |
| 1486 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) |
| 1487 | return -ENODEV; |
| 1488 | |
| 1489 | drm_modeset_lock_all(dev); |
| 1490 | |
| 1491 | reg = I915_READ(ILK_DPFC_CONTROL); |
| 1492 | dev_priv->fbc.false_color = val; |
| 1493 | |
| 1494 | I915_WRITE(ILK_DPFC_CONTROL, val ? |
| 1495 | (reg | FBC_CTL_FALSE_COLOR) : |
| 1496 | (reg & ~FBC_CTL_FALSE_COLOR)); |
| 1497 | |
| 1498 | drm_modeset_unlock_all(dev); |
| 1499 | return 0; |
| 1500 | } |
| 1501 | |
| 1502 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, |
| 1503 | i915_fbc_fc_get, i915_fbc_fc_set, |
| 1504 | "%llu\n"); |
| 1505 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1506 | static int i915_ips_status(struct seq_file *m, void *unused) |
| 1507 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1508 | struct drm_info_node *node = m->private; |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1509 | struct drm_device *dev = node->minor->dev; |
| 1510 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1511 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 1512 | if (!HAS_IPS(dev)) { |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1513 | seq_puts(m, "not supported\n"); |
| 1514 | return 0; |
| 1515 | } |
| 1516 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1517 | intel_runtime_pm_get(dev_priv); |
| 1518 | |
Rodrigo Vivi | 0eaa53f | 2014-06-30 04:45:01 -0700 | [diff] [blame] | 1519 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
| 1520 | yesno(i915.enable_ips)); |
| 1521 | |
| 1522 | if (INTEL_INFO(dev)->gen >= 8) { |
| 1523 | seq_puts(m, "Currently: unknown\n"); |
| 1524 | } else { |
| 1525 | if (I915_READ(IPS_CTL) & IPS_ENABLE) |
| 1526 | seq_puts(m, "Currently: enabled\n"); |
| 1527 | else |
| 1528 | seq_puts(m, "Currently: disabled\n"); |
| 1529 | } |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1530 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1531 | intel_runtime_pm_put(dev_priv); |
| 1532 | |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 1533 | return 0; |
| 1534 | } |
| 1535 | |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1536 | static int i915_sr_status(struct seq_file *m, void *unused) |
| 1537 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1538 | struct drm_info_node *node = m->private; |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1539 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1540 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1541 | bool sr_enabled = false; |
| 1542 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1543 | intel_runtime_pm_get(dev_priv); |
| 1544 | |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 1545 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1546 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1547 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1548 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
| 1549 | else if (IS_I915GM(dev)) |
| 1550 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
| 1551 | else if (IS_PINEVIEW(dev)) |
| 1552 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; |
| 1553 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 1554 | intel_runtime_pm_put(dev_priv); |
| 1555 | |
Chris Wilson | 5ba2aaa | 2010-08-19 18:04:08 +0100 | [diff] [blame] | 1556 | seq_printf(m, "self-refresh: %s\n", |
| 1557 | sr_enabled ? "enabled" : "disabled"); |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 1558 | |
| 1559 | return 0; |
| 1560 | } |
| 1561 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1562 | static int i915_emon_status(struct seq_file *m, void *unused) |
| 1563 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1564 | struct drm_info_node *node = m->private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1565 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1566 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1567 | unsigned long temp, chipset, gfx; |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1568 | int ret; |
| 1569 | |
Chris Wilson | 582be6b | 2012-04-30 19:35:02 +0100 | [diff] [blame] | 1570 | if (!IS_GEN5(dev)) |
| 1571 | return -ENODEV; |
| 1572 | |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1573 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1574 | if (ret) |
| 1575 | return ret; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1576 | |
| 1577 | temp = i915_mch_val(dev_priv); |
| 1578 | chipset = i915_chipset_val(dev_priv); |
| 1579 | gfx = i915_gfx_val(dev_priv); |
Chris Wilson | de227ef | 2010-07-03 07:58:38 +0100 | [diff] [blame] | 1580 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1581 | |
| 1582 | seq_printf(m, "GMCH temp: %ld\n", temp); |
| 1583 | seq_printf(m, "Chipset power: %ld\n", chipset); |
| 1584 | seq_printf(m, "GFX power: %ld\n", gfx); |
| 1585 | seq_printf(m, "Total power: %ld\n", chipset + gfx); |
| 1586 | |
| 1587 | return 0; |
| 1588 | } |
| 1589 | |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1590 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
| 1591 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1592 | struct drm_info_node *node = m->private; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1593 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1594 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1595 | int ret = 0; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1596 | int gpu_freq, ia_freq; |
| 1597 | |
Jesse Barnes | 1c70c0c | 2011-06-29 13:34:36 -0700 | [diff] [blame] | 1598 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1599 | seq_puts(m, "unsupported on this chipset\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1600 | return 0; |
| 1601 | } |
| 1602 | |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1603 | intel_runtime_pm_get(dev_priv); |
| 1604 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 1605 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 1606 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1607 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1608 | if (ret) |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1609 | goto out; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1610 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1611 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1612 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 1613 | for (gpu_freq = dev_priv->rps.min_freq_softlimit; |
| 1614 | gpu_freq <= dev_priv->rps.max_freq_softlimit; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1615 | gpu_freq++) { |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 1616 | ia_freq = gpu_freq; |
| 1617 | sandybridge_pcode_read(dev_priv, |
| 1618 | GEN6_PCODE_READ_MIN_FREQ_TABLE, |
| 1619 | &ia_freq); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 1620 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
| 1621 | gpu_freq * GT_FREQUENCY_MULTIPLIER, |
| 1622 | ((ia_freq >> 0) & 0xff) * 100, |
| 1623 | ((ia_freq >> 8) & 0xff) * 100); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1624 | } |
| 1625 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1626 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1627 | |
Paulo Zanoni | 5bfa019 | 2013-12-19 11:54:52 -0200 | [diff] [blame] | 1628 | out: |
| 1629 | intel_runtime_pm_put(dev_priv); |
| 1630 | return ret; |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 1631 | } |
| 1632 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1633 | static int i915_opregion(struct seq_file *m, void *unused) |
| 1634 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1635 | struct drm_info_node *node = m->private; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1636 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1637 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1638 | struct intel_opregion *opregion = &dev_priv->opregion; |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1639 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1640 | int ret; |
| 1641 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1642 | if (data == NULL) |
| 1643 | return -ENOMEM; |
| 1644 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1645 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1646 | if (ret) |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1647 | goto out; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1648 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1649 | if (opregion->header) { |
| 1650 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); |
| 1651 | seq_write(m, data, OPREGION_SIZE); |
| 1652 | } |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1653 | |
| 1654 | mutex_unlock(&dev->struct_mutex); |
| 1655 | |
Daniel Vetter | 0d38f00 | 2012-04-21 22:49:10 +0200 | [diff] [blame] | 1656 | out: |
| 1657 | kfree(data); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1658 | return 0; |
| 1659 | } |
| 1660 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1661 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
| 1662 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1663 | struct drm_info_node *node = m->private; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1664 | struct drm_device *dev = node->minor->dev; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1665 | struct intel_fbdev *ifbdev = NULL; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1666 | struct intel_framebuffer *fb; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1667 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1668 | #ifdef CONFIG_DRM_I915_FBDEV |
| 1669 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1670 | |
| 1671 | ifbdev = dev_priv->fbdev; |
| 1672 | fb = to_intel_framebuffer(ifbdev->helper.fb); |
| 1673 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1674 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1675 | fb->base.width, |
| 1676 | fb->base.height, |
| 1677 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1678 | fb->base.bits_per_pixel, |
| 1679 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1680 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1681 | seq_putc(m, '\n'); |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1682 | #endif |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1683 | |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1684 | mutex_lock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1685 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
Daniel Vetter | 131a56d | 2013-10-17 14:35:31 +0200 | [diff] [blame] | 1686 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1687 | continue; |
| 1688 | |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1689 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1690 | fb->base.width, |
| 1691 | fb->base.height, |
| 1692 | fb->base.depth, |
Daniel Vetter | 623f978 | 2012-12-11 16:21:38 +0100 | [diff] [blame] | 1693 | fb->base.bits_per_pixel, |
| 1694 | atomic_read(&fb->base.refcount.refcount)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1695 | describe_obj(m, fb->obj); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1696 | seq_putc(m, '\n'); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1697 | } |
Daniel Vetter | 4b096ac | 2012-12-10 21:19:18 +0100 | [diff] [blame] | 1698 | mutex_unlock(&dev->mode_config.fb_lock); |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 1699 | |
| 1700 | return 0; |
| 1701 | } |
| 1702 | |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1703 | static void describe_ctx_ringbuf(struct seq_file *m, |
| 1704 | struct intel_ringbuffer *ringbuf) |
| 1705 | { |
| 1706 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", |
| 1707 | ringbuf->space, ringbuf->head, ringbuf->tail, |
| 1708 | ringbuf->last_retired_head); |
| 1709 | } |
| 1710 | |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1711 | static int i915_context_status(struct seq_file *m, void *unused) |
| 1712 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1713 | struct drm_info_node *node = m->private; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1714 | struct drm_device *dev = node->minor->dev; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 1715 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1716 | struct intel_engine_cs *ring; |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 1717 | struct intel_context *ctx; |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1718 | int ret, i; |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1719 | |
Daniel Vetter | f3d2887 | 2014-05-29 23:23:08 +0200 | [diff] [blame] | 1720 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1721 | if (ret) |
| 1722 | return ret; |
| 1723 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1724 | if (dev_priv->ips.pwrctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1725 | seq_puts(m, "power context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1726 | describe_obj(m, dev_priv->ips.pwrctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1727 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1728 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1729 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1730 | if (dev_priv->ips.renderctx) { |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1731 | seq_puts(m, "render context "); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1732 | describe_obj(m, dev_priv->ips.renderctx); |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 1733 | seq_putc(m, '\n'); |
Ben Widawsky | dc501fb | 2011-06-29 11:41:51 -0700 | [diff] [blame] | 1734 | } |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1735 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1736 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1737 | if (!i915.enable_execlists && |
| 1738 | ctx->legacy_hw_ctx.rcs_state == NULL) |
Chris Wilson | b77f699 | 2014-04-30 08:30:00 +0100 | [diff] [blame] | 1739 | continue; |
| 1740 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1741 | seq_puts(m, "HW context "); |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 1742 | describe_ctx(m, ctx); |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1743 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1744 | if (ring->default_context == ctx) |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1745 | seq_printf(m, "(default context %s) ", |
| 1746 | ring->name); |
| 1747 | } |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1748 | |
Oscar Mateo | c9fe99b | 2014-07-24 17:04:46 +0100 | [diff] [blame] | 1749 | if (i915.enable_execlists) { |
| 1750 | seq_putc(m, '\n'); |
| 1751 | for_each_ring(ring, dev_priv, i) { |
| 1752 | struct drm_i915_gem_object *ctx_obj = |
| 1753 | ctx->engine[i].state; |
| 1754 | struct intel_ringbuffer *ringbuf = |
| 1755 | ctx->engine[i].ringbuf; |
| 1756 | |
| 1757 | seq_printf(m, "%s: ", ring->name); |
| 1758 | if (ctx_obj) |
| 1759 | describe_obj(m, ctx_obj); |
| 1760 | if (ringbuf) |
| 1761 | describe_ctx_ringbuf(m, ringbuf); |
| 1762 | seq_putc(m, '\n'); |
| 1763 | } |
| 1764 | } else { |
| 1765 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); |
| 1766 | } |
| 1767 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1768 | seq_putc(m, '\n'); |
Ben Widawsky | a168c29 | 2013-02-14 15:05:12 -0800 | [diff] [blame] | 1769 | } |
| 1770 | |
Daniel Vetter | f3d2887 | 2014-05-29 23:23:08 +0200 | [diff] [blame] | 1771 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 1772 | |
| 1773 | return 0; |
| 1774 | } |
| 1775 | |
Thomas Daniel | 064ca1d | 2014-12-02 13:21:18 +0000 | [diff] [blame] | 1776 | static void i915_dump_lrc_obj(struct seq_file *m, |
| 1777 | struct intel_engine_cs *ring, |
| 1778 | struct drm_i915_gem_object *ctx_obj) |
| 1779 | { |
| 1780 | struct page *page; |
| 1781 | uint32_t *reg_state; |
| 1782 | int j; |
| 1783 | unsigned long ggtt_offset = 0; |
| 1784 | |
| 1785 | if (ctx_obj == NULL) { |
| 1786 | seq_printf(m, "Context on %s with no gem object\n", |
| 1787 | ring->name); |
| 1788 | return; |
| 1789 | } |
| 1790 | |
| 1791 | seq_printf(m, "CONTEXT: %s %u\n", ring->name, |
| 1792 | intel_execlists_ctx_id(ctx_obj)); |
| 1793 | |
| 1794 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) |
| 1795 | seq_puts(m, "\tNot bound in GGTT\n"); |
| 1796 | else |
| 1797 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); |
| 1798 | |
| 1799 | if (i915_gem_object_get_pages(ctx_obj)) { |
| 1800 | seq_puts(m, "\tFailed to get pages for context object\n"); |
| 1801 | return; |
| 1802 | } |
| 1803 | |
| 1804 | page = i915_gem_object_get_page(ctx_obj, 1); |
| 1805 | if (!WARN_ON(page == NULL)) { |
| 1806 | reg_state = kmap_atomic(page); |
| 1807 | |
| 1808 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { |
| 1809 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 1810 | ggtt_offset + 4096 + (j * 4), |
| 1811 | reg_state[j], reg_state[j + 1], |
| 1812 | reg_state[j + 2], reg_state[j + 3]); |
| 1813 | } |
| 1814 | kunmap_atomic(reg_state); |
| 1815 | } |
| 1816 | |
| 1817 | seq_putc(m, '\n'); |
| 1818 | } |
| 1819 | |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 1820 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
| 1821 | { |
| 1822 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 1823 | struct drm_device *dev = node->minor->dev; |
| 1824 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1825 | struct intel_engine_cs *ring; |
| 1826 | struct intel_context *ctx; |
| 1827 | int ret, i; |
| 1828 | |
| 1829 | if (!i915.enable_execlists) { |
| 1830 | seq_printf(m, "Logical Ring Contexts are disabled\n"); |
| 1831 | return 0; |
| 1832 | } |
| 1833 | |
| 1834 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1835 | if (ret) |
| 1836 | return ret; |
| 1837 | |
| 1838 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
| 1839 | for_each_ring(ring, dev_priv, i) { |
Thomas Daniel | 064ca1d | 2014-12-02 13:21:18 +0000 | [diff] [blame] | 1840 | if (ring->default_context != ctx) |
| 1841 | i915_dump_lrc_obj(m, ring, |
| 1842 | ctx->engine[i].state); |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 1843 | } |
| 1844 | } |
| 1845 | |
| 1846 | mutex_unlock(&dev->struct_mutex); |
| 1847 | |
| 1848 | return 0; |
| 1849 | } |
| 1850 | |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 1851 | static int i915_execlists(struct seq_file *m, void *data) |
| 1852 | { |
| 1853 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
| 1854 | struct drm_device *dev = node->minor->dev; |
| 1855 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1856 | struct intel_engine_cs *ring; |
| 1857 | u32 status_pointer; |
| 1858 | u8 read_pointer; |
| 1859 | u8 write_pointer; |
| 1860 | u32 status; |
| 1861 | u32 ctx_id; |
| 1862 | struct list_head *cursor; |
| 1863 | int ring_id, i; |
| 1864 | int ret; |
| 1865 | |
| 1866 | if (!i915.enable_execlists) { |
| 1867 | seq_puts(m, "Logical Ring Contexts are disabled\n"); |
| 1868 | return 0; |
| 1869 | } |
| 1870 | |
| 1871 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1872 | if (ret) |
| 1873 | return ret; |
| 1874 | |
Michel Thierry | fc0412e | 2014-10-16 16:13:38 +0100 | [diff] [blame] | 1875 | intel_runtime_pm_get(dev_priv); |
| 1876 | |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 1877 | for_each_ring(ring, dev_priv, ring_id) { |
| 1878 | struct intel_ctx_submit_request *head_req = NULL; |
| 1879 | int count = 0; |
| 1880 | unsigned long flags; |
| 1881 | |
| 1882 | seq_printf(m, "%s\n", ring->name); |
| 1883 | |
| 1884 | status = I915_READ(RING_EXECLIST_STATUS(ring)); |
| 1885 | ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4); |
| 1886 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
| 1887 | status, ctx_id); |
| 1888 | |
| 1889 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); |
| 1890 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
| 1891 | |
| 1892 | read_pointer = ring->next_context_status_buffer; |
| 1893 | write_pointer = status_pointer & 0x07; |
| 1894 | if (read_pointer > write_pointer) |
| 1895 | write_pointer += 6; |
| 1896 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
| 1897 | read_pointer, write_pointer); |
| 1898 | |
| 1899 | for (i = 0; i < 6; i++) { |
| 1900 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i); |
| 1901 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4); |
| 1902 | |
| 1903 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", |
| 1904 | i, status, ctx_id); |
| 1905 | } |
| 1906 | |
| 1907 | spin_lock_irqsave(&ring->execlist_lock, flags); |
| 1908 | list_for_each(cursor, &ring->execlist_queue) |
| 1909 | count++; |
| 1910 | head_req = list_first_entry_or_null(&ring->execlist_queue, |
| 1911 | struct intel_ctx_submit_request, execlist_link); |
| 1912 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
| 1913 | |
| 1914 | seq_printf(m, "\t%d requests in queue\n", count); |
| 1915 | if (head_req) { |
| 1916 | struct drm_i915_gem_object *ctx_obj; |
| 1917 | |
| 1918 | ctx_obj = head_req->ctx->engine[ring_id].state; |
| 1919 | seq_printf(m, "\tHead request id: %u\n", |
| 1920 | intel_execlists_ctx_id(ctx_obj)); |
| 1921 | seq_printf(m, "\tHead request tail: %u\n", |
| 1922 | head_req->tail); |
| 1923 | } |
| 1924 | |
| 1925 | seq_putc(m, '\n'); |
| 1926 | } |
| 1927 | |
Michel Thierry | fc0412e | 2014-10-16 16:13:38 +0100 | [diff] [blame] | 1928 | intel_runtime_pm_put(dev_priv); |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 1929 | mutex_unlock(&dev->struct_mutex); |
| 1930 | |
| 1931 | return 0; |
| 1932 | } |
| 1933 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1934 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
| 1935 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1936 | struct drm_info_node *node = m->private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1937 | struct drm_device *dev = node->minor->dev; |
| 1938 | struct drm_i915_private *dev_priv = dev->dev_private; |
Deepak S | 43709ba | 2013-11-23 14:55:44 +0530 | [diff] [blame] | 1939 | unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1940 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1941 | spin_lock_irq(&dev_priv->uncore.lock); |
Deepak S | 43709ba | 2013-11-23 14:55:44 +0530 | [diff] [blame] | 1942 | if (IS_VALLEYVIEW(dev)) { |
| 1943 | fw_rendercount = dev_priv->uncore.fw_rendercount; |
| 1944 | fw_mediacount = dev_priv->uncore.fw_mediacount; |
| 1945 | } else |
| 1946 | forcewake_count = dev_priv->uncore.forcewake_count; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1947 | spin_unlock_irq(&dev_priv->uncore.lock); |
Daniel Vetter | 9f1f46a | 2011-12-14 13:57:03 +0100 | [diff] [blame] | 1948 | |
Deepak S | 43709ba | 2013-11-23 14:55:44 +0530 | [diff] [blame] | 1949 | if (IS_VALLEYVIEW(dev)) { |
| 1950 | seq_printf(m, "fw_rendercount = %u\n", fw_rendercount); |
| 1951 | seq_printf(m, "fw_mediacount = %u\n", fw_mediacount); |
| 1952 | } else |
| 1953 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 1954 | |
| 1955 | return 0; |
| 1956 | } |
| 1957 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1958 | static const char *swizzle_string(unsigned swizzle) |
| 1959 | { |
Damien Lespiau | aee56cf | 2013-06-24 22:59:49 +0100 | [diff] [blame] | 1960 | switch (swizzle) { |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1961 | case I915_BIT_6_SWIZZLE_NONE: |
| 1962 | return "none"; |
| 1963 | case I915_BIT_6_SWIZZLE_9: |
| 1964 | return "bit9"; |
| 1965 | case I915_BIT_6_SWIZZLE_9_10: |
| 1966 | return "bit9/bit10"; |
| 1967 | case I915_BIT_6_SWIZZLE_9_11: |
| 1968 | return "bit9/bit11"; |
| 1969 | case I915_BIT_6_SWIZZLE_9_10_11: |
| 1970 | return "bit9/bit10/bit11"; |
| 1971 | case I915_BIT_6_SWIZZLE_9_17: |
| 1972 | return "bit9/bit17"; |
| 1973 | case I915_BIT_6_SWIZZLE_9_10_17: |
| 1974 | return "bit9/bit10/bit17"; |
| 1975 | case I915_BIT_6_SWIZZLE_UNKNOWN: |
Masanari Iida | 8a168ca | 2012-12-29 02:00:09 +0900 | [diff] [blame] | 1976 | return "unknown"; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1977 | } |
| 1978 | |
| 1979 | return "bug"; |
| 1980 | } |
| 1981 | |
| 1982 | static int i915_swizzle_info(struct seq_file *m, void *data) |
| 1983 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 1984 | struct drm_info_node *node = m->private; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1985 | struct drm_device *dev = node->minor->dev; |
| 1986 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1987 | int ret; |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1988 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1989 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1990 | if (ret) |
| 1991 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 1992 | intel_runtime_pm_get(dev_priv); |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 1993 | |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 1994 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
| 1995 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); |
| 1996 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", |
| 1997 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); |
| 1998 | |
| 1999 | if (IS_GEN3(dev) || IS_GEN4(dev)) { |
| 2000 | seq_printf(m, "DDC = 0x%08x\n", |
| 2001 | I915_READ(DCC)); |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 2002 | seq_printf(m, "DDC2 = 0x%08x\n", |
| 2003 | I915_READ(DCC2)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2004 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
| 2005 | I915_READ16(C0DRB3)); |
| 2006 | seq_printf(m, "C1DRB3 = 0x%04x\n", |
| 2007 | I915_READ16(C1DRB3)); |
Ben Widawsky | 9d3203e | 2013-11-02 21:07:14 -0700 | [diff] [blame] | 2008 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 2009 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
| 2010 | I915_READ(MAD_DIMM_C0)); |
| 2011 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", |
| 2012 | I915_READ(MAD_DIMM_C1)); |
| 2013 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", |
| 2014 | I915_READ(MAD_DIMM_C2)); |
| 2015 | seq_printf(m, "TILECTL = 0x%08x\n", |
| 2016 | I915_READ(TILECTL)); |
Robert Beckett | 5907f5f | 2014-01-23 14:23:14 +0000 | [diff] [blame] | 2017 | if (INTEL_INFO(dev)->gen >= 8) |
Ben Widawsky | 9d3203e | 2013-11-02 21:07:14 -0700 | [diff] [blame] | 2018 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
| 2019 | I915_READ(GAMTARBMODE)); |
| 2020 | else |
| 2021 | seq_printf(m, "ARB_MODE = 0x%08x\n", |
| 2022 | I915_READ(ARB_MODE)); |
Daniel Vetter | 3fa7d23 | 2012-01-31 16:47:56 +0100 | [diff] [blame] | 2023 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
| 2024 | I915_READ(DISP_ARB_CTL)); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2025 | } |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 2026 | |
| 2027 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
| 2028 | seq_puts(m, "L-shaped memory detected\n"); |
| 2029 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2030 | intel_runtime_pm_put(dev_priv); |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 2031 | mutex_unlock(&dev->struct_mutex); |
| 2032 | |
| 2033 | return 0; |
| 2034 | } |
| 2035 | |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2036 | static int per_file_ctx(int id, void *ptr, void *data) |
| 2037 | { |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2038 | struct intel_context *ctx = ptr; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2039 | struct seq_file *m = data; |
Daniel Vetter | ae6c480 | 2014-08-06 15:04:53 +0200 | [diff] [blame] | 2040 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
| 2041 | |
| 2042 | if (!ppgtt) { |
| 2043 | seq_printf(m, " no ppgtt for context %d\n", |
| 2044 | ctx->user_handle); |
| 2045 | return 0; |
| 2046 | } |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2047 | |
Oscar Mateo | f83d651 | 2014-05-22 14:13:38 +0100 | [diff] [blame] | 2048 | if (i915_gem_context_is_default(ctx)) |
| 2049 | seq_puts(m, " default context:\n"); |
| 2050 | else |
Oscar Mateo | 821d66d | 2014-07-03 16:28:00 +0100 | [diff] [blame] | 2051 | seq_printf(m, " context %d:\n", ctx->user_handle); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2052 | ppgtt->debug_dump(ppgtt, m); |
| 2053 | |
| 2054 | return 0; |
| 2055 | } |
| 2056 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2057 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2058 | { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2059 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2060 | struct intel_engine_cs *ring; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2061 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 2062 | int unused, i; |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2063 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2064 | if (!ppgtt) |
| 2065 | return; |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2066 | |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2067 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); |
Ben Widawsky | 5abbcca | 2014-02-21 13:06:34 -0800 | [diff] [blame] | 2068 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2069 | for_each_ring(ring, dev_priv, unused) { |
| 2070 | seq_printf(m, "%s\n", ring->name); |
| 2071 | for (i = 0; i < 4; i++) { |
| 2072 | u32 offset = 0x270 + i * 8; |
| 2073 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); |
| 2074 | pdp <<= 32; |
| 2075 | pdp |= I915_READ(ring->mmio_base + offset); |
Ville Syrjälä | a2a5b15 | 2014-03-31 18:17:16 +0300 | [diff] [blame] | 2076 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2077 | } |
| 2078 | } |
| 2079 | } |
| 2080 | |
| 2081 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
| 2082 | { |
| 2083 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2084 | struct intel_engine_cs *ring; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2085 | struct drm_file *file; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2086 | int i; |
| 2087 | |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2088 | if (INTEL_INFO(dev)->gen == 6) |
| 2089 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
| 2090 | |
Chris Wilson | a2c7f6f | 2012-09-01 20:51:22 +0100 | [diff] [blame] | 2091 | for_each_ring(ring, dev_priv, i) { |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2092 | seq_printf(m, "%s\n", ring->name); |
| 2093 | if (INTEL_INFO(dev)->gen == 7) |
| 2094 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); |
| 2095 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); |
| 2096 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); |
| 2097 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); |
| 2098 | } |
| 2099 | if (dev_priv->mm.aliasing_ppgtt) { |
| 2100 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 2101 | |
Damien Lespiau | 267f0c9 | 2013-06-24 22:59:48 +0100 | [diff] [blame] | 2102 | seq_puts(m, "aliasing PPGTT:\n"); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2103 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2104 | |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 2105 | ppgtt->debug_dump(ppgtt, m); |
Daniel Vetter | ae6c480 | 2014-08-06 15:04:53 +0200 | [diff] [blame] | 2106 | } |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2107 | |
| 2108 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
| 2109 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2110 | |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2111 | seq_printf(m, "proc: %s\n", |
| 2112 | get_pid_task(file->pid, PIDTYPE_PID)->comm); |
Ben Widawsky | 1c60fef | 2013-12-06 14:11:30 -0800 | [diff] [blame] | 2113 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2114 | } |
| 2115 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2116 | } |
| 2117 | |
| 2118 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
| 2119 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2120 | struct drm_info_node *node = m->private; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2121 | struct drm_device *dev = node->minor->dev; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2122 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2123 | |
| 2124 | int ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2125 | if (ret) |
| 2126 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2127 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | 77df677 | 2013-11-02 21:07:30 -0700 | [diff] [blame] | 2128 | |
| 2129 | if (INTEL_INFO(dev)->gen >= 8) |
| 2130 | gen8_ppgtt_info(m, dev); |
| 2131 | else if (INTEL_INFO(dev)->gen >= 6) |
| 2132 | gen6_ppgtt_info(m, dev); |
| 2133 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2134 | intel_runtime_pm_put(dev_priv); |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 2135 | mutex_unlock(&dev->struct_mutex); |
| 2136 | |
| 2137 | return 0; |
| 2138 | } |
| 2139 | |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2140 | static int i915_llc(struct seq_file *m, void *data) |
| 2141 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2142 | struct drm_info_node *node = m->private; |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 2143 | struct drm_device *dev = node->minor->dev; |
| 2144 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2145 | |
| 2146 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ |
| 2147 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
| 2148 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); |
| 2149 | |
| 2150 | return 0; |
| 2151 | } |
| 2152 | |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2153 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
| 2154 | { |
| 2155 | struct drm_info_node *node = m->private; |
| 2156 | struct drm_device *dev = node->minor->dev; |
| 2157 | struct drm_i915_private *dev_priv = dev->dev_private; |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2158 | u32 psrperf = 0; |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2159 | u32 stat[3]; |
| 2160 | enum pipe pipe; |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2161 | bool enabled = false; |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2162 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2163 | intel_runtime_pm_get(dev_priv); |
| 2164 | |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2165 | mutex_lock(&dev_priv->psr.lock); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2166 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
| 2167 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); |
Daniel Vetter | 2807cf6 | 2014-07-11 10:30:11 -0700 | [diff] [blame] | 2168 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
Rodrigo Vivi | 5755c78 | 2014-06-12 10:16:45 -0700 | [diff] [blame] | 2169 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2170 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
| 2171 | dev_priv->psr.busy_frontbuffer_bits); |
| 2172 | seq_printf(m, "Re-enable work scheduled: %s\n", |
| 2173 | yesno(work_busy(&dev_priv->psr.work.work))); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2174 | |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2175 | if (HAS_PSR(dev)) { |
| 2176 | if (HAS_DDI(dev)) |
| 2177 | enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
| 2178 | else { |
| 2179 | for_each_pipe(dev_priv, pipe) { |
| 2180 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & |
| 2181 | VLV_EDP_PSR_CURR_STATE_MASK; |
| 2182 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || |
| 2183 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) |
| 2184 | enabled = true; |
| 2185 | } |
| 2186 | } |
| 2187 | } |
| 2188 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2189 | |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2190 | if (!HAS_DDI(dev)) |
| 2191 | for_each_pipe(dev_priv, pipe) { |
| 2192 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || |
| 2193 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) |
| 2194 | seq_printf(m, " pipe %c", pipe_name(pipe)); |
| 2195 | } |
| 2196 | seq_puts(m, "\n"); |
| 2197 | |
| 2198 | /* CHV PSR has no kind of performance counter */ |
| 2199 | if (HAS_PSR(dev) && HAS_DDI(dev)) { |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 2200 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & |
| 2201 | EDP_PSR_PERF_CNT_MASK; |
Rodrigo Vivi | a6cbdb8 | 2014-11-14 08:52:40 -0800 | [diff] [blame] | 2202 | |
| 2203 | seq_printf(m, "Performance_Counter: %u\n", psrperf); |
| 2204 | } |
Daniel Vetter | fa128fa | 2014-07-11 10:30:17 -0700 | [diff] [blame] | 2205 | mutex_unlock(&dev_priv->psr.lock); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2206 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 2207 | intel_runtime_pm_put(dev_priv); |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 2208 | return 0; |
| 2209 | } |
| 2210 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 2211 | static int i915_sink_crc(struct seq_file *m, void *data) |
| 2212 | { |
| 2213 | struct drm_info_node *node = m->private; |
| 2214 | struct drm_device *dev = node->minor->dev; |
| 2215 | struct intel_encoder *encoder; |
| 2216 | struct intel_connector *connector; |
| 2217 | struct intel_dp *intel_dp = NULL; |
| 2218 | int ret; |
| 2219 | u8 crc[6]; |
| 2220 | |
| 2221 | drm_modeset_lock_all(dev); |
| 2222 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 2223 | base.head) { |
| 2224 | |
| 2225 | if (connector->base.dpms != DRM_MODE_DPMS_ON) |
| 2226 | continue; |
| 2227 | |
Paulo Zanoni | b6ae3c7 | 2014-02-13 17:51:33 -0200 | [diff] [blame] | 2228 | if (!connector->base.encoder) |
| 2229 | continue; |
| 2230 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 2231 | encoder = to_intel_encoder(connector->base.encoder); |
| 2232 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 2233 | continue; |
| 2234 | |
| 2235 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 2236 | |
| 2237 | ret = intel_dp_sink_crc(intel_dp, crc); |
| 2238 | if (ret) |
| 2239 | goto out; |
| 2240 | |
| 2241 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", |
| 2242 | crc[0], crc[1], crc[2], |
| 2243 | crc[3], crc[4], crc[5]); |
| 2244 | goto out; |
| 2245 | } |
| 2246 | ret = -ENODEV; |
| 2247 | out: |
| 2248 | drm_modeset_unlock_all(dev); |
| 2249 | return ret; |
| 2250 | } |
| 2251 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2252 | static int i915_energy_uJ(struct seq_file *m, void *data) |
| 2253 | { |
| 2254 | struct drm_info_node *node = m->private; |
| 2255 | struct drm_device *dev = node->minor->dev; |
| 2256 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2257 | u64 power; |
| 2258 | u32 units; |
| 2259 | |
| 2260 | if (INTEL_INFO(dev)->gen < 6) |
| 2261 | return -ENODEV; |
| 2262 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 2263 | intel_runtime_pm_get(dev_priv); |
| 2264 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2265 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
| 2266 | power = (power & 0x1f00) >> 8; |
| 2267 | units = 1000000 / (1 << power); /* convert to uJ */ |
| 2268 | power = I915_READ(MCH_SECP_NRG_STTS); |
| 2269 | power *= units; |
| 2270 | |
Paulo Zanoni | 36623ef | 2014-02-21 13:52:23 -0300 | [diff] [blame] | 2271 | intel_runtime_pm_put(dev_priv); |
| 2272 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2273 | seq_printf(m, "%llu", (long long unsigned)power); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2274 | |
| 2275 | return 0; |
| 2276 | } |
| 2277 | |
| 2278 | static int i915_pc8_status(struct seq_file *m, void *unused) |
| 2279 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2280 | struct drm_info_node *node = m->private; |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2281 | struct drm_device *dev = node->minor->dev; |
| 2282 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2283 | |
Zhenyu Wang | 85b8d5c | 2014-04-01 19:39:48 -0300 | [diff] [blame] | 2284 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2285 | seq_puts(m, "not supported\n"); |
| 2286 | return 0; |
| 2287 | } |
| 2288 | |
Paulo Zanoni | 86c4ec0 | 2014-02-21 13:52:24 -0300 | [diff] [blame] | 2289 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2290 | seq_printf(m, "IRQs disabled: %s\n", |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 2291 | yesno(!intel_irqs_enabled(dev_priv))); |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 2292 | |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 2293 | return 0; |
| 2294 | } |
| 2295 | |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2296 | static const char *power_domain_str(enum intel_display_power_domain domain) |
| 2297 | { |
| 2298 | switch (domain) { |
| 2299 | case POWER_DOMAIN_PIPE_A: |
| 2300 | return "PIPE_A"; |
| 2301 | case POWER_DOMAIN_PIPE_B: |
| 2302 | return "PIPE_B"; |
| 2303 | case POWER_DOMAIN_PIPE_C: |
| 2304 | return "PIPE_C"; |
| 2305 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: |
| 2306 | return "PIPE_A_PANEL_FITTER"; |
| 2307 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: |
| 2308 | return "PIPE_B_PANEL_FITTER"; |
| 2309 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: |
| 2310 | return "PIPE_C_PANEL_FITTER"; |
| 2311 | case POWER_DOMAIN_TRANSCODER_A: |
| 2312 | return "TRANSCODER_A"; |
| 2313 | case POWER_DOMAIN_TRANSCODER_B: |
| 2314 | return "TRANSCODER_B"; |
| 2315 | case POWER_DOMAIN_TRANSCODER_C: |
| 2316 | return "TRANSCODER_C"; |
| 2317 | case POWER_DOMAIN_TRANSCODER_EDP: |
| 2318 | return "TRANSCODER_EDP"; |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 2319 | case POWER_DOMAIN_PORT_DDI_A_2_LANES: |
| 2320 | return "PORT_DDI_A_2_LANES"; |
| 2321 | case POWER_DOMAIN_PORT_DDI_A_4_LANES: |
| 2322 | return "PORT_DDI_A_4_LANES"; |
| 2323 | case POWER_DOMAIN_PORT_DDI_B_2_LANES: |
| 2324 | return "PORT_DDI_B_2_LANES"; |
| 2325 | case POWER_DOMAIN_PORT_DDI_B_4_LANES: |
| 2326 | return "PORT_DDI_B_4_LANES"; |
| 2327 | case POWER_DOMAIN_PORT_DDI_C_2_LANES: |
| 2328 | return "PORT_DDI_C_2_LANES"; |
| 2329 | case POWER_DOMAIN_PORT_DDI_C_4_LANES: |
| 2330 | return "PORT_DDI_C_4_LANES"; |
| 2331 | case POWER_DOMAIN_PORT_DDI_D_2_LANES: |
| 2332 | return "PORT_DDI_D_2_LANES"; |
| 2333 | case POWER_DOMAIN_PORT_DDI_D_4_LANES: |
| 2334 | return "PORT_DDI_D_4_LANES"; |
| 2335 | case POWER_DOMAIN_PORT_DSI: |
| 2336 | return "PORT_DSI"; |
| 2337 | case POWER_DOMAIN_PORT_CRT: |
| 2338 | return "PORT_CRT"; |
| 2339 | case POWER_DOMAIN_PORT_OTHER: |
| 2340 | return "PORT_OTHER"; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2341 | case POWER_DOMAIN_VGA: |
| 2342 | return "VGA"; |
| 2343 | case POWER_DOMAIN_AUDIO: |
| 2344 | return "AUDIO"; |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 2345 | case POWER_DOMAIN_PLLS: |
| 2346 | return "PLLS"; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2347 | case POWER_DOMAIN_INIT: |
| 2348 | return "INIT"; |
| 2349 | default: |
| 2350 | WARN_ON(1); |
| 2351 | return "?"; |
| 2352 | } |
| 2353 | } |
| 2354 | |
| 2355 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
| 2356 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2357 | struct drm_info_node *node = m->private; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 2358 | struct drm_device *dev = node->minor->dev; |
| 2359 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2360 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 2361 | int i; |
| 2362 | |
| 2363 | mutex_lock(&power_domains->lock); |
| 2364 | |
| 2365 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); |
| 2366 | for (i = 0; i < power_domains->power_well_count; i++) { |
| 2367 | struct i915_power_well *power_well; |
| 2368 | enum intel_display_power_domain power_domain; |
| 2369 | |
| 2370 | power_well = &power_domains->power_wells[i]; |
| 2371 | seq_printf(m, "%-25s %d\n", power_well->name, |
| 2372 | power_well->count); |
| 2373 | |
| 2374 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; |
| 2375 | power_domain++) { |
| 2376 | if (!(BIT(power_domain) & power_well->domains)) |
| 2377 | continue; |
| 2378 | |
| 2379 | seq_printf(m, " %-23s %d\n", |
| 2380 | power_domain_str(power_domain), |
| 2381 | power_domains->domain_use_count[power_domain]); |
| 2382 | } |
| 2383 | } |
| 2384 | |
| 2385 | mutex_unlock(&power_domains->lock); |
| 2386 | |
| 2387 | return 0; |
| 2388 | } |
| 2389 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2390 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
| 2391 | struct drm_display_mode *mode) |
| 2392 | { |
| 2393 | int i; |
| 2394 | |
| 2395 | for (i = 0; i < tabs; i++) |
| 2396 | seq_putc(m, '\t'); |
| 2397 | |
| 2398 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", |
| 2399 | mode->base.id, mode->name, |
| 2400 | mode->vrefresh, mode->clock, |
| 2401 | mode->hdisplay, mode->hsync_start, |
| 2402 | mode->hsync_end, mode->htotal, |
| 2403 | mode->vdisplay, mode->vsync_start, |
| 2404 | mode->vsync_end, mode->vtotal, |
| 2405 | mode->type, mode->flags); |
| 2406 | } |
| 2407 | |
| 2408 | static void intel_encoder_info(struct seq_file *m, |
| 2409 | struct intel_crtc *intel_crtc, |
| 2410 | struct intel_encoder *intel_encoder) |
| 2411 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2412 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2413 | struct drm_device *dev = node->minor->dev; |
| 2414 | struct drm_crtc *crtc = &intel_crtc->base; |
| 2415 | struct intel_connector *intel_connector; |
| 2416 | struct drm_encoder *encoder; |
| 2417 | |
| 2418 | encoder = &intel_encoder->base; |
| 2419 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", |
Jani Nikula | 8e329a0 | 2014-06-03 14:56:21 +0300 | [diff] [blame] | 2420 | encoder->base.id, encoder->name); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2421 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
| 2422 | struct drm_connector *connector = &intel_connector->base; |
| 2423 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", |
| 2424 | connector->base.id, |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 2425 | connector->name, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2426 | drm_get_connector_status_name(connector->status)); |
| 2427 | if (connector->status == connector_status_connected) { |
| 2428 | struct drm_display_mode *mode = &crtc->mode; |
| 2429 | seq_printf(m, ", mode:\n"); |
| 2430 | intel_seq_print_mode(m, 2, mode); |
| 2431 | } else { |
| 2432 | seq_putc(m, '\n'); |
| 2433 | } |
| 2434 | } |
| 2435 | } |
| 2436 | |
| 2437 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) |
| 2438 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2439 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2440 | struct drm_device *dev = node->minor->dev; |
| 2441 | struct drm_crtc *crtc = &intel_crtc->base; |
| 2442 | struct intel_encoder *intel_encoder; |
| 2443 | |
Matt Roper | 5aa8a93 | 2014-06-16 10:12:55 -0700 | [diff] [blame] | 2444 | if (crtc->primary->fb) |
| 2445 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
| 2446 | crtc->primary->fb->base.id, crtc->x, crtc->y, |
| 2447 | crtc->primary->fb->width, crtc->primary->fb->height); |
| 2448 | else |
| 2449 | seq_puts(m, "\tprimary plane disabled\n"); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2450 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
| 2451 | intel_encoder_info(m, intel_crtc, intel_encoder); |
| 2452 | } |
| 2453 | |
| 2454 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) |
| 2455 | { |
| 2456 | struct drm_display_mode *mode = panel->fixed_mode; |
| 2457 | |
| 2458 | seq_printf(m, "\tfixed mode:\n"); |
| 2459 | intel_seq_print_mode(m, 2, mode); |
| 2460 | } |
| 2461 | |
| 2462 | static void intel_dp_info(struct seq_file *m, |
| 2463 | struct intel_connector *intel_connector) |
| 2464 | { |
| 2465 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
| 2466 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 2467 | |
| 2468 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); |
| 2469 | seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : |
| 2470 | "no"); |
| 2471 | if (intel_encoder->type == INTEL_OUTPUT_EDP) |
| 2472 | intel_panel_info(m, &intel_connector->panel); |
| 2473 | } |
| 2474 | |
| 2475 | static void intel_hdmi_info(struct seq_file *m, |
| 2476 | struct intel_connector *intel_connector) |
| 2477 | { |
| 2478 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
| 2479 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); |
| 2480 | |
| 2481 | seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : |
| 2482 | "no"); |
| 2483 | } |
| 2484 | |
| 2485 | static void intel_lvds_info(struct seq_file *m, |
| 2486 | struct intel_connector *intel_connector) |
| 2487 | { |
| 2488 | intel_panel_info(m, &intel_connector->panel); |
| 2489 | } |
| 2490 | |
| 2491 | static void intel_connector_info(struct seq_file *m, |
| 2492 | struct drm_connector *connector) |
| 2493 | { |
| 2494 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 2495 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
Jesse Barnes | f103fc7 | 2014-02-20 12:39:57 -0800 | [diff] [blame] | 2496 | struct drm_display_mode *mode; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2497 | |
| 2498 | seq_printf(m, "connector %d: type %s, status: %s\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 2499 | connector->base.id, connector->name, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2500 | drm_get_connector_status_name(connector->status)); |
| 2501 | if (connector->status == connector_status_connected) { |
| 2502 | seq_printf(m, "\tname: %s\n", connector->display_info.name); |
| 2503 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", |
| 2504 | connector->display_info.width_mm, |
| 2505 | connector->display_info.height_mm); |
| 2506 | seq_printf(m, "\tsubpixel order: %s\n", |
| 2507 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); |
| 2508 | seq_printf(m, "\tCEA rev: %d\n", |
| 2509 | connector->display_info.cea_rev); |
| 2510 | } |
Dave Airlie | 36cd744 | 2014-05-02 13:44:18 +1000 | [diff] [blame] | 2511 | if (intel_encoder) { |
| 2512 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
| 2513 | intel_encoder->type == INTEL_OUTPUT_EDP) |
| 2514 | intel_dp_info(m, intel_connector); |
| 2515 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) |
| 2516 | intel_hdmi_info(m, intel_connector); |
| 2517 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) |
| 2518 | intel_lvds_info(m, intel_connector); |
| 2519 | } |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2520 | |
Jesse Barnes | f103fc7 | 2014-02-20 12:39:57 -0800 | [diff] [blame] | 2521 | seq_printf(m, "\tmodes:\n"); |
| 2522 | list_for_each_entry(mode, &connector->modes, head) |
| 2523 | intel_seq_print_mode(m, 2, mode); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2524 | } |
| 2525 | |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2526 | static bool cursor_active(struct drm_device *dev, int pipe) |
| 2527 | { |
| 2528 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2529 | u32 state; |
| 2530 | |
| 2531 | if (IS_845G(dev) || IS_I865G(dev)) |
| 2532 | state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2533 | else |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2534 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2535 | |
| 2536 | return state; |
| 2537 | } |
| 2538 | |
| 2539 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) |
| 2540 | { |
| 2541 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2542 | u32 pos; |
| 2543 | |
Ville Syrjälä | 5efb3e2 | 2014-04-09 13:28:53 +0300 | [diff] [blame] | 2544 | pos = I915_READ(CURPOS(pipe)); |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2545 | |
| 2546 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; |
| 2547 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) |
| 2548 | *x = -*x; |
| 2549 | |
| 2550 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; |
| 2551 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) |
| 2552 | *y = -*y; |
| 2553 | |
| 2554 | return cursor_active(dev, pipe); |
| 2555 | } |
| 2556 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2557 | static int i915_display_info(struct seq_file *m, void *unused) |
| 2558 | { |
Damien Lespiau | 9f25d00 | 2014-05-13 15:30:28 +0100 | [diff] [blame] | 2559 | struct drm_info_node *node = m->private; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2560 | struct drm_device *dev = node->minor->dev; |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2561 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2562 | struct intel_crtc *crtc; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2563 | struct drm_connector *connector; |
| 2564 | |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2565 | intel_runtime_pm_get(dev_priv); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2566 | drm_modeset_lock_all(dev); |
| 2567 | seq_printf(m, "CRTC info\n"); |
| 2568 | seq_printf(m, "---------\n"); |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 2569 | for_each_intel_crtc(dev, crtc) { |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2570 | bool active; |
| 2571 | int x, y; |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2572 | |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2573 | seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2574 | crtc->base.base.id, pipe_name(crtc->pipe), |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2575 | yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h); |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2576 | if (crtc->active) { |
Chris Wilson | 065f2ec | 2014-03-12 09:13:13 +0000 | [diff] [blame] | 2577 | intel_crtc_info(m, crtc); |
| 2578 | |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2579 | active = cursor_position(dev, crtc->pipe, &x, &y); |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2580 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
Chris Wilson | 4b0e333 | 2014-05-30 16:35:26 +0300 | [diff] [blame] | 2581 | yesno(crtc->cursor_base), |
Chris Wilson | 57127ef | 2014-07-04 08:20:11 +0100 | [diff] [blame] | 2582 | x, y, crtc->cursor_width, crtc->cursor_height, |
| 2583 | crtc->cursor_addr, yesno(active)); |
Paulo Zanoni | a23dc65 | 2014-04-01 14:55:11 -0300 | [diff] [blame] | 2584 | } |
Daniel Vetter | cace841 | 2014-05-22 17:56:31 +0200 | [diff] [blame] | 2585 | |
| 2586 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", |
| 2587 | yesno(!crtc->cpu_fifo_underrun_disabled), |
| 2588 | yesno(!crtc->pch_fifo_underrun_disabled)); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2589 | } |
| 2590 | |
| 2591 | seq_printf(m, "\n"); |
| 2592 | seq_printf(m, "Connector info\n"); |
| 2593 | seq_printf(m, "--------------\n"); |
| 2594 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 2595 | intel_connector_info(m, connector); |
| 2596 | } |
| 2597 | drm_modeset_unlock_all(dev); |
Paulo Zanoni | b0e5ddf | 2014-04-01 14:55:10 -0300 | [diff] [blame] | 2598 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 2599 | |
| 2600 | return 0; |
| 2601 | } |
| 2602 | |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2603 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
| 2604 | { |
| 2605 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2606 | struct drm_device *dev = node->minor->dev; |
| 2607 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2608 | struct intel_engine_cs *ring; |
| 2609 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 2610 | int i, j, ret; |
| 2611 | |
| 2612 | if (!i915_semaphore_is_enabled(dev)) { |
| 2613 | seq_puts(m, "Semaphores are disabled\n"); |
| 2614 | return 0; |
| 2615 | } |
| 2616 | |
| 2617 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2618 | if (ret) |
| 2619 | return ret; |
Paulo Zanoni | 0387206 | 2014-07-09 14:31:57 -0300 | [diff] [blame] | 2620 | intel_runtime_pm_get(dev_priv); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2621 | |
| 2622 | if (IS_BROADWELL(dev)) { |
| 2623 | struct page *page; |
| 2624 | uint64_t *seqno; |
| 2625 | |
| 2626 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); |
| 2627 | |
| 2628 | seqno = (uint64_t *)kmap_atomic(page); |
| 2629 | for_each_ring(ring, dev_priv, i) { |
| 2630 | uint64_t offset; |
| 2631 | |
| 2632 | seq_printf(m, "%s\n", ring->name); |
| 2633 | |
| 2634 | seq_puts(m, " Last signal:"); |
| 2635 | for (j = 0; j < num_rings; j++) { |
| 2636 | offset = i * I915_NUM_RINGS + j; |
| 2637 | seq_printf(m, "0x%08llx (0x%02llx) ", |
| 2638 | seqno[offset], offset * 8); |
| 2639 | } |
| 2640 | seq_putc(m, '\n'); |
| 2641 | |
| 2642 | seq_puts(m, " Last wait: "); |
| 2643 | for (j = 0; j < num_rings; j++) { |
| 2644 | offset = i + (j * I915_NUM_RINGS); |
| 2645 | seq_printf(m, "0x%08llx (0x%02llx) ", |
| 2646 | seqno[offset], offset * 8); |
| 2647 | } |
| 2648 | seq_putc(m, '\n'); |
| 2649 | |
| 2650 | } |
| 2651 | kunmap_atomic(seqno); |
| 2652 | } else { |
| 2653 | seq_puts(m, " Last signal:"); |
| 2654 | for_each_ring(ring, dev_priv, i) |
| 2655 | for (j = 0; j < num_rings; j++) |
| 2656 | seq_printf(m, "0x%08x\n", |
| 2657 | I915_READ(ring->semaphore.mbox.signal[j])); |
| 2658 | seq_putc(m, '\n'); |
| 2659 | } |
| 2660 | |
| 2661 | seq_puts(m, "\nSync seqno:\n"); |
| 2662 | for_each_ring(ring, dev_priv, i) { |
| 2663 | for (j = 0; j < num_rings; j++) { |
| 2664 | seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); |
| 2665 | } |
| 2666 | seq_putc(m, '\n'); |
| 2667 | } |
| 2668 | seq_putc(m, '\n'); |
| 2669 | |
Paulo Zanoni | 0387206 | 2014-07-09 14:31:57 -0300 | [diff] [blame] | 2670 | intel_runtime_pm_put(dev_priv); |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 2671 | mutex_unlock(&dev->struct_mutex); |
| 2672 | return 0; |
| 2673 | } |
| 2674 | |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 2675 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
| 2676 | { |
| 2677 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2678 | struct drm_device *dev = node->minor->dev; |
| 2679 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2680 | int i; |
| 2681 | |
| 2682 | drm_modeset_lock_all(dev); |
| 2683 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 2684 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 2685 | |
| 2686 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); |
Ander Conselvan de Oliveira | 1e6f2dd | 2014-10-29 11:32:31 +0200 | [diff] [blame] | 2687 | seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n", |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 2688 | pll->config.crtc_mask, pll->active, yesno(pll->on)); |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 2689 | seq_printf(m, " tracked hardware state:\n"); |
Ander Conselvan de Oliveira | 3e369b7 | 2014-10-29 11:32:32 +0200 | [diff] [blame] | 2690 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
| 2691 | seq_printf(m, " dpll_md: 0x%08x\n", |
| 2692 | pll->config.hw_state.dpll_md); |
| 2693 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); |
| 2694 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); |
| 2695 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 2696 | } |
| 2697 | drm_modeset_unlock_all(dev); |
| 2698 | |
| 2699 | return 0; |
| 2700 | } |
| 2701 | |
Damien Lespiau | 1ed1ef9 | 2014-08-30 16:50:59 +0100 | [diff] [blame] | 2702 | static int i915_wa_registers(struct seq_file *m, void *unused) |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2703 | { |
| 2704 | int i; |
| 2705 | int ret; |
| 2706 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2707 | struct drm_device *dev = node->minor->dev; |
| 2708 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2709 | |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2710 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 2711 | if (ret) |
| 2712 | return ret; |
| 2713 | |
| 2714 | intel_runtime_pm_get(dev_priv); |
| 2715 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 2716 | seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count); |
| 2717 | for (i = 0; i < dev_priv->workarounds.count; ++i) { |
Mika Kuoppala | 2fa60f6 | 2014-10-07 17:21:27 +0300 | [diff] [blame] | 2718 | u32 addr, mask, value, read; |
| 2719 | bool ok; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2720 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 2721 | addr = dev_priv->workarounds.reg[i].addr; |
| 2722 | mask = dev_priv->workarounds.reg[i].mask; |
Mika Kuoppala | 2fa60f6 | 2014-10-07 17:21:27 +0300 | [diff] [blame] | 2723 | value = dev_priv->workarounds.reg[i].value; |
| 2724 | read = I915_READ(addr); |
| 2725 | ok = (value & mask) == (read & mask); |
| 2726 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", |
| 2727 | addr, value, mask, read, ok ? "OK" : "FAIL"); |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 2728 | } |
| 2729 | |
| 2730 | intel_runtime_pm_put(dev_priv); |
| 2731 | mutex_unlock(&dev->struct_mutex); |
| 2732 | |
| 2733 | return 0; |
| 2734 | } |
| 2735 | |
Damien Lespiau | c5511e4 | 2014-11-04 17:06:51 +0000 | [diff] [blame] | 2736 | static int i915_ddb_info(struct seq_file *m, void *unused) |
| 2737 | { |
| 2738 | struct drm_info_node *node = m->private; |
| 2739 | struct drm_device *dev = node->minor->dev; |
| 2740 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2741 | struct skl_ddb_allocation *ddb; |
| 2742 | struct skl_ddb_entry *entry; |
| 2743 | enum pipe pipe; |
| 2744 | int plane; |
| 2745 | |
Damien Lespiau | 2fcffe1 | 2014-12-03 17:33:24 +0000 | [diff] [blame] | 2746 | if (INTEL_INFO(dev)->gen < 9) |
| 2747 | return 0; |
| 2748 | |
Damien Lespiau | c5511e4 | 2014-11-04 17:06:51 +0000 | [diff] [blame] | 2749 | drm_modeset_lock_all(dev); |
| 2750 | |
| 2751 | ddb = &dev_priv->wm.skl_hw.ddb; |
| 2752 | |
| 2753 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); |
| 2754 | |
| 2755 | for_each_pipe(dev_priv, pipe) { |
| 2756 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); |
| 2757 | |
| 2758 | for_each_plane(pipe, plane) { |
| 2759 | entry = &ddb->plane[pipe][plane]; |
| 2760 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, |
| 2761 | entry->start, entry->end, |
| 2762 | skl_ddb_entry_size(entry)); |
| 2763 | } |
| 2764 | |
| 2765 | entry = &ddb->cursor[pipe]; |
| 2766 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
| 2767 | entry->end, skl_ddb_entry_size(entry)); |
| 2768 | } |
| 2769 | |
| 2770 | drm_modeset_unlock_all(dev); |
| 2771 | |
| 2772 | return 0; |
| 2773 | } |
| 2774 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2775 | struct pipe_crc_info { |
| 2776 | const char *name; |
| 2777 | struct drm_device *dev; |
| 2778 | enum pipe pipe; |
| 2779 | }; |
| 2780 | |
Dave Airlie | 11bed958 | 2014-05-12 15:22:27 +1000 | [diff] [blame] | 2781 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
| 2782 | { |
| 2783 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2784 | struct drm_device *dev = node->minor->dev; |
| 2785 | struct drm_encoder *encoder; |
| 2786 | struct intel_encoder *intel_encoder; |
| 2787 | struct intel_digital_port *intel_dig_port; |
| 2788 | drm_modeset_lock_all(dev); |
| 2789 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 2790 | intel_encoder = to_intel_encoder(encoder); |
| 2791 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) |
| 2792 | continue; |
| 2793 | intel_dig_port = enc_to_dig_port(encoder); |
| 2794 | if (!intel_dig_port->dp.can_mst) |
| 2795 | continue; |
| 2796 | |
| 2797 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
| 2798 | } |
| 2799 | drm_modeset_unlock_all(dev); |
| 2800 | return 0; |
| 2801 | } |
| 2802 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2803 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2804 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2805 | struct pipe_crc_info *info = inode->i_private; |
| 2806 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 2807 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2808 | |
Daniel Vetter | 7eb1c49 | 2013-11-14 11:30:43 +0100 | [diff] [blame] | 2809 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
| 2810 | return -ENODEV; |
| 2811 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2812 | spin_lock_irq(&pipe_crc->lock); |
| 2813 | |
| 2814 | if (pipe_crc->opened) { |
| 2815 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2816 | return -EBUSY; /* already open */ |
| 2817 | } |
| 2818 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2819 | pipe_crc->opened = true; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2820 | filep->private_data = inode->i_private; |
| 2821 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2822 | spin_unlock_irq(&pipe_crc->lock); |
| 2823 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2824 | return 0; |
| 2825 | } |
| 2826 | |
| 2827 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) |
| 2828 | { |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2829 | struct pipe_crc_info *info = inode->i_private; |
| 2830 | struct drm_i915_private *dev_priv = info->dev->dev_private; |
| 2831 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2832 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2833 | spin_lock_irq(&pipe_crc->lock); |
| 2834 | pipe_crc->opened = false; |
| 2835 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | be5c7a9 | 2013-10-15 18:55:41 +0100 | [diff] [blame] | 2836 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2837 | return 0; |
| 2838 | } |
| 2839 | |
| 2840 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ |
| 2841 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) |
| 2842 | /* account for \'0' */ |
| 2843 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) |
| 2844 | |
| 2845 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) |
| 2846 | { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2847 | assert_spin_locked(&pipe_crc->lock); |
| 2848 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
| 2849 | INTEL_PIPE_CRC_ENTRIES_NR); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2850 | } |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2851 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2852 | static ssize_t |
| 2853 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, |
| 2854 | loff_t *pos) |
| 2855 | { |
| 2856 | struct pipe_crc_info *info = filep->private_data; |
| 2857 | struct drm_device *dev = info->dev; |
| 2858 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2859 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
| 2860 | char buf[PIPE_CRC_BUFFER_LEN]; |
| 2861 | int head, tail, n_entries, n; |
| 2862 | ssize_t bytes_read; |
| 2863 | |
| 2864 | /* |
| 2865 | * Don't allow user space to provide buffers not big enough to hold |
| 2866 | * a line of data. |
| 2867 | */ |
| 2868 | if (count < PIPE_CRC_LINE_LEN) |
| 2869 | return -EINVAL; |
| 2870 | |
| 2871 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) |
| 2872 | return 0; |
| 2873 | |
| 2874 | /* nothing to read */ |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2875 | spin_lock_irq(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2876 | while (pipe_crc_data_count(pipe_crc) == 0) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2877 | int ret; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2878 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2879 | if (filep->f_flags & O_NONBLOCK) { |
| 2880 | spin_unlock_irq(&pipe_crc->lock); |
| 2881 | return -EAGAIN; |
| 2882 | } |
| 2883 | |
| 2884 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
| 2885 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); |
| 2886 | if (ret) { |
| 2887 | spin_unlock_irq(&pipe_crc->lock); |
| 2888 | return ret; |
| 2889 | } |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2890 | } |
| 2891 | |
| 2892 | /* We now have one or more entries to read */ |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2893 | head = pipe_crc->head; |
| 2894 | tail = pipe_crc->tail; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2895 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
| 2896 | count / PIPE_CRC_LINE_LEN); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2897 | spin_unlock_irq(&pipe_crc->lock); |
| 2898 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2899 | bytes_read = 0; |
| 2900 | n = 0; |
| 2901 | do { |
| 2902 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
| 2903 | int ret; |
| 2904 | |
| 2905 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
| 2906 | "%8u %8x %8x %8x %8x %8x\n", |
| 2907 | entry->frame, entry->crc[0], |
| 2908 | entry->crc[1], entry->crc[2], |
| 2909 | entry->crc[3], entry->crc[4]); |
| 2910 | |
| 2911 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, |
| 2912 | buf, PIPE_CRC_LINE_LEN); |
| 2913 | if (ret == PIPE_CRC_LINE_LEN) |
| 2914 | return -EFAULT; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 2915 | |
| 2916 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); |
| 2917 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2918 | n++; |
| 2919 | } while (--n_entries); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2920 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 2921 | spin_lock_irq(&pipe_crc->lock); |
| 2922 | pipe_crc->tail = tail; |
| 2923 | spin_unlock_irq(&pipe_crc->lock); |
| 2924 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2925 | return bytes_read; |
| 2926 | } |
| 2927 | |
| 2928 | static const struct file_operations i915_pipe_crc_fops = { |
| 2929 | .owner = THIS_MODULE, |
| 2930 | .open = i915_pipe_crc_open, |
| 2931 | .read = i915_pipe_crc_read, |
| 2932 | .release = i915_pipe_crc_release, |
| 2933 | }; |
| 2934 | |
| 2935 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { |
| 2936 | { |
| 2937 | .name = "i915_pipe_A_crc", |
| 2938 | .pipe = PIPE_A, |
| 2939 | }, |
| 2940 | { |
| 2941 | .name = "i915_pipe_B_crc", |
| 2942 | .pipe = PIPE_B, |
| 2943 | }, |
| 2944 | { |
| 2945 | .name = "i915_pipe_C_crc", |
| 2946 | .pipe = PIPE_C, |
| 2947 | }, |
| 2948 | }; |
| 2949 | |
| 2950 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, |
| 2951 | enum pipe pipe) |
| 2952 | { |
| 2953 | struct drm_device *dev = minor->dev; |
| 2954 | struct dentry *ent; |
| 2955 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; |
| 2956 | |
| 2957 | info->dev = dev; |
| 2958 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, |
| 2959 | &i915_pipe_crc_fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 2960 | if (!ent) |
| 2961 | return -ENOMEM; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2962 | |
| 2963 | return drm_add_fake_info_node(minor, ent, info); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 2964 | } |
| 2965 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 2966 | static const char * const pipe_crc_sources[] = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2967 | "none", |
| 2968 | "plane1", |
| 2969 | "plane2", |
| 2970 | "pf", |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2971 | "pipe", |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 2972 | "TV", |
| 2973 | "DP-B", |
| 2974 | "DP-C", |
| 2975 | "DP-D", |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 2976 | "auto", |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2977 | }; |
| 2978 | |
| 2979 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) |
| 2980 | { |
| 2981 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); |
| 2982 | return pipe_crc_sources[source]; |
| 2983 | } |
| 2984 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2985 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2986 | { |
| 2987 | struct drm_device *dev = m->private; |
| 2988 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2989 | int i; |
| 2990 | |
| 2991 | for (i = 0; i < I915_MAX_PIPES; i++) |
| 2992 | seq_printf(m, "%c %s\n", pipe_name(i), |
| 2993 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); |
| 2994 | |
| 2995 | return 0; |
| 2996 | } |
| 2997 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 2998 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 2999 | { |
| 3000 | struct drm_device *dev = inode->i_private; |
| 3001 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3002 | return single_open(file, display_crc_ctl_show, dev); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3003 | } |
| 3004 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3005 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3006 | uint32_t *val) |
| 3007 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3008 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 3009 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 3010 | |
| 3011 | switch (*source) { |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3012 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3013 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; |
| 3014 | break; |
| 3015 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 3016 | *val = 0; |
| 3017 | break; |
| 3018 | default: |
| 3019 | return -EINVAL; |
| 3020 | } |
| 3021 | |
| 3022 | return 0; |
| 3023 | } |
| 3024 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3025 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
| 3026 | enum intel_pipe_crc_source *source) |
| 3027 | { |
| 3028 | struct intel_encoder *encoder; |
| 3029 | struct intel_crtc *crtc; |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 3030 | struct intel_digital_port *dig_port; |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3031 | int ret = 0; |
| 3032 | |
| 3033 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 3034 | |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 3035 | drm_modeset_lock_all(dev); |
Damien Lespiau | b2784e1 | 2014-08-05 11:29:37 +0100 | [diff] [blame] | 3036 | for_each_intel_encoder(dev, encoder) { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3037 | if (!encoder->base.crtc) |
| 3038 | continue; |
| 3039 | |
| 3040 | crtc = to_intel_crtc(encoder->base.crtc); |
| 3041 | |
| 3042 | if (crtc->pipe != pipe) |
| 3043 | continue; |
| 3044 | |
| 3045 | switch (encoder->type) { |
| 3046 | case INTEL_OUTPUT_TVOUT: |
| 3047 | *source = INTEL_PIPE_CRC_SOURCE_TV; |
| 3048 | break; |
| 3049 | case INTEL_OUTPUT_DISPLAYPORT: |
| 3050 | case INTEL_OUTPUT_EDP: |
Daniel Vetter | 2675680 | 2013-11-01 10:50:23 +0100 | [diff] [blame] | 3051 | dig_port = enc_to_dig_port(&encoder->base); |
| 3052 | switch (dig_port->port) { |
| 3053 | case PORT_B: |
| 3054 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; |
| 3055 | break; |
| 3056 | case PORT_C: |
| 3057 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; |
| 3058 | break; |
| 3059 | case PORT_D: |
| 3060 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; |
| 3061 | break; |
| 3062 | default: |
| 3063 | WARN(1, "nonexisting DP port %c\n", |
| 3064 | port_name(dig_port->port)); |
| 3065 | break; |
| 3066 | } |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3067 | break; |
Paulo Zanoni | 6847d71 | 2014-10-27 17:47:52 -0200 | [diff] [blame] | 3068 | default: |
| 3069 | break; |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3070 | } |
| 3071 | } |
Daniel Vetter | 6e9f798 | 2014-05-29 23:54:47 +0200 | [diff] [blame] | 3072 | drm_modeset_unlock_all(dev); |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3073 | |
| 3074 | return ret; |
| 3075 | } |
| 3076 | |
| 3077 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, |
| 3078 | enum pipe pipe, |
| 3079 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3080 | uint32_t *val) |
| 3081 | { |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3082 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3083 | bool need_stable_symbols = false; |
| 3084 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3085 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 3086 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 3087 | if (ret) |
| 3088 | return ret; |
| 3089 | } |
| 3090 | |
| 3091 | switch (*source) { |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3092 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3093 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; |
| 3094 | break; |
| 3095 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 3096 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3097 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3098 | break; |
| 3099 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 3100 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3101 | need_stable_symbols = true; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3102 | break; |
Ville Syrjälä | 2be5792 | 2014-12-09 21:28:29 +0200 | [diff] [blame^] | 3103 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
| 3104 | if (!IS_CHERRYVIEW(dev)) |
| 3105 | return -EINVAL; |
| 3106 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; |
| 3107 | need_stable_symbols = true; |
| 3108 | break; |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3109 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 3110 | *val = 0; |
| 3111 | break; |
| 3112 | default: |
| 3113 | return -EINVAL; |
| 3114 | } |
| 3115 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3116 | /* |
| 3117 | * When the pipe CRC tap point is after the transcoders we need |
| 3118 | * to tweak symbol-level features to produce a deterministic series of |
| 3119 | * symbols for a given frame. We need to reset those features only once |
| 3120 | * a frame (instead of every nth symbol): |
| 3121 | * - DC-balance: used to ensure a better clock recovery from the data |
| 3122 | * link (SDVO) |
| 3123 | * - DisplayPort scrambling: used for EMI reduction |
| 3124 | */ |
| 3125 | if (need_stable_symbols) { |
| 3126 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3127 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3128 | tmp |= DC_BALANCE_RESET_VLV; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3129 | switch (pipe) { |
| 3130 | case PIPE_A: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3131 | tmp |= PIPE_A_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3132 | break; |
| 3133 | case PIPE_B: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3134 | tmp |= PIPE_B_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3135 | break; |
| 3136 | case PIPE_C: |
| 3137 | tmp |= PIPE_C_SCRAMBLE_RESET; |
| 3138 | break; |
| 3139 | default: |
| 3140 | return -EINVAL; |
| 3141 | } |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3142 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3143 | } |
| 3144 | |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3145 | return 0; |
| 3146 | } |
| 3147 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3148 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3149 | enum pipe pipe, |
| 3150 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3151 | uint32_t *val) |
| 3152 | { |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3153 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3154 | bool need_stable_symbols = false; |
| 3155 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3156 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
| 3157 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); |
| 3158 | if (ret) |
| 3159 | return ret; |
| 3160 | } |
| 3161 | |
| 3162 | switch (*source) { |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3163 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3164 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; |
| 3165 | break; |
| 3166 | case INTEL_PIPE_CRC_SOURCE_TV: |
| 3167 | if (!SUPPORTS_TV(dev)) |
| 3168 | return -EINVAL; |
| 3169 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; |
| 3170 | break; |
| 3171 | case INTEL_PIPE_CRC_SOURCE_DP_B: |
| 3172 | if (!IS_G4X(dev)) |
| 3173 | return -EINVAL; |
| 3174 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3175 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3176 | break; |
| 3177 | case INTEL_PIPE_CRC_SOURCE_DP_C: |
| 3178 | if (!IS_G4X(dev)) |
| 3179 | return -EINVAL; |
| 3180 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3181 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3182 | break; |
| 3183 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
| 3184 | if (!IS_G4X(dev)) |
| 3185 | return -EINVAL; |
| 3186 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3187 | need_stable_symbols = true; |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3188 | break; |
| 3189 | case INTEL_PIPE_CRC_SOURCE_NONE: |
| 3190 | *val = 0; |
| 3191 | break; |
| 3192 | default: |
| 3193 | return -EINVAL; |
| 3194 | } |
| 3195 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3196 | /* |
| 3197 | * When the pipe CRC tap point is after the transcoders we need |
| 3198 | * to tweak symbol-level features to produce a deterministic series of |
| 3199 | * symbols for a given frame. We need to reset those features only once |
| 3200 | * a frame (instead of every nth symbol): |
| 3201 | * - DC-balance: used to ensure a better clock recovery from the data |
| 3202 | * link (SDVO) |
| 3203 | * - DisplayPort scrambling: used for EMI reduction |
| 3204 | */ |
| 3205 | if (need_stable_symbols) { |
| 3206 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3207 | |
| 3208 | WARN_ON(!IS_G4X(dev)); |
| 3209 | |
| 3210 | I915_WRITE(PORT_DFT_I9XX, |
| 3211 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); |
| 3212 | |
| 3213 | if (pipe == PIPE_A) |
| 3214 | tmp |= PIPE_A_SCRAMBLE_RESET; |
| 3215 | else |
| 3216 | tmp |= PIPE_B_SCRAMBLE_RESET; |
| 3217 | |
| 3218 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3219 | } |
| 3220 | |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3221 | return 0; |
| 3222 | } |
| 3223 | |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3224 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
| 3225 | enum pipe pipe) |
| 3226 | { |
| 3227 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3228 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3229 | |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3230 | switch (pipe) { |
| 3231 | case PIPE_A: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3232 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3233 | break; |
| 3234 | case PIPE_B: |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3235 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
Ville Syrjälä | eb73667 | 2014-12-09 21:28:28 +0200 | [diff] [blame] | 3236 | break; |
| 3237 | case PIPE_C: |
| 3238 | tmp &= ~PIPE_C_SCRAMBLE_RESET; |
| 3239 | break; |
| 3240 | default: |
| 3241 | return; |
| 3242 | } |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3243 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
| 3244 | tmp &= ~DC_BALANCE_RESET_VLV; |
| 3245 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3246 | |
| 3247 | } |
| 3248 | |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3249 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
| 3250 | enum pipe pipe) |
| 3251 | { |
| 3252 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3253 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
| 3254 | |
| 3255 | if (pipe == PIPE_A) |
| 3256 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
| 3257 | else |
| 3258 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
| 3259 | I915_WRITE(PORT_DFT2_G4X, tmp); |
| 3260 | |
| 3261 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { |
| 3262 | I915_WRITE(PORT_DFT_I9XX, |
| 3263 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); |
| 3264 | } |
| 3265 | } |
| 3266 | |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3267 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3268 | uint32_t *val) |
| 3269 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3270 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 3271 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; |
| 3272 | |
| 3273 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3274 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 3275 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; |
| 3276 | break; |
| 3277 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 3278 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; |
| 3279 | break; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3280 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
| 3281 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; |
| 3282 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3283 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3284 | *val = 0; |
| 3285 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3286 | default: |
| 3287 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3288 | } |
| 3289 | |
| 3290 | return 0; |
| 3291 | } |
| 3292 | |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3293 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
| 3294 | { |
| 3295 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3296 | struct intel_crtc *crtc = |
| 3297 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); |
| 3298 | |
| 3299 | drm_modeset_lock_all(dev); |
| 3300 | /* |
| 3301 | * If we use the eDP transcoder we need to make sure that we don't |
| 3302 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only |
| 3303 | * relevant on hsw with pipe A when using the always-on power well |
| 3304 | * routing. |
| 3305 | */ |
| 3306 | if (crtc->config.cpu_transcoder == TRANSCODER_EDP && |
| 3307 | !crtc->config.pch_pfit.enabled) { |
| 3308 | crtc->config.pch_pfit.force_thru = true; |
| 3309 | |
| 3310 | intel_display_power_get(dev_priv, |
| 3311 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); |
| 3312 | |
| 3313 | dev_priv->display.crtc_disable(&crtc->base); |
| 3314 | dev_priv->display.crtc_enable(&crtc->base); |
| 3315 | } |
| 3316 | drm_modeset_unlock_all(dev); |
| 3317 | } |
| 3318 | |
| 3319 | static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
| 3320 | { |
| 3321 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3322 | struct intel_crtc *crtc = |
| 3323 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); |
| 3324 | |
| 3325 | drm_modeset_lock_all(dev); |
| 3326 | /* |
| 3327 | * If we use the eDP transcoder we need to make sure that we don't |
| 3328 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only |
| 3329 | * relevant on hsw with pipe A when using the always-on power well |
| 3330 | * routing. |
| 3331 | */ |
| 3332 | if (crtc->config.pch_pfit.force_thru) { |
| 3333 | crtc->config.pch_pfit.force_thru = false; |
| 3334 | |
| 3335 | dev_priv->display.crtc_disable(&crtc->base); |
| 3336 | dev_priv->display.crtc_enable(&crtc->base); |
| 3337 | |
| 3338 | intel_display_power_put(dev_priv, |
| 3339 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); |
| 3340 | } |
| 3341 | drm_modeset_unlock_all(dev); |
| 3342 | } |
| 3343 | |
| 3344 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, |
| 3345 | enum pipe pipe, |
| 3346 | enum intel_pipe_crc_source *source, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3347 | uint32_t *val) |
| 3348 | { |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3349 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
| 3350 | *source = INTEL_PIPE_CRC_SOURCE_PF; |
| 3351 | |
| 3352 | switch (*source) { |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3353 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
| 3354 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; |
| 3355 | break; |
| 3356 | case INTEL_PIPE_CRC_SOURCE_PLANE2: |
| 3357 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; |
| 3358 | break; |
| 3359 | case INTEL_PIPE_CRC_SOURCE_PF: |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3360 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
| 3361 | hsw_trans_edp_pipe_A_crc_wa(dev); |
| 3362 | |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3363 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
| 3364 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3365 | case INTEL_PIPE_CRC_SOURCE_NONE: |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3366 | *val = 0; |
| 3367 | break; |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 3368 | default: |
| 3369 | return -EINVAL; |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3370 | } |
| 3371 | |
| 3372 | return 0; |
| 3373 | } |
| 3374 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3375 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
| 3376 | enum intel_pipe_crc_source source) |
| 3377 | { |
| 3378 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 3379 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
Paulo Zanoni | 8c740dc | 2014-10-17 18:42:03 -0300 | [diff] [blame] | 3380 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
| 3381 | pipe)); |
Borislav Petkov | 432f334 | 2013-11-21 16:49:46 +0100 | [diff] [blame] | 3382 | u32 val = 0; /* shut up gcc */ |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3383 | int ret; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3384 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 3385 | if (pipe_crc->source == source) |
| 3386 | return 0; |
| 3387 | |
Damien Lespiau | ae676fc | 2013-10-15 18:55:32 +0100 | [diff] [blame] | 3388 | /* forbid changing the source without going back to 'none' */ |
| 3389 | if (pipe_crc->source && source) |
| 3390 | return -EINVAL; |
| 3391 | |
Daniel Vetter | 9d8b058 | 2014-11-25 14:00:40 +0100 | [diff] [blame] | 3392 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) { |
| 3393 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
| 3394 | return -EIO; |
| 3395 | } |
| 3396 | |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3397 | if (IS_GEN2(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3398 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 52f843f | 2013-10-21 17:26:38 +0200 | [diff] [blame] | 3399 | else if (INTEL_INFO(dev)->gen < 5) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3400 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 7ac0129 | 2013-10-18 16:37:06 +0200 | [diff] [blame] | 3401 | else if (IS_VALLEYVIEW(dev)) |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3402 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 4b79ebf | 2013-10-16 22:55:59 +0200 | [diff] [blame] | 3403 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 3404 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3405 | else |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3406 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 3407 | |
| 3408 | if (ret != 0) |
| 3409 | return ret; |
| 3410 | |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 3411 | /* none -> real source transition */ |
| 3412 | if (source) { |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 3413 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
| 3414 | pipe_name(pipe), pipe_crc_source_name(source)); |
| 3415 | |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3416 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
| 3417 | INTEL_PIPE_CRC_ENTRIES_NR, |
| 3418 | GFP_KERNEL); |
| 3419 | if (!pipe_crc->entries) |
| 3420 | return -ENOMEM; |
| 3421 | |
Paulo Zanoni | 8c740dc | 2014-10-17 18:42:03 -0300 | [diff] [blame] | 3422 | /* |
| 3423 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets |
| 3424 | * enabled and disabled dynamically based on package C states, |
| 3425 | * user space can't make reliable use of the CRCs, so let's just |
| 3426 | * completely disable it. |
| 3427 | */ |
| 3428 | hsw_disable_ips(crtc); |
| 3429 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3430 | spin_lock_irq(&pipe_crc->lock); |
| 3431 | pipe_crc->head = 0; |
| 3432 | pipe_crc->tail = 0; |
| 3433 | spin_unlock_irq(&pipe_crc->lock); |
Damien Lespiau | 4b58436 | 2013-10-15 18:55:33 +0100 | [diff] [blame] | 3434 | } |
| 3435 | |
Damien Lespiau | cc3da17 | 2013-10-15 18:55:31 +0100 | [diff] [blame] | 3436 | pipe_crc->source = source; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3437 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3438 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
| 3439 | POSTING_READ(PIPE_CRC_CTL(pipe)); |
| 3440 | |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3441 | /* real source -> none transition */ |
| 3442 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3443 | struct intel_pipe_crc_entry *entries; |
Daniel Vetter | a33d710 | 2014-06-06 08:22:08 +0200 | [diff] [blame] | 3444 | struct intel_crtc *crtc = |
| 3445 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3446 | |
Damien Lespiau | 7cd6ccf | 2013-10-15 18:55:38 +0100 | [diff] [blame] | 3447 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
| 3448 | pipe_name(pipe)); |
| 3449 | |
Daniel Vetter | a33d710 | 2014-06-06 08:22:08 +0200 | [diff] [blame] | 3450 | drm_modeset_lock(&crtc->base.mutex, NULL); |
| 3451 | if (crtc->active) |
| 3452 | intel_wait_for_vblank(dev, pipe); |
| 3453 | drm_modeset_unlock(&crtc->base.mutex); |
Daniel Vetter | bcf17ab | 2013-10-16 22:55:50 +0200 | [diff] [blame] | 3454 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3455 | spin_lock_irq(&pipe_crc->lock); |
| 3456 | entries = pipe_crc->entries; |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3457 | pipe_crc->entries = NULL; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 3458 | spin_unlock_irq(&pipe_crc->lock); |
| 3459 | |
| 3460 | kfree(entries); |
Daniel Vetter | 8409360 | 2013-11-01 10:50:21 +0100 | [diff] [blame] | 3461 | |
| 3462 | if (IS_G4X(dev)) |
| 3463 | g4x_undo_pipe_scramble_reset(dev, pipe); |
Daniel Vetter | 8d2f24c | 2013-11-01 10:50:22 +0100 | [diff] [blame] | 3464 | else if (IS_VALLEYVIEW(dev)) |
| 3465 | vlv_undo_pipe_scramble_reset(dev, pipe); |
Daniel Vetter | fabf6e5 | 2014-05-29 14:10:22 +0200 | [diff] [blame] | 3466 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
| 3467 | hsw_undo_trans_edp_pipe_A_crc_wa(dev); |
Paulo Zanoni | 8c740dc | 2014-10-17 18:42:03 -0300 | [diff] [blame] | 3468 | |
| 3469 | hsw_enable_ips(crtc); |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 3470 | } |
| 3471 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3472 | return 0; |
| 3473 | } |
| 3474 | |
| 3475 | /* |
| 3476 | * Parse pipe CRC command strings: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3477 | * command: wsp* object wsp+ name wsp+ source wsp* |
| 3478 | * object: 'pipe' |
| 3479 | * name: (A | B | C) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3480 | * source: (none | plane1 | plane2 | pf) |
| 3481 | * wsp: (#0x20 | #0x9 | #0xA)+ |
| 3482 | * |
| 3483 | * eg.: |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3484 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
| 3485 | * "pipe A none" -> Stop CRC |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3486 | */ |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3487 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3488 | { |
| 3489 | int n_words = 0; |
| 3490 | |
| 3491 | while (*buf) { |
| 3492 | char *end; |
| 3493 | |
| 3494 | /* skip leading white space */ |
| 3495 | buf = skip_spaces(buf); |
| 3496 | if (!*buf) |
| 3497 | break; /* end of buffer */ |
| 3498 | |
| 3499 | /* find end of word */ |
| 3500 | for (end = buf; *end && !isspace(*end); end++) |
| 3501 | ; |
| 3502 | |
| 3503 | if (n_words == max_words) { |
| 3504 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", |
| 3505 | max_words); |
| 3506 | return -EINVAL; /* ran out of words[] before bytes */ |
| 3507 | } |
| 3508 | |
| 3509 | if (*end) |
| 3510 | *end++ = '\0'; |
| 3511 | words[n_words++] = buf; |
| 3512 | buf = end; |
| 3513 | } |
| 3514 | |
| 3515 | return n_words; |
| 3516 | } |
| 3517 | |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3518 | enum intel_pipe_crc_object { |
| 3519 | PIPE_CRC_OBJECT_PIPE, |
| 3520 | }; |
| 3521 | |
Daniel Vetter | e8dfcf7 | 2013-10-16 11:51:54 +0200 | [diff] [blame] | 3522 | static const char * const pipe_crc_objects[] = { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3523 | "pipe", |
| 3524 | }; |
| 3525 | |
| 3526 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3527 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3528 | { |
| 3529 | int i; |
| 3530 | |
| 3531 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) |
| 3532 | if (!strcmp(buf, pipe_crc_objects[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3533 | *o = i; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3534 | return 0; |
| 3535 | } |
| 3536 | |
| 3537 | return -EINVAL; |
| 3538 | } |
| 3539 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3540 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3541 | { |
| 3542 | const char name = buf[0]; |
| 3543 | |
| 3544 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) |
| 3545 | return -EINVAL; |
| 3546 | |
| 3547 | *pipe = name - 'A'; |
| 3548 | |
| 3549 | return 0; |
| 3550 | } |
| 3551 | |
| 3552 | static int |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3553 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3554 | { |
| 3555 | int i; |
| 3556 | |
| 3557 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) |
| 3558 | if (!strcmp(buf, pipe_crc_sources[i])) { |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3559 | *s = i; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3560 | return 0; |
| 3561 | } |
| 3562 | |
| 3563 | return -EINVAL; |
| 3564 | } |
| 3565 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3566 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3567 | { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3568 | #define N_WORDS 3 |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3569 | int n_words; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3570 | char *words[N_WORDS]; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3571 | enum pipe pipe; |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3572 | enum intel_pipe_crc_object object; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3573 | enum intel_pipe_crc_source source; |
| 3574 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3575 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3576 | if (n_words != N_WORDS) { |
| 3577 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", |
| 3578 | N_WORDS); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3579 | return -EINVAL; |
| 3580 | } |
| 3581 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3582 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3583 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3584 | return -EINVAL; |
| 3585 | } |
| 3586 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3587 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3588 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
| 3589 | return -EINVAL; |
| 3590 | } |
| 3591 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3592 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
Damien Lespiau | b94dec8 | 2013-10-15 18:55:35 +0100 | [diff] [blame] | 3593 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3594 | return -EINVAL; |
| 3595 | } |
| 3596 | |
| 3597 | return pipe_crc_set_source(dev, pipe, source); |
| 3598 | } |
| 3599 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3600 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
| 3601 | size_t len, loff_t *offp) |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3602 | { |
| 3603 | struct seq_file *m = file->private_data; |
| 3604 | struct drm_device *dev = m->private; |
| 3605 | char *tmpbuf; |
| 3606 | int ret; |
| 3607 | |
| 3608 | if (len == 0) |
| 3609 | return 0; |
| 3610 | |
| 3611 | if (len > PAGE_SIZE - 1) { |
| 3612 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", |
| 3613 | PAGE_SIZE); |
| 3614 | return -E2BIG; |
| 3615 | } |
| 3616 | |
| 3617 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); |
| 3618 | if (!tmpbuf) |
| 3619 | return -ENOMEM; |
| 3620 | |
| 3621 | if (copy_from_user(tmpbuf, ubuf, len)) { |
| 3622 | ret = -EFAULT; |
| 3623 | goto out; |
| 3624 | } |
| 3625 | tmpbuf[len] = '\0'; |
| 3626 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3627 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3628 | |
| 3629 | out: |
| 3630 | kfree(tmpbuf); |
| 3631 | if (ret < 0) |
| 3632 | return ret; |
| 3633 | |
| 3634 | *offp += len; |
| 3635 | return len; |
| 3636 | } |
| 3637 | |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3638 | static const struct file_operations i915_display_crc_ctl_fops = { |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3639 | .owner = THIS_MODULE, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3640 | .open = display_crc_ctl_open, |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3641 | .read = seq_read, |
| 3642 | .llseek = seq_lseek, |
| 3643 | .release = single_release, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 3644 | .write = display_crc_ctl_write |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 3645 | }; |
| 3646 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3647 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3648 | { |
| 3649 | struct drm_device *dev = m->private; |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 3650 | int num_levels = ilk_wm_max_level(dev) + 1; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3651 | int level; |
| 3652 | |
| 3653 | drm_modeset_lock_all(dev); |
| 3654 | |
| 3655 | for (level = 0; level < num_levels; level++) { |
| 3656 | unsigned int latency = wm[level]; |
| 3657 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3658 | /* |
| 3659 | * - WM1+ latency values in 0.5us units |
| 3660 | * - latencies are in us on gen9 |
| 3661 | */ |
| 3662 | if (INTEL_INFO(dev)->gen >= 9) |
| 3663 | latency *= 10; |
| 3664 | else if (level > 0) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3665 | latency *= 5; |
| 3666 | |
| 3667 | seq_printf(m, "WM%d %u (%u.%u usec)\n", |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3668 | level, wm[level], latency / 10, latency % 10); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3669 | } |
| 3670 | |
| 3671 | drm_modeset_unlock_all(dev); |
| 3672 | } |
| 3673 | |
| 3674 | static int pri_wm_latency_show(struct seq_file *m, void *data) |
| 3675 | { |
| 3676 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3677 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3678 | const uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3679 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3680 | if (INTEL_INFO(dev)->gen >= 9) |
| 3681 | latencies = dev_priv->wm.skl_latency; |
| 3682 | else |
| 3683 | latencies = to_i915(dev)->wm.pri_latency; |
| 3684 | |
| 3685 | wm_latency_show(m, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3686 | |
| 3687 | return 0; |
| 3688 | } |
| 3689 | |
| 3690 | static int spr_wm_latency_show(struct seq_file *m, void *data) |
| 3691 | { |
| 3692 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3693 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3694 | const uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3695 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3696 | if (INTEL_INFO(dev)->gen >= 9) |
| 3697 | latencies = dev_priv->wm.skl_latency; |
| 3698 | else |
| 3699 | latencies = to_i915(dev)->wm.spr_latency; |
| 3700 | |
| 3701 | wm_latency_show(m, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3702 | |
| 3703 | return 0; |
| 3704 | } |
| 3705 | |
| 3706 | static int cur_wm_latency_show(struct seq_file *m, void *data) |
| 3707 | { |
| 3708 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3709 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3710 | const uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3711 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3712 | if (INTEL_INFO(dev)->gen >= 9) |
| 3713 | latencies = dev_priv->wm.skl_latency; |
| 3714 | else |
| 3715 | latencies = to_i915(dev)->wm.cur_latency; |
| 3716 | |
| 3717 | wm_latency_show(m, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3718 | |
| 3719 | return 0; |
| 3720 | } |
| 3721 | |
| 3722 | static int pri_wm_latency_open(struct inode *inode, struct file *file) |
| 3723 | { |
| 3724 | struct drm_device *dev = inode->i_private; |
| 3725 | |
Sonika Jindal | 9ad0257 | 2014-07-21 15:23:39 +0530 | [diff] [blame] | 3726 | if (HAS_GMCH_DISPLAY(dev)) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3727 | return -ENODEV; |
| 3728 | |
| 3729 | return single_open(file, pri_wm_latency_show, dev); |
| 3730 | } |
| 3731 | |
| 3732 | static int spr_wm_latency_open(struct inode *inode, struct file *file) |
| 3733 | { |
| 3734 | struct drm_device *dev = inode->i_private; |
| 3735 | |
Sonika Jindal | 9ad0257 | 2014-07-21 15:23:39 +0530 | [diff] [blame] | 3736 | if (HAS_GMCH_DISPLAY(dev)) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3737 | return -ENODEV; |
| 3738 | |
| 3739 | return single_open(file, spr_wm_latency_show, dev); |
| 3740 | } |
| 3741 | |
| 3742 | static int cur_wm_latency_open(struct inode *inode, struct file *file) |
| 3743 | { |
| 3744 | struct drm_device *dev = inode->i_private; |
| 3745 | |
Sonika Jindal | 9ad0257 | 2014-07-21 15:23:39 +0530 | [diff] [blame] | 3746 | if (HAS_GMCH_DISPLAY(dev)) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3747 | return -ENODEV; |
| 3748 | |
| 3749 | return single_open(file, cur_wm_latency_show, dev); |
| 3750 | } |
| 3751 | |
| 3752 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3753 | size_t len, loff_t *offp, uint16_t wm[8]) |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3754 | { |
| 3755 | struct seq_file *m = file->private_data; |
| 3756 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3757 | uint16_t new[8] = { 0 }; |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 3758 | int num_levels = ilk_wm_max_level(dev) + 1; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3759 | int level; |
| 3760 | int ret; |
| 3761 | char tmp[32]; |
| 3762 | |
| 3763 | if (len >= sizeof(tmp)) |
| 3764 | return -EINVAL; |
| 3765 | |
| 3766 | if (copy_from_user(tmp, ubuf, len)) |
| 3767 | return -EFAULT; |
| 3768 | |
| 3769 | tmp[len] = '\0'; |
| 3770 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3771 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
| 3772 | &new[0], &new[1], &new[2], &new[3], |
| 3773 | &new[4], &new[5], &new[6], &new[7]); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3774 | if (ret != num_levels) |
| 3775 | return -EINVAL; |
| 3776 | |
| 3777 | drm_modeset_lock_all(dev); |
| 3778 | |
| 3779 | for (level = 0; level < num_levels; level++) |
| 3780 | wm[level] = new[level]; |
| 3781 | |
| 3782 | drm_modeset_unlock_all(dev); |
| 3783 | |
| 3784 | return len; |
| 3785 | } |
| 3786 | |
| 3787 | |
| 3788 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3789 | size_t len, loff_t *offp) |
| 3790 | { |
| 3791 | struct seq_file *m = file->private_data; |
| 3792 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3793 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3794 | uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3795 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3796 | if (INTEL_INFO(dev)->gen >= 9) |
| 3797 | latencies = dev_priv->wm.skl_latency; |
| 3798 | else |
| 3799 | latencies = to_i915(dev)->wm.pri_latency; |
| 3800 | |
| 3801 | return wm_latency_write(file, ubuf, len, offp, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3802 | } |
| 3803 | |
| 3804 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3805 | size_t len, loff_t *offp) |
| 3806 | { |
| 3807 | struct seq_file *m = file->private_data; |
| 3808 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3809 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3810 | uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3811 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3812 | if (INTEL_INFO(dev)->gen >= 9) |
| 3813 | latencies = dev_priv->wm.skl_latency; |
| 3814 | else |
| 3815 | latencies = to_i915(dev)->wm.spr_latency; |
| 3816 | |
| 3817 | return wm_latency_write(file, ubuf, len, offp, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3818 | } |
| 3819 | |
| 3820 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, |
| 3821 | size_t len, loff_t *offp) |
| 3822 | { |
| 3823 | struct seq_file *m = file->private_data; |
| 3824 | struct drm_device *dev = m->private; |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3825 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3826 | uint16_t *latencies; |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3827 | |
Damien Lespiau | 97e94b2 | 2014-11-04 17:06:50 +0000 | [diff] [blame] | 3828 | if (INTEL_INFO(dev)->gen >= 9) |
| 3829 | latencies = dev_priv->wm.skl_latency; |
| 3830 | else |
| 3831 | latencies = to_i915(dev)->wm.cur_latency; |
| 3832 | |
| 3833 | return wm_latency_write(file, ubuf, len, offp, latencies); |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 3834 | } |
| 3835 | |
| 3836 | static const struct file_operations i915_pri_wm_latency_fops = { |
| 3837 | .owner = THIS_MODULE, |
| 3838 | .open = pri_wm_latency_open, |
| 3839 | .read = seq_read, |
| 3840 | .llseek = seq_lseek, |
| 3841 | .release = single_release, |
| 3842 | .write = pri_wm_latency_write |
| 3843 | }; |
| 3844 | |
| 3845 | static const struct file_operations i915_spr_wm_latency_fops = { |
| 3846 | .owner = THIS_MODULE, |
| 3847 | .open = spr_wm_latency_open, |
| 3848 | .read = seq_read, |
| 3849 | .llseek = seq_lseek, |
| 3850 | .release = single_release, |
| 3851 | .write = spr_wm_latency_write |
| 3852 | }; |
| 3853 | |
| 3854 | static const struct file_operations i915_cur_wm_latency_fops = { |
| 3855 | .owner = THIS_MODULE, |
| 3856 | .open = cur_wm_latency_open, |
| 3857 | .read = seq_read, |
| 3858 | .llseek = seq_lseek, |
| 3859 | .release = single_release, |
| 3860 | .write = cur_wm_latency_write |
| 3861 | }; |
| 3862 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3863 | static int |
| 3864 | i915_wedged_get(void *data, u64 *val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3865 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3866 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3867 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3868 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3869 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3870 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3871 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3872 | } |
| 3873 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3874 | static int |
| 3875 | i915_wedged_set(void *data, u64 val) |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3876 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3877 | struct drm_device *dev = data; |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 3878 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3879 | |
| 3880 | intel_runtime_pm_get(dev_priv); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3881 | |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 3882 | i915_handle_error(dev, val, |
| 3883 | "Manually setting wedged to %llu", val); |
Imre Deak | d46c051 | 2014-04-14 20:24:27 +0300 | [diff] [blame] | 3884 | |
| 3885 | intel_runtime_pm_put(dev_priv); |
| 3886 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3887 | return 0; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3888 | } |
| 3889 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3890 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
| 3891 | i915_wedged_get, i915_wedged_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 3892 | "%llu\n"); |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 3893 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3894 | static int |
| 3895 | i915_ring_stop_get(void *data, u64 *val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3896 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3897 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 3898 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3899 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3900 | *val = dev_priv->gpu_error.stop_rings; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3901 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3902 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3903 | } |
| 3904 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3905 | static int |
| 3906 | i915_ring_stop_set(void *data, u64 val) |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3907 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3908 | struct drm_device *dev = data; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3909 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3910 | int ret; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3911 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3912 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3913 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 3914 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3915 | if (ret) |
| 3916 | return ret; |
| 3917 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 3918 | dev_priv->gpu_error.stop_rings = val; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3919 | mutex_unlock(&dev->struct_mutex); |
| 3920 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3921 | return 0; |
Daniel Vetter | e5eb3d6 | 2012-05-03 14:48:16 +0200 | [diff] [blame] | 3922 | } |
| 3923 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 3924 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
| 3925 | i915_ring_stop_get, i915_ring_stop_set, |
| 3926 | "0x%08llx\n"); |
Daniel Vetter | d544230 | 2012-04-27 15:17:40 +0200 | [diff] [blame] | 3927 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 3928 | static int |
| 3929 | i915_ring_missed_irq_get(void *data, u64 *val) |
| 3930 | { |
| 3931 | struct drm_device *dev = data; |
| 3932 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3933 | |
| 3934 | *val = dev_priv->gpu_error.missed_irq_rings; |
| 3935 | return 0; |
| 3936 | } |
| 3937 | |
| 3938 | static int |
| 3939 | i915_ring_missed_irq_set(void *data, u64 val) |
| 3940 | { |
| 3941 | struct drm_device *dev = data; |
| 3942 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3943 | int ret; |
| 3944 | |
| 3945 | /* Lock against concurrent debugfs callers */ |
| 3946 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3947 | if (ret) |
| 3948 | return ret; |
| 3949 | dev_priv->gpu_error.missed_irq_rings = val; |
| 3950 | mutex_unlock(&dev->struct_mutex); |
| 3951 | |
| 3952 | return 0; |
| 3953 | } |
| 3954 | |
| 3955 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, |
| 3956 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, |
| 3957 | "0x%08llx\n"); |
| 3958 | |
| 3959 | static int |
| 3960 | i915_ring_test_irq_get(void *data, u64 *val) |
| 3961 | { |
| 3962 | struct drm_device *dev = data; |
| 3963 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3964 | |
| 3965 | *val = dev_priv->gpu_error.test_irq_rings; |
| 3966 | |
| 3967 | return 0; |
| 3968 | } |
| 3969 | |
| 3970 | static int |
| 3971 | i915_ring_test_irq_set(void *data, u64 val) |
| 3972 | { |
| 3973 | struct drm_device *dev = data; |
| 3974 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3975 | int ret; |
| 3976 | |
| 3977 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
| 3978 | |
| 3979 | /* Lock against concurrent debugfs callers */ |
| 3980 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 3981 | if (ret) |
| 3982 | return ret; |
| 3983 | |
| 3984 | dev_priv->gpu_error.test_irq_rings = val; |
| 3985 | mutex_unlock(&dev->struct_mutex); |
| 3986 | |
| 3987 | return 0; |
| 3988 | } |
| 3989 | |
| 3990 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, |
| 3991 | i915_ring_test_irq_get, i915_ring_test_irq_set, |
| 3992 | "0x%08llx\n"); |
| 3993 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 3994 | #define DROP_UNBOUND 0x1 |
| 3995 | #define DROP_BOUND 0x2 |
| 3996 | #define DROP_RETIRE 0x4 |
| 3997 | #define DROP_ACTIVE 0x8 |
| 3998 | #define DROP_ALL (DROP_UNBOUND | \ |
| 3999 | DROP_BOUND | \ |
| 4000 | DROP_RETIRE | \ |
| 4001 | DROP_ACTIVE) |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4002 | static int |
| 4003 | i915_drop_caches_get(void *data, u64 *val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4004 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4005 | *val = DROP_ALL; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4006 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4007 | return 0; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4008 | } |
| 4009 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4010 | static int |
| 4011 | i915_drop_caches_set(void *data, u64 val) |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4012 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4013 | struct drm_device *dev = data; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4014 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4015 | int ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4016 | |
Ben Widawsky | 2f9fe5f | 2013-11-25 09:54:37 -0800 | [diff] [blame] | 4017 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4018 | |
| 4019 | /* No need to check and wait for gpu resets, only libdrm auto-restarts |
| 4020 | * on ioctls on -EAGAIN. */ |
| 4021 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 4022 | if (ret) |
| 4023 | return ret; |
| 4024 | |
| 4025 | if (val & DROP_ACTIVE) { |
| 4026 | ret = i915_gpu_idle(dev); |
| 4027 | if (ret) |
| 4028 | goto unlock; |
| 4029 | } |
| 4030 | |
| 4031 | if (val & (DROP_RETIRE | DROP_ACTIVE)) |
| 4032 | i915_gem_retire_requests(dev); |
| 4033 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 4034 | if (val & DROP_BOUND) |
| 4035 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); |
Chris Wilson | 4ad72b7 | 2014-09-03 19:23:37 +0100 | [diff] [blame] | 4036 | |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 4037 | if (val & DROP_UNBOUND) |
| 4038 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4039 | |
| 4040 | unlock: |
| 4041 | mutex_unlock(&dev->struct_mutex); |
| 4042 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4043 | return ret; |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4044 | } |
| 4045 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4046 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
| 4047 | i915_drop_caches_get, i915_drop_caches_set, |
| 4048 | "0x%08llx\n"); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 4049 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4050 | static int |
| 4051 | i915_max_freq_get(void *data, u64 *val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4052 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4053 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 4054 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4055 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4056 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 4057 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4058 | return -ENODEV; |
| 4059 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 4060 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 4061 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4062 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4063 | if (ret) |
| 4064 | return ret; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4065 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4066 | if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4067 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4068 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4069 | *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4070 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4071 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4072 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4073 | } |
| 4074 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4075 | static int |
| 4076 | i915_max_freq_set(void *data, u64 val) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4077 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4078 | struct drm_device *dev = data; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4079 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4080 | u32 rp_state_cap, hw_max, hw_min; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4081 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4082 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 4083 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4084 | return -ENODEV; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4085 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 4086 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 4087 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4088 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4089 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4090 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4091 | if (ret) |
| 4092 | return ret; |
| 4093 | |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4094 | /* |
| 4095 | * Turbo will still be enabled, but won't go above the set value. |
| 4096 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4097 | if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 4098 | val = vlv_freq_opcode(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4099 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 4100 | hw_max = dev_priv->rps.max_freq; |
| 4101 | hw_min = dev_priv->rps.min_freq; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4102 | } else { |
| 4103 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4104 | |
| 4105 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4106 | hw_max = dev_priv->rps.max_freq; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4107 | hw_min = (rp_state_cap >> 16) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4108 | } |
| 4109 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4110 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4111 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4112 | return -EINVAL; |
| 4113 | } |
| 4114 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4115 | dev_priv->rps.max_freq_softlimit = val; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4116 | |
| 4117 | if (IS_VALLEYVIEW(dev)) |
| 4118 | valleyview_set_rps(dev, val); |
| 4119 | else |
| 4120 | gen6_set_rps(dev, val); |
| 4121 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4122 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4123 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4124 | return 0; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4125 | } |
| 4126 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4127 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
| 4128 | i915_max_freq_get, i915_max_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 4129 | "%llu\n"); |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4130 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4131 | static int |
| 4132 | i915_min_freq_get(void *data, u64 *val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4133 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4134 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 4135 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4136 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4137 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 4138 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4139 | return -ENODEV; |
| 4140 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 4141 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 4142 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4143 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4144 | if (ret) |
| 4145 | return ret; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4146 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4147 | if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4148 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4149 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4150 | *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4151 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4152 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4153 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4154 | } |
| 4155 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4156 | static int |
| 4157 | i915_min_freq_set(void *data, u64 val) |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4158 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4159 | struct drm_device *dev = data; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4160 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4161 | u32 rp_state_cap, hw_max, hw_min; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4162 | int ret; |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4163 | |
Tom O'Rourke | daa3afb | 2014-05-30 16:22:10 -0700 | [diff] [blame] | 4164 | if (INTEL_INFO(dev)->gen < 6) |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4165 | return -ENODEV; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4166 | |
Tom O'Rourke | 5c9669c | 2013-09-16 14:56:43 -0700 | [diff] [blame] | 4167 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 4168 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4169 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4170 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4171 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4172 | if (ret) |
| 4173 | return ret; |
| 4174 | |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4175 | /* |
| 4176 | * Turbo will still be enabled, but won't go below the set value. |
| 4177 | */ |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4178 | if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 4179 | val = vlv_freq_opcode(dev_priv, val); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4180 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 4181 | hw_max = dev_priv->rps.max_freq; |
| 4182 | hw_min = dev_priv->rps.min_freq; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4183 | } else { |
| 4184 | do_div(val, GT_FREQUENCY_MULTIPLIER); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4185 | |
| 4186 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4187 | hw_max = dev_priv->rps.max_freq; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4188 | hw_min = (rp_state_cap >> 16) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4189 | } |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4190 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4191 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4192 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4193 | return -EINVAL; |
| 4194 | } |
| 4195 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4196 | dev_priv->rps.min_freq_softlimit = val; |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 4197 | |
| 4198 | if (IS_VALLEYVIEW(dev)) |
| 4199 | valleyview_set_rps(dev, val); |
| 4200 | else |
| 4201 | gen6_set_rps(dev, val); |
| 4202 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4203 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4204 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4205 | return 0; |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4206 | } |
| 4207 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4208 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
| 4209 | i915_min_freq_get, i915_min_freq_set, |
Mika Kuoppala | 3a3b4f9 | 2013-04-12 12:10:05 +0300 | [diff] [blame] | 4210 | "%llu\n"); |
Jesse Barnes | 1523c31 | 2012-05-25 12:34:54 -0700 | [diff] [blame] | 4211 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4212 | static int |
| 4213 | i915_cache_sharing_get(void *data, u64 *val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4214 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4215 | struct drm_device *dev = data; |
Jani Nikula | e277a1f | 2014-03-31 14:27:14 +0300 | [diff] [blame] | 4216 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4217 | u32 snpcr; |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4218 | int ret; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4219 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4220 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 4221 | return -ENODEV; |
| 4222 | |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 4223 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 4224 | if (ret) |
| 4225 | return ret; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4226 | intel_runtime_pm_get(dev_priv); |
Daniel Vetter | 22bcfc6 | 2012-08-09 15:07:02 +0200 | [diff] [blame] | 4227 | |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4228 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4229 | |
| 4230 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4231 | mutex_unlock(&dev_priv->dev->struct_mutex); |
| 4232 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4233 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4234 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4235 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4236 | } |
| 4237 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4238 | static int |
| 4239 | i915_cache_sharing_set(void *data, u64 val) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4240 | { |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4241 | struct drm_device *dev = data; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4242 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4243 | u32 snpcr; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4244 | |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 4245 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
| 4246 | return -ENODEV; |
| 4247 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4248 | if (val > 3) |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4249 | return -EINVAL; |
| 4250 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4251 | intel_runtime_pm_get(dev_priv); |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4252 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4253 | |
| 4254 | /* Update the cache sharing policy here as well */ |
| 4255 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 4256 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 4257 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); |
| 4258 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
| 4259 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4260 | intel_runtime_pm_put(dev_priv); |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4261 | return 0; |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4262 | } |
| 4263 | |
Kees Cook | 647416f | 2013-03-10 14:10:06 -0700 | [diff] [blame] | 4264 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
| 4265 | i915_cache_sharing_get, i915_cache_sharing_set, |
| 4266 | "%llu\n"); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4267 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4268 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
| 4269 | { |
| 4270 | struct drm_device *dev = inode->i_private; |
| 4271 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4272 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 4273 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4274 | return 0; |
| 4275 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 4276 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4277 | |
| 4278 | return 0; |
| 4279 | } |
| 4280 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 4281 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4282 | { |
| 4283 | struct drm_device *dev = inode->i_private; |
| 4284 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4285 | |
Daniel Vetter | 075edca | 2012-01-24 09:44:28 +0100 | [diff] [blame] | 4286 | if (INTEL_INFO(dev)->gen < 6) |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4287 | return 0; |
| 4288 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 4289 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4290 | |
| 4291 | return 0; |
| 4292 | } |
| 4293 | |
| 4294 | static const struct file_operations i915_forcewake_fops = { |
| 4295 | .owner = THIS_MODULE, |
| 4296 | .open = i915_forcewake_open, |
| 4297 | .release = i915_forcewake_release, |
| 4298 | }; |
| 4299 | |
| 4300 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) |
| 4301 | { |
| 4302 | struct drm_device *dev = minor->dev; |
| 4303 | struct dentry *ent; |
| 4304 | |
| 4305 | ent = debugfs_create_file("i915_forcewake_user", |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 4306 | S_IRUSR, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4307 | root, dev, |
| 4308 | &i915_forcewake_fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 4309 | if (!ent) |
| 4310 | return -ENOMEM; |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4311 | |
Ben Widawsky | 8eb5729 | 2011-05-11 15:10:58 -0700 | [diff] [blame] | 4312 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4313 | } |
| 4314 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4315 | static int i915_debugfs_create(struct dentry *root, |
| 4316 | struct drm_minor *minor, |
| 4317 | const char *name, |
| 4318 | const struct file_operations *fops) |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4319 | { |
| 4320 | struct drm_device *dev = minor->dev; |
| 4321 | struct dentry *ent; |
| 4322 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4323 | ent = debugfs_create_file(name, |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4324 | S_IRUGO | S_IWUSR, |
| 4325 | root, dev, |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4326 | fops); |
Wei Yongjun | f3c5fe9 | 2013-12-16 14:13:25 +0800 | [diff] [blame] | 4327 | if (!ent) |
| 4328 | return -ENOMEM; |
Jesse Barnes | 358733e | 2011-07-27 11:53:01 -0700 | [diff] [blame] | 4329 | |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4330 | return drm_add_fake_info_node(minor, ent, fops); |
Jesse Barnes | 07b7ddd | 2011-08-03 11:28:44 -0700 | [diff] [blame] | 4331 | } |
| 4332 | |
Lespiau, Damien | 06c5bf8 | 2013-10-17 19:09:56 +0100 | [diff] [blame] | 4333 | static const struct drm_info_list i915_debugfs_list[] = { |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 4334 | {"i915_capabilities", i915_capabilities, 0}, |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4335 | {"i915_gem_objects", i915_gem_object_info, 0}, |
Chris Wilson | 08c1832 | 2011-01-10 00:00:24 +0000 | [diff] [blame] | 4336 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 4337 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 4338 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
Ben Gamari | 433e12f | 2009-02-17 20:08:51 -0500 | [diff] [blame] | 4339 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
Chris Wilson | 6d2b888 | 2013-08-07 18:30:54 +0100 | [diff] [blame] | 4340 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 4341 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4342 | {"i915_gem_request", i915_gem_request_info, 0}, |
| 4343 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, |
Chris Wilson | a6172a8 | 2009-02-11 14:26:38 +0000 | [diff] [blame] | 4344 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4345 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4346 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
| 4347 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, |
| 4348 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, |
Xiang, Haihao | 9010ebf | 2013-05-29 09:22:36 -0700 | [diff] [blame] | 4349 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
Deepak S | adb4bd1 | 2014-03-31 11:30:02 +0530 | [diff] [blame] | 4350 | {"i915_frequency_info", i915_frequency_info, 0}, |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 4351 | {"i915_drpc_info", i915_drpc_info, 0}, |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 4352 | {"i915_emon_status", i915_emon_status, 0}, |
Jesse Barnes | 23b2f8b | 2011-06-28 13:04:16 -0700 | [diff] [blame] | 4353 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 4354 | {"i915_fbc_status", i915_fbc_status, 0}, |
Paulo Zanoni | 92d4462 | 2013-05-31 16:33:24 -0300 | [diff] [blame] | 4355 | {"i915_ips_status", i915_ips_status, 0}, |
Jesse Barnes | 4a9bef3 | 2010-02-05 12:47:35 -0800 | [diff] [blame] | 4356 | {"i915_sr_status", i915_sr_status, 0}, |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 4357 | {"i915_opregion", i915_opregion, 0}, |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 4358 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
Ben Widawsky | e76d363 | 2011-03-19 18:14:29 -0700 | [diff] [blame] | 4359 | {"i915_context_status", i915_context_status, 0}, |
Ben Widawsky | c0ab1ae | 2014-08-07 13:24:26 +0100 | [diff] [blame] | 4360 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
Oscar Mateo | 4ba70e4 | 2014-08-07 13:23:20 +0100 | [diff] [blame] | 4361 | {"i915_execlists", i915_execlists, 0}, |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4362 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
Daniel Vetter | ea16a3c | 2011-12-14 13:57:16 +0100 | [diff] [blame] | 4363 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
Daniel Vetter | 3cf17fc | 2012-02-09 17:15:49 +0100 | [diff] [blame] | 4364 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
Ben Widawsky | 63573eb | 2013-07-04 11:02:07 -0700 | [diff] [blame] | 4365 | {"i915_llc", i915_llc, 0}, |
Rodrigo Vivi | e91fd8c | 2013-07-11 18:44:59 -0300 | [diff] [blame] | 4366 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 4367 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
Jesse Barnes | ec013e7 | 2013-08-20 10:29:23 +0100 | [diff] [blame] | 4368 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
Paulo Zanoni | 371db66 | 2013-08-19 13:18:10 -0300 | [diff] [blame] | 4369 | {"i915_pc8_status", i915_pc8_status, 0}, |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 4370 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 4371 | {"i915_display_info", i915_display_info, 0}, |
Ben Widawsky | e04934c | 2014-06-30 09:53:42 -0700 | [diff] [blame] | 4372 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
Daniel Vetter | 728e29d | 2014-06-25 22:01:53 +0300 | [diff] [blame] | 4373 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
Dave Airlie | 11bed958 | 2014-05-12 15:22:27 +1000 | [diff] [blame] | 4374 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
Damien Lespiau | 1ed1ef9 | 2014-08-30 16:50:59 +0100 | [diff] [blame] | 4375 | {"i915_wa_registers", i915_wa_registers, 0}, |
Damien Lespiau | c5511e4 | 2014-11-04 17:06:51 +0000 | [diff] [blame] | 4376 | {"i915_ddb_info", i915_ddb_info, 0}, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4377 | }; |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4378 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4379 | |
Lespiau, Damien | 06c5bf8 | 2013-10-17 19:09:56 +0100 | [diff] [blame] | 4380 | static const struct i915_debugfs_files { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4381 | const char *name; |
| 4382 | const struct file_operations *fops; |
| 4383 | } i915_debugfs_files[] = { |
| 4384 | {"i915_wedged", &i915_wedged_fops}, |
| 4385 | {"i915_max_freq", &i915_max_freq_fops}, |
| 4386 | {"i915_min_freq", &i915_min_freq_fops}, |
| 4387 | {"i915_cache_sharing", &i915_cache_sharing_fops}, |
| 4388 | {"i915_ring_stop", &i915_ring_stop_fops}, |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 4389 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
| 4390 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4391 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
| 4392 | {"i915_error_state", &i915_error_state_fops}, |
| 4393 | {"i915_next_seqno", &i915_next_seqno_fops}, |
Damien Lespiau | bd9db02 | 2013-10-15 18:55:36 +0100 | [diff] [blame] | 4394 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
Ville Syrjälä | 369a134 | 2014-01-22 14:36:08 +0200 | [diff] [blame] | 4395 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
| 4396 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, |
| 4397 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 4398 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4399 | }; |
| 4400 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4401 | void intel_display_crc_init(struct drm_device *dev) |
| 4402 | { |
| 4403 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b378360 | 2013-11-14 11:30:42 +0100 | [diff] [blame] | 4404 | enum pipe pipe; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4405 | |
Damien Lespiau | 055e393 | 2014-08-18 13:49:10 +0100 | [diff] [blame] | 4406 | for_each_pipe(dev_priv, pipe) { |
Daniel Vetter | b378360 | 2013-11-14 11:30:42 +0100 | [diff] [blame] | 4407 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4408 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 4409 | pipe_crc->opened = false; |
| 4410 | spin_lock_init(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4411 | init_waitqueue_head(&pipe_crc->wq); |
| 4412 | } |
| 4413 | } |
| 4414 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4415 | int i915_debugfs_init(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4416 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4417 | int ret, i; |
Chris Wilson | f3cd474 | 2009-10-13 22:20:20 +0100 | [diff] [blame] | 4418 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4419 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
| 4420 | if (ret) |
| 4421 | return ret; |
Daniel Vetter | 6a9c308 | 2011-12-14 13:57:11 +0100 | [diff] [blame] | 4422 | |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4423 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
| 4424 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); |
| 4425 | if (ret) |
| 4426 | return ret; |
| 4427 | } |
| 4428 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4429 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 4430 | ret = i915_debugfs_create(minor->debugfs_root, minor, |
| 4431 | i915_debugfs_files[i].name, |
| 4432 | i915_debugfs_files[i].fops); |
| 4433 | if (ret) |
| 4434 | return ret; |
| 4435 | } |
Mika Kuoppala | 4063321 | 2012-12-04 15:12:00 +0200 | [diff] [blame] | 4436 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4437 | return drm_debugfs_create_files(i915_debugfs_list, |
| 4438 | I915_DEBUGFS_ENTRIES, |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4439 | minor->debugfs_root, minor); |
| 4440 | } |
| 4441 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4442 | void i915_debugfs_cleanup(struct drm_minor *minor) |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4443 | { |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4444 | int i; |
| 4445 | |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 4446 | drm_debugfs_remove_files(i915_debugfs_list, |
| 4447 | I915_DEBUGFS_ENTRIES, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4448 | |
Ben Widawsky | 6d794d4 | 2011-04-25 11:25:56 -0700 | [diff] [blame] | 4449 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
| 4450 | 1, minor); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4451 | |
Daniel Vetter | e309a99 | 2013-10-16 22:55:51 +0200 | [diff] [blame] | 4452 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 4453 | struct drm_info_list *info_list = |
| 4454 | (struct drm_info_list *)&i915_pipe_crc_data[i]; |
| 4455 | |
| 4456 | drm_debugfs_remove_files(info_list, 1, minor); |
| 4457 | } |
| 4458 | |
Daniel Vetter | 34b9674 | 2013-07-04 20:49:44 +0200 | [diff] [blame] | 4459 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
| 4460 | struct drm_info_list *info_list = |
| 4461 | (struct drm_info_list *) i915_debugfs_files[i].fops; |
| 4462 | |
| 4463 | drm_debugfs_remove_files(info_list, 1, minor); |
| 4464 | } |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 4465 | } |