Alexander Shiyan | 6a8a0c1 | 2014-03-11 21:55:14 +0400 | [diff] [blame] | 1 | /* |
| 2 | * SYSCON GPIO driver |
| 3 | * |
| 4 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/err.h> |
| 13 | #include <linux/gpio.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/of.h> |
| 16 | #include <linux/of_device.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/regmap.h> |
| 19 | #include <linux/mfd/syscon.h> |
| 20 | |
| 21 | #define GPIO_SYSCON_FEAT_IN BIT(0) |
| 22 | #define GPIO_SYSCON_FEAT_OUT BIT(1) |
| 23 | #define GPIO_SYSCON_FEAT_DIR BIT(2) |
| 24 | |
| 25 | /* SYSCON driver is designed to use 32-bit wide registers */ |
| 26 | #define SYSCON_REG_SIZE (4) |
| 27 | #define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8) |
| 28 | |
| 29 | /** |
| 30 | * struct syscon_gpio_data - Configuration for the device. |
| 31 | * compatible: SYSCON driver compatible string. |
| 32 | * flags: Set of GPIO_SYSCON_FEAT_ flags: |
| 33 | * GPIO_SYSCON_FEAT_IN: GPIOs supports input, |
| 34 | * GPIO_SYSCON_FEAT_OUT: GPIOs supports output, |
| 35 | * GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction. |
| 36 | * bit_count: Number of bits used as GPIOs. |
| 37 | * dat_bit_offset: Offset (in bits) to the first GPIO bit. |
| 38 | * dir_bit_offset: Optional offset (in bits) to the first bit to switch |
| 39 | * GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag). |
Grygorii Strashko | 2c341d6 | 2014-09-03 20:05:32 +0300 | [diff] [blame^] | 40 | * set: HW specific callback to assigns output value |
| 41 | * for signal "offset" |
Alexander Shiyan | 6a8a0c1 | 2014-03-11 21:55:14 +0400 | [diff] [blame] | 42 | */ |
| 43 | |
| 44 | struct syscon_gpio_data { |
| 45 | const char *compatible; |
| 46 | unsigned int flags; |
| 47 | unsigned int bit_count; |
| 48 | unsigned int dat_bit_offset; |
| 49 | unsigned int dir_bit_offset; |
Grygorii Strashko | 2c341d6 | 2014-09-03 20:05:32 +0300 | [diff] [blame^] | 50 | void (*set)(struct gpio_chip *chip, |
| 51 | unsigned offset, int value); |
Alexander Shiyan | 6a8a0c1 | 2014-03-11 21:55:14 +0400 | [diff] [blame] | 52 | }; |
| 53 | |
| 54 | struct syscon_gpio_priv { |
| 55 | struct gpio_chip chip; |
| 56 | struct regmap *syscon; |
| 57 | const struct syscon_gpio_data *data; |
| 58 | }; |
| 59 | |
| 60 | static inline struct syscon_gpio_priv *to_syscon_gpio(struct gpio_chip *chip) |
| 61 | { |
| 62 | return container_of(chip, struct syscon_gpio_priv, chip); |
| 63 | } |
| 64 | |
| 65 | static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 66 | { |
| 67 | struct syscon_gpio_priv *priv = to_syscon_gpio(chip); |
| 68 | unsigned int val, offs = priv->data->dat_bit_offset + offset; |
| 69 | int ret; |
| 70 | |
| 71 | ret = regmap_read(priv->syscon, |
| 72 | (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val); |
| 73 | if (ret) |
| 74 | return ret; |
| 75 | |
| 76 | return !!(val & BIT(offs % SYSCON_REG_BITS)); |
| 77 | } |
| 78 | |
| 79 | static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val) |
| 80 | { |
| 81 | struct syscon_gpio_priv *priv = to_syscon_gpio(chip); |
| 82 | unsigned int offs = priv->data->dat_bit_offset + offset; |
| 83 | |
| 84 | regmap_update_bits(priv->syscon, |
| 85 | (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, |
| 86 | BIT(offs % SYSCON_REG_BITS), |
| 87 | val ? BIT(offs % SYSCON_REG_BITS) : 0); |
| 88 | } |
| 89 | |
| 90 | static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset) |
| 91 | { |
| 92 | struct syscon_gpio_priv *priv = to_syscon_gpio(chip); |
| 93 | |
| 94 | if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { |
| 95 | unsigned int offs = priv->data->dir_bit_offset + offset; |
| 96 | |
| 97 | regmap_update_bits(priv->syscon, |
| 98 | (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, |
| 99 | BIT(offs % SYSCON_REG_BITS), 0); |
| 100 | } |
| 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val) |
| 106 | { |
| 107 | struct syscon_gpio_priv *priv = to_syscon_gpio(chip); |
| 108 | |
| 109 | if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { |
| 110 | unsigned int offs = priv->data->dir_bit_offset + offset; |
| 111 | |
| 112 | regmap_update_bits(priv->syscon, |
| 113 | (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, |
| 114 | BIT(offs % SYSCON_REG_BITS), |
| 115 | BIT(offs % SYSCON_REG_BITS)); |
| 116 | } |
| 117 | |
Grygorii Strashko | 2c341d6 | 2014-09-03 20:05:32 +0300 | [diff] [blame^] | 118 | priv->data->set(chip, offset, val); |
Alexander Shiyan | 6a8a0c1 | 2014-03-11 21:55:14 +0400 | [diff] [blame] | 119 | |
| 120 | return 0; |
| 121 | } |
| 122 | |
| 123 | static const struct syscon_gpio_data clps711x_mctrl_gpio = { |
| 124 | /* ARM CLPS711X SYSFLG1 Bits 8-10 */ |
| 125 | .compatible = "cirrus,clps711x-syscon1", |
| 126 | .flags = GPIO_SYSCON_FEAT_IN, |
| 127 | .bit_count = 3, |
| 128 | .dat_bit_offset = 0x40 * 8 + 8, |
| 129 | }; |
| 130 | |
| 131 | static const struct of_device_id syscon_gpio_ids[] = { |
| 132 | { |
| 133 | .compatible = "cirrus,clps711x-mctrl-gpio", |
| 134 | .data = &clps711x_mctrl_gpio, |
| 135 | }, |
| 136 | { } |
| 137 | }; |
| 138 | MODULE_DEVICE_TABLE(of, syscon_gpio_ids); |
| 139 | |
| 140 | static int syscon_gpio_probe(struct platform_device *pdev) |
| 141 | { |
| 142 | struct device *dev = &pdev->dev; |
| 143 | const struct of_device_id *of_id = of_match_device(syscon_gpio_ids, dev); |
| 144 | struct syscon_gpio_priv *priv; |
| 145 | |
| 146 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
| 147 | if (!priv) |
| 148 | return -ENOMEM; |
| 149 | |
| 150 | priv->data = of_id->data; |
| 151 | |
| 152 | priv->syscon = |
| 153 | syscon_regmap_lookup_by_compatible(priv->data->compatible); |
| 154 | if (IS_ERR(priv->syscon)) |
| 155 | return PTR_ERR(priv->syscon); |
| 156 | |
| 157 | priv->chip.dev = dev; |
| 158 | priv->chip.owner = THIS_MODULE; |
| 159 | priv->chip.label = dev_name(dev); |
| 160 | priv->chip.base = -1; |
| 161 | priv->chip.ngpio = priv->data->bit_count; |
| 162 | priv->chip.get = syscon_gpio_get; |
| 163 | if (priv->data->flags & GPIO_SYSCON_FEAT_IN) |
| 164 | priv->chip.direction_input = syscon_gpio_dir_in; |
| 165 | if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) { |
Grygorii Strashko | 2c341d6 | 2014-09-03 20:05:32 +0300 | [diff] [blame^] | 166 | priv->chip.set = priv->data->set ? : syscon_gpio_set; |
Alexander Shiyan | 6a8a0c1 | 2014-03-11 21:55:14 +0400 | [diff] [blame] | 167 | priv->chip.direction_output = syscon_gpio_dir_out; |
| 168 | } |
| 169 | |
| 170 | platform_set_drvdata(pdev, priv); |
| 171 | |
| 172 | return gpiochip_add(&priv->chip); |
| 173 | } |
| 174 | |
| 175 | static int syscon_gpio_remove(struct platform_device *pdev) |
| 176 | { |
| 177 | struct syscon_gpio_priv *priv = platform_get_drvdata(pdev); |
| 178 | |
abdoulaye berthe | 9f5132a | 2014-07-12 22:30:12 +0200 | [diff] [blame] | 179 | gpiochip_remove(&priv->chip); |
| 180 | return 0; |
Alexander Shiyan | 6a8a0c1 | 2014-03-11 21:55:14 +0400 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | static struct platform_driver syscon_gpio_driver = { |
| 184 | .driver = { |
| 185 | .name = "gpio-syscon", |
| 186 | .owner = THIS_MODULE, |
| 187 | .of_match_table = syscon_gpio_ids, |
| 188 | }, |
| 189 | .probe = syscon_gpio_probe, |
| 190 | .remove = syscon_gpio_remove, |
| 191 | }; |
| 192 | module_platform_driver(syscon_gpio_driver); |
| 193 | |
| 194 | MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); |
| 195 | MODULE_DESCRIPTION("SYSCON GPIO driver"); |
| 196 | MODULE_LICENSE("GPL"); |