R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 11 | #include <dt-bindings/pinctrl/dra.h> |
| 12 | |
| 13 | #include "skeleton.dtsi" |
| 14 | |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 15 | #define MAX_SOURCES 400 |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 16 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 17 | / { |
| 18 | #address-cells = <1>; |
| 19 | #size-cells = <1>; |
| 20 | |
| 21 | compatible = "ti,dra7xx"; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 22 | interrupt-parent = <&crossbar_mpu>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 23 | |
| 24 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 25 | i2c0 = &i2c1; |
| 26 | i2c1 = &i2c2; |
| 27 | i2c2 = &i2c3; |
| 28 | i2c3 = &i2c4; |
| 29 | i2c4 = &i2c5; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 30 | serial0 = &uart1; |
| 31 | serial1 = &uart2; |
| 32 | serial2 = &uart3; |
| 33 | serial3 = &uart4; |
| 34 | serial4 = &uart5; |
| 35 | serial5 = &uart6; |
Nishanth Menon | 065bd7f | 2014-10-21 11:18:15 -0500 | [diff] [blame] | 36 | serial6 = &uart7; |
| 37 | serial7 = &uart8; |
| 38 | serial8 = &uart9; |
| 39 | serial9 = &uart10; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 40 | ethernet0 = &cpsw_emac0; |
| 41 | ethernet1 = &cpsw_emac1; |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 42 | d_can0 = &dcan1; |
| 43 | d_can1 = &dcan2; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 44 | }; |
| 45 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 46 | timer { |
| 47 | compatible = "arm,armv7-timer"; |
| 48 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 49 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 50 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 51 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 52 | interrupt-parent = <&gic>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 53 | }; |
| 54 | |
| 55 | gic: interrupt-controller@48211000 { |
| 56 | compatible = "arm,cortex-a15-gic"; |
| 57 | interrupt-controller; |
| 58 | #interrupt-cells = <3>; |
| 59 | reg = <0x48211000 0x1000>, |
| 60 | <0x48212000 0x1000>, |
| 61 | <0x48214000 0x2000>, |
| 62 | <0x48216000 0x2000>; |
| 63 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 64 | interrupt-parent = <&gic>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 65 | }; |
| 66 | |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 67 | wakeupgen: interrupt-controller@48281000 { |
| 68 | compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; |
| 69 | interrupt-controller; |
| 70 | #interrupt-cells = <3>; |
| 71 | reg = <0x48281000 0x1000>; |
| 72 | interrupt-parent = <&gic>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | /* |
Geert Uytterhoeven | 5c5be9d | 2014-03-28 11:11:37 +0100 | [diff] [blame] | 76 | * The soc node represents the soc top level view. It is used for IPs |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 77 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 78 | */ |
| 79 | soc { |
| 80 | compatible = "ti,omap-infra"; |
| 81 | mpu { |
| 82 | compatible = "ti,omap5-mpu"; |
| 83 | ti,hwmods = "mpu"; |
| 84 | }; |
| 85 | }; |
| 86 | |
| 87 | /* |
| 88 | * XXX: Use a flat representation of the SOC interconnect. |
| 89 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 90 | * Since it will not bring real advantage to represent that in DT for |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 91 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 92 | * hierarchy. |
| 93 | */ |
| 94 | ocp { |
Rajendra Nayak | fba387a | 2014-04-10 11:34:32 -0500 | [diff] [blame] | 95 | compatible = "ti,dra7-l3-noc", "simple-bus"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 96 | #address-cells = <1>; |
| 97 | #size-cells = <1>; |
| 98 | ranges; |
| 99 | ti,hwmods = "l3_main_1", "l3_main_2"; |
Rajendra Nayak | fba387a | 2014-04-10 11:34:32 -0500 | [diff] [blame] | 100 | reg = <0x44000000 0x1000000>, |
| 101 | <0x45000000 0x1000>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 102 | interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 103 | <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 104 | |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 105 | l4_cfg: l4@4a000000 { |
| 106 | compatible = "ti,dra7-l4-cfg", "simple-bus"; |
| 107 | #address-cells = <1>; |
| 108 | #size-cells = <1>; |
| 109 | ranges = <0 0x4a000000 0x22c000>; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 110 | |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 111 | scm: scm@2000 { |
| 112 | compatible = "ti,dra7-scm-core", "simple-bus"; |
| 113 | reg = <0x2000 0x2000>; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 114 | #address-cells = <1>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 115 | #size-cells = <1>; |
| 116 | ranges = <0 0x2000 0x2000>; |
| 117 | |
| 118 | scm_conf: scm_conf@0 { |
Kishon Vijay Abraham I | cd45567 | 2015-07-27 17:46:41 +0530 | [diff] [blame] | 119 | compatible = "syscon", "simple-bus"; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 120 | reg = <0x0 0x1400>; |
| 121 | #address-cells = <1>; |
| 122 | #size-cells = <1>; |
Kishon Vijay Abraham I | 9a5e3f2 | 2015-09-04 17:38:24 +0530 | [diff] [blame] | 123 | ranges = <0 0x0 0x1400>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 124 | |
| 125 | pbias_regulator: pbias_regulator { |
Kishon Vijay Abraham I | 737f146 | 2015-09-04 17:30:25 +0530 | [diff] [blame] | 126 | compatible = "ti,pbias-dra7", "ti,pbias-omap"; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 127 | reg = <0xe00 0x4>; |
| 128 | syscon = <&scm_conf>; |
| 129 | pbias_mmc_reg: pbias_mmc_omap5 { |
| 130 | regulator-name = "pbias_mmc_omap5"; |
| 131 | regulator-min-microvolt = <1800000>; |
| 132 | regulator-max-microvolt = <3000000>; |
| 133 | }; |
| 134 | }; |
Tomi Valkeinen | 2d5a3c8 | 2015-02-23 12:53:56 +0200 | [diff] [blame] | 135 | |
| 136 | scm_conf_clocks: clocks { |
| 137 | #address-cells = <1>; |
| 138 | #size-cells = <0>; |
| 139 | }; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 140 | }; |
| 141 | |
| 142 | dra7_pmx_core: pinmux@1400 { |
| 143 | compatible = "ti,dra7-padconf", |
| 144 | "pinctrl-single"; |
Roger Quadros | 1c5cb6f | 2015-07-27 13:27:29 +0300 | [diff] [blame] | 145 | reg = <0x1400 0x0468>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 146 | #address-cells = <1>; |
| 147 | #size-cells = <0>; |
| 148 | #interrupt-cells = <1>; |
| 149 | interrupt-controller; |
| 150 | pinctrl-single,register-width = <32>; |
| 151 | pinctrl-single,function-mask = <0x3fffffff>; |
| 152 | }; |
Roger Quadros | 33cb3a1 | 2015-08-04 12:10:14 +0300 | [diff] [blame] | 153 | |
| 154 | scm_conf1: scm_conf@1c04 { |
| 155 | compatible = "syscon"; |
| 156 | reg = <0x1c04 0x0020>; |
| 157 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 158 | }; |
| 159 | |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 160 | cm_core_aon: cm_core_aon@5000 { |
| 161 | compatible = "ti,dra7-cm-core-aon"; |
| 162 | reg = <0x5000 0x2000>; |
| 163 | |
| 164 | cm_core_aon_clocks: clocks { |
| 165 | #address-cells = <1>; |
| 166 | #size-cells = <0>; |
| 167 | }; |
| 168 | |
| 169 | cm_core_aon_clockdomains: clockdomains { |
| 170 | }; |
| 171 | }; |
| 172 | |
| 173 | cm_core: cm_core@8000 { |
| 174 | compatible = "ti,dra7-cm-core"; |
| 175 | reg = <0x8000 0x3000>; |
| 176 | |
| 177 | cm_core_clocks: clocks { |
| 178 | #address-cells = <1>; |
| 179 | #size-cells = <0>; |
| 180 | }; |
| 181 | |
| 182 | cm_core_clockdomains: clockdomains { |
| 183 | }; |
| 184 | }; |
| 185 | }; |
| 186 | |
| 187 | l4_wkup: l4@4ae00000 { |
| 188 | compatible = "ti,dra7-l4-wkup", "simple-bus"; |
| 189 | #address-cells = <1>; |
| 190 | #size-cells = <1>; |
| 191 | ranges = <0 0x4ae00000 0x3f000>; |
| 192 | |
| 193 | counter32k: counter@4000 { |
| 194 | compatible = "ti,omap-counter32k"; |
| 195 | reg = <0x4000 0x40>; |
| 196 | ti,hwmods = "counter_32k"; |
| 197 | }; |
| 198 | |
| 199 | prm: prm@6000 { |
| 200 | compatible = "ti,dra7-prm"; |
| 201 | reg = <0x6000 0x3000>; |
| 202 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| 203 | |
| 204 | prm_clocks: clocks { |
| 205 | #address-cells = <1>; |
| 206 | #size-cells = <0>; |
| 207 | }; |
| 208 | |
| 209 | prm_clockdomains: clockdomains { |
| 210 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 211 | }; |
| 212 | }; |
| 213 | |
Kishon Vijay Abraham I | 18dcd79 | 2014-07-14 16:12:23 +0530 | [diff] [blame] | 214 | axi@0 { |
| 215 | compatible = "simple-bus"; |
| 216 | #size-cells = <1>; |
| 217 | #address-cells = <1>; |
| 218 | ranges = <0x51000000 0x51000000 0x3000 |
| 219 | 0x0 0x20000000 0x10000000>; |
Kishon Vijay Abraham I | 73c8f0c | 2015-07-28 19:09:10 +0530 | [diff] [blame] | 220 | pcie1: pcie@51000000 { |
Kishon Vijay Abraham I | 18dcd79 | 2014-07-14 16:12:23 +0530 | [diff] [blame] | 221 | compatible = "ti,dra7-pcie"; |
| 222 | reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; |
| 223 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 224 | interrupts = <0 232 0x4>, <0 233 0x4>; |
| 225 | #address-cells = <3>; |
| 226 | #size-cells = <2>; |
| 227 | device_type = "pci"; |
| 228 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 229 | 0x82000000 0 0x20013000 0x13000 0 0xffed000>; |
| 230 | #interrupt-cells = <1>; |
| 231 | num-lanes = <1>; |
| 232 | ti,hwmods = "pcie1"; |
| 233 | phys = <&pcie1_phy>; |
| 234 | phy-names = "pcie-phy0"; |
| 235 | interrupt-map-mask = <0 0 0 7>; |
| 236 | interrupt-map = <0 0 0 1 &pcie1_intc 1>, |
| 237 | <0 0 0 2 &pcie1_intc 2>, |
| 238 | <0 0 0 3 &pcie1_intc 3>, |
| 239 | <0 0 0 4 &pcie1_intc 4>; |
| 240 | pcie1_intc: interrupt-controller { |
| 241 | interrupt-controller; |
| 242 | #address-cells = <0>; |
| 243 | #interrupt-cells = <1>; |
| 244 | }; |
| 245 | }; |
| 246 | }; |
| 247 | |
| 248 | axi@1 { |
| 249 | compatible = "simple-bus"; |
| 250 | #size-cells = <1>; |
| 251 | #address-cells = <1>; |
| 252 | ranges = <0x51800000 0x51800000 0x3000 |
| 253 | 0x0 0x30000000 0x10000000>; |
| 254 | status = "disabled"; |
| 255 | pcie@51000000 { |
| 256 | compatible = "ti,dra7-pcie"; |
| 257 | reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; |
| 258 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 259 | interrupts = <0 355 0x4>, <0 356 0x4>; |
| 260 | #address-cells = <3>; |
| 261 | #size-cells = <2>; |
| 262 | device_type = "pci"; |
| 263 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 264 | 0x82000000 0 0x30013000 0x13000 0 0xffed000>; |
| 265 | #interrupt-cells = <1>; |
| 266 | num-lanes = <1>; |
| 267 | ti,hwmods = "pcie2"; |
| 268 | phys = <&pcie2_phy>; |
| 269 | phy-names = "pcie-phy0"; |
| 270 | interrupt-map-mask = <0 0 0 7>; |
| 271 | interrupt-map = <0 0 0 1 &pcie2_intc 1>, |
| 272 | <0 0 0 2 &pcie2_intc 2>, |
| 273 | <0 0 0 3 &pcie2_intc 3>, |
| 274 | <0 0 0 4 &pcie2_intc 4>; |
| 275 | pcie2_intc: interrupt-controller { |
| 276 | interrupt-controller; |
| 277 | #address-cells = <0>; |
| 278 | #interrupt-cells = <1>; |
| 279 | }; |
| 280 | }; |
| 281 | }; |
| 282 | |
Keerthy | f7397ed | 2015-03-23 14:39:38 -0500 | [diff] [blame] | 283 | bandgap: bandgap@4a0021e0 { |
| 284 | reg = <0x4a0021e0 0xc |
| 285 | 0x4a00232c 0xc |
| 286 | 0x4a002380 0x2c |
| 287 | 0x4a0023C0 0x3c |
| 288 | 0x4a002564 0x8 |
| 289 | 0x4a002574 0x50>; |
| 290 | compatible = "ti,dra752-bandgap"; |
| 291 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| 292 | #thermal-sensor-cells = <1>; |
| 293 | }; |
| 294 | |
Suman Anna | 99639ac | 2015-10-02 18:23:22 -0500 | [diff] [blame] | 295 | dsp1_system: dsp_system@40d00000 { |
| 296 | compatible = "syscon"; |
| 297 | reg = <0x40d00000 0x100>; |
| 298 | }; |
| 299 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 300 | sdma: dma-controller@4a056000 { |
| 301 | compatible = "ti,omap4430-sdma"; |
| 302 | reg = <0x4a056000 0x1000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 303 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| 304 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 305 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 306 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 307 | #dma-cells = <1>; |
Peter Ujfalusi | 08d9b32 | 2015-02-20 15:42:06 +0200 | [diff] [blame] | 308 | dma-channels = <32>; |
| 309 | dma-requests = <127>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 310 | }; |
| 311 | |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 312 | sdma_xbar: dma-router@4a002b78 { |
| 313 | compatible = "ti,dra7-dma-crossbar"; |
| 314 | reg = <0x4a002b78 0xfc>; |
| 315 | #dma-cells = <1>; |
| 316 | dma-requests = <205>; |
| 317 | ti,dma-safe-map = <0>; |
| 318 | dma-masters = <&sdma>; |
| 319 | }; |
| 320 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 321 | gpio1: gpio@4ae10000 { |
| 322 | compatible = "ti,omap4-gpio"; |
| 323 | reg = <0x4ae10000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 324 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 325 | ti,hwmods = "gpio1"; |
| 326 | gpio-controller; |
| 327 | #gpio-cells = <2>; |
| 328 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 329 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 330 | }; |
| 331 | |
| 332 | gpio2: gpio@48055000 { |
| 333 | compatible = "ti,omap4-gpio"; |
| 334 | reg = <0x48055000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 335 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 336 | ti,hwmods = "gpio2"; |
| 337 | gpio-controller; |
| 338 | #gpio-cells = <2>; |
| 339 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 340 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 341 | }; |
| 342 | |
| 343 | gpio3: gpio@48057000 { |
| 344 | compatible = "ti,omap4-gpio"; |
| 345 | reg = <0x48057000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 346 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 347 | ti,hwmods = "gpio3"; |
| 348 | gpio-controller; |
| 349 | #gpio-cells = <2>; |
| 350 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 351 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 352 | }; |
| 353 | |
| 354 | gpio4: gpio@48059000 { |
| 355 | compatible = "ti,omap4-gpio"; |
| 356 | reg = <0x48059000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 357 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 358 | ti,hwmods = "gpio4"; |
| 359 | gpio-controller; |
| 360 | #gpio-cells = <2>; |
| 361 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 362 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 363 | }; |
| 364 | |
| 365 | gpio5: gpio@4805b000 { |
| 366 | compatible = "ti,omap4-gpio"; |
| 367 | reg = <0x4805b000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 368 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 369 | ti,hwmods = "gpio5"; |
| 370 | gpio-controller; |
| 371 | #gpio-cells = <2>; |
| 372 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 373 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 374 | }; |
| 375 | |
| 376 | gpio6: gpio@4805d000 { |
| 377 | compatible = "ti,omap4-gpio"; |
| 378 | reg = <0x4805d000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 379 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 380 | ti,hwmods = "gpio6"; |
| 381 | gpio-controller; |
| 382 | #gpio-cells = <2>; |
| 383 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 384 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 385 | }; |
| 386 | |
| 387 | gpio7: gpio@48051000 { |
| 388 | compatible = "ti,omap4-gpio"; |
| 389 | reg = <0x48051000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 390 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 391 | ti,hwmods = "gpio7"; |
| 392 | gpio-controller; |
| 393 | #gpio-cells = <2>; |
| 394 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 395 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 396 | }; |
| 397 | |
| 398 | gpio8: gpio@48053000 { |
| 399 | compatible = "ti,omap4-gpio"; |
| 400 | reg = <0x48053000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 401 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 402 | ti,hwmods = "gpio8"; |
| 403 | gpio-controller; |
| 404 | #gpio-cells = <2>; |
| 405 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 406 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 407 | }; |
| 408 | |
| 409 | uart1: serial@4806a000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 410 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 411 | reg = <0x4806a000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 412 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 413 | ti,hwmods = "uart1"; |
| 414 | clock-frequency = <48000000>; |
| 415 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 416 | dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 417 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 418 | }; |
| 419 | |
| 420 | uart2: serial@4806c000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 421 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 422 | reg = <0x4806c000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 423 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 424 | ti,hwmods = "uart2"; |
| 425 | clock-frequency = <48000000>; |
| 426 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 427 | dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 428 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 429 | }; |
| 430 | |
| 431 | uart3: serial@48020000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 432 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 433 | reg = <0x48020000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 434 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 435 | ti,hwmods = "uart3"; |
| 436 | clock-frequency = <48000000>; |
| 437 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 438 | dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 439 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 440 | }; |
| 441 | |
| 442 | uart4: serial@4806e000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 443 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 444 | reg = <0x4806e000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 445 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 446 | ti,hwmods = "uart4"; |
| 447 | clock-frequency = <48000000>; |
| 448 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 449 | dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 450 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 451 | }; |
| 452 | |
| 453 | uart5: serial@48066000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 454 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 455 | reg = <0x48066000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 456 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 457 | ti,hwmods = "uart5"; |
| 458 | clock-frequency = <48000000>; |
| 459 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 460 | dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 461 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 462 | }; |
| 463 | |
| 464 | uart6: serial@48068000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 465 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 466 | reg = <0x48068000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 467 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 468 | ti,hwmods = "uart6"; |
| 469 | clock-frequency = <48000000>; |
| 470 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 471 | dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 472 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 473 | }; |
| 474 | |
| 475 | uart7: serial@48420000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 476 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 477 | reg = <0x48420000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 478 | interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 479 | ti,hwmods = "uart7"; |
| 480 | clock-frequency = <48000000>; |
| 481 | status = "disabled"; |
| 482 | }; |
| 483 | |
| 484 | uart8: serial@48422000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 485 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 486 | reg = <0x48422000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 487 | interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 488 | ti,hwmods = "uart8"; |
| 489 | clock-frequency = <48000000>; |
| 490 | status = "disabled"; |
| 491 | }; |
| 492 | |
| 493 | uart9: serial@48424000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 494 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 495 | reg = <0x48424000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 496 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 497 | ti,hwmods = "uart9"; |
| 498 | clock-frequency = <48000000>; |
| 499 | status = "disabled"; |
| 500 | }; |
| 501 | |
| 502 | uart10: serial@4ae2b000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 503 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 504 | reg = <0x4ae2b000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 505 | interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 506 | ti,hwmods = "uart10"; |
| 507 | clock-frequency = <48000000>; |
| 508 | status = "disabled"; |
| 509 | }; |
| 510 | |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 511 | mailbox1: mailbox@4a0f4000 { |
| 512 | compatible = "ti,omap4-mailbox"; |
| 513 | reg = <0x4a0f4000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 514 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| 515 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 516 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 517 | ti,hwmods = "mailbox1"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 518 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 519 | ti,mbox-num-users = <3>; |
| 520 | ti,mbox-num-fifos = <8>; |
| 521 | status = "disabled"; |
| 522 | }; |
| 523 | |
| 524 | mailbox2: mailbox@4883a000 { |
| 525 | compatible = "ti,omap4-mailbox"; |
| 526 | reg = <0x4883a000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 527 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
| 528 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, |
| 529 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, |
| 530 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 531 | ti,hwmods = "mailbox2"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 532 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 533 | ti,mbox-num-users = <4>; |
| 534 | ti,mbox-num-fifos = <12>; |
| 535 | status = "disabled"; |
| 536 | }; |
| 537 | |
| 538 | mailbox3: mailbox@4883c000 { |
| 539 | compatible = "ti,omap4-mailbox"; |
| 540 | reg = <0x4883c000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 541 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
| 542 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, |
| 543 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, |
| 544 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 545 | ti,hwmods = "mailbox3"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 546 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 547 | ti,mbox-num-users = <4>; |
| 548 | ti,mbox-num-fifos = <12>; |
| 549 | status = "disabled"; |
| 550 | }; |
| 551 | |
| 552 | mailbox4: mailbox@4883e000 { |
| 553 | compatible = "ti,omap4-mailbox"; |
| 554 | reg = <0x4883e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 555 | interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| 556 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, |
| 557 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| 558 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 559 | ti,hwmods = "mailbox4"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 560 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 561 | ti,mbox-num-users = <4>; |
| 562 | ti,mbox-num-fifos = <12>; |
| 563 | status = "disabled"; |
| 564 | }; |
| 565 | |
| 566 | mailbox5: mailbox@48840000 { |
| 567 | compatible = "ti,omap4-mailbox"; |
| 568 | reg = <0x48840000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 569 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| 570 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| 571 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| 572 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 573 | ti,hwmods = "mailbox5"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 574 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 575 | ti,mbox-num-users = <4>; |
| 576 | ti,mbox-num-fifos = <12>; |
| 577 | status = "disabled"; |
| 578 | }; |
| 579 | |
| 580 | mailbox6: mailbox@48842000 { |
| 581 | compatible = "ti,omap4-mailbox"; |
| 582 | reg = <0x48842000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 583 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| 584 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| 585 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| 586 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 587 | ti,hwmods = "mailbox6"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 588 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 589 | ti,mbox-num-users = <4>; |
| 590 | ti,mbox-num-fifos = <12>; |
| 591 | status = "disabled"; |
| 592 | }; |
| 593 | |
| 594 | mailbox7: mailbox@48844000 { |
| 595 | compatible = "ti,omap4-mailbox"; |
| 596 | reg = <0x48844000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 597 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
| 598 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
| 599 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, |
| 600 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 601 | ti,hwmods = "mailbox7"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 602 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 603 | ti,mbox-num-users = <4>; |
| 604 | ti,mbox-num-fifos = <12>; |
| 605 | status = "disabled"; |
| 606 | }; |
| 607 | |
| 608 | mailbox8: mailbox@48846000 { |
| 609 | compatible = "ti,omap4-mailbox"; |
| 610 | reg = <0x48846000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 611 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| 612 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
| 613 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, |
| 614 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 615 | ti,hwmods = "mailbox8"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 616 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 617 | ti,mbox-num-users = <4>; |
| 618 | ti,mbox-num-fifos = <12>; |
| 619 | status = "disabled"; |
| 620 | }; |
| 621 | |
| 622 | mailbox9: mailbox@4885e000 { |
| 623 | compatible = "ti,omap4-mailbox"; |
| 624 | reg = <0x4885e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 625 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
| 626 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, |
| 627 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, |
| 628 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 629 | ti,hwmods = "mailbox9"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 630 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 631 | ti,mbox-num-users = <4>; |
| 632 | ti,mbox-num-fifos = <12>; |
| 633 | status = "disabled"; |
| 634 | }; |
| 635 | |
| 636 | mailbox10: mailbox@48860000 { |
| 637 | compatible = "ti,omap4-mailbox"; |
| 638 | reg = <0x48860000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 639 | interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
| 640 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, |
| 641 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, |
| 642 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 643 | ti,hwmods = "mailbox10"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 644 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 645 | ti,mbox-num-users = <4>; |
| 646 | ti,mbox-num-fifos = <12>; |
| 647 | status = "disabled"; |
| 648 | }; |
| 649 | |
| 650 | mailbox11: mailbox@48862000 { |
| 651 | compatible = "ti,omap4-mailbox"; |
| 652 | reg = <0x48862000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 653 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, |
| 654 | <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, |
| 655 | <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, |
| 656 | <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 657 | ti,hwmods = "mailbox11"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 658 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 659 | ti,mbox-num-users = <4>; |
| 660 | ti,mbox-num-fifos = <12>; |
| 661 | status = "disabled"; |
| 662 | }; |
| 663 | |
| 664 | mailbox12: mailbox@48864000 { |
| 665 | compatible = "ti,omap4-mailbox"; |
| 666 | reg = <0x48864000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 667 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, |
| 668 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, |
| 669 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, |
| 670 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 671 | ti,hwmods = "mailbox12"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 672 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 673 | ti,mbox-num-users = <4>; |
| 674 | ti,mbox-num-fifos = <12>; |
| 675 | status = "disabled"; |
| 676 | }; |
| 677 | |
| 678 | mailbox13: mailbox@48802000 { |
| 679 | compatible = "ti,omap4-mailbox"; |
| 680 | reg = <0x48802000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 681 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
| 682 | <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, |
| 683 | <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, |
| 684 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 685 | ti,hwmods = "mailbox13"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 686 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 687 | ti,mbox-num-users = <4>; |
| 688 | ti,mbox-num-fifos = <12>; |
| 689 | status = "disabled"; |
| 690 | }; |
| 691 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 692 | timer1: timer@4ae18000 { |
| 693 | compatible = "ti,omap5430-timer"; |
| 694 | reg = <0x4ae18000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 695 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 696 | ti,hwmods = "timer1"; |
| 697 | ti,timer-alwon; |
| 698 | }; |
| 699 | |
| 700 | timer2: timer@48032000 { |
| 701 | compatible = "ti,omap5430-timer"; |
| 702 | reg = <0x48032000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 703 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 704 | ti,hwmods = "timer2"; |
| 705 | }; |
| 706 | |
| 707 | timer3: timer@48034000 { |
| 708 | compatible = "ti,omap5430-timer"; |
| 709 | reg = <0x48034000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 710 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 711 | ti,hwmods = "timer3"; |
| 712 | }; |
| 713 | |
| 714 | timer4: timer@48036000 { |
| 715 | compatible = "ti,omap5430-timer"; |
| 716 | reg = <0x48036000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 717 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 718 | ti,hwmods = "timer4"; |
| 719 | }; |
| 720 | |
| 721 | timer5: timer@48820000 { |
| 722 | compatible = "ti,omap5430-timer"; |
| 723 | reg = <0x48820000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 724 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 725 | ti,hwmods = "timer5"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 726 | }; |
| 727 | |
| 728 | timer6: timer@48822000 { |
| 729 | compatible = "ti,omap5430-timer"; |
| 730 | reg = <0x48822000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 731 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 732 | ti,hwmods = "timer6"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 733 | }; |
| 734 | |
| 735 | timer7: timer@48824000 { |
| 736 | compatible = "ti,omap5430-timer"; |
| 737 | reg = <0x48824000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 738 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 739 | ti,hwmods = "timer7"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 740 | }; |
| 741 | |
| 742 | timer8: timer@48826000 { |
| 743 | compatible = "ti,omap5430-timer"; |
| 744 | reg = <0x48826000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 745 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 746 | ti,hwmods = "timer8"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 747 | }; |
| 748 | |
| 749 | timer9: timer@4803e000 { |
| 750 | compatible = "ti,omap5430-timer"; |
| 751 | reg = <0x4803e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 752 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 753 | ti,hwmods = "timer9"; |
| 754 | }; |
| 755 | |
| 756 | timer10: timer@48086000 { |
| 757 | compatible = "ti,omap5430-timer"; |
| 758 | reg = <0x48086000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 759 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 760 | ti,hwmods = "timer10"; |
| 761 | }; |
| 762 | |
| 763 | timer11: timer@48088000 { |
| 764 | compatible = "ti,omap5430-timer"; |
| 765 | reg = <0x48088000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 766 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 767 | ti,hwmods = "timer11"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 768 | }; |
| 769 | |
| 770 | timer13: timer@48828000 { |
| 771 | compatible = "ti,omap5430-timer"; |
| 772 | reg = <0x48828000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 773 | interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 774 | ti,hwmods = "timer13"; |
| 775 | status = "disabled"; |
| 776 | }; |
| 777 | |
| 778 | timer14: timer@4882a000 { |
| 779 | compatible = "ti,omap5430-timer"; |
| 780 | reg = <0x4882a000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 781 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 782 | ti,hwmods = "timer14"; |
| 783 | status = "disabled"; |
| 784 | }; |
| 785 | |
| 786 | timer15: timer@4882c000 { |
| 787 | compatible = "ti,omap5430-timer"; |
| 788 | reg = <0x4882c000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 789 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 790 | ti,hwmods = "timer15"; |
| 791 | status = "disabled"; |
| 792 | }; |
| 793 | |
| 794 | timer16: timer@4882e000 { |
| 795 | compatible = "ti,omap5430-timer"; |
| 796 | reg = <0x4882e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 797 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 798 | ti,hwmods = "timer16"; |
| 799 | status = "disabled"; |
| 800 | }; |
| 801 | |
| 802 | wdt2: wdt@4ae14000 { |
Lokesh Vutla | be66883 | 2014-11-12 10:54:15 +0530 | [diff] [blame] | 803 | compatible = "ti,omap3-wdt"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 804 | reg = <0x4ae14000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 805 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 806 | ti,hwmods = "wd_timer2"; |
| 807 | }; |
| 808 | |
Suman Anna | dbd7c19 | 2014-01-13 18:26:46 -0600 | [diff] [blame] | 809 | hwspinlock: spinlock@4a0f6000 { |
| 810 | compatible = "ti,omap4-hwspinlock"; |
| 811 | reg = <0x4a0f6000 0x1000>; |
| 812 | ti,hwmods = "spinlock"; |
| 813 | #hwlock-cells = <1>; |
| 814 | }; |
| 815 | |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 816 | dmm@4e000000 { |
| 817 | compatible = "ti,omap5-dmm"; |
| 818 | reg = <0x4e000000 0x800>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 819 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 820 | ti,hwmods = "dmm"; |
| 821 | }; |
| 822 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 823 | i2c1: i2c@48070000 { |
| 824 | compatible = "ti,omap4-i2c"; |
| 825 | reg = <0x48070000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 826 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 827 | #address-cells = <1>; |
| 828 | #size-cells = <0>; |
| 829 | ti,hwmods = "i2c1"; |
| 830 | status = "disabled"; |
| 831 | }; |
| 832 | |
| 833 | i2c2: i2c@48072000 { |
| 834 | compatible = "ti,omap4-i2c"; |
| 835 | reg = <0x48072000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 836 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 837 | #address-cells = <1>; |
| 838 | #size-cells = <0>; |
| 839 | ti,hwmods = "i2c2"; |
| 840 | status = "disabled"; |
| 841 | }; |
| 842 | |
| 843 | i2c3: i2c@48060000 { |
| 844 | compatible = "ti,omap4-i2c"; |
| 845 | reg = <0x48060000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 846 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 847 | #address-cells = <1>; |
| 848 | #size-cells = <0>; |
| 849 | ti,hwmods = "i2c3"; |
| 850 | status = "disabled"; |
| 851 | }; |
| 852 | |
| 853 | i2c4: i2c@4807a000 { |
| 854 | compatible = "ti,omap4-i2c"; |
| 855 | reg = <0x4807a000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 856 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 857 | #address-cells = <1>; |
| 858 | #size-cells = <0>; |
| 859 | ti,hwmods = "i2c4"; |
| 860 | status = "disabled"; |
| 861 | }; |
| 862 | |
| 863 | i2c5: i2c@4807c000 { |
| 864 | compatible = "ti,omap4-i2c"; |
| 865 | reg = <0x4807c000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 866 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 867 | #address-cells = <1>; |
| 868 | #size-cells = <0>; |
| 869 | ti,hwmods = "i2c5"; |
| 870 | status = "disabled"; |
| 871 | }; |
| 872 | |
| 873 | mmc1: mmc@4809c000 { |
| 874 | compatible = "ti,omap4-hsmmc"; |
| 875 | reg = <0x4809c000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 876 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 877 | ti,hwmods = "mmc1"; |
| 878 | ti,dual-volt; |
| 879 | ti,needs-special-reset; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 880 | dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 881 | dma-names = "tx", "rx"; |
| 882 | status = "disabled"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 883 | pbias-supply = <&pbias_mmc_reg>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 884 | }; |
| 885 | |
| 886 | mmc2: mmc@480b4000 { |
| 887 | compatible = "ti,omap4-hsmmc"; |
| 888 | reg = <0x480b4000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 889 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 890 | ti,hwmods = "mmc2"; |
| 891 | ti,needs-special-reset; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 892 | dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 893 | dma-names = "tx", "rx"; |
| 894 | status = "disabled"; |
| 895 | }; |
| 896 | |
| 897 | mmc3: mmc@480ad000 { |
| 898 | compatible = "ti,omap4-hsmmc"; |
| 899 | reg = <0x480ad000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 900 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 901 | ti,hwmods = "mmc3"; |
| 902 | ti,needs-special-reset; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 903 | dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 904 | dma-names = "tx", "rx"; |
| 905 | status = "disabled"; |
| 906 | }; |
| 907 | |
| 908 | mmc4: mmc@480d1000 { |
| 909 | compatible = "ti,omap4-hsmmc"; |
| 910 | reg = <0x480d1000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 911 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 912 | ti,hwmods = "mmc4"; |
| 913 | ti,needs-special-reset; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 914 | dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 915 | dma-names = "tx", "rx"; |
| 916 | status = "disabled"; |
| 917 | }; |
| 918 | |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 919 | abb_mpu: regulator-abb-mpu { |
| 920 | compatible = "ti,abb-v3"; |
| 921 | regulator-name = "abb_mpu"; |
| 922 | #address-cells = <0>; |
| 923 | #size-cells = <0>; |
| 924 | clocks = <&sys_clkin1>; |
| 925 | ti,settling-time = <50>; |
| 926 | ti,clock-cycles = <16>; |
| 927 | |
| 928 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 929 | <0x4ae06014 0x4>, <0x4a003b20 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 930 | <0x4ae0c158 0x4>; |
| 931 | reg-names = "setup-address", "control-address", |
| 932 | "int-address", "efuse-address", |
| 933 | "ldo-address"; |
| 934 | ti,tranxdone-status-mask = <0x80>; |
| 935 | /* LDOVBBMPU_FBB_MUX_CTRL */ |
| 936 | ti,ldovbb-override-mask = <0x400>; |
| 937 | /* LDOVBBMPU_FBB_VSET_OUT */ |
| 938 | ti,ldovbb-vset-mask = <0x1F>; |
| 939 | |
| 940 | /* |
| 941 | * NOTE: only FBB mode used but actual vset will |
| 942 | * determine final biasing |
| 943 | */ |
| 944 | ti,abb_info = < |
| 945 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 946 | 1060000 0 0x0 0 0x02000000 0x01F00000 |
| 947 | 1160000 0 0x4 0 0x02000000 0x01F00000 |
| 948 | 1210000 0 0x8 0 0x02000000 0x01F00000 |
| 949 | >; |
| 950 | }; |
| 951 | |
| 952 | abb_ivahd: regulator-abb-ivahd { |
| 953 | compatible = "ti,abb-v3"; |
| 954 | regulator-name = "abb_ivahd"; |
| 955 | #address-cells = <0>; |
| 956 | #size-cells = <0>; |
| 957 | clocks = <&sys_clkin1>; |
| 958 | ti,settling-time = <50>; |
| 959 | ti,clock-cycles = <16>; |
| 960 | |
| 961 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 962 | <0x4ae06010 0x4>, <0x4a0025cc 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 963 | <0x4a002470 0x4>; |
| 964 | reg-names = "setup-address", "control-address", |
| 965 | "int-address", "efuse-address", |
| 966 | "ldo-address"; |
| 967 | ti,tranxdone-status-mask = <0x40000000>; |
| 968 | /* LDOVBBIVA_FBB_MUX_CTRL */ |
| 969 | ti,ldovbb-override-mask = <0x400>; |
| 970 | /* LDOVBBIVA_FBB_VSET_OUT */ |
| 971 | ti,ldovbb-vset-mask = <0x1F>; |
| 972 | |
| 973 | /* |
| 974 | * NOTE: only FBB mode used but actual vset will |
| 975 | * determine final biasing |
| 976 | */ |
| 977 | ti,abb_info = < |
| 978 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 979 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 980 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 981 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 982 | >; |
| 983 | }; |
| 984 | |
| 985 | abb_dspeve: regulator-abb-dspeve { |
| 986 | compatible = "ti,abb-v3"; |
| 987 | regulator-name = "abb_dspeve"; |
| 988 | #address-cells = <0>; |
| 989 | #size-cells = <0>; |
| 990 | clocks = <&sys_clkin1>; |
| 991 | ti,settling-time = <50>; |
| 992 | ti,clock-cycles = <16>; |
| 993 | |
| 994 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 995 | <0x4ae06010 0x4>, <0x4a0025e0 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 996 | <0x4a00246c 0x4>; |
| 997 | reg-names = "setup-address", "control-address", |
| 998 | "int-address", "efuse-address", |
| 999 | "ldo-address"; |
| 1000 | ti,tranxdone-status-mask = <0x20000000>; |
| 1001 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ |
| 1002 | ti,ldovbb-override-mask = <0x400>; |
| 1003 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ |
| 1004 | ti,ldovbb-vset-mask = <0x1F>; |
| 1005 | |
| 1006 | /* |
| 1007 | * NOTE: only FBB mode used but actual vset will |
| 1008 | * determine final biasing |
| 1009 | */ |
| 1010 | ti,abb_info = < |
| 1011 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1012 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 1013 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 1014 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 1015 | >; |
| 1016 | }; |
| 1017 | |
| 1018 | abb_gpu: regulator-abb-gpu { |
| 1019 | compatible = "ti,abb-v3"; |
| 1020 | regulator-name = "abb_gpu"; |
| 1021 | #address-cells = <0>; |
| 1022 | #size-cells = <0>; |
| 1023 | clocks = <&sys_clkin1>; |
| 1024 | ti,settling-time = <50>; |
| 1025 | ti,clock-cycles = <16>; |
| 1026 | |
| 1027 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 1028 | <0x4ae06010 0x4>, <0x4a003b08 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 1029 | <0x4ae0c154 0x4>; |
| 1030 | reg-names = "setup-address", "control-address", |
| 1031 | "int-address", "efuse-address", |
| 1032 | "ldo-address"; |
| 1033 | ti,tranxdone-status-mask = <0x10000000>; |
| 1034 | /* LDOVBBGPU_FBB_MUX_CTRL */ |
| 1035 | ti,ldovbb-override-mask = <0x400>; |
| 1036 | /* LDOVBBGPU_FBB_VSET_OUT */ |
| 1037 | ti,ldovbb-vset-mask = <0x1F>; |
| 1038 | |
| 1039 | /* |
| 1040 | * NOTE: only FBB mode used but actual vset will |
| 1041 | * determine final biasing |
| 1042 | */ |
| 1043 | ti,abb_info = < |
| 1044 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1045 | 1090000 0 0x0 0 0x02000000 0x01F00000 |
| 1046 | 1210000 0 0x4 0 0x02000000 0x01F00000 |
| 1047 | 1280000 0 0x8 0 0x02000000 0x01F00000 |
| 1048 | >; |
| 1049 | }; |
| 1050 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1051 | mcspi1: spi@48098000 { |
| 1052 | compatible = "ti,omap4-mcspi"; |
| 1053 | reg = <0x48098000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1054 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1055 | #address-cells = <1>; |
| 1056 | #size-cells = <0>; |
| 1057 | ti,hwmods = "mcspi1"; |
| 1058 | ti,spi-num-cs = <4>; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 1059 | dmas = <&sdma_xbar 35>, |
| 1060 | <&sdma_xbar 36>, |
| 1061 | <&sdma_xbar 37>, |
| 1062 | <&sdma_xbar 38>, |
| 1063 | <&sdma_xbar 39>, |
| 1064 | <&sdma_xbar 40>, |
| 1065 | <&sdma_xbar 41>, |
| 1066 | <&sdma_xbar 42>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1067 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 1068 | "tx2", "rx2", "tx3", "rx3"; |
| 1069 | status = "disabled"; |
| 1070 | }; |
| 1071 | |
| 1072 | mcspi2: spi@4809a000 { |
| 1073 | compatible = "ti,omap4-mcspi"; |
| 1074 | reg = <0x4809a000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1075 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1076 | #address-cells = <1>; |
| 1077 | #size-cells = <0>; |
| 1078 | ti,hwmods = "mcspi2"; |
| 1079 | ti,spi-num-cs = <2>; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 1080 | dmas = <&sdma_xbar 43>, |
| 1081 | <&sdma_xbar 44>, |
| 1082 | <&sdma_xbar 45>, |
| 1083 | <&sdma_xbar 46>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1084 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 1085 | status = "disabled"; |
| 1086 | }; |
| 1087 | |
| 1088 | mcspi3: spi@480b8000 { |
| 1089 | compatible = "ti,omap4-mcspi"; |
| 1090 | reg = <0x480b8000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1091 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1092 | #address-cells = <1>; |
| 1093 | #size-cells = <0>; |
| 1094 | ti,hwmods = "mcspi3"; |
| 1095 | ti,spi-num-cs = <2>; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 1096 | dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1097 | dma-names = "tx0", "rx0"; |
| 1098 | status = "disabled"; |
| 1099 | }; |
| 1100 | |
| 1101 | mcspi4: spi@480ba000 { |
| 1102 | compatible = "ti,omap4-mcspi"; |
| 1103 | reg = <0x480ba000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1104 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1105 | #address-cells = <1>; |
| 1106 | #size-cells = <0>; |
| 1107 | ti,hwmods = "mcspi4"; |
| 1108 | ti,spi-num-cs = <1>; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 1109 | dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1110 | dma-names = "tx0", "rx0"; |
| 1111 | status = "disabled"; |
| 1112 | }; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1113 | |
| 1114 | qspi: qspi@4b300000 { |
| 1115 | compatible = "ti,dra7xxx-qspi"; |
| 1116 | reg = <0x4b300000 0x100>; |
| 1117 | reg-names = "qspi_base"; |
| 1118 | #address-cells = <1>; |
| 1119 | #size-cells = <0>; |
| 1120 | ti,hwmods = "qspi"; |
| 1121 | clocks = <&qspi_gfclk_div>; |
| 1122 | clock-names = "fck"; |
| 1123 | num-cs = <4>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1124 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1125 | status = "disabled"; |
| 1126 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1127 | |
| 1128 | omap_control_sata: control-phy@4a002374 { |
| 1129 | compatible = "ti,control-phy-pipe3"; |
| 1130 | reg = <0x4a002374 0x4>; |
| 1131 | reg-names = "power"; |
| 1132 | clocks = <&sys_clkin1>; |
| 1133 | clock-names = "sysclk"; |
| 1134 | }; |
| 1135 | |
| 1136 | /* OCP2SCP3 */ |
| 1137 | ocp2scp@4a090000 { |
| 1138 | compatible = "ti,omap-ocp2scp"; |
| 1139 | #address-cells = <1>; |
| 1140 | #size-cells = <1>; |
| 1141 | ranges; |
| 1142 | reg = <0x4a090000 0x20>; |
| 1143 | ti,hwmods = "ocp2scp3"; |
| 1144 | sata_phy: phy@4A096000 { |
| 1145 | compatible = "ti,phy-pipe3-sata"; |
| 1146 | reg = <0x4A096000 0x80>, /* phy_rx */ |
| 1147 | <0x4A096400 0x64>, /* phy_tx */ |
| 1148 | <0x4A096800 0x40>; /* pll_ctrl */ |
| 1149 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 1150 | ctrl-module = <&omap_control_sata>; |
Roger Quadros | 773c5a0 | 2015-01-13 14:23:21 +0200 | [diff] [blame] | 1151 | clocks = <&sys_clkin1>, <&sata_ref_clk>; |
| 1152 | clock-names = "sysclk", "refclk"; |
Roger Quadros | 257d5d9 | 2015-07-17 16:47:23 +0300 | [diff] [blame] | 1153 | syscon-pllreset = <&scm_conf 0x3fc>; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1154 | #phy-cells = <0>; |
| 1155 | }; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1156 | |
| 1157 | pcie1_phy: pciephy@4a094000 { |
| 1158 | compatible = "ti,phy-pipe3-pcie"; |
| 1159 | reg = <0x4a094000 0x80>, /* phy_rx */ |
| 1160 | <0x4a094400 0x64>; /* phy_tx */ |
| 1161 | reg-names = "phy_rx", "phy_tx"; |
| 1162 | ctrl-module = <&omap_control_pcie1phy>; |
| 1163 | clocks = <&dpll_pcie_ref_ck>, |
| 1164 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1165 | <&optfclk_pciephy1_32khz>, |
| 1166 | <&optfclk_pciephy1_clk>, |
| 1167 | <&optfclk_pciephy1_div_clk>, |
| 1168 | <&optfclk_pciephy_div>; |
| 1169 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1170 | "wkupclk", "refclk", |
| 1171 | "div-clk", "phy-div"; |
| 1172 | #phy-cells = <0>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1173 | }; |
| 1174 | |
| 1175 | pcie2_phy: pciephy@4a095000 { |
| 1176 | compatible = "ti,phy-pipe3-pcie"; |
| 1177 | reg = <0x4a095000 0x80>, /* phy_rx */ |
| 1178 | <0x4a095400 0x64>; /* phy_tx */ |
| 1179 | reg-names = "phy_rx", "phy_tx"; |
| 1180 | ctrl-module = <&omap_control_pcie2phy>; |
| 1181 | clocks = <&dpll_pcie_ref_ck>, |
| 1182 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1183 | <&optfclk_pciephy2_32khz>, |
| 1184 | <&optfclk_pciephy2_clk>, |
| 1185 | <&optfclk_pciephy2_div_clk>, |
| 1186 | <&optfclk_pciephy_div>; |
| 1187 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1188 | "wkupclk", "refclk", |
| 1189 | "div-clk", "phy-div"; |
| 1190 | #phy-cells = <0>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1191 | status = "disabled"; |
| 1192 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1193 | }; |
| 1194 | |
| 1195 | sata: sata@4a141100 { |
| 1196 | compatible = "snps,dwc-ahci"; |
| 1197 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1198 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1199 | phys = <&sata_phy>; |
| 1200 | phy-names = "sata-phy"; |
| 1201 | clocks = <&sata_ref_clk>; |
| 1202 | ti,hwmods = "sata"; |
| 1203 | }; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1204 | |
Kishon Vijay Abraham I | d1ff66b | 2014-07-14 16:12:21 +0530 | [diff] [blame] | 1205 | omap_control_pcie1phy: control-phy@0x4a003c40 { |
| 1206 | compatible = "ti,control-phy-pcie"; |
| 1207 | reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| 1208 | reg-names = "power", "control_sma", "pcie_pcs"; |
| 1209 | clocks = <&sys_clkin1>; |
| 1210 | clock-names = "sysclk"; |
| 1211 | }; |
| 1212 | |
| 1213 | omap_control_pcie2phy: control-pcie@0x4a003c44 { |
| 1214 | compatible = "ti,control-phy-pcie"; |
| 1215 | reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| 1216 | reg-names = "power", "control_sma", "pcie_pcs"; |
| 1217 | clocks = <&sys_clkin1>; |
| 1218 | clock-names = "sysclk"; |
| 1219 | status = "disabled"; |
| 1220 | }; |
| 1221 | |
Nishanth Menon | 00edd31 | 2015-04-08 18:56:27 -0500 | [diff] [blame] | 1222 | rtc: rtc@48838000 { |
Lokesh Vutla | bc07831 | 2014-11-19 17:53:08 +0530 | [diff] [blame] | 1223 | compatible = "ti,am3352-rtc"; |
| 1224 | reg = <0x48838000 0x100>; |
| 1225 | interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, |
| 1226 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; |
| 1227 | ti,hwmods = "rtcss"; |
| 1228 | clocks = <&sys_32k_ck>; |
| 1229 | }; |
| 1230 | |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1231 | omap_control_usb2phy1: control-phy@4a002300 { |
| 1232 | compatible = "ti,control-phy-usb2"; |
| 1233 | reg = <0x4a002300 0x4>; |
| 1234 | reg-names = "power"; |
| 1235 | }; |
| 1236 | |
| 1237 | omap_control_usb3phy1: control-phy@4a002370 { |
| 1238 | compatible = "ti,control-phy-pipe3"; |
| 1239 | reg = <0x4a002370 0x4>; |
| 1240 | reg-names = "power"; |
| 1241 | }; |
| 1242 | |
| 1243 | omap_control_usb2phy2: control-phy@0x4a002e74 { |
| 1244 | compatible = "ti,control-phy-usb2-dra7"; |
| 1245 | reg = <0x4a002e74 0x4>; |
| 1246 | reg-names = "power"; |
| 1247 | }; |
| 1248 | |
| 1249 | /* OCP2SCP1 */ |
| 1250 | ocp2scp@4a080000 { |
| 1251 | compatible = "ti,omap-ocp2scp"; |
| 1252 | #address-cells = <1>; |
| 1253 | #size-cells = <1>; |
| 1254 | ranges; |
| 1255 | reg = <0x4a080000 0x20>; |
| 1256 | ti,hwmods = "ocp2scp1"; |
| 1257 | |
| 1258 | usb2_phy1: phy@4a084000 { |
| 1259 | compatible = "ti,omap-usb2"; |
| 1260 | reg = <0x4a084000 0x400>; |
| 1261 | ctrl-module = <&omap_control_usb2phy1>; |
| 1262 | clocks = <&usb_phy1_always_on_clk32k>, |
| 1263 | <&usb_otg_ss1_refclk960m>; |
| 1264 | clock-names = "wkupclk", |
| 1265 | "refclk"; |
| 1266 | #phy-cells = <0>; |
| 1267 | }; |
| 1268 | |
| 1269 | usb2_phy2: phy@4a085000 { |
| 1270 | compatible = "ti,omap-usb2"; |
| 1271 | reg = <0x4a085000 0x400>; |
| 1272 | ctrl-module = <&omap_control_usb2phy2>; |
| 1273 | clocks = <&usb_phy2_always_on_clk32k>, |
| 1274 | <&usb_otg_ss2_refclk960m>; |
| 1275 | clock-names = "wkupclk", |
| 1276 | "refclk"; |
| 1277 | #phy-cells = <0>; |
| 1278 | }; |
| 1279 | |
| 1280 | usb3_phy1: phy@4a084400 { |
| 1281 | compatible = "ti,omap-usb3"; |
| 1282 | reg = <0x4a084400 0x80>, |
| 1283 | <0x4a084800 0x64>, |
| 1284 | <0x4a084c00 0x40>; |
| 1285 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 1286 | ctrl-module = <&omap_control_usb3phy1>; |
| 1287 | clocks = <&usb_phy3_always_on_clk32k>, |
| 1288 | <&sys_clkin1>, |
| 1289 | <&usb_otg_ss1_refclk960m>; |
| 1290 | clock-names = "wkupclk", |
| 1291 | "sysclk", |
| 1292 | "refclk"; |
| 1293 | #phy-cells = <0>; |
| 1294 | }; |
| 1295 | }; |
| 1296 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1297 | omap_dwc3_1: omap_dwc3_1@48880000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1298 | compatible = "ti,dwc3"; |
| 1299 | ti,hwmods = "usb_otg_ss1"; |
| 1300 | reg = <0x48880000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1301 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1302 | #address-cells = <1>; |
| 1303 | #size-cells = <1>; |
| 1304 | utmi-mode = <2>; |
| 1305 | ranges; |
| 1306 | usb1: usb@48890000 { |
| 1307 | compatible = "snps,dwc3"; |
| 1308 | reg = <0x48890000 0x17000>; |
Roger Quadros | 964927f | 2015-07-08 13:42:32 +0300 | [diff] [blame] | 1309 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, |
| 1310 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, |
| 1311 | <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| 1312 | interrupt-names = "peripheral", |
| 1313 | "host", |
| 1314 | "otg"; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1315 | phys = <&usb2_phy1>, <&usb3_phy1>; |
| 1316 | phy-names = "usb2-phy", "usb3-phy"; |
| 1317 | tx-fifo-resize; |
| 1318 | maximum-speed = "super-speed"; |
| 1319 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1320 | snps,dis_u3_susphy_quirk; |
| 1321 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1322 | }; |
| 1323 | }; |
| 1324 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1325 | omap_dwc3_2: omap_dwc3_2@488c0000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1326 | compatible = "ti,dwc3"; |
| 1327 | ti,hwmods = "usb_otg_ss2"; |
| 1328 | reg = <0x488c0000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1329 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1330 | #address-cells = <1>; |
| 1331 | #size-cells = <1>; |
| 1332 | utmi-mode = <2>; |
| 1333 | ranges; |
| 1334 | usb2: usb@488d0000 { |
| 1335 | compatible = "snps,dwc3"; |
| 1336 | reg = <0x488d0000 0x17000>; |
Roger Quadros | 964927f | 2015-07-08 13:42:32 +0300 | [diff] [blame] | 1337 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
| 1338 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
| 1339 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
| 1340 | interrupt-names = "peripheral", |
| 1341 | "host", |
| 1342 | "otg"; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1343 | phys = <&usb2_phy2>; |
| 1344 | phy-names = "usb2-phy"; |
| 1345 | tx-fifo-resize; |
| 1346 | maximum-speed = "high-speed"; |
| 1347 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1348 | snps,dis_u3_susphy_quirk; |
| 1349 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1350 | }; |
| 1351 | }; |
| 1352 | |
| 1353 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1354 | omap_dwc3_3: omap_dwc3_3@48900000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1355 | compatible = "ti,dwc3"; |
| 1356 | ti,hwmods = "usb_otg_ss3"; |
| 1357 | reg = <0x48900000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1358 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1359 | #address-cells = <1>; |
| 1360 | #size-cells = <1>; |
| 1361 | utmi-mode = <2>; |
| 1362 | ranges; |
| 1363 | status = "disabled"; |
| 1364 | usb3: usb@48910000 { |
| 1365 | compatible = "snps,dwc3"; |
| 1366 | reg = <0x48910000 0x17000>; |
Roger Quadros | 964927f | 2015-07-08 13:42:32 +0300 | [diff] [blame] | 1367 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
| 1368 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
| 1369 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
| 1370 | interrupt-names = "peripheral", |
| 1371 | "host", |
| 1372 | "otg"; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1373 | tx-fifo-resize; |
| 1374 | maximum-speed = "high-speed"; |
| 1375 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1376 | snps,dis_u3_susphy_quirk; |
| 1377 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1378 | }; |
| 1379 | }; |
| 1380 | |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1381 | elm: elm@48078000 { |
| 1382 | compatible = "ti,am3352-elm"; |
| 1383 | reg = <0x48078000 0xfc0>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1384 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1385 | ti,hwmods = "elm"; |
| 1386 | status = "disabled"; |
| 1387 | }; |
| 1388 | |
| 1389 | gpmc: gpmc@50000000 { |
| 1390 | compatible = "ti,am3352-gpmc"; |
| 1391 | ti,hwmods = "gpmc"; |
| 1392 | reg = <0x50000000 0x37c>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1393 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1394 | gpmc,num-cs = <8>; |
| 1395 | gpmc,num-waitpins = <2>; |
| 1396 | #address-cells = <2>; |
| 1397 | #size-cells = <1>; |
| 1398 | status = "disabled"; |
| 1399 | }; |
Peter Ujfalusi | 2ca0945 | 2014-05-07 13:20:48 +0300 | [diff] [blame] | 1400 | |
| 1401 | atl: atl@4843c000 { |
| 1402 | compatible = "ti,dra7-atl"; |
| 1403 | reg = <0x4843c000 0x3ff>; |
| 1404 | ti,hwmods = "atl"; |
| 1405 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, |
| 1406 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; |
| 1407 | clocks = <&atl_gfclk_mux>; |
| 1408 | clock-names = "fck"; |
| 1409 | status = "disabled"; |
| 1410 | }; |
Olof Johansson | 412a9bb | 2014-07-18 22:16:15 -0700 | [diff] [blame] | 1411 | |
Peter Ujfalusi | 026d4d6 | 2015-08-24 10:19:58 +0300 | [diff] [blame] | 1412 | mcasp3: mcasp@48468000 { |
| 1413 | compatible = "ti,dra7-mcasp-audio"; |
| 1414 | ti,hwmods = "mcasp3"; |
| 1415 | reg = <0x48468000 0x2000>; |
| 1416 | reg-names = "mpu"; |
| 1417 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, |
| 1418 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; |
| 1419 | interrupt-names = "tx", "rx"; |
| 1420 | dmas = <&sdma_xbar 133>, <&sdma_xbar 132>; |
| 1421 | dma-names = "tx", "rx"; |
| 1422 | clocks = <&mcasp3_ahclkx_mux>; |
| 1423 | clock-names = "fck"; |
| 1424 | status = "disabled"; |
| 1425 | }; |
| 1426 | |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1427 | crossbar_mpu: crossbar@4a002a48 { |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1428 | compatible = "ti,irq-crossbar"; |
| 1429 | reg = <0x4a002a48 0x130>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1430 | interrupt-controller; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 1431 | interrupt-parent = <&wakeupgen>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1432 | #interrupt-cells = <3>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1433 | ti,max-irqs = <160>; |
| 1434 | ti,max-crossbar-sources = <MAX_SOURCES>; |
| 1435 | ti,reg-size = <2>; |
| 1436 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; |
| 1437 | ti,irqs-skip = <10 133 139 140>; |
| 1438 | ti,irqs-safe-map = <0>; |
| 1439 | }; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 1440 | |
Vishal Mahaveer | c263a5b | 2015-08-25 13:57:49 -0500 | [diff] [blame] | 1441 | mac: ethernet@48484000 { |
Mugunthan V N | e209531 | 2015-08-12 15:22:54 +0530 | [diff] [blame] | 1442 | compatible = "ti,dra7-cpsw","ti,cpsw"; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 1443 | ti,hwmods = "gmac"; |
| 1444 | clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; |
| 1445 | clock-names = "fck", "cpts"; |
| 1446 | cpdma_channels = <8>; |
| 1447 | ale_entries = <1024>; |
| 1448 | bd_ram_size = <0x2000>; |
| 1449 | no_bd_ram = <0>; |
| 1450 | rx_descs = <64>; |
| 1451 | mac_control = <0x20>; |
| 1452 | slaves = <2>; |
| 1453 | active_slave = <0>; |
| 1454 | cpts_clock_mult = <0x80000000>; |
| 1455 | cpts_clock_shift = <29>; |
| 1456 | reg = <0x48484000 0x1000 |
| 1457 | 0x48485200 0x2E00>; |
| 1458 | #address-cells = <1>; |
| 1459 | #size-cells = <1>; |
| 1460 | /* |
| 1461 | * rx_thresh_pend |
| 1462 | * rx_pend |
| 1463 | * tx_pend |
| 1464 | * misc_pend |
| 1465 | */ |
| 1466 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| 1467 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| 1468 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| 1469 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; |
| 1470 | ranges; |
| 1471 | status = "disabled"; |
| 1472 | |
| 1473 | davinci_mdio: mdio@48485000 { |
| 1474 | compatible = "ti,davinci_mdio"; |
| 1475 | #address-cells = <1>; |
| 1476 | #size-cells = <0>; |
| 1477 | ti,hwmods = "davinci_mdio"; |
| 1478 | bus_freq = <1000000>; |
| 1479 | reg = <0x48485000 0x100>; |
| 1480 | }; |
| 1481 | |
| 1482 | cpsw_emac0: slave@48480200 { |
| 1483 | /* Filled in by U-Boot */ |
| 1484 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1485 | }; |
| 1486 | |
| 1487 | cpsw_emac1: slave@48480300 { |
| 1488 | /* Filled in by U-Boot */ |
| 1489 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1490 | }; |
| 1491 | |
| 1492 | phy_sel: cpsw-phy-sel@4a002554 { |
| 1493 | compatible = "ti,dra7xx-cpsw-phy-sel"; |
| 1494 | reg= <0x4a002554 0x4>; |
| 1495 | reg-names = "gmii-sel"; |
| 1496 | }; |
| 1497 | }; |
| 1498 | |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 1499 | dcan1: can@481cc000 { |
| 1500 | compatible = "ti,dra7-d_can"; |
| 1501 | ti,hwmods = "dcan1"; |
| 1502 | reg = <0x4ae3c000 0x2000>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 1503 | syscon-raminit = <&scm_conf 0x558 0>; |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 1504 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| 1505 | clocks = <&dcan1_sys_clk_mux>; |
| 1506 | status = "disabled"; |
| 1507 | }; |
| 1508 | |
| 1509 | dcan2: can@481d0000 { |
| 1510 | compatible = "ti,dra7-d_can"; |
| 1511 | ti,hwmods = "dcan2"; |
| 1512 | reg = <0x48480000 0x2000>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 1513 | syscon-raminit = <&scm_conf 0x558 1>; |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 1514 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| 1515 | clocks = <&sys_clkin1>; |
| 1516 | status = "disabled"; |
| 1517 | }; |
Tomi Valkeinen | 95c1cd1 | 2014-07-09 16:15:18 +0530 | [diff] [blame] | 1518 | |
| 1519 | dss: dss@58000000 { |
| 1520 | compatible = "ti,dra7-dss"; |
| 1521 | /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ |
| 1522 | /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ |
| 1523 | status = "disabled"; |
| 1524 | ti,hwmods = "dss_core"; |
| 1525 | /* CTRL_CORE_DSS_PLL_CONTROL */ |
| 1526 | syscon-pll-ctrl = <&scm_conf 0x538>; |
| 1527 | #address-cells = <1>; |
| 1528 | #size-cells = <1>; |
| 1529 | ranges; |
| 1530 | |
| 1531 | dispc@58001000 { |
| 1532 | compatible = "ti,dra7-dispc"; |
| 1533 | reg = <0x58001000 0x1000>; |
| 1534 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 1535 | ti,hwmods = "dss_dispc"; |
| 1536 | clocks = <&dss_dss_clk>; |
| 1537 | clock-names = "fck"; |
| 1538 | /* CTRL_CORE_SMA_SW_1 */ |
| 1539 | syscon-pol = <&scm_conf 0x534>; |
| 1540 | }; |
| 1541 | |
| 1542 | hdmi: encoder@58060000 { |
| 1543 | compatible = "ti,dra7-hdmi"; |
| 1544 | reg = <0x58040000 0x200>, |
| 1545 | <0x58040200 0x80>, |
| 1546 | <0x58040300 0x80>, |
| 1547 | <0x58060000 0x19000>; |
| 1548 | reg-names = "wp", "pll", "phy", "core"; |
| 1549 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 1550 | status = "disabled"; |
| 1551 | ti,hwmods = "dss_hdmi"; |
| 1552 | clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; |
| 1553 | clock-names = "fck", "sys_clk"; |
| 1554 | }; |
| 1555 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1556 | }; |
Keerthy | f7397ed | 2015-03-23 14:39:38 -0500 | [diff] [blame] | 1557 | |
| 1558 | thermal_zones: thermal-zones { |
| 1559 | #include "omap4-cpu-thermal.dtsi" |
| 1560 | #include "omap5-gpu-thermal.dtsi" |
| 1561 | #include "omap5-core-thermal.dtsi" |
| 1562 | }; |
| 1563 | |
| 1564 | }; |
| 1565 | |
| 1566 | &cpu_thermal { |
| 1567 | polling-delay = <500>; /* milliseconds */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1568 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 1569 | |
| 1570 | /include/ "dra7xx-clocks.dtsi" |